Lines Matching +full:1 +full:c600000
54 cpu1: cpu@1 {
164 #reset-cells = <1>;
200 #clock-cells = <1>;
207 #power-domain-cells = <1>;
376 #address-cells = <1>;
377 #size-cells = <1>;
384 #hwlock-cells = <1>;
668 #clock-cells = <1>;
669 #reset-cells = <1>;
670 #power-domain-cells = <1>;
688 spmi_bus: spmi@1c40000 {
754 pinctrl-1 = <&sdc2_off_state>;
799 #reset-cells = <1>;
804 lanes-per-direction = <1>;
857 #address-cells = <1>;
858 #size-cells = <1>;
869 pinctrl-1 = <&qup_i2c0_sleep>;
872 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
874 #address-cells = <1>;
886 pinctrl-1 = <&qup_spi0_sleep>;
889 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
891 #address-cells = <1>;
903 pinctrl-1 = <&qup_i2c1_sleep>;
905 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
906 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
908 #address-cells = <1>;
920 pinctrl-1 = <&qup_i2c2_sleep>;
923 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
925 #address-cells = <1>;
937 pinctrl-1 = <&qup_spi2_sleep>;
940 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
942 #address-cells = <1>;
954 pinctrl-1 = <&qup_i2c3_sleep>;
957 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
959 #address-cells = <1>;
971 pinctrl-1 = <&qup_i2c4_sleep>;
974 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
976 #address-cells = <1>;
1007 #address-cells = <1>;
1008 #size-cells = <1>;
1019 pinctrl-1 = <&qup_i2c5_sleep>;
1022 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1024 #address-cells = <1>;
1036 pinctrl-1 = <&qup_spi5_sleep>;
1039 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1041 #address-cells = <1>;
1053 pinctrl-1 = <&qup_i2c6_sleep>;
1055 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1056 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1058 #address-cells = <1>;
1070 pinctrl-1 = <&qup_spi6_sleep>;
1072 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1073 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1075 #address-cells = <1>;
1087 pinctrl-1 = <&qup_i2c7_sleep>;
1090 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1092 #address-cells = <1>;
1104 pinctrl-1 = <&qup_i2c8_sleep>;
1107 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1109 #address-cells = <1>;
1121 pinctrl-1 = <&qup_spi8_sleep>;
1124 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1126 #address-cells = <1>;
1138 pinctrl-1 = <&qup_i2c9_sleep>;
1141 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1143 #address-cells = <1>;
1155 pinctrl-1 = <&qup_spi9_sleep>;
1158 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1160 #address-cells = <1>;
1169 #address-cells = <1>;
1170 #size-cells = <1>;
1229 #interrupt-cells = <1>;
1242 #address-cells = <1>;
1243 #size-cells = <1>;
1278 #address-cells = <1>;
1341 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1349 #address-cells = <1>;
1355 #address-cells = <1>;
1365 port@1 {
1366 reg = <1>;
1396 #clock-cells = <1>;
1417 <&mdss_dsi0_phy 1>,
1435 #clock-cells = <1>;
1436 #power-domain-cells = <1>;
1439 apps_smmu: iommu@c600000 {
1508 #global-interrupts = <1>;
1517 #mbox-cells = <1>;
1522 #address-cells = <1>;
1523 #size-cells = <1>;
1537 frame-number = <1>;
1591 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,