Lines Matching +full:0 +full:x5f800000
24 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
107 reg = <0x0 0x102>;
116 reg = <0x0 0x103>;
170 reg = <0x0 0x40000000 0x0 0x0>;
192 mboxes = <&apcs_glb 0>;
264 reg = <0x0 0x45700000 0x0 0x600000>;
269 reg = <0x0 0x45e00000 0x0 0x140000>;
274 reg = <0x0 0x45fff000 0x0 0x1000>;
279 reg = <0x0 0x46000000 0x0 0x200000>;
284 reg = <0x0 0x46200000 0x0 0x2d00000>;
289 reg = <0x0 0x4ab00000 0x0 0x500000>;
294 reg = <0x0 0x4b000000 0x0 0x7e00000>;
299 reg = <0x0 0x52e00000 0x0 0x500000>;
304 reg = <0x0 0x53300000 0x0 0x200000>;
309 reg = <0x0 0x53500000 0x0 0x1e00000>;
314 reg = <0x0 0x55300000 0x0 0x1e00000>;
319 reg = <0x0 0x57100000 0x0 0x10000>;
324 reg = <0x0 0x57110000 0x0 0x5000>;
329 reg = <0x0 0x57115000 0x0 0x2000>;
334 reg = <0x0 0x5c000000 0x0 0x00f00000>;
339 reg = <0x0 0x5cf00000 0x0 0x0100000>;
344 reg = <0x0 0x5f800000 0x0 0x1e00000>;
349 reg = <0x0 0x5e400000 0x0 0x1400000>;
354 reg = <0x0 0xf3000000 0x0 0x400000>;
359 reg = <0x0 0xf3400000 0x0 0x800000>;
364 reg = <0x1 0x3fc00000 0x0 0x400000>;
375 soc@0 {
378 ranges = <0x00 0x00 0x00 0xffffffff>;
383 reg = <0x00340000 0x20000>;
389 reg = <0x00500000 0x400000>,
390 <0x00900000 0x400000>,
391 <0x00d00000 0x400000>;
395 gpio-ranges = <&tlmm 0 0 134>;
667 reg = <0x01400000 0x1f0000>;
677 reg = <0x01613000 0x180>;
678 #phy-cells = <0>;
690 reg = <0x01c40000 0x1100>,
691 <0x01e00000 0x2000000>,
692 <0x03e00000 0x100000>,
693 <0x03f00000 0xa0000>,
694 <0x01c0a000 0x26000>;
698 qcom,ee = <0>;
699 qcom,channel = <0>;
701 #size-cells = <0>;
708 reg = <0x045f0000 0x7000>;
713 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
724 iommus = <&apps_smmu 0x160 0x0>;
728 qcom,dll-config = <0x000f642c>;
729 qcom,ddr-config = <0x80040873>;
740 reg = <0x04784000 0x1000>;
751 iommus = <&apps_smmu 0x180 0x0>;
753 pinctrl-0 = <&sdc2_on_state>;
759 qcom,dll-config = <0x0007642c>;
760 qcom,ddr-config = <0x80040873>;
768 reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
789 <0 0>,
790 <0 0>,
792 <0 0>,
793 <0 0>,
794 <0 0>,
806 iommus = <&apps_smmu 0x200 0x0>;
813 reg = <0x04807000 0xdb8>;
822 resets = <&ufs_mem_hc 0>;
827 #phy-cells = <0>;
834 reg = <0x04a00000 0x60000>;
844 dma-channel-mask = <0x1f>;
845 iommus = <&apps_smmu 0x136 0x0>;
852 reg = <0x04ac0000 0x2000>;
856 iommus = <&apps_smmu 0x123 0x0>;
864 reg = <0x04a80000 0x4000>;
868 pinctrl-0 = <&qup_i2c0_default>;
871 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
872 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
875 #size-cells = <0>;
881 reg = <0x04a80000 0x4000>;
885 pinctrl-0 = <&qup_spi0_default>;
888 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
889 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
892 #size-cells = <0>;
898 reg = <0x04a84000 0x4000>;
902 pinctrl-0 = <&qup_i2c1_default>;
905 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
909 #size-cells = <0>;
915 reg = <0x04a88000 0x4000>;
919 pinctrl-0 = <&qup_i2c2_default>;
922 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
926 #size-cells = <0>;
932 reg = <0x04a88000 0x4000>;
936 pinctrl-0 = <&qup_spi2_default>;
939 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
943 #size-cells = <0>;
949 reg = <0x04a8c000 0x4000>;
953 pinctrl-0 = <&qup_i2c3_default>;
956 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
960 #size-cells = <0>;
966 reg = <0x04a90000 0x4000>;
970 pinctrl-0 = <&qup_i2c4_default>;
973 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
977 #size-cells = <0>;
984 reg = <0x04c00000 0x60000>;
994 dma-channel-mask = <0x0f>;
995 iommus = <&apps_smmu 0x156 0x0>;
1002 reg = <0x04cc0000 0x2000>;
1006 iommus = <&apps_smmu 0x143 0x0>;
1014 reg = <0x04c80000 0x4000>;
1018 pinctrl-0 = <&qup_i2c5_default>;
1021 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1022 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1025 #size-cells = <0>;
1031 reg = <0x04c80000 0x4000>;
1035 pinctrl-0 = <&qup_spi5_default>;
1038 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1039 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1042 #size-cells = <0>;
1048 reg = <0x04c84000 0x4000>;
1052 pinctrl-0 = <&qup_i2c6_default>;
1055 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1059 #size-cells = <0>;
1065 reg = <0x04c84000 0x4000>;
1069 pinctrl-0 = <&qup_spi6_default>;
1072 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1076 #size-cells = <0>;
1082 reg = <0x04c88000 0x4000>;
1086 pinctrl-0 = <&qup_i2c7_default>;
1089 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1093 #size-cells = <0>;
1099 reg = <0x04c8c000 0x4000>;
1103 pinctrl-0 = <&qup_i2c8_default>;
1106 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1110 #size-cells = <0>;
1116 reg = <0x04c8c000 0x4000>;
1120 pinctrl-0 = <&qup_spi8_default>;
1123 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1127 #size-cells = <0>;
1133 reg = <0x04c90000 0x4000>;
1137 pinctrl-0 = <&qup_i2c9_default>;
1140 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1144 #size-cells = <0>;
1150 reg = <0x04c90000 0x4000>;
1154 pinctrl-0 = <&qup_spi9_default>;
1157 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1161 #size-cells = <0>;
1168 reg = <0x04ef8800 0x400>;
1205 reg = <0x04e00000 0xcd00>;
1207 iommus = <&apps_smmu 0x100 0x0>;
1219 reg = <0x04690000 0x10000>;
1224 reg = <0x05e00000 0x1000>;
1240 iommus = <&apps_smmu 0x400 0x0>;
1250 reg = <0x05e01000 0x83208>,
1251 <0x05eb0000 0x2008>;
1255 interrupts = <0>;
1279 #size-cells = <0>;
1281 port@0 {
1282 reg = <0>;
1321 reg = <0x05e94000 0x400>;
1341 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1350 #size-cells = <0>;
1356 #size-cells = <0>;
1358 port@0 {
1359 reg = <0>;
1389 reg = <0x05e94400 0x100>,
1390 <0x05e94500 0x300>,
1391 <0x05e94800 0x188>;
1397 #phy-cells = <0>;
1413 reg = <0x05f00000 0x20000>;
1416 <&mdss_dsi0_phy 0>,
1418 <0>,
1419 <0>,
1420 <0>,
1441 reg = <0x0c600000 0x80000>;
1515 reg = <0x0f111000 0x1000>;
1525 reg = <0x0f120000 0x1000>;
1529 frame-number = <0>;
1532 reg = <0x0f121000 0x1000>,
1533 <0x0f122000 0x1000>;
1539 reg = <0x0f123000 0x1000>;
1546 reg = <0x0f124000 0x1000>;
1553 reg = <0x0f125000 0x1000>;
1560 reg = <0x0f126000 0x1000>;
1567 reg = <0x0f127000 0x1000>;
1574 reg = <0x0f128000 0x1000>;
1581 reg = <0x0f200000 0x20000>,
1582 <0x0f300000 0x100000>;
1594 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;