Lines Matching +full:0 +full:x53500000
25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
58 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
76 reg = <0x0 0x3>;
85 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
108 reg = <0x0 0x102>;
117 reg = <0x0 0x103>;
171 reg = <0x0 0x40000000 0x0 0x0>;
193 mboxes = <&apcs_glb 0>;
265 reg = <0x0 0x45700000 0x0 0x600000>;
270 reg = <0x0 0x45e00000 0x0 0x140000>;
275 reg = <0x0 0x45fff000 0x0 0x1000>;
280 reg = <0x0 0x46000000 0x0 0x200000>;
285 reg = <0x0 0x46200000 0x0 0x2d00000>;
290 reg = <0x0 0x4ab00000 0x0 0x500000>;
295 reg = <0x0 0x4b000000 0x0 0x7e00000>;
300 reg = <0x0 0x52e00000 0x0 0x500000>;
305 reg = <0x0 0x53300000 0x0 0x200000>;
310 reg = <0x0 0x53500000 0x0 0x1e00000>;
315 reg = <0x0 0x55300000 0x0 0x1e00000>;
320 reg = <0x0 0x57100000 0x0 0x10000>;
325 reg = <0x0 0x57110000 0x0 0x5000>;
330 reg = <0x0 0x57115000 0x0 0x2000>;
335 reg = <0x0 0x5c000000 0x0 0x00f00000>;
340 reg = <0x0 0x5cf00000 0x0 0x0100000>;
345 reg = <0x0 0x5f800000 0x0 0x1e00000>;
350 reg = <0x0 0x5e400000 0x0 0x1400000>;
355 reg = <0x0 0xf3000000 0x0 0x400000>;
360 reg = <0x0 0xf3400000 0x0 0x800000>;
365 reg = <0x1 0x3fc00000 0x0 0x400000>;
376 soc@0 {
379 ranges = <0x00 0x00 0x00 0xffffffff>;
384 reg = <0x00340000 0x20000>;
390 reg = <0x00500000 0x400000>,
391 <0x00900000 0x400000>,
392 <0x00d00000 0x400000>;
396 gpio-ranges = <&tlmm 0 0 134>;
668 reg = <0x01400000 0x1f0000>;
678 reg = <0x01613000 0x180>;
679 #phy-cells = <0>;
691 reg = <0x01c40000 0x1100>,
692 <0x01e00000 0x2000000>,
693 <0x03e00000 0x100000>,
694 <0x03f00000 0xa0000>,
695 <0x01c0a000 0x26000>;
699 qcom,ee = <0>;
700 qcom,channel = <0>;
702 #size-cells = <0>;
709 reg = <0x045f0000 0x7000>;
714 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
725 iommus = <&apps_smmu 0x160 0x0>;
729 qcom,dll-config = <0x000f642c>;
730 qcom,ddr-config = <0x80040873>;
741 reg = <0x04784000 0x1000>;
752 iommus = <&apps_smmu 0x180 0x0>;
754 pinctrl-0 = <&sdc2_on_state>;
760 qcom,dll-config = <0x0007642c>;
761 qcom,ddr-config = <0x80040873>;
769 reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
790 <0 0>,
791 <0 0>,
793 <0 0>,
794 <0 0>,
795 <0 0>,
807 iommus = <&apps_smmu 0x200 0x0>;
814 reg = <0x04807000 0xdb8>;
823 resets = <&ufs_mem_hc 0>;
828 #phy-cells = <0>;
835 reg = <0x04a00000 0x60000>;
845 dma-channel-mask = <0x1f>;
846 iommus = <&apps_smmu 0x136 0x0>;
853 reg = <0x04ac0000 0x2000>;
857 iommus = <&apps_smmu 0x123 0x0>;
865 reg = <0x04a80000 0x4000>;
869 pinctrl-0 = <&qup_i2c0_default>;
872 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
873 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
876 #size-cells = <0>;
882 reg = <0x04a80000 0x4000>;
886 pinctrl-0 = <&qup_spi0_default>;
889 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
890 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
893 #size-cells = <0>;
899 reg = <0x04a84000 0x4000>;
903 pinctrl-0 = <&qup_i2c1_default>;
906 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
910 #size-cells = <0>;
916 reg = <0x04a88000 0x4000>;
920 pinctrl-0 = <&qup_i2c2_default>;
923 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
927 #size-cells = <0>;
933 reg = <0x04a88000 0x4000>;
937 pinctrl-0 = <&qup_spi2_default>;
940 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
944 #size-cells = <0>;
950 reg = <0x04a8c000 0x4000>;
954 pinctrl-0 = <&qup_i2c3_default>;
957 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
961 #size-cells = <0>;
967 reg = <0x04a90000 0x4000>;
971 pinctrl-0 = <&qup_i2c4_default>;
974 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
978 #size-cells = <0>;
985 reg = <0x04c00000 0x60000>;
995 dma-channel-mask = <0x0f>;
996 iommus = <&apps_smmu 0x156 0x0>;
1003 reg = <0x04cc0000 0x2000>;
1007 iommus = <&apps_smmu 0x143 0x0>;
1015 reg = <0x04c80000 0x4000>;
1019 pinctrl-0 = <&qup_i2c5_default>;
1022 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1023 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1026 #size-cells = <0>;
1032 reg = <0x04c80000 0x4000>;
1036 pinctrl-0 = <&qup_spi5_default>;
1039 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1040 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1043 #size-cells = <0>;
1049 reg = <0x04c84000 0x4000>;
1053 pinctrl-0 = <&qup_i2c6_default>;
1056 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1060 #size-cells = <0>;
1066 reg = <0x04c84000 0x4000>;
1070 pinctrl-0 = <&qup_spi6_default>;
1073 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1077 #size-cells = <0>;
1083 reg = <0x04c88000 0x4000>;
1087 pinctrl-0 = <&qup_i2c7_default>;
1090 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1094 #size-cells = <0>;
1100 reg = <0x04c8c000 0x4000>;
1104 pinctrl-0 = <&qup_i2c8_default>;
1107 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1111 #size-cells = <0>;
1117 reg = <0x04c8c000 0x4000>;
1121 pinctrl-0 = <&qup_spi8_default>;
1124 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1128 #size-cells = <0>;
1134 reg = <0x04c90000 0x4000>;
1138 pinctrl-0 = <&qup_i2c9_default>;
1141 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1145 #size-cells = <0>;
1151 reg = <0x04c90000 0x4000>;
1155 pinctrl-0 = <&qup_spi9_default>;
1158 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1162 #size-cells = <0>;
1169 reg = <0x04ef8800 0x400>;
1206 reg = <0x04e00000 0xcd00>;
1208 iommus = <&apps_smmu 0x100 0x0>;
1222 reg = <0x04690000 0x10000>;
1227 reg = <0x05e00000 0x1000>;
1243 iommus = <&apps_smmu 0x400 0x0>;
1253 reg = <0x05e01000 0x83208>,
1254 <0x05eb0000 0x3000>;
1258 interrupts = <0>;
1282 #size-cells = <0>;
1284 port@0 {
1285 reg = <0>;
1324 reg = <0x05e94000 0x400>;
1354 #size-cells = <0>;
1360 #size-cells = <0>;
1362 port@0 {
1363 reg = <0>;
1393 reg = <0x05e94400 0x100>,
1394 <0x05e94500 0x300>,
1395 <0x05e94800 0x188>;
1401 #phy-cells = <0>;
1417 reg = <0x05f00000 0x20000>;
1422 <0>,
1423 <0>,
1424 <0>,
1445 reg = <0x0c600000 0x80000>;
1519 reg = <0x0f111000 0x1000>;
1529 reg = <0x0f120000 0x1000>;
1533 frame-number = <0>;
1536 reg = <0x0f121000 0x1000>,
1537 <0x0f122000 0x1000>;
1543 reg = <0x0f123000 0x1000>;
1550 reg = <0x0f124000 0x1000>;
1557 reg = <0x0f125000 0x1000>;
1564 reg = <0x0f126000 0x1000>;
1571 reg = <0x0f127000 0x1000>;
1578 reg = <0x0f128000 0x1000>;
1585 reg = <0x0f200000 0x20000>,
1586 <0x0f300000 0x100000>;
1598 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;