Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
836 gcc: clock-controller@1400000 { label
837 compatible = "qcom,gcc-sm6115";
851 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
854 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
895 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
896 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
897 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
898 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
904 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
905 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
942 clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
943 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
944 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
971 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
996 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1110 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1111 <&gcc GCC_SDCC1_APPS_CLK>,
1113 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1116 resets = <&gcc GCC_SDCC1_BCR>;
1166 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1167 <&gcc GCC_SDCC2_APPS_CLK>,
1174 resets = <&gcc GCC_SDCC2_BCR>;
1215 resets = <&gcc GCC_UFS_PHY_BCR>;
1218 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1221 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1222 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
1223 <&gcc GCC_UFS_PHY_AHB_CLK>,
1224 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1226 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1227 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1228 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1255 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1256 <&gcc GCC_UFS_CLKREF_CLK>;
1261 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1295 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1296 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1307 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1332 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1357 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1382 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1407 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1432 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1457 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1482 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1507 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1524 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1549 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1574 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1591 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1616 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1645 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1646 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1647 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1648 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1649 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1650 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1653 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1654 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1666 resets = <&gcc GCC_USB30_PRIM_BCR>;
1667 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1724 <&gcc GCC_BIMC_GPU_AXI_CLK>,
1725 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1819 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1820 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1840 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1842 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1859 clocks = <&gcc GCC_DISP_AHB_CLK>,
1860 <&gcc GCC_DISP_HF_AXI_CLK>,
1889 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1963 <&gcc GCC_DISP_HF_AXI_CLK>;
2050 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
3108 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;