Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
15 #include <dt-bindings/interconnect/qcom,sm6115.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,apr.h>
19 #include <dt-bindings/sound/qcom,q6asm.h>
20 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
21 #include <dt-bindings/thermal/thermal.h>
24 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
32 xo_board: xo-board {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
44 #address-cells = <2>;
45 #size-cells = <0>;
52 capacity-dmips-mhz = <1024>;
53 dynamic-power-coefficient = <100>;
54 enable-method = "psci";
55 next-level-cache = <&l2_0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 power-domains = <&cpu_pd0>;
58 power-domain-names = "psci";
59 l2_0: l2-cache {
61 cache-level = <2>;
62 cache-unified;
71 capacity-dmips-mhz = <1024>;
72 dynamic-power-coefficient = <100>;
73 enable-method = "psci";
74 next-level-cache = <&l2_0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
76 power-domains = <&cpu_pd1>;
77 power-domain-names = "psci";
85 capacity-dmips-mhz = <1024>;
86 dynamic-power-coefficient = <100>;
87 enable-method = "psci";
88 next-level-cache = <&l2_0>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
90 power-domains = <&cpu_pd2>;
91 power-domain-names = "psci";
99 capacity-dmips-mhz = <1024>;
100 dynamic-power-coefficient = <100>;
101 enable-method = "psci";
102 next-level-cache = <&l2_0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
104 power-domains = <&cpu_pd3>;
105 power-domain-names = "psci";
113 enable-method = "psci";
114 capacity-dmips-mhz = <1638>;
115 dynamic-power-coefficient = <282>;
116 next-level-cache = <&l2_1>;
117 qcom,freq-domain = <&cpufreq_hw 1>;
118 power-domains = <&cpu_pd4>;
119 power-domain-names = "psci";
120 l2_1: l2-cache {
122 cache-level = <2>;
123 cache-unified;
132 capacity-dmips-mhz = <1638>;
133 dynamic-power-coefficient = <282>;
134 enable-method = "psci";
135 next-level-cache = <&l2_1>;
136 qcom,freq-domain = <&cpufreq_hw 1>;
137 power-domains = <&cpu_pd5>;
138 power-domain-names = "psci";
146 capacity-dmips-mhz = <1638>;
147 dynamic-power-coefficient = <282>;
148 enable-method = "psci";
149 next-level-cache = <&l2_1>;
150 qcom,freq-domain = <&cpufreq_hw 1>;
151 power-domains = <&cpu_pd6>;
152 power-domain-names = "psci";
160 capacity-dmips-mhz = <1638>;
161 dynamic-power-coefficient = <282>;
162 enable-method = "psci";
163 next-level-cache = <&l2_1>;
164 qcom,freq-domain = <&cpufreq_hw 1>;
165 power-domains = <&cpu_pd7>;
166 power-domain-names = "psci";
169 cpu-map {
207 idle-states {
208 entry-method = "psci";
210 little_cpu_sleep_0: cpu-sleep-0-0 {
211 compatible = "arm,idle-state";
212 idle-state-name = "silver-rail-power-collapse";
213 arm,psci-suspend-param = <0x40000003>;
214 entry-latency-us = <290>;
215 exit-latency-us = <376>;
216 min-residency-us = <1182>;
217 local-timer-stop;
220 big_cpu_sleep_0: cpu-sleep-1-0 {
221 compatible = "arm,idle-state";
222 idle-state-name = "gold-rail-power-collapse";
223 arm,psci-suspend-param = <0x40000003>;
224 entry-latency-us = <297>;
225 exit-latency-us = <324>;
226 min-residency-us = <1110>;
227 local-timer-stop;
231 domain-idle-states {
232 cluster_0_sleep_0: cluster-sleep-0-0 {
234 compatible = "domain-idle-state";
235 arm,psci-suspend-param = <0x40000022>;
236 entry-latency-us = <360>;
237 exit-latency-us = <421>;
238 min-residency-us = <782>;
241 cluster_0_sleep_1: cluster-sleep-0-1 {
243 compatible = "domain-idle-state";
244 arm,psci-suspend-param = <0x41000044>;
245 entry-latency-us = <800>;
246 exit-latency-us = <2118>;
247 min-residency-us = <7376>;
250 cluster_1_sleep_0: cluster-sleep-1-0 {
252 compatible = "domain-idle-state";
253 arm,psci-suspend-param = <0x40000042>;
254 entry-latency-us = <314>;
255 exit-latency-us = <345>;
256 min-residency-us = <660>;
259 cluster_1_sleep_1: cluster-sleep-1-1 {
261 compatible = "domain-idle-state";
262 arm,psci-suspend-param = <0x41000044>;
263 entry-latency-us = <640>;
264 exit-latency-us = <1654>;
265 min-residency-us = <8094>;
272 compatible = "qcom,scm-sm6115", "qcom,scm";
273 #reset-cells = <1>;
285 qup_opp_table: opp-table-qup {
286 compatible = "operating-points-v2";
288 opp-75000000 {
289 opp-hz = /bits/ 64 <75000000>;
290 required-opps = <&rpmpd_opp_low_svs>;
293 opp-100000000 {
294 opp-hz = /bits/ 64 <100000000>;
295 required-opps = <&rpmpd_opp_svs>;
298 opp-128000000 {
299 opp-hz = /bits/ 64 <128000000>;
300 required-opps = <&rpmpd_opp_nom>;
305 compatible = "arm,armv8-pmuv3";
310 compatible = "arm,psci-1.0";
313 cpu_pd0: power-domain-cpu0 {
314 #power-domain-cells = <0>;
315 power-domains = <&cluster_0_pd>;
316 domain-idle-states = <&little_cpu_sleep_0>;
319 cpu_pd1: power-domain-cpu1 {
320 #power-domain-cells = <0>;
321 power-domains = <&cluster_0_pd>;
322 domain-idle-states = <&little_cpu_sleep_0>;
325 cpu_pd2: power-domain-cpu2 {
326 #power-domain-cells = <0>;
327 power-domains = <&cluster_0_pd>;
328 domain-idle-states = <&little_cpu_sleep_0>;
331 cpu_pd3: power-domain-cpu3 {
332 #power-domain-cells = <0>;
333 power-domains = <&cluster_0_pd>;
334 domain-idle-states = <&little_cpu_sleep_0>;
337 cpu_pd4: power-domain-cpu4 {
338 #power-domain-cells = <0>;
339 power-domains = <&cluster_1_pd>;
340 domain-idle-states = <&big_cpu_sleep_0>;
343 cpu_pd5: power-domain-cpu5 {
344 #power-domain-cells = <0>;
345 power-domains = <&cluster_1_pd>;
346 domain-idle-states = <&big_cpu_sleep_0>;
349 cpu_pd6: power-domain-cpu6 {
350 #power-domain-cells = <0>;
351 power-domains = <&cluster_1_pd>;
352 domain-idle-states = <&big_cpu_sleep_0>;
355 cpu_pd7: power-domain-cpu7 {
356 #power-domain-cells = <0>;
357 power-domains = <&cluster_1_pd>;
358 domain-idle-states = <&big_cpu_sleep_0>;
361 cluster_0_pd: power-domain-cpu-cluster0 {
362 #power-domain-cells = <0>;
363 domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>;
366 cluster_1_pd: power-domain-cpu-cluster1 {
367 #power-domain-cells = <0>;
368 domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>;
373 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
375 glink-edge {
376 compatible = "qcom,glink-rpm";
379 qcom,rpm-msg-ram = <&rpm_msg_ram>;
382 rpm_requests: rpm-requests {
383 compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm";
384 qcom,glink-channels = "rpm_requests";
386 rpmcc: clock-controller {
387 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
389 clock-names = "xo";
390 #clock-cells = <1>;
393 rpmpd: power-controller {
394 compatible = "qcom,sm6115-rpmpd";
395 #power-domain-cells = <1>;
396 operating-points-v2 = <&rpmpd_opp_table>;
398 rpmpd_opp_table: opp-table {
399 compatible = "operating-points-v2";
402 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
406 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
410 opp-level = <RPM_SMD_LEVEL_SVS>;
414 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
418 opp-level = <RPM_SMD_LEVEL_NOM>;
422 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
426 opp-level = <RPM_SMD_LEVEL_TURBO>;
430 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
438 reserved_memory: reserved-memory {
439 #address-cells = <2>;
440 #size-cells = <2>;
445 no-map;
450 no-map;
455 no-map;
461 no-map;
464 qcom,rpm-msg-ram = <&rpm_msg_ram>;
469 no-map;
474 no-map;
479 no-map;
484 no-map;
489 no-map;
494 no-map;
499 no-map;
504 no-map;
509 no-map;
514 no-map;
519 no-map;
524 no-map;
528 compatible = "qcom,rmtfs-mem";
530 no-map;
532 qcom,client-id = <1>;
537 smp2p-adsp {
545 qcom,local-pid = <0>;
546 qcom,remote-pid = <2>;
548 adsp_smp2p_out: master-kernel {
549 qcom,entry-name = "master-kernel";
550 #qcom,smem-state-cells = <1>;
553 adsp_smp2p_in: slave-kernel {
554 qcom,entry-name = "slave-kernel";
556 interrupt-controller;
557 #interrupt-cells = <2>;
561 smp2p-cdsp {
569 qcom,local-pid = <0>;
570 qcom,remote-pid = <5>;
572 cdsp_smp2p_out: master-kernel {
573 qcom,entry-name = "master-kernel";
574 #qcom,smem-state-cells = <1>;
577 cdsp_smp2p_in: slave-kernel {
578 qcom,entry-name = "slave-kernel";
580 interrupt-controller;
581 #interrupt-cells = <2>;
585 smp2p-mpss {
593 qcom,local-pid = <0>;
594 qcom,remote-pid = <1>;
596 modem_smp2p_out: master-kernel {
597 qcom,entry-name = "master-kernel";
598 #qcom,smem-state-cells = <1>;
601 modem_smp2p_in: slave-kernel {
602 qcom,entry-name = "slave-kernel";
604 interrupt-controller;
605 #interrupt-cells = <2>;
610 compatible = "simple-bus";
611 #address-cells = <2>;
612 #size-cells = <2>;
614 dma-ranges = <0 0 0 0 0x10 0>;
617 compatible = "qcom,tcsr-mutex";
619 #hwlock-cells = <1>;
623 compatible = "qcom,sm6115-tcsr", "syscon";
628 compatible = "qcom,sm6115-tlmm";
632 reg-names = "west", "south", "east";
634 gpio-controller;
635 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
636 #gpio-cells = <2>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
640 qup_i2c0_default: qup-i2c0-default-state {
643 drive-strength = <2>;
644 bias-pull-up;
647 qup_i2c1_default: qup-i2c1-default-state {
650 drive-strength = <2>;
651 bias-pull-up;
654 qup_i2c2_default: qup-i2c2-default-state {
657 drive-strength = <2>;
658 bias-pull-up;
661 qup_i2c3_default: qup-i2c3-default-state {
664 drive-strength = <2>;
665 bias-pull-up;
668 qup_i2c4_default: qup-i2c4-default-state {
671 drive-strength = <2>;
672 bias-pull-up;
675 qup_i2c5_default: qup-i2c5-default-state {
678 drive-strength = <2>;
679 bias-pull-up;
682 qup_spi0_default: qup-spi0-default-state {
685 drive-strength = <2>;
686 bias-pull-up;
689 qup_spi1_default: qup-spi1-default-state {
692 drive-strength = <2>;
693 bias-pull-up;
696 qup_spi2_default: qup-spi2-default-state {
699 drive-strength = <2>;
700 bias-pull-up;
703 qup_spi3_default: qup-spi3-default-state {
706 drive-strength = <2>;
707 bias-pull-up;
710 qup_spi4_default: qup-spi4-default-state {
713 drive-strength = <2>;
714 bias-pull-up;
717 qup_spi5_default: qup-spi5-default-state {
720 drive-strength = <2>;
721 bias-pull-up;
724 sdc1_state_on: sdc1-on-state {
725 clk-pins {
727 bias-disable;
728 drive-strength = <16>;
731 cmd-pins {
733 bias-pull-up;
734 drive-strength = <10>;
737 data-pins {
739 bias-pull-up;
740 drive-strength = <10>;
743 rclk-pins {
745 bias-pull-down;
749 sdc1_state_off: sdc1-off-state {
750 clk-pins {
752 bias-disable;
753 drive-strength = <2>;
756 cmd-pins {
758 bias-pull-up;
759 drive-strength = <2>;
762 data-pins {
764 bias-pull-up;
765 drive-strength = <2>;
768 rclk-pins {
770 bias-pull-down;
774 sdc2_state_on: sdc2-on-state {
775 clk-pins {
777 bias-disable;
778 drive-strength = <16>;
781 cmd-pins {
783 bias-pull-up;
784 drive-strength = <10>;
787 data-pins {
789 bias-pull-up;
790 drive-strength = <10>;
794 sdc2_state_off: sdc2-off-state {
795 clk-pins {
797 bias-disable;
798 drive-strength = <2>;
801 cmd-pins {
803 bias-pull-up;
804 drive-strength = <2>;
807 data-pins {
809 bias-pull-up;
810 drive-strength = <2>;
816 compatible = "qcom,sm6115-lpass-lpi-pinctrl";
821 clock-names = "audio";
823 gpio-controller;
824 #gpio-cells = <2>;
825 gpio-ranges = <&lpass_tlmm 0 0 19>;
829 gcc: clock-controller@1400000 {
830 compatible = "qcom,gcc-sm6115";
833 clock-names = "bi_tcxo", "sleep_clk";
834 #clock-cells = <1>;
835 #reset-cells = <1>;
836 #power-domain-cells = <1>;
840 compatible = "qcom,sm6115-qusb2-phy";
842 #phy-cells = <0>;
845 clock-names = "cfg_ahb", "ref";
848 nvmem-cells = <&qusb2_hstx_trim>;
853 cryptobam: dma-controller@1b04000 {
854 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
858 clock-names = "bam_clk";
859 #dma-cells = <1>;
861 qcom,controlled-remotely;
870 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
873 clock-names = "core";
876 dma-names = "rx", "tx";
885 compatible = "qcom,sm6115-qmp-usb3-phy";
892 clock-names = "cfg_ahb",
899 reset-names = "phy", "phy_phy";
901 #clock-cells = <0>;
902 clock-output-names = "usb3_phy_pipe_clk_src";
904 #phy-cells = <0>;
905 orientation-switch;
907 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
912 #address-cells = <1>;
913 #size-cells = <0>;
926 remote-endpoint = <&usb_dwc3_ss>;
933 compatible = "qcom,sm6115-snoc";
939 clock-names = "cpu_axi",
943 #interconnect-cells = <2>;
945 clk_virt: interconnect-clk {
946 compatible = "qcom,sm6115-clk-virt";
947 #interconnect-cells = <2>;
950 mmrt_virt: interconnect-mmrt {
951 compatible = "qcom,sm6115-mmrt-virt";
952 #interconnect-cells = <2>;
955 mmnrt_virt: interconnect-mmnrt {
956 compatible = "qcom,sm6115-mmnrt-virt";
957 #interconnect-cells = <2>;
962 compatible = "qcom,sm6115-cnoc";
965 clock-names = "usb_axi";
966 #interconnect-cells = <2>;
970 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
972 #address-cells = <1>;
973 #size-cells = <1>;
975 qusb2_hstx_trim: hstx-trim@25b {
980 gpu_speed_bin: gpu-speed-bin@6006 {
987 compatible = "qcom,prng-ee";
990 clock-names = "core";
994 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
998 operating-points-v2 = <&cpu_bwmon_opp_table>;
1002 cpu_bwmon_opp_table: opp-table {
1003 compatible = "operating-points-v2";
1005 opp-0 {
1006 opp-peak-kBps = <(200 * 4 * 1000)>;
1009 opp-1 {
1010 opp-peak-kBps = <(300 * 4 * 1000)>;
1013 opp-2 {
1014 opp-peak-kBps = <(451 * 4 * 1000)>;
1017 opp-3 {
1018 opp-peak-kBps = <(547 * 4 * 1000)>;
1021 opp-4 {
1022 opp-peak-kBps = <(681 * 4 * 1000)>;
1025 opp-5 {
1026 opp-peak-kBps = <(768 * 4 * 1000)>;
1029 opp-6 {
1030 opp-peak-kBps = <(1017 * 4 * 1000)>;
1033 opp-7 {
1034 opp-peak-kBps = <(1353 * 4 * 1000)>;
1037 opp-8 {
1038 opp-peak-kBps = <(1555 * 4 * 1000)>;
1041 opp-9 {
1042 opp-peak-kBps = <(1804 * 4 * 1000)>;
1048 compatible = "qcom,spmi-pmic-arb";
1054 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1055 interrupt-names = "periph_irq";
1059 #address-cells = <2>;
1060 #size-cells = <0>;
1061 interrupt-controller;
1062 #interrupt-cells = <4>;
1065 tsens0: thermal-sensor@4411000 {
1066 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1072 interrupt-names = "uplow", "critical";
1073 #thermal-sensor-cells = <1>;
1077 compatible = "qcom,sm6115-bimc";
1079 #interconnect-cells = <2>;
1083 compatible = "qcom,rpm-msg-ram";
1088 compatible = "qcom,rpm-stats";
1093 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1097 reg-names = "hc", "cqhci", "ice";
1101 interrupt-names = "hc_irq", "pwr_irq";
1107 clock-names = "iface", "core", "xo", "ice";
1111 power-domains = <&rpmpd SM6115_VDDCX>;
1112 operating-points-v2 = <&sdhc1_opp_table>;
1118 interconnect-names = "sdhc-ddr",
1119 "cpu-sdhc";
1121 bus-width = <8>;
1124 sdhc1_opp_table: opp-table {
1125 compatible = "operating-points-v2";
1127 opp-100000000 {
1128 opp-hz = /bits/ 64 <100000000>;
1129 required-opps = <&rpmpd_opp_low_svs>;
1130 opp-peak-kBps = <250000 133320>;
1131 opp-avg-kBps = <102400 65000>;
1134 opp-192000000 {
1135 opp-hz = /bits/ 64 <192000000>;
1136 required-opps = <&rpmpd_opp_low_svs>;
1137 opp-peak-kBps = <800000 300000>;
1138 opp-avg-kBps = <204800 200000>;
1141 opp-384000000 {
1142 opp-hz = /bits/ 64 <384000000>;
1143 required-opps = <&rpmpd_opp_svs_plus>;
1144 opp-peak-kBps = <800000 300000>;
1145 opp-avg-kBps = <204800 200000>;
1151 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1153 reg-names = "hc";
1157 interrupt-names = "hc_irq", "pwr_irq";
1162 clock-names = "iface", "core", "xo";
1164 power-domains = <&rpmpd SM6115_VDDCX>;
1165 operating-points-v2 = <&sdhc2_opp_table>;
1172 interconnect-names = "sdhc-ddr",
1173 "cpu-sdhc";
1175 bus-width = <4>;
1176 qcom,dll-config = <0x0007642c>;
1177 qcom,ddr-config = <0x80040868>;
1180 sdhc2_opp_table: opp-table {
1181 compatible = "operating-points-v2";
1183 opp-100000000 {
1184 opp-hz = /bits/ 64 <100000000>;
1185 required-opps = <&rpmpd_opp_low_svs>;
1186 opp-peak-kBps = <250000 133320>;
1187 opp-avg-kBps = <261438 150000>;
1190 opp-202000000 {
1191 opp-hz = /bits/ 64 <202000000>;
1192 required-opps = <&rpmpd_opp_nom>;
1193 opp-peak-kBps = <800000 300000>;
1194 opp-avg-kBps = <261438 300000>;
1200 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1202 reg-names = "std", "ice";
1205 phy-names = "ufsphy";
1206 lanes-per-direction = <1>;
1207 #reset-cells = <1>;
1209 reset-names = "rst";
1211 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1222 clock-names = "core_clk",
1231 freq-table-hz = <50000000 200000000>,
1244 compatible = "qcom,sm6115-qmp-ufs-phy";
1250 clock-names = "ref",
1254 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1257 reset-names = "ufsphy";
1259 #phy-cells = <0>;
1264 gpi_dma0: dma-controller@4a00000 {
1265 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1277 dma-channels = <10>;
1278 dma-channel-mask = <0xf>;
1280 #dma-cells = <3>;
1285 compatible = "qcom,geni-se-qup";
1287 clock-names = "m-ahb", "s-ahb";
1290 #address-cells = <2>;
1291 #size-cells = <2>;
1297 compatible = "qcom,geni-i2c";
1299 clock-names = "se";
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&qup_i2c0_default>;
1306 dma-names = "tx", "rx";
1313 interconnect-names = "qup-core",
1314 "qup-config",
1315 "qup-memory";
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1322 compatible = "qcom,geni-spi";
1324 clock-names = "se";
1326 pinctrl-names = "default";
1327 pinctrl-0 = <&qup_spi0_default>;
1331 dma-names = "tx", "rx";
1338 interconnect-names = "qup-core",
1339 "qup-config",
1340 "qup-memory";
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1347 compatible = "qcom,geni-i2c";
1349 clock-names = "se";
1351 pinctrl-names = "default";
1352 pinctrl-0 = <&qup_i2c1_default>;
1356 dma-names = "tx", "rx";
1363 interconnect-names = "qup-core",
1364 "qup-config",
1365 "qup-memory";
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1372 compatible = "qcom,geni-spi";
1374 clock-names = "se";
1376 pinctrl-names = "default";
1377 pinctrl-0 = <&qup_spi1_default>;
1381 dma-names = "tx", "rx";
1388 interconnect-names = "qup-core",
1389 "qup-config",
1390 "qup-memory";
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1397 compatible = "qcom,geni-i2c";
1399 clock-names = "se";
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&qup_i2c2_default>;
1406 dma-names = "tx", "rx";
1413 interconnect-names = "qup-core",
1414 "qup-config",
1415 "qup-memory";
1416 #address-cells = <1>;
1417 #size-cells = <0>;
1422 compatible = "qcom,geni-spi";
1424 clock-names = "se";
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&qup_spi2_default>;
1431 dma-names = "tx", "rx";
1438 interconnect-names = "qup-core",
1439 "qup-config",
1440 "qup-memory";
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1447 compatible = "qcom,geni-i2c";
1449 clock-names = "se";
1451 pinctrl-names = "default";
1452 pinctrl-0 = <&qup_i2c3_default>;
1456 dma-names = "tx", "rx";
1463 interconnect-names = "qup-core",
1464 "qup-config",
1465 "qup-memory";
1466 #address-cells = <1>;
1467 #size-cells = <0>;
1472 compatible = "qcom,geni-spi";
1474 clock-names = "se";
1476 pinctrl-names = "default";
1477 pinctrl-0 = <&qup_spi3_default>;
1481 dma-names = "tx", "rx";
1488 interconnect-names = "qup-core",
1489 "qup-config",
1490 "qup-memory";
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1497 compatible = "qcom,geni-uart";
1499 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1501 clock-names = "se";
1502 power-domains = <&rpmpd SM6115_VDDCX>;
1503 operating-points-v2 = <&qup_opp_table>;
1508 interconnect-names = "qup-core",
1509 "qup-config";
1514 compatible = "qcom,geni-i2c";
1516 clock-names = "se";
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&qup_i2c4_default>;
1523 dma-names = "tx", "rx";
1530 interconnect-names = "qup-core",
1531 "qup-config",
1532 "qup-memory";
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1539 compatible = "qcom,geni-spi";
1541 clock-names = "se";
1543 pinctrl-names = "default";
1544 pinctrl-0 = <&qup_spi4_default>;
1548 dma-names = "tx", "rx";
1555 interconnect-names = "qup-core",
1556 "qup-config",
1557 "qup-memory";
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1564 compatible = "qcom,geni-debug-uart";
1566 clock-names = "se";
1573 interconnect-names = "qup-core",
1574 "qup-config";
1579 compatible = "qcom,geni-i2c";
1581 clock-names = "se";
1583 pinctrl-names = "default";
1584 pinctrl-0 = <&qup_i2c5_default>;
1588 dma-names = "tx", "rx";
1595 interconnect-names = "qup-core",
1596 "qup-config",
1597 "qup-memory";
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1604 compatible = "qcom,geni-spi";
1606 clock-names = "se";
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&qup_spi5_default>;
1613 dma-names = "tx", "rx";
1620 interconnect-names = "qup-core",
1621 "qup-config",
1622 "qup-memory";
1623 #address-cells = <1>;
1624 #size-cells = <0>;
1630 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1632 #address-cells = <2>;
1633 #size-cells = <2>;
1642 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1644 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1646 assigned-clock-rates = <19200000>, <66666667>;
1652 interrupt-names = "pwr_event",
1658 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1659 /* TODO: USB<->IPA path */
1664 interconnect-names = "usb-ddr",
1665 "apps-usb";
1674 phy-names = "usb2-phy", "usb3-phy";
1678 snps,has-lpm-erratum;
1679 snps,hird-threshold = /bits/ 8 <0x10>;
1681 snps,parkmode-disable-ss-quirk;
1683 usb-role-switch;
1686 #address-cells = <1>;
1687 #size-cells = <0>;
1700 remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1708 compatible = "qcom,adreno-610.0", "qcom,adreno";
1710 reg-names = "kgsl_3d0_reg_memory";
1719 clock-names = "core",
1729 operating-points-v2 = <&gpu_opp_table>;
1730 power-domains = <&rpmpd SM6115_VDDCX>;
1733 nvmem-cells = <&gpu_speed_bin>;
1734 nvmem-cell-names = "speed_bin";
1735 #cooling-cells = <2>;
1739 zap-shader {
1740 memory-region = <&pil_gpu_mem>;
1743 gpu_opp_table: opp-table {
1744 compatible = "operating-points-v2";
1746 opp-320000000 {
1747 opp-hz = /bits/ 64 <320000000>;
1748 required-opps = <&rpmpd_opp_low_svs>;
1749 opp-supported-hw = <0x1f>;
1752 opp-465000000 {
1753 opp-hz = /bits/ 64 <465000000>;
1754 required-opps = <&rpmpd_opp_svs>;
1755 opp-supported-hw = <0x1f>;
1758 opp-600000000 {
1759 opp-hz = /bits/ 64 <600000000>;
1760 required-opps = <&rpmpd_opp_svs_plus>;
1761 opp-supported-hw = <0x1f>;
1764 opp-745000000 {
1765 opp-hz = /bits/ 64 <745000000>;
1766 required-opps = <&rpmpd_opp_nom>;
1767 opp-supported-hw = <0xf>;
1770 opp-820000000 {
1771 opp-hz = /bits/ 64 <820000000>;
1772 required-opps = <&rpmpd_opp_nom_plus>;
1773 opp-supported-hw = <0x7>;
1776 opp-900000000 {
1777 opp-hz = /bits/ 64 <900000000>;
1778 required-opps = <&rpmpd_opp_turbo>;
1779 opp-supported-hw = <0x7>;
1783 opp-950000000 {
1784 opp-hz = /bits/ 64 <950000000>;
1785 required-opps = <&rpmpd_opp_turbo_plus>;
1786 opp-supported-hw = <0x4>;
1789 opp-980000000 {
1790 opp-hz = /bits/ 64 <980000000>;
1791 required-opps = <&rpmpd_opp_turbo_plus>;
1792 opp-supported-hw = <0x3>;
1798 compatible = "qcom,adreno-gmu-wrapper";
1800 reg-names = "gmu";
1801 power-domains = <&gpucc GPU_CX_GDSC>,
1803 power-domain-names = "cx", "gx";
1806 gpucc: clock-controller@5990000 {
1807 compatible = "qcom,sm6115-gpucc";
1812 #clock-cells = <1>;
1813 #reset-cells = <1>;
1814 #power-domain-cells = <1>;
1818 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1819 "qcom,smmu-500", "arm,mmu-500";
1834 clock-names = "mem",
1837 power-domains = <&gpucc GPU_CX_GDSC>;
1839 #global-interrupts = <1>;
1840 #iommu-cells = <2>;
1843 mdss: display-subsystem@5e00000 {
1844 compatible = "qcom,sm6115-mdss";
1846 reg-names = "mdss";
1848 power-domains = <&dispcc MDSS_GDSC>;
1855 interrupt-controller;
1856 #interrupt-cells = <1>;
1865 interconnect-names = "mdp0-mem",
1866 "cpu-cfg";
1868 #address-cells = <2>;
1869 #size-cells = <2>;
1874 mdp: display-controller@5e01000 {
1875 compatible = "qcom,sm6115-dpu";
1878 reg-names = "mdp", "vbif";
1886 clock-names = "bus",
1893 operating-points-v2 = <&mdp_opp_table>;
1894 power-domains = <&rpmpd SM6115_VDDCX>;
1896 interrupt-parent = <&mdss>;
1900 #address-cells = <1>;
1901 #size-cells = <0>;
1906 remote-endpoint = <&mdss_dsi0_in>;
1911 mdp_opp_table: opp-table {
1912 compatible = "operating-points-v2";
1914 opp-19200000 {
1915 opp-hz = /bits/ 64 <19200000>;
1916 required-opps = <&rpmpd_opp_min_svs>;
1919 opp-192000000 {
1920 opp-hz = /bits/ 64 <192000000>;
1921 required-opps = <&rpmpd_opp_low_svs>;
1924 opp-256000000 {
1925 opp-hz = /bits/ 64 <256000000>;
1926 required-opps = <&rpmpd_opp_svs>;
1929 opp-307200000 {
1930 opp-hz = /bits/ 64 <307200000>;
1931 required-opps = <&rpmpd_opp_svs_plus>;
1934 opp-384000000 {
1935 opp-hz = /bits/ 64 <384000000>;
1936 required-opps = <&rpmpd_opp_nom>;
1942 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1944 reg-names = "dsi_ctrl";
1946 interrupt-parent = <&mdss>;
1955 clock-names = "byte",
1962 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1964 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1967 operating-points-v2 = <&dsi_opp_table>;
1968 power-domains = <&rpmpd SM6115_VDDCX>;
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1977 #address-cells = <1>;
1978 #size-cells = <0>;
1983 remote-endpoint = <&dpu_intf1_out>;
1994 dsi_opp_table: opp-table {
1995 compatible = "operating-points-v2";
1997 opp-19200000 {
1998 opp-hz = /bits/ 64 <19200000>;
1999 required-opps = <&rpmpd_opp_min_svs>;
2002 opp-164000000 {
2003 opp-hz = /bits/ 64 <164000000>;
2004 required-opps = <&rpmpd_opp_low_svs>;
2007 opp-187500000 {
2008 opp-hz = /bits/ 64 <187500000>;
2009 required-opps = <&rpmpd_opp_svs>;
2015 compatible = "qcom,dsi-phy-14nm-2290";
2019 reg-names = "dsi_phy",
2023 #clock-cells = <1>;
2024 #phy-cells = <0>;
2028 clock-names = "iface", "ref";
2034 dispcc: clock-controller@5f00000 {
2035 compatible = "qcom,sm6115-dispcc";
2042 #clock-cells = <1>;
2043 #reset-cells = <1>;
2044 #power-domain-cells = <1>;
2048 compatible = "qcom,sm6115-mpss-pas";
2051 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
2057 interrupt-names = "wdog", "fatal", "ready", "handover",
2058 "stop-ack", "shutdown-ack";
2061 clock-names = "xo";
2063 power-domains = <&rpmpd SM6115_VDDCX>;
2065 memory-region = <&pil_modem_mem>;
2067 qcom,smem-states = <&modem_smp2p_out 0>;
2068 qcom,smem-state-names = "stop";
2072 glink-edge {
2075 qcom,remote-pid = <1>;
2081 compatible = "arm,coresight-stm", "arm,primecell";
2084 reg-names = "stm-base", "stm-stimulus-base";
2087 clock-names = "apb_pclk";
2091 out-ports {
2094 remote-endpoint = <&funnel_in0_in>;
2101 compatible = "arm,coresight-cti", "arm,primecell";
2105 clock-names = "apb_pclk";
2111 compatible = "arm,coresight-cti", "arm,primecell";
2115 clock-names = "apb_pclk";
2121 compatible = "arm,coresight-cti", "arm,primecell";
2125 clock-names = "apb_pclk";
2131 compatible = "arm,coresight-cti", "arm,primecell";
2135 clock-names = "apb_pclk";
2141 compatible = "arm,coresight-cti", "arm,primecell";
2145 clock-names = "apb_pclk";
2151 compatible = "arm,coresight-cti", "arm,primecell";
2155 clock-names = "apb_pclk";
2161 compatible = "arm,coresight-cti", "arm,primecell";
2165 clock-names = "apb_pclk";
2171 compatible = "arm,coresight-cti", "arm,primecell";
2175 clock-names = "apb_pclk";
2181 compatible = "arm,coresight-cti", "arm,primecell";
2185 clock-names = "apb_pclk";
2191 compatible = "arm,coresight-cti", "arm,primecell";
2195 clock-names = "apb_pclk";
2201 compatible = "arm,coresight-cti", "arm,primecell";
2205 clock-names = "apb_pclk";
2211 compatible = "arm,coresight-cti", "arm,primecell";
2215 clock-names = "apb_pclk";
2221 compatible = "arm,coresight-cti", "arm,primecell";
2225 clock-names = "apb_pclk";
2231 compatible = "arm,coresight-cti", "arm,primecell";
2235 clock-names = "apb_pclk";
2241 compatible = "arm,coresight-cti", "arm,primecell";
2245 clock-names = "apb_pclk";
2251 compatible = "arm,coresight-cti", "arm,primecell";
2255 clock-names = "apb_pclk";
2261 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2265 clock-names = "apb_pclk";
2269 out-ports {
2272 remote-endpoint = <&etr_in>;
2277 in-ports {
2280 remote-endpoint = <&etf_out>;
2287 compatible = "arm,coresight-tmc", "arm,primecell";
2291 clock-names = "apb_pclk";
2295 in-ports {
2298 remote-endpoint = <&merge_funnel_out>;
2303 out-ports {
2306 remote-endpoint = <&replicator_in>;
2313 compatible = "arm,coresight-tmc", "arm,primecell";
2317 clock-names = "apb_pclk";
2321 in-ports {
2324 remote-endpoint = <&replicator_out>;
2331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2335 clock-names = "apb_pclk";
2339 out-ports {
2342 remote-endpoint = <&merge_funnel_in0>;
2347 in-ports {
2350 remote-endpoint = <&stm_out>;
2357 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2361 clock-names = "apb_pclk";
2365 out-ports {
2368 remote-endpoint = <&merge_funnel_in1>;
2373 in-ports {
2376 remote-endpoint = <&funnel_apss1_out>;
2383 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2387 clock-names = "apb_pclk";
2391 out-ports {
2394 remote-endpoint = <&etf_in>;
2399 in-ports {
2400 #address-cells = <1>;
2401 #size-cells = <0>;
2406 remote-endpoint = <&funnel_in0_out>;
2413 remote-endpoint = <&funnel_in1_out>;
2420 compatible = "arm,coresight-etm4x", "arm,primecell";
2424 clock-names = "apb_pclk";
2425 arm,coresight-loses-context-with-cpu;
2431 out-ports {
2434 remote-endpoint = <&funnel_apss0_in0>;
2441 compatible = "arm,coresight-etm4x", "arm,primecell";
2445 clock-names = "apb_pclk";
2446 arm,coresight-loses-context-with-cpu;
2452 out-ports {
2455 remote-endpoint = <&funnel_apss0_in1>;
2462 compatible = "arm,coresight-etm4x", "arm,primecell";
2466 clock-names = "apb_pclk";
2467 arm,coresight-loses-context-with-cpu;
2473 out-ports {
2476 remote-endpoint = <&funnel_apss0_in2>;
2483 compatible = "arm,coresight-etm4x", "arm,primecell";
2487 clock-names = "apb_pclk";
2488 arm,coresight-loses-context-with-cpu;
2494 out-ports {
2497 remote-endpoint = <&funnel_apss0_in3>;
2504 compatible = "arm,coresight-etm4x", "arm,primecell";
2508 clock-names = "apb_pclk";
2509 arm,coresight-loses-context-with-cpu;
2515 out-ports {
2518 remote-endpoint = <&funnel_apss0_in4>;
2525 compatible = "arm,coresight-etm4x", "arm,primecell";
2529 clock-names = "apb_pclk";
2530 arm,coresight-loses-context-with-cpu;
2536 out-ports {
2539 remote-endpoint = <&funnel_apss0_in5>;
2546 compatible = "arm,coresight-etm4x", "arm,primecell";
2550 clock-names = "apb_pclk";
2551 arm,coresight-loses-context-with-cpu;
2557 out-ports {
2560 remote-endpoint = <&funnel_apss0_in6>;
2567 compatible = "arm,coresight-etm4x", "arm,primecell";
2571 clock-names = "apb_pclk";
2572 arm,coresight-loses-context-with-cpu;
2578 out-ports {
2581 remote-endpoint = <&funnel_apss0_in7>;
2588 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2592 clock-names = "apb_pclk";
2596 out-ports {
2599 remote-endpoint = <&funnel_apss1_in>;
2604 in-ports {
2605 #address-cells = <1>;
2606 #size-cells = <0>;
2611 remote-endpoint = <&etm0_out>;
2618 remote-endpoint = <&etm1_out>;
2625 remote-endpoint = <&etm2_out>;
2632 remote-endpoint = <&etm3_out>;
2639 remote-endpoint = <&etm4_out>;
2646 remote-endpoint = <&etm5_out>;
2653 remote-endpoint = <&etm6_out>;
2660 remote-endpoint = <&etm7_out>;
2667 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2671 clock-names = "apb_pclk";
2675 out-ports {
2678 remote-endpoint = <&funnel_in1_in>;
2683 in-ports {
2686 remote-endpoint = <&funnel_apss0_out>;
2693 compatible = "qcom,sm6115-adsp-pas";
2696 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2701 interrupt-names = "wdog", "fatal", "ready",
2702 "handover", "stop-ack";
2705 clock-names = "xo";
2707 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2710 memory-region = <&pil_adsp_mem>;
2712 qcom,smem-states = <&adsp_smp2p_out 0>;
2713 qcom,smem-state-names = "stop";
2717 glink-edge {
2720 qcom,remote-pid = <2>;
2724 compatible = "qcom,apr-v2";
2725 qcom,glink-channels = "apr_audio_svc";
2727 #address-cells = <1>;
2728 #size-cells = <0>;
2733 qcom,protection-domain = "avs/audio",
2740 qcom,protection-domain = "avs/audio",
2743 compatible = "qcom,q6afe-dais";
2744 #address-cells = <1>;
2745 #size-cells = <0>;
2746 #sound-dai-cells = <1>;
2749 q6afecc: clock-controller {
2750 compatible = "qcom,q6afe-clocks";
2751 #clock-cells = <2>;
2758 qcom,protection-domain = "avs/audio",
2761 compatible = "qcom,q6asm-dais";
2762 #address-cells = <1>;
2763 #size-cells = <0>;
2764 #sound-dai-cells = <1>;
2784 qcom,protection-domain = "avs/audio",
2787 compatible = "qcom,q6adm-routing";
2788 #sound-dai-cells = <0>;
2795 qcom,glink-channels = "fastrpcglink-apps-dsp";
2797 qcom,non-secure-domain;
2798 #address-cells = <1>;
2799 #size-cells = <0>;
2801 compute-cb@3 {
2802 compatible = "qcom,fastrpc-compute-cb";
2807 compute-cb@4 {
2808 compatible = "qcom,fastrpc-compute-cb";
2813 compute-cb@5 {
2814 compatible = "qcom,fastrpc-compute-cb";
2819 compute-cb@6 {
2820 compatible = "qcom,fastrpc-compute-cb";
2825 compute-cb@7 {
2826 compatible = "qcom,fastrpc-compute-cb";
2835 compatible = "qcom,sm6115-cdsp-pas";
2838 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2843 interrupt-names = "wdog", "fatal", "ready",
2844 "handover", "stop-ack";
2847 clock-names = "xo";
2849 power-domains = <&rpmpd SM6115_VDDCX>;
2851 memory-region = <&pil_cdsp_mem>;
2853 qcom,smem-states = <&cdsp_smp2p_out 0>;
2854 qcom,smem-state-names = "stop";
2858 glink-edge {
2861 qcom,remote-pid = <5>;
2866 qcom,glink-channels = "fastrpcglink-apps-dsp";
2868 qcom,non-secure-domain;
2869 #address-cells = <1>;
2870 #size-cells = <0>;
2872 compute-cb@1 {
2873 compatible = "qcom,fastrpc-compute-cb";
2878 compute-cb@2 {
2879 compatible = "qcom,fastrpc-compute-cb";
2884 compute-cb@3 {
2885 compatible = "qcom,fastrpc-compute-cb";
2890 compute-cb@4 {
2891 compatible = "qcom,fastrpc-compute-cb";
2896 compute-cb@5 {
2897 compatible = "qcom,fastrpc-compute-cb";
2902 compute-cb@6 {
2903 compatible = "qcom,fastrpc-compute-cb";
2914 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2916 #iommu-cells = <2>;
2917 #global-interrupts = <1>;
2987 compatible = "qcom,wcn3990-wifi";
2989 reg-names = "membase";
2990 memory-region = <&wlan_msa_mem>;
3004 qcom,msa-fixed-perm;
3009 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
3016 compatible = "qcom,sm6115-apcs-hmss-global",
3017 "qcom,msm8994-apcs-kpss-global";
3020 #mbox-cells = <1>;
3024 compatible = "arm,armv7-timer-mem";
3026 #address-cells = <2>;
3027 #size-cells = <1>;
3029 clock-frequency = <19200000>;
3033 frame-number = <0>;
3040 frame-number = <1>;
3047 frame-number = <2>;
3054 frame-number = <3>;
3061 frame-number = <4>;
3068 frame-number = <5>;
3075 frame-number = <6>;
3081 intc: interrupt-controller@f200000 {
3082 compatible = "arm,gic-v3";
3085 #interrupt-cells = <3>;
3086 interrupt-controller;
3087 interrupt-parent = <&intc>;
3088 #redistributor-regions = <1>;
3089 redistributor-stride = <0x0 0x20000>;
3094 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
3098 reg-names = "freq-domain0", "freq-domain1";
3100 clock-names = "xo", "alternate";
3102 #freq-domain-cells = <1>;
3103 #clock-cells = <1>;
3107 thermal-zones {
3108 mapss-thermal {
3109 thermal-sensors = <&tsens0 0>;
3112 trip-point0 {
3118 trip-point1 {
3126 cdsp-hvx-thermal {
3127 thermal-sensors = <&tsens0 1>;
3130 trip-point0 {
3136 trip-point1 {
3144 wlan-thermal {
3145 thermal-sensors = <&tsens0 2>;
3148 trip-point0 {
3154 trip-point1 {
3162 camera-thermal {
3163 thermal-sensors = <&tsens0 3>;
3166 trip-point0 {
3172 trip-point1 {
3180 video-thermal {
3181 thermal-sensors = <&tsens0 4>;
3184 trip-point0 {
3190 trip-point1 {
3198 modem1-thermal {
3199 thermal-sensors = <&tsens0 5>;
3202 trip-point0 {
3208 trip-point1 {
3216 cpu4-thermal {
3217 thermal-sensors = <&tsens0 6>;
3220 cpu4_alert0: trip-point0 {
3226 cpu4_alert1: trip-point1 {
3232 cpu4_crit: cpu-crit {
3240 cpu5-thermal {
3241 thermal-sensors = <&tsens0 7>;
3244 cpu5_alert0: trip-point0 {
3250 cpu5_alert1: trip-point1 {
3256 cpu5_crit: cpu-crit {
3264 cpu6-thermal {
3265 thermal-sensors = <&tsens0 8>;
3268 cpu6_alert0: trip-point0 {
3274 cpu6_alert1: trip-point1 {
3280 cpu6_crit: cpu-crit {
3288 cpu7-thermal {
3289 thermal-sensors = <&tsens0 9>;
3292 cpu7_alert0: trip-point0 {
3298 cpu7_alert1: trip-point1 {
3304 cpu7_crit: cpu-crit {
3312 cpu45-thermal {
3313 thermal-sensors = <&tsens0 10>;
3316 cpu45_alert0: trip-point0 {
3322 cpu45_alert1: trip-point1 {
3328 cpu45_crit: cpu-crit {
3336 cpu67-thermal {
3337 thermal-sensors = <&tsens0 11>;
3340 cpu67_alert0: trip-point0 {
3346 cpu67_alert1: trip-point1 {
3352 cpu67_crit: cpu-crit {
3360 cpu0123-thermal {
3361 thermal-sensors = <&tsens0 12>;
3364 cpu0123_alert0: trip-point0 {
3370 cpu0123_alert1: trip-point1 {
3376 cpu0123_crit: cpu-crit {
3384 modem0-thermal {
3385 thermal-sensors = <&tsens0 13>;
3388 trip-point0 {
3394 trip-point1 {
3402 display-thermal {
3403 thermal-sensors = <&tsens0 14>;
3406 trip-point0 {
3412 trip-point1 {
3420 gpu-thermal {
3421 polling-delay-passive = <250>;
3423 thermal-sensors = <&tsens0 15>;
3425 cooling-maps {
3428 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3433 gpu_alert0: trip-point0 {
3439 trip-point1 {
3449 compatible = "arm,armv8-timer";