Lines Matching +full:sdm845 +full:- +full:ipa
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/soc/qcom,apr.h>
18 #include <dt-bindings/sound/qcom,q6asm.h>
19 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
20 #include <dt-bindings/thermal/thermal.h>
23 interrupt-parent = <&intc>;
25 #address-cells = <2>;
26 #size-cells = <2>;
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
43 #address-cells = <2>;
44 #size-cells = <0>;
51 capacity-dmips-mhz = <1024>;
52 dynamic-power-coefficient = <100>;
53 enable-method = "psci";
54 next-level-cache = <&l2_0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
56 power-domains = <&cpu_pd0>;
57 power-domain-names = "psci";
58 l2_0: l2-cache {
60 cache-level = <2>;
61 cache-unified;
70 capacity-dmips-mhz = <1024>;
71 dynamic-power-coefficient = <100>;
72 enable-method = "psci";
73 next-level-cache = <&l2_0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
75 power-domains = <&cpu_pd1>;
76 power-domain-names = "psci";
84 capacity-dmips-mhz = <1024>;
85 dynamic-power-coefficient = <100>;
86 enable-method = "psci";
87 next-level-cache = <&l2_0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
89 power-domains = <&cpu_pd2>;
90 power-domain-names = "psci";
98 capacity-dmips-mhz = <1024>;
99 dynamic-power-coefficient = <100>;
100 enable-method = "psci";
101 next-level-cache = <&l2_0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 power-domains = <&cpu_pd3>;
104 power-domain-names = "psci";
112 enable-method = "psci";
113 capacity-dmips-mhz = <1638>;
114 dynamic-power-coefficient = <282>;
115 next-level-cache = <&l2_1>;
116 qcom,freq-domain = <&cpufreq_hw 1>;
117 power-domains = <&cpu_pd4>;
118 power-domain-names = "psci";
119 l2_1: l2-cache {
121 cache-level = <2>;
122 cache-unified;
131 capacity-dmips-mhz = <1638>;
132 dynamic-power-coefficient = <282>;
133 enable-method = "psci";
134 next-level-cache = <&l2_1>;
135 qcom,freq-domain = <&cpufreq_hw 1>;
136 power-domains = <&cpu_pd5>;
137 power-domain-names = "psci";
145 capacity-dmips-mhz = <1638>;
146 dynamic-power-coefficient = <282>;
147 enable-method = "psci";
148 next-level-cache = <&l2_1>;
149 qcom,freq-domain = <&cpufreq_hw 1>;
150 power-domains = <&cpu_pd6>;
151 power-domain-names = "psci";
159 capacity-dmips-mhz = <1638>;
160 dynamic-power-coefficient = <282>;
161 enable-method = "psci";
162 next-level-cache = <&l2_1>;
163 qcom,freq-domain = <&cpufreq_hw 1>;
164 power-domains = <&cpu_pd7>;
165 power-domain-names = "psci";
168 cpu-map {
206 idle-states {
207 entry-method = "psci";
209 little_cpu_sleep_0: cpu-sleep-0-0 {
210 compatible = "arm,idle-state";
211 idle-state-name = "silver-rail-power-collapse";
212 arm,psci-suspend-param = <0x40000003>;
213 entry-latency-us = <290>;
214 exit-latency-us = <376>;
215 min-residency-us = <1182>;
216 local-timer-stop;
219 big_cpu_sleep_0: cpu-sleep-1-0 {
220 compatible = "arm,idle-state";
221 idle-state-name = "gold-rail-power-collapse";
222 arm,psci-suspend-param = <0x40000003>;
223 entry-latency-us = <297>;
224 exit-latency-us = <324>;
225 min-residency-us = <1110>;
226 local-timer-stop;
230 domain-idle-states {
231 cluster_0_sleep_0: cluster-sleep-0-0 {
233 compatible = "domain-idle-state";
234 arm,psci-suspend-param = <0x40000022>;
235 entry-latency-us = <360>;
236 exit-latency-us = <421>;
237 min-residency-us = <782>;
240 cluster_0_sleep_1: cluster-sleep-0-1 {
242 compatible = "domain-idle-state";
243 arm,psci-suspend-param = <0x41000044>;
244 entry-latency-us = <800>;
245 exit-latency-us = <2118>;
246 min-residency-us = <7376>;
249 cluster_1_sleep_0: cluster-sleep-1-0 {
251 compatible = "domain-idle-state";
252 arm,psci-suspend-param = <0x40000042>;
253 entry-latency-us = <314>;
254 exit-latency-us = <345>;
255 min-residency-us = <660>;
258 cluster_1_sleep_1: cluster-sleep-1-1 {
260 compatible = "domain-idle-state";
261 arm,psci-suspend-param = <0x41000044>;
262 entry-latency-us = <640>;
263 exit-latency-us = <1654>;
264 min-residency-us = <8094>;
271 compatible = "qcom,scm-sm6115", "qcom,scm";
272 #reset-cells = <1>;
284 qup_opp_table: opp-table-qup {
285 compatible = "operating-points-v2";
287 opp-75000000 {
288 opp-hz = /bits/ 64 <75000000>;
289 required-opps = <&rpmpd_opp_low_svs>;
292 opp-100000000 {
293 opp-hz = /bits/ 64 <100000000>;
294 required-opps = <&rpmpd_opp_svs>;
297 opp-128000000 {
298 opp-hz = /bits/ 64 <128000000>;
299 required-opps = <&rpmpd_opp_nom>;
304 compatible = "arm,armv8-pmuv3";
309 compatible = "arm,psci-1.0";
312 cpu_pd0: power-domain-cpu0 {
313 #power-domain-cells = <0>;
314 power-domains = <&cluster_0_pd>;
315 domain-idle-states = <&little_cpu_sleep_0>;
318 cpu_pd1: power-domain-cpu1 {
319 #power-domain-cells = <0>;
320 power-domains = <&cluster_0_pd>;
321 domain-idle-states = <&little_cpu_sleep_0>;
324 cpu_pd2: power-domain-cpu2 {
325 #power-domain-cells = <0>;
326 power-domains = <&cluster_0_pd>;
327 domain-idle-states = <&little_cpu_sleep_0>;
330 cpu_pd3: power-domain-cpu3 {
331 #power-domain-cells = <0>;
332 power-domains = <&cluster_0_pd>;
333 domain-idle-states = <&little_cpu_sleep_0>;
336 cpu_pd4: power-domain-cpu4 {
337 #power-domain-cells = <0>;
338 power-domains = <&cluster_1_pd>;
339 domain-idle-states = <&big_cpu_sleep_0>;
342 cpu_pd5: power-domain-cpu5 {
343 #power-domain-cells = <0>;
344 power-domains = <&cluster_1_pd>;
345 domain-idle-states = <&big_cpu_sleep_0>;
348 cpu_pd6: power-domain-cpu6 {
349 #power-domain-cells = <0>;
350 power-domains = <&cluster_1_pd>;
351 domain-idle-states = <&big_cpu_sleep_0>;
354 cpu_pd7: power-domain-cpu7 {
355 #power-domain-cells = <0>;
356 power-domains = <&cluster_1_pd>;
357 domain-idle-states = <&big_cpu_sleep_0>;
360 cluster_0_pd: power-domain-cpu-cluster0 {
361 #power-domain-cells = <0>;
362 domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>;
365 cluster_1_pd: power-domain-cpu-cluster1 {
366 #power-domain-cells = <0>;
367 domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>;
372 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
374 glink-edge {
375 compatible = "qcom,glink-rpm";
378 qcom,rpm-msg-ram = <&rpm_msg_ram>;
381 rpm_requests: rpm-requests {
382 compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm";
383 qcom,glink-channels = "rpm_requests";
385 rpmcc: clock-controller {
386 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
388 clock-names = "xo";
389 #clock-cells = <1>;
392 rpmpd: power-controller {
393 compatible = "qcom,sm6115-rpmpd";
394 #power-domain-cells = <1>;
395 operating-points-v2 = <&rpmpd_opp_table>;
397 rpmpd_opp_table: opp-table {
398 compatible = "operating-points-v2";
401 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
405 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
409 opp-level = <RPM_SMD_LEVEL_SVS>;
413 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
417 opp-level = <RPM_SMD_LEVEL_NOM>;
421 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
425 opp-level = <RPM_SMD_LEVEL_TURBO>;
429 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
437 reserved_memory: reserved-memory {
438 #address-cells = <2>;
439 #size-cells = <2>;
444 no-map;
449 no-map;
454 no-map;
460 no-map;
463 qcom,rpm-msg-ram = <&rpm_msg_ram>;
468 no-map;
473 no-map;
478 no-map;
483 no-map;
488 no-map;
493 no-map;
498 no-map;
503 no-map;
508 no-map;
513 no-map;
518 no-map;
523 no-map;
527 compatible = "qcom,rmtfs-mem";
529 no-map;
531 qcom,client-id = <1>;
536 smp2p-adsp {
544 qcom,local-pid = <0>;
545 qcom,remote-pid = <2>;
547 adsp_smp2p_out: master-kernel {
548 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells = <1>;
552 adsp_smp2p_in: slave-kernel {
553 qcom,entry-name = "slave-kernel";
555 interrupt-controller;
556 #interrupt-cells = <2>;
560 smp2p-cdsp {
568 qcom,local-pid = <0>;
569 qcom,remote-pid = <5>;
571 cdsp_smp2p_out: master-kernel {
572 qcom,entry-name = "master-kernel";
573 #qcom,smem-state-cells = <1>;
576 cdsp_smp2p_in: slave-kernel {
577 qcom,entry-name = "slave-kernel";
579 interrupt-controller;
580 #interrupt-cells = <2>;
584 smp2p-mpss {
592 qcom,local-pid = <0>;
593 qcom,remote-pid = <1>;
595 modem_smp2p_out: master-kernel {
596 qcom,entry-name = "master-kernel";
597 #qcom,smem-state-cells = <1>;
600 modem_smp2p_in: slave-kernel {
601 qcom,entry-name = "slave-kernel";
603 interrupt-controller;
604 #interrupt-cells = <2>;
609 compatible = "simple-bus";
610 #address-cells = <2>;
611 #size-cells = <2>;
613 dma-ranges = <0 0 0 0 0x10 0>;
616 compatible = "qcom,tcsr-mutex";
618 #hwlock-cells = <1>;
622 compatible = "qcom,sm6115-tcsr", "syscon";
627 compatible = "qcom,sm6115-tlmm";
631 reg-names = "west", "south", "east";
633 gpio-controller;
634 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
635 #gpio-cells = <2>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
639 qup_i2c0_default: qup-i2c0-default-state {
642 drive-strength = <2>;
643 bias-pull-up;
646 qup_i2c1_default: qup-i2c1-default-state {
649 drive-strength = <2>;
650 bias-pull-up;
653 qup_i2c2_default: qup-i2c2-default-state {
656 drive-strength = <2>;
657 bias-pull-up;
660 qup_i2c3_default: qup-i2c3-default-state {
663 drive-strength = <2>;
664 bias-pull-up;
667 qup_i2c4_default: qup-i2c4-default-state {
670 drive-strength = <2>;
671 bias-pull-up;
674 qup_i2c5_default: qup-i2c5-default-state {
677 drive-strength = <2>;
678 bias-pull-up;
681 qup_spi0_default: qup-spi0-default-state {
684 drive-strength = <2>;
685 bias-pull-up;
688 qup_spi1_default: qup-spi1-default-state {
691 drive-strength = <2>;
692 bias-pull-up;
695 qup_spi2_default: qup-spi2-default-state {
698 drive-strength = <2>;
699 bias-pull-up;
702 qup_spi3_default: qup-spi3-default-state {
705 drive-strength = <2>;
706 bias-pull-up;
709 qup_spi4_default: qup-spi4-default-state {
712 drive-strength = <2>;
713 bias-pull-up;
716 qup_spi5_default: qup-spi5-default-state {
719 drive-strength = <2>;
720 bias-pull-up;
723 sdc1_state_on: sdc1-on-state {
724 clk-pins {
726 bias-disable;
727 drive-strength = <16>;
730 cmd-pins {
732 bias-pull-up;
733 drive-strength = <10>;
736 data-pins {
738 bias-pull-up;
739 drive-strength = <10>;
742 rclk-pins {
744 bias-pull-down;
748 sdc1_state_off: sdc1-off-state {
749 clk-pins {
751 bias-disable;
752 drive-strength = <2>;
755 cmd-pins {
757 bias-pull-up;
758 drive-strength = <2>;
761 data-pins {
763 bias-pull-up;
764 drive-strength = <2>;
767 rclk-pins {
769 bias-pull-down;
773 sdc2_state_on: sdc2-on-state {
774 clk-pins {
776 bias-disable;
777 drive-strength = <16>;
780 cmd-pins {
782 bias-pull-up;
783 drive-strength = <10>;
786 data-pins {
788 bias-pull-up;
789 drive-strength = <10>;
793 sdc2_state_off: sdc2-off-state {
794 clk-pins {
796 bias-disable;
797 drive-strength = <2>;
800 cmd-pins {
802 bias-pull-up;
803 drive-strength = <2>;
806 data-pins {
808 bias-pull-up;
809 drive-strength = <2>;
815 compatible = "qcom,sm6115-lpass-lpi-pinctrl";
820 clock-names = "audio";
822 gpio-controller;
823 #gpio-cells = <2>;
824 gpio-ranges = <&lpass_tlmm 0 0 19>;
828 gcc: clock-controller@1400000 {
829 compatible = "qcom,gcc-sm6115";
832 clock-names = "bi_tcxo", "sleep_clk";
833 #clock-cells = <1>;
834 #reset-cells = <1>;
835 #power-domain-cells = <1>;
839 compatible = "qcom,sm6115-qusb2-phy";
841 #phy-cells = <0>;
844 clock-names = "cfg_ahb", "ref";
847 nvmem-cells = <&qusb2_hstx_trim>;
852 cryptobam: dma-controller@1b04000 {
853 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
857 clock-names = "bam_clk";
858 #dma-cells = <1>;
860 qcom,controlled-remotely;
869 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
872 clock-names = "core";
875 dma-names = "rx", "tx";
884 compatible = "qcom,sm6115-qmp-usb3-phy";
891 clock-names = "cfg_ahb",
898 reset-names = "phy", "phy_phy";
900 #clock-cells = <0>;
901 clock-output-names = "usb3_phy_pipe_clk_src";
903 #phy-cells = <0>;
904 orientation-switch;
906 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
911 #address-cells = <1>;
912 #size-cells = <0>;
925 remote-endpoint = <&usb_dwc3_ss>;
932 compatible = "qcom,sm6115-snoc";
938 clock-names = "cpu_axi",
941 "ipa";
942 #interconnect-cells = <2>;
944 clk_virt: interconnect-clk {
945 compatible = "qcom,sm6115-clk-virt";
946 #interconnect-cells = <2>;
949 mmrt_virt: interconnect-mmrt {
950 compatible = "qcom,sm6115-mmrt-virt";
951 #interconnect-cells = <2>;
954 mmnrt_virt: interconnect-mmnrt {
955 compatible = "qcom,sm6115-mmnrt-virt";
956 #interconnect-cells = <2>;
961 compatible = "qcom,sm6115-cnoc";
964 clock-names = "usb_axi";
965 #interconnect-cells = <2>;
969 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
971 #address-cells = <1>;
972 #size-cells = <1>;
974 qusb2_hstx_trim: hstx-trim@25b {
979 gpu_speed_bin: gpu-speed-bin@6006 {
986 compatible = "qcom,prng-ee";
989 clock-names = "core";
993 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
997 operating-points-v2 = <&cpu_bwmon_opp_table>;
1001 cpu_bwmon_opp_table: opp-table {
1002 compatible = "operating-points-v2";
1004 opp-0 {
1005 opp-peak-kBps = <(200 * 4 * 1000)>;
1008 opp-1 {
1009 opp-peak-kBps = <(300 * 4 * 1000)>;
1012 opp-2 {
1013 opp-peak-kBps = <(451 * 4 * 1000)>;
1016 opp-3 {
1017 opp-peak-kBps = <(547 * 4 * 1000)>;
1020 opp-4 {
1021 opp-peak-kBps = <(681 * 4 * 1000)>;
1024 opp-5 {
1025 opp-peak-kBps = <(768 * 4 * 1000)>;
1028 opp-6 {
1029 opp-peak-kBps = <(1017 * 4 * 1000)>;
1032 opp-7 {
1033 opp-peak-kBps = <(1353 * 4 * 1000)>;
1036 opp-8 {
1037 opp-peak-kBps = <(1555 * 4 * 1000)>;
1040 opp-9 {
1041 opp-peak-kBps = <(1804 * 4 * 1000)>;
1047 compatible = "qcom,spmi-pmic-arb";
1053 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1054 interrupt-names = "periph_irq";
1058 #address-cells = <2>;
1059 #size-cells = <0>;
1060 interrupt-controller;
1061 #interrupt-cells = <4>;
1064 tsens0: thermal-sensor@4411000 {
1065 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1071 interrupt-names = "uplow", "critical";
1072 #thermal-sensor-cells = <1>;
1076 compatible = "qcom,sm6115-bimc";
1078 #interconnect-cells = <2>;
1082 compatible = "qcom,rpm-msg-ram";
1087 compatible = "qcom,rpm-stats";
1092 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1096 reg-names = "hc", "cqhci", "ice";
1100 interrupt-names = "hc_irq", "pwr_irq";
1106 clock-names = "iface", "core", "xo", "ice";
1110 power-domains = <&rpmpd SM6115_VDDCX>;
1111 operating-points-v2 = <&sdhc1_opp_table>;
1117 interconnect-names = "sdhc-ddr",
1118 "cpu-sdhc";
1120 bus-width = <8>;
1123 sdhc1_opp_table: opp-table {
1124 compatible = "operating-points-v2";
1126 opp-100000000 {
1127 opp-hz = /bits/ 64 <100000000>;
1128 required-opps = <&rpmpd_opp_low_svs>;
1129 opp-peak-kBps = <250000 133320>;
1130 opp-avg-kBps = <102400 65000>;
1133 opp-192000000 {
1134 opp-hz = /bits/ 64 <192000000>;
1135 required-opps = <&rpmpd_opp_low_svs>;
1136 opp-peak-kBps = <800000 300000>;
1137 opp-avg-kBps = <204800 200000>;
1140 opp-384000000 {
1141 opp-hz = /bits/ 64 <384000000>;
1142 required-opps = <&rpmpd_opp_svs_plus>;
1143 opp-peak-kBps = <800000 300000>;
1144 opp-avg-kBps = <204800 200000>;
1150 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1152 reg-names = "hc";
1156 interrupt-names = "hc_irq", "pwr_irq";
1161 clock-names = "iface", "core", "xo";
1163 power-domains = <&rpmpd SM6115_VDDCX>;
1164 operating-points-v2 = <&sdhc2_opp_table>;
1171 interconnect-names = "sdhc-ddr",
1172 "cpu-sdhc";
1174 bus-width = <4>;
1175 qcom,dll-config = <0x0007642c>;
1176 qcom,ddr-config = <0x80040868>;
1179 sdhc2_opp_table: opp-table {
1180 compatible = "operating-points-v2";
1182 opp-100000000 {
1183 opp-hz = /bits/ 64 <100000000>;
1184 required-opps = <&rpmpd_opp_low_svs>;
1185 opp-peak-kBps = <250000 133320>;
1186 opp-avg-kBps = <261438 150000>;
1189 opp-202000000 {
1190 opp-hz = /bits/ 64 <202000000>;
1191 required-opps = <&rpmpd_opp_nom>;
1192 opp-peak-kBps = <800000 300000>;
1193 opp-avg-kBps = <261438 300000>;
1199 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1201 reg-names = "std", "ice";
1204 phy-names = "ufsphy";
1205 lanes-per-direction = <1>;
1206 #reset-cells = <1>;
1208 reset-names = "rst";
1210 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1221 clock-names = "core_clk",
1230 freq-table-hz = <50000000 200000000>,
1243 compatible = "qcom,sm6115-qmp-ufs-phy";
1249 clock-names = "ref",
1253 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1256 reset-names = "ufsphy";
1258 #phy-cells = <0>;
1263 gpi_dma0: dma-controller@4a00000 {
1264 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1276 dma-channels = <10>;
1277 dma-channel-mask = <0xf>;
1279 #dma-cells = <3>;
1284 compatible = "qcom,geni-se-qup";
1286 clock-names = "m-ahb", "s-ahb";
1289 #address-cells = <2>;
1290 #size-cells = <2>;
1296 compatible = "qcom,geni-i2c";
1298 clock-names = "se";
1300 pinctrl-names = "default";
1301 pinctrl-0 = <&qup_i2c0_default>;
1305 dma-names = "tx", "rx";
1312 interconnect-names = "qup-core",
1313 "qup-config",
1314 "qup-memory";
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1321 compatible = "qcom,geni-spi";
1323 clock-names = "se";
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&qup_spi0_default>;
1330 dma-names = "tx", "rx";
1337 interconnect-names = "qup-core",
1338 "qup-config",
1339 "qup-memory";
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1346 compatible = "qcom,geni-i2c";
1348 clock-names = "se";
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&qup_i2c1_default>;
1355 dma-names = "tx", "rx";
1362 interconnect-names = "qup-core",
1363 "qup-config",
1364 "qup-memory";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1371 compatible = "qcom,geni-spi";
1373 clock-names = "se";
1375 pinctrl-names = "default";
1376 pinctrl-0 = <&qup_spi1_default>;
1380 dma-names = "tx", "rx";
1387 interconnect-names = "qup-core",
1388 "qup-config",
1389 "qup-memory";
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1396 compatible = "qcom,geni-i2c";
1398 clock-names = "se";
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&qup_i2c2_default>;
1405 dma-names = "tx", "rx";
1412 interconnect-names = "qup-core",
1413 "qup-config",
1414 "qup-memory";
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1421 compatible = "qcom,geni-spi";
1423 clock-names = "se";
1425 pinctrl-names = "default";
1426 pinctrl-0 = <&qup_spi2_default>;
1430 dma-names = "tx", "rx";
1437 interconnect-names = "qup-core",
1438 "qup-config",
1439 "qup-memory";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1446 compatible = "qcom,geni-i2c";
1448 clock-names = "se";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_default>;
1455 dma-names = "tx", "rx";
1462 interconnect-names = "qup-core",
1463 "qup-config",
1464 "qup-memory";
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1471 compatible = "qcom,geni-spi";
1473 clock-names = "se";
1475 pinctrl-names = "default";
1476 pinctrl-0 = <&qup_spi3_default>;
1480 dma-names = "tx", "rx";
1487 interconnect-names = "qup-core",
1488 "qup-config",
1489 "qup-memory";
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1496 compatible = "qcom,geni-uart";
1498 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1500 clock-names = "se";
1501 power-domains = <&rpmpd SM6115_VDDCX>;
1502 operating-points-v2 = <&qup_opp_table>;
1507 interconnect-names = "qup-core",
1508 "qup-config";
1513 compatible = "qcom,geni-i2c";
1515 clock-names = "se";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_i2c4_default>;
1522 dma-names = "tx", "rx";
1529 interconnect-names = "qup-core",
1530 "qup-config",
1531 "qup-memory";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1538 compatible = "qcom,geni-spi";
1540 clock-names = "se";
1542 pinctrl-names = "default";
1543 pinctrl-0 = <&qup_spi4_default>;
1547 dma-names = "tx", "rx";
1554 interconnect-names = "qup-core",
1555 "qup-config",
1556 "qup-memory";
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1563 compatible = "qcom,geni-debug-uart";
1565 clock-names = "se";
1572 interconnect-names = "qup-core",
1573 "qup-config";
1578 compatible = "qcom,geni-i2c";
1580 clock-names = "se";
1582 pinctrl-names = "default";
1583 pinctrl-0 = <&qup_i2c5_default>;
1587 dma-names = "tx", "rx";
1594 interconnect-names = "qup-core",
1595 "qup-config",
1596 "qup-memory";
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1603 compatible = "qcom,geni-spi";
1605 clock-names = "se";
1607 pinctrl-names = "default";
1608 pinctrl-0 = <&qup_spi5_default>;
1612 dma-names = "tx", "rx";
1619 interconnect-names = "qup-core",
1620 "qup-config",
1621 "qup-memory";
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1629 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1631 #address-cells = <2>;
1632 #size-cells = <2>;
1641 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1643 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1645 assigned-clock-rates = <19200000>, <66666667>;
1651 interrupt-names = "pwr_event",
1657 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1658 /* TODO: USB<->IPA path */
1663 interconnect-names = "usb-ddr",
1664 "apps-usb";
1673 phy-names = "usb2-phy", "usb3-phy";
1677 snps,has-lpm-erratum;
1678 snps,hird-threshold = /bits/ 8 <0x10>;
1680 snps,parkmode-disable-ss-quirk;
1682 usb-role-switch;
1685 #address-cells = <1>;
1686 #size-cells = <0>;
1699 remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1707 compatible = "qcom,adreno-610.0", "qcom,adreno";
1709 reg-names = "kgsl_3d0_reg_memory";
1718 clock-names = "core",
1728 operating-points-v2 = <&gpu_opp_table>;
1729 power-domains = <&rpmpd SM6115_VDDCX>;
1732 nvmem-cells = <&gpu_speed_bin>;
1733 nvmem-cell-names = "speed_bin";
1734 #cooling-cells = <2>;
1738 zap-shader {
1739 memory-region = <&pil_gpu_mem>;
1742 gpu_opp_table: opp-table {
1743 compatible = "operating-points-v2";
1745 opp-320000000 {
1746 opp-hz = /bits/ 64 <320000000>;
1747 required-opps = <&rpmpd_opp_low_svs>;
1748 opp-supported-hw = <0x1f>;
1751 opp-465000000 {
1752 opp-hz = /bits/ 64 <465000000>;
1753 required-opps = <&rpmpd_opp_svs>;
1754 opp-supported-hw = <0x1f>;
1757 opp-600000000 {
1758 opp-hz = /bits/ 64 <600000000>;
1759 required-opps = <&rpmpd_opp_svs_plus>;
1760 opp-supported-hw = <0x1f>;
1763 opp-745000000 {
1764 opp-hz = /bits/ 64 <745000000>;
1765 required-opps = <&rpmpd_opp_nom>;
1766 opp-supported-hw = <0xf>;
1769 opp-820000000 {
1770 opp-hz = /bits/ 64 <820000000>;
1771 required-opps = <&rpmpd_opp_nom_plus>;
1772 opp-supported-hw = <0x7>;
1775 opp-900000000 {
1776 opp-hz = /bits/ 64 <900000000>;
1777 required-opps = <&rpmpd_opp_turbo>;
1778 opp-supported-hw = <0x7>;
1782 opp-950000000 {
1783 opp-hz = /bits/ 64 <950000000>;
1784 required-opps = <&rpmpd_opp_turbo_plus>;
1785 opp-supported-hw = <0x4>;
1788 opp-980000000 {
1789 opp-hz = /bits/ 64 <980000000>;
1790 required-opps = <&rpmpd_opp_turbo_plus>;
1791 opp-supported-hw = <0x3>;
1797 compatible = "qcom,adreno-gmu-wrapper";
1799 reg-names = "gmu";
1800 power-domains = <&gpucc GPU_CX_GDSC>,
1802 power-domain-names = "cx", "gx";
1805 gpucc: clock-controller@5990000 {
1806 compatible = "qcom,sm6115-gpucc";
1811 #clock-cells = <1>;
1812 #reset-cells = <1>;
1813 #power-domain-cells = <1>;
1817 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1818 "qcom,smmu-500", "arm,mmu-500";
1833 clock-names = "mem",
1836 power-domains = <&gpucc GPU_CX_GDSC>;
1838 #global-interrupts = <1>;
1839 #iommu-cells = <2>;
1842 mdss: display-subsystem@5e00000 {
1843 compatible = "qcom,sm6115-mdss";
1845 reg-names = "mdss";
1847 power-domains = <&dispcc MDSS_GDSC>;
1854 interrupt-controller;
1855 #interrupt-cells = <1>;
1864 interconnect-names = "mdp0-mem",
1865 "cpu-cfg";
1867 #address-cells = <2>;
1868 #size-cells = <2>;
1873 mdp: display-controller@5e01000 {
1874 compatible = "qcom,sm6115-dpu";
1877 reg-names = "mdp", "vbif";
1885 clock-names = "bus",
1892 operating-points-v2 = <&mdp_opp_table>;
1893 power-domains = <&rpmpd SM6115_VDDCX>;
1895 interrupt-parent = <&mdss>;
1899 #address-cells = <1>;
1900 #size-cells = <0>;
1905 remote-endpoint = <&mdss_dsi0_in>;
1910 mdp_opp_table: opp-table {
1911 compatible = "operating-points-v2";
1913 opp-19200000 {
1914 opp-hz = /bits/ 64 <19200000>;
1915 required-opps = <&rpmpd_opp_min_svs>;
1918 opp-192000000 {
1919 opp-hz = /bits/ 64 <192000000>;
1920 required-opps = <&rpmpd_opp_low_svs>;
1923 opp-256000000 {
1924 opp-hz = /bits/ 64 <256000000>;
1925 required-opps = <&rpmpd_opp_svs>;
1928 opp-307200000 {
1929 opp-hz = /bits/ 64 <307200000>;
1930 required-opps = <&rpmpd_opp_svs_plus>;
1933 opp-384000000 {
1934 opp-hz = /bits/ 64 <384000000>;
1935 required-opps = <&rpmpd_opp_nom>;
1941 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1943 reg-names = "dsi_ctrl";
1945 interrupt-parent = <&mdss>;
1954 clock-names = "byte",
1961 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1963 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1965 operating-points-v2 = <&dsi_opp_table>;
1966 power-domains = <&rpmpd SM6115_VDDCX>;
1969 #address-cells = <1>;
1970 #size-cells = <0>;
1975 #address-cells = <1>;
1976 #size-cells = <0>;
1981 remote-endpoint = <&dpu_intf1_out>;
1992 dsi_opp_table: opp-table {
1993 compatible = "operating-points-v2";
1995 opp-19200000 {
1996 opp-hz = /bits/ 64 <19200000>;
1997 required-opps = <&rpmpd_opp_min_svs>;
2000 opp-164000000 {
2001 opp-hz = /bits/ 64 <164000000>;
2002 required-opps = <&rpmpd_opp_low_svs>;
2005 opp-187500000 {
2006 opp-hz = /bits/ 64 <187500000>;
2007 required-opps = <&rpmpd_opp_svs>;
2013 compatible = "qcom,dsi-phy-14nm-2290";
2017 reg-names = "dsi_phy",
2021 #clock-cells = <1>;
2022 #phy-cells = <0>;
2026 clock-names = "iface", "ref";
2032 dispcc: clock-controller@5f00000 {
2033 compatible = "qcom,sm6115-dispcc";
2040 #clock-cells = <1>;
2041 #reset-cells = <1>;
2042 #power-domain-cells = <1>;
2046 compatible = "qcom,sm6115-mpss-pas";
2049 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
2055 interrupt-names = "wdog", "fatal", "ready", "handover",
2056 "stop-ack", "shutdown-ack";
2059 clock-names = "xo";
2061 power-domains = <&rpmpd SM6115_VDDCX>;
2063 memory-region = <&pil_modem_mem>;
2065 qcom,smem-states = <&modem_smp2p_out 0>;
2066 qcom,smem-state-names = "stop";
2070 glink-edge {
2073 qcom,remote-pid = <1>;
2079 compatible = "arm,coresight-stm", "arm,primecell";
2082 reg-names = "stm-base", "stm-stimulus-base";
2085 clock-names = "apb_pclk";
2089 out-ports {
2092 remote-endpoint = <&funnel_in0_in>;
2099 compatible = "arm,coresight-cti", "arm,primecell";
2103 clock-names = "apb_pclk";
2109 compatible = "arm,coresight-cti", "arm,primecell";
2113 clock-names = "apb_pclk";
2119 compatible = "arm,coresight-cti", "arm,primecell";
2123 clock-names = "apb_pclk";
2129 compatible = "arm,coresight-cti", "arm,primecell";
2133 clock-names = "apb_pclk";
2139 compatible = "arm,coresight-cti", "arm,primecell";
2143 clock-names = "apb_pclk";
2149 compatible = "arm,coresight-cti", "arm,primecell";
2153 clock-names = "apb_pclk";
2159 compatible = "arm,coresight-cti", "arm,primecell";
2163 clock-names = "apb_pclk";
2169 compatible = "arm,coresight-cti", "arm,primecell";
2173 clock-names = "apb_pclk";
2179 compatible = "arm,coresight-cti", "arm,primecell";
2183 clock-names = "apb_pclk";
2189 compatible = "arm,coresight-cti", "arm,primecell";
2193 clock-names = "apb_pclk";
2199 compatible = "arm,coresight-cti", "arm,primecell";
2203 clock-names = "apb_pclk";
2209 compatible = "arm,coresight-cti", "arm,primecell";
2213 clock-names = "apb_pclk";
2219 compatible = "arm,coresight-cti", "arm,primecell";
2223 clock-names = "apb_pclk";
2229 compatible = "arm,coresight-cti", "arm,primecell";
2233 clock-names = "apb_pclk";
2239 compatible = "arm,coresight-cti", "arm,primecell";
2243 clock-names = "apb_pclk";
2249 compatible = "arm,coresight-cti", "arm,primecell";
2253 clock-names = "apb_pclk";
2259 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2263 clock-names = "apb_pclk";
2267 out-ports {
2270 remote-endpoint = <&etr_in>;
2275 in-ports {
2278 remote-endpoint = <&etf_out>;
2285 compatible = "arm,coresight-tmc", "arm,primecell";
2289 clock-names = "apb_pclk";
2293 in-ports {
2296 remote-endpoint = <&merge_funnel_out>;
2301 out-ports {
2304 remote-endpoint = <&replicator_in>;
2311 compatible = "arm,coresight-tmc", "arm,primecell";
2315 clock-names = "apb_pclk";
2319 in-ports {
2322 remote-endpoint = <&replicator_out>;
2329 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2333 clock-names = "apb_pclk";
2337 out-ports {
2340 remote-endpoint = <&merge_funnel_in0>;
2345 in-ports {
2348 remote-endpoint = <&stm_out>;
2355 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2359 clock-names = "apb_pclk";
2363 out-ports {
2366 remote-endpoint = <&merge_funnel_in1>;
2371 in-ports {
2374 remote-endpoint = <&funnel_apss1_out>;
2381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2385 clock-names = "apb_pclk";
2389 out-ports {
2392 remote-endpoint = <&etf_in>;
2397 in-ports {
2398 #address-cells = <1>;
2399 #size-cells = <0>;
2404 remote-endpoint = <&funnel_in0_out>;
2411 remote-endpoint = <&funnel_in1_out>;
2418 compatible = "arm,coresight-etm4x", "arm,primecell";
2422 clock-names = "apb_pclk";
2423 arm,coresight-loses-context-with-cpu;
2429 out-ports {
2432 remote-endpoint = <&funnel_apss0_in0>;
2439 compatible = "arm,coresight-etm4x", "arm,primecell";
2443 clock-names = "apb_pclk";
2444 arm,coresight-loses-context-with-cpu;
2450 out-ports {
2453 remote-endpoint = <&funnel_apss0_in1>;
2460 compatible = "arm,coresight-etm4x", "arm,primecell";
2464 clock-names = "apb_pclk";
2465 arm,coresight-loses-context-with-cpu;
2471 out-ports {
2474 remote-endpoint = <&funnel_apss0_in2>;
2481 compatible = "arm,coresight-etm4x", "arm,primecell";
2485 clock-names = "apb_pclk";
2486 arm,coresight-loses-context-with-cpu;
2492 out-ports {
2495 remote-endpoint = <&funnel_apss0_in3>;
2502 compatible = "arm,coresight-etm4x", "arm,primecell";
2506 clock-names = "apb_pclk";
2507 arm,coresight-loses-context-with-cpu;
2513 out-ports {
2516 remote-endpoint = <&funnel_apss0_in4>;
2523 compatible = "arm,coresight-etm4x", "arm,primecell";
2527 clock-names = "apb_pclk";
2528 arm,coresight-loses-context-with-cpu;
2534 out-ports {
2537 remote-endpoint = <&funnel_apss0_in5>;
2544 compatible = "arm,coresight-etm4x", "arm,primecell";
2548 clock-names = "apb_pclk";
2549 arm,coresight-loses-context-with-cpu;
2555 out-ports {
2558 remote-endpoint = <&funnel_apss0_in6>;
2565 compatible = "arm,coresight-etm4x", "arm,primecell";
2569 clock-names = "apb_pclk";
2570 arm,coresight-loses-context-with-cpu;
2576 out-ports {
2579 remote-endpoint = <&funnel_apss0_in7>;
2586 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2590 clock-names = "apb_pclk";
2594 out-ports {
2597 remote-endpoint = <&funnel_apss1_in>;
2602 in-ports {
2603 #address-cells = <1>;
2604 #size-cells = <0>;
2609 remote-endpoint = <&etm0_out>;
2616 remote-endpoint = <&etm1_out>;
2623 remote-endpoint = <&etm2_out>;
2630 remote-endpoint = <&etm3_out>;
2637 remote-endpoint = <&etm4_out>;
2644 remote-endpoint = <&etm5_out>;
2651 remote-endpoint = <&etm6_out>;
2658 remote-endpoint = <&etm7_out>;
2665 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2669 clock-names = "apb_pclk";
2673 out-ports {
2676 remote-endpoint = <&funnel_in1_in>;
2681 in-ports {
2684 remote-endpoint = <&funnel_apss0_out>;
2691 compatible = "qcom,sm6115-adsp-pas";
2694 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2699 interrupt-names = "wdog", "fatal", "ready",
2700 "handover", "stop-ack";
2703 clock-names = "xo";
2705 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2708 memory-region = <&pil_adsp_mem>;
2710 qcom,smem-states = <&adsp_smp2p_out 0>;
2711 qcom,smem-state-names = "stop";
2715 glink-edge {
2718 qcom,remote-pid = <2>;
2722 compatible = "qcom,apr-v2";
2723 qcom,glink-channels = "apr_audio_svc";
2725 #address-cells = <1>;
2726 #size-cells = <0>;
2731 qcom,protection-domain = "avs/audio",
2738 qcom,protection-domain = "avs/audio",
2741 compatible = "qcom,q6afe-dais";
2742 #address-cells = <1>;
2743 #size-cells = <0>;
2744 #sound-dai-cells = <1>;
2747 q6afecc: clock-controller {
2748 compatible = "qcom,q6afe-clocks";
2749 #clock-cells = <2>;
2756 qcom,protection-domain = "avs/audio",
2759 compatible = "qcom,q6asm-dais";
2760 #address-cells = <1>;
2761 #size-cells = <0>;
2762 #sound-dai-cells = <1>;
2782 qcom,protection-domain = "avs/audio",
2785 compatible = "qcom,q6adm-routing";
2786 #sound-dai-cells = <0>;
2793 qcom,glink-channels = "fastrpcglink-apps-dsp";
2795 qcom,non-secure-domain;
2796 #address-cells = <1>;
2797 #size-cells = <0>;
2799 compute-cb@3 {
2800 compatible = "qcom,fastrpc-compute-cb";
2805 compute-cb@4 {
2806 compatible = "qcom,fastrpc-compute-cb";
2811 compute-cb@5 {
2812 compatible = "qcom,fastrpc-compute-cb";
2817 compute-cb@6 {
2818 compatible = "qcom,fastrpc-compute-cb";
2823 compute-cb@7 {
2824 compatible = "qcom,fastrpc-compute-cb";
2833 compatible = "qcom,sm6115-cdsp-pas";
2836 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2841 interrupt-names = "wdog", "fatal", "ready",
2842 "handover", "stop-ack";
2845 clock-names = "xo";
2847 power-domains = <&rpmpd SM6115_VDDCX>;
2849 memory-region = <&pil_cdsp_mem>;
2851 qcom,smem-states = <&cdsp_smp2p_out 0>;
2852 qcom,smem-state-names = "stop";
2856 glink-edge {
2859 qcom,remote-pid = <5>;
2864 qcom,glink-channels = "fastrpcglink-apps-dsp";
2866 qcom,non-secure-domain;
2867 #address-cells = <1>;
2868 #size-cells = <0>;
2870 compute-cb@1 {
2871 compatible = "qcom,fastrpc-compute-cb";
2876 compute-cb@2 {
2877 compatible = "qcom,fastrpc-compute-cb";
2882 compute-cb@3 {
2883 compatible = "qcom,fastrpc-compute-cb";
2888 compute-cb@4 {
2889 compatible = "qcom,fastrpc-compute-cb";
2894 compute-cb@5 {
2895 compatible = "qcom,fastrpc-compute-cb";
2900 compute-cb@6 {
2901 compatible = "qcom,fastrpc-compute-cb";
2912 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2914 #iommu-cells = <2>;
2915 #global-interrupts = <1>;
2985 compatible = "qcom,wcn3990-wifi";
2987 reg-names = "membase";
2988 memory-region = <&wlan_msa_mem>;
3002 qcom,msa-fixed-perm;
3007 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
3014 compatible = "qcom,sm6115-apcs-hmss-global",
3015 "qcom,msm8994-apcs-kpss-global";
3018 #mbox-cells = <1>;
3022 compatible = "arm,armv7-timer-mem";
3024 #address-cells = <2>;
3025 #size-cells = <1>;
3027 clock-frequency = <19200000>;
3031 frame-number = <0>;
3038 frame-number = <1>;
3045 frame-number = <2>;
3052 frame-number = <3>;
3059 frame-number = <4>;
3066 frame-number = <5>;
3073 frame-number = <6>;
3079 intc: interrupt-controller@f200000 {
3080 compatible = "arm,gic-v3";
3083 #interrupt-cells = <3>;
3084 interrupt-controller;
3085 interrupt-parent = <&intc>;
3086 #redistributor-regions = <1>;
3087 redistributor-stride = <0x0 0x20000>;
3092 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
3096 reg-names = "freq-domain0", "freq-domain1";
3098 clock-names = "xo", "alternate";
3100 #freq-domain-cells = <1>;
3101 #clock-cells = <1>;
3105 thermal-zones {
3106 mapss-thermal {
3107 thermal-sensors = <&tsens0 0>;
3110 trip-point0 {
3116 trip-point1 {
3124 cdsp-hvx-thermal {
3125 thermal-sensors = <&tsens0 1>;
3128 trip-point0 {
3134 trip-point1 {
3142 wlan-thermal {
3143 thermal-sensors = <&tsens0 2>;
3146 trip-point0 {
3152 trip-point1 {
3160 camera-thermal {
3161 thermal-sensors = <&tsens0 3>;
3164 trip-point0 {
3170 trip-point1 {
3178 video-thermal {
3179 thermal-sensors = <&tsens0 4>;
3182 trip-point0 {
3188 trip-point1 {
3196 modem1-thermal {
3197 thermal-sensors = <&tsens0 5>;
3200 trip-point0 {
3206 trip-point1 {
3214 cpu4-thermal {
3215 thermal-sensors = <&tsens0 6>;
3218 cpu4_alert0: trip-point0 {
3224 cpu4_alert1: trip-point1 {
3230 cpu4_crit: cpu-crit {
3238 cpu5-thermal {
3239 thermal-sensors = <&tsens0 7>;
3242 cpu5_alert0: trip-point0 {
3248 cpu5_alert1: trip-point1 {
3254 cpu5_crit: cpu-crit {
3262 cpu6-thermal {
3263 thermal-sensors = <&tsens0 8>;
3266 cpu6_alert0: trip-point0 {
3272 cpu6_alert1: trip-point1 {
3278 cpu6_crit: cpu-crit {
3286 cpu7-thermal {
3287 thermal-sensors = <&tsens0 9>;
3290 cpu7_alert0: trip-point0 {
3296 cpu7_alert1: trip-point1 {
3302 cpu7_crit: cpu-crit {
3310 cpu45-thermal {
3311 thermal-sensors = <&tsens0 10>;
3314 cpu45_alert0: trip-point0 {
3320 cpu45_alert1: trip-point1 {
3326 cpu45_crit: cpu-crit {
3334 cpu67-thermal {
3335 thermal-sensors = <&tsens0 11>;
3338 cpu67_alert0: trip-point0 {
3344 cpu67_alert1: trip-point1 {
3350 cpu67_crit: cpu-crit {
3358 cpu0123-thermal {
3359 thermal-sensors = <&tsens0 12>;
3362 cpu0123_alert0: trip-point0 {
3368 cpu0123_alert1: trip-point1 {
3374 cpu0123_crit: cpu-crit {
3382 modem0-thermal {
3383 thermal-sensors = <&tsens0 13>;
3386 trip-point0 {
3392 trip-point1 {
3400 display-thermal {
3401 thermal-sensors = <&tsens0 14>;
3404 trip-point0 {
3410 trip-point1 {
3418 gpu-thermal {
3419 polling-delay-passive = <250>;
3421 thermal-sensors = <&tsens0 15>;
3423 cooling-maps {
3426 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3431 gpu_alert0: trip-point0 {
3437 trip-point1 {
3447 compatible = "arm,armv8-timer";