Lines Matching +full:sdm845 +full:- +full:dwc3
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
40 #address-cells = <2>;
41 #size-cells = <0>;
48 capacity-dmips-mhz = <1024>;
49 dynamic-power-coefficient = <100>;
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
53 power-domains = <&CPU_PD0>;
54 power-domain-names = "psci";
55 L2_0: l2-cache {
57 cache-level = <2>;
58 cache-unified;
67 capacity-dmips-mhz = <1024>;
68 dynamic-power-coefficient = <100>;
69 enable-method = "psci";
70 next-level-cache = <&L2_0>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
72 power-domains = <&CPU_PD1>;
73 power-domain-names = "psci";
81 capacity-dmips-mhz = <1024>;
82 dynamic-power-coefficient = <100>;
83 enable-method = "psci";
84 next-level-cache = <&L2_0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
86 power-domains = <&CPU_PD2>;
87 power-domain-names = "psci";
95 capacity-dmips-mhz = <1024>;
96 dynamic-power-coefficient = <100>;
97 enable-method = "psci";
98 next-level-cache = <&L2_0>;
99 qcom,freq-domain = <&cpufreq_hw 0>;
100 power-domains = <&CPU_PD3>;
101 power-domain-names = "psci";
109 enable-method = "psci";
110 capacity-dmips-mhz = <1638>;
111 dynamic-power-coefficient = <282>;
112 next-level-cache = <&L2_1>;
113 qcom,freq-domain = <&cpufreq_hw 1>;
114 power-domains = <&CPU_PD4>;
115 power-domain-names = "psci";
116 L2_1: l2-cache {
118 cache-level = <2>;
119 cache-unified;
128 capacity-dmips-mhz = <1638>;
129 dynamic-power-coefficient = <282>;
130 enable-method = "psci";
131 next-level-cache = <&L2_1>;
132 qcom,freq-domain = <&cpufreq_hw 1>;
133 power-domains = <&CPU_PD5>;
134 power-domain-names = "psci";
142 capacity-dmips-mhz = <1638>;
143 dynamic-power-coefficient = <282>;
144 enable-method = "psci";
145 next-level-cache = <&L2_1>;
146 qcom,freq-domain = <&cpufreq_hw 1>;
147 power-domains = <&CPU_PD6>;
148 power-domain-names = "psci";
156 capacity-dmips-mhz = <1638>;
157 dynamic-power-coefficient = <282>;
158 enable-method = "psci";
159 next-level-cache = <&L2_1>;
160 qcom,freq-domain = <&cpufreq_hw 1>;
161 power-domains = <&CPU_PD7>;
162 power-domain-names = "psci";
165 cpu-map {
203 idle-states {
204 entry-method = "psci";
206 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
207 compatible = "arm,idle-state";
208 idle-state-name = "silver-rail-power-collapse";
209 arm,psci-suspend-param = <0x40000003>;
210 entry-latency-us = <290>;
211 exit-latency-us = <376>;
212 min-residency-us = <1182>;
213 local-timer-stop;
216 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
217 compatible = "arm,idle-state";
218 idle-state-name = "gold-rail-power-collapse";
219 arm,psci-suspend-param = <0x40000003>;
220 entry-latency-us = <297>;
221 exit-latency-us = <324>;
222 min-residency-us = <1110>;
223 local-timer-stop;
227 domain-idle-states {
228 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
230 compatible = "domain-idle-state";
231 arm,psci-suspend-param = <0x40000022>;
232 entry-latency-us = <360>;
233 exit-latency-us = <421>;
234 min-residency-us = <782>;
237 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
239 compatible = "domain-idle-state";
240 arm,psci-suspend-param = <0x41000044>;
241 entry-latency-us = <800>;
242 exit-latency-us = <2118>;
243 min-residency-us = <7376>;
246 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
248 compatible = "domain-idle-state";
249 arm,psci-suspend-param = <0x40000042>;
250 entry-latency-us = <314>;
251 exit-latency-us = <345>;
252 min-residency-us = <660>;
255 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
257 compatible = "domain-idle-state";
258 arm,psci-suspend-param = <0x41000044>;
259 entry-latency-us = <640>;
260 exit-latency-us = <1654>;
261 min-residency-us = <8094>;
268 compatible = "qcom,scm-sm6115", "qcom,scm";
269 #reset-cells = <1>;
281 qup_opp_table: opp-table-qup {
282 compatible = "operating-points-v2";
284 opp-75000000 {
285 opp-hz = /bits/ 64 <75000000>;
286 required-opps = <&rpmpd_opp_low_svs>;
289 opp-100000000 {
290 opp-hz = /bits/ 64 <100000000>;
291 required-opps = <&rpmpd_opp_svs>;
294 opp-128000000 {
295 opp-hz = /bits/ 64 <128000000>;
296 required-opps = <&rpmpd_opp_nom>;
301 compatible = "arm,armv8-pmuv3";
306 compatible = "arm,psci-1.0";
309 CPU_PD0: power-domain-cpu0 {
310 #power-domain-cells = <0>;
311 power-domains = <&CLUSTER_0_PD>;
312 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
315 CPU_PD1: power-domain-cpu1 {
316 #power-domain-cells = <0>;
317 power-domains = <&CLUSTER_0_PD>;
318 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
321 CPU_PD2: power-domain-cpu2 {
322 #power-domain-cells = <0>;
323 power-domains = <&CLUSTER_0_PD>;
324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
327 CPU_PD3: power-domain-cpu3 {
328 #power-domain-cells = <0>;
329 power-domains = <&CLUSTER_0_PD>;
330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
333 CPU_PD4: power-domain-cpu4 {
334 #power-domain-cells = <0>;
335 power-domains = <&CLUSTER_1_PD>;
336 domain-idle-states = <&BIG_CPU_SLEEP_0>;
339 CPU_PD5: power-domain-cpu5 {
340 #power-domain-cells = <0>;
341 power-domains = <&CLUSTER_1_PD>;
342 domain-idle-states = <&BIG_CPU_SLEEP_0>;
345 CPU_PD6: power-domain-cpu6 {
346 #power-domain-cells = <0>;
347 power-domains = <&CLUSTER_1_PD>;
348 domain-idle-states = <&BIG_CPU_SLEEP_0>;
351 CPU_PD7: power-domain-cpu7 {
352 #power-domain-cells = <0>;
353 power-domains = <&CLUSTER_1_PD>;
354 domain-idle-states = <&BIG_CPU_SLEEP_0>;
357 CLUSTER_0_PD: power-domain-cpu-cluster0 {
358 #power-domain-cells = <0>;
359 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
362 CLUSTER_1_PD: power-domain-cpu-cluster1 {
363 #power-domain-cells = <0>;
364 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
369 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
371 glink-edge {
372 compatible = "qcom,glink-rpm";
375 qcom,rpm-msg-ram = <&rpm_msg_ram>;
378 rpm_requests: rpm-requests {
379 compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm";
380 qcom,glink-channels = "rpm_requests";
382 rpmcc: clock-controller {
383 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
385 clock-names = "xo";
386 #clock-cells = <1>;
389 rpmpd: power-controller {
390 compatible = "qcom,sm6115-rpmpd";
391 #power-domain-cells = <1>;
392 operating-points-v2 = <&rpmpd_opp_table>;
394 rpmpd_opp_table: opp-table {
395 compatible = "operating-points-v2";
398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
406 opp-level = <RPM_SMD_LEVEL_SVS>;
410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
414 opp-level = <RPM_SMD_LEVEL_NOM>;
418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
422 opp-level = <RPM_SMD_LEVEL_TURBO>;
426 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
434 reserved_memory: reserved-memory {
435 #address-cells = <2>;
436 #size-cells = <2>;
441 no-map;
446 no-map;
451 no-map;
457 no-map;
460 qcom,rpm-msg-ram = <&rpm_msg_ram>;
465 no-map;
470 no-map;
475 no-map;
480 no-map;
485 no-map;
490 no-map;
495 no-map;
500 no-map;
505 no-map;
510 no-map;
515 no-map;
520 no-map;
524 compatible = "qcom,rmtfs-mem";
526 no-map;
528 qcom,client-id = <1>;
533 smp2p-adsp {
541 qcom,local-pid = <0>;
542 qcom,remote-pid = <2>;
544 adsp_smp2p_out: master-kernel {
545 qcom,entry-name = "master-kernel";
546 #qcom,smem-state-cells = <1>;
549 adsp_smp2p_in: slave-kernel {
550 qcom,entry-name = "slave-kernel";
552 interrupt-controller;
553 #interrupt-cells = <2>;
557 smp2p-cdsp {
565 qcom,local-pid = <0>;
566 qcom,remote-pid = <5>;
568 cdsp_smp2p_out: master-kernel {
569 qcom,entry-name = "master-kernel";
570 #qcom,smem-state-cells = <1>;
573 cdsp_smp2p_in: slave-kernel {
574 qcom,entry-name = "slave-kernel";
576 interrupt-controller;
577 #interrupt-cells = <2>;
581 smp2p-mpss {
589 qcom,local-pid = <0>;
590 qcom,remote-pid = <1>;
592 modem_smp2p_out: master-kernel {
593 qcom,entry-name = "master-kernel";
594 #qcom,smem-state-cells = <1>;
597 modem_smp2p_in: slave-kernel {
598 qcom,entry-name = "slave-kernel";
600 interrupt-controller;
601 #interrupt-cells = <2>;
606 compatible = "simple-bus";
607 #address-cells = <2>;
608 #size-cells = <2>;
610 dma-ranges = <0 0 0 0 0x10 0>;
613 compatible = "qcom,tcsr-mutex";
615 #hwlock-cells = <1>;
619 compatible = "qcom,sm6115-tcsr", "syscon";
624 compatible = "qcom,sm6115-tlmm";
628 reg-names = "west", "south", "east";
630 gpio-controller;
631 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
632 #gpio-cells = <2>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
636 qup_i2c0_default: qup-i2c0-default-state {
639 drive-strength = <2>;
640 bias-pull-up;
643 qup_i2c1_default: qup-i2c1-default-state {
646 drive-strength = <2>;
647 bias-pull-up;
650 qup_i2c2_default: qup-i2c2-default-state {
653 drive-strength = <2>;
654 bias-pull-up;
657 qup_i2c3_default: qup-i2c3-default-state {
660 drive-strength = <2>;
661 bias-pull-up;
664 qup_i2c4_default: qup-i2c4-default-state {
667 drive-strength = <2>;
668 bias-pull-up;
671 qup_i2c5_default: qup-i2c5-default-state {
674 drive-strength = <2>;
675 bias-pull-up;
678 qup_spi0_default: qup-spi0-default-state {
681 drive-strength = <2>;
682 bias-pull-up;
685 qup_spi1_default: qup-spi1-default-state {
688 drive-strength = <2>;
689 bias-pull-up;
692 qup_spi2_default: qup-spi2-default-state {
695 drive-strength = <2>;
696 bias-pull-up;
699 qup_spi3_default: qup-spi3-default-state {
702 drive-strength = <2>;
703 bias-pull-up;
706 qup_spi4_default: qup-spi4-default-state {
709 drive-strength = <2>;
710 bias-pull-up;
713 qup_spi5_default: qup-spi5-default-state {
716 drive-strength = <2>;
717 bias-pull-up;
720 sdc1_state_on: sdc1-on-state {
721 clk-pins {
723 bias-disable;
724 drive-strength = <16>;
727 cmd-pins {
729 bias-pull-up;
730 drive-strength = <10>;
733 data-pins {
735 bias-pull-up;
736 drive-strength = <10>;
739 rclk-pins {
741 bias-pull-down;
745 sdc1_state_off: sdc1-off-state {
746 clk-pins {
748 bias-disable;
749 drive-strength = <2>;
752 cmd-pins {
754 bias-pull-up;
755 drive-strength = <2>;
758 data-pins {
760 bias-pull-up;
761 drive-strength = <2>;
764 rclk-pins {
766 bias-pull-down;
770 sdc2_state_on: sdc2-on-state {
771 clk-pins {
773 bias-disable;
774 drive-strength = <16>;
777 cmd-pins {
779 bias-pull-up;
780 drive-strength = <10>;
783 data-pins {
785 bias-pull-up;
786 drive-strength = <10>;
790 sdc2_state_off: sdc2-off-state {
791 clk-pins {
793 bias-disable;
794 drive-strength = <2>;
797 cmd-pins {
799 bias-pull-up;
800 drive-strength = <2>;
803 data-pins {
805 bias-pull-up;
806 drive-strength = <2>;
811 gcc: clock-controller@1400000 {
812 compatible = "qcom,gcc-sm6115";
815 clock-names = "bi_tcxo", "sleep_clk";
816 #clock-cells = <1>;
817 #reset-cells = <1>;
818 #power-domain-cells = <1>;
822 compatible = "qcom,sm6115-qusb2-phy";
824 #phy-cells = <0>;
827 clock-names = "cfg_ahb", "ref";
830 nvmem-cells = <&qusb2_hstx_trim>;
835 cryptobam: dma-controller@1b04000 {
836 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
840 clock-names = "bam_clk";
841 #dma-cells = <1>;
843 qcom,controlled-remotely;
852 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
855 clock-names = "core";
858 dma-names = "rx", "tx";
867 compatible = "qcom,sm6115-qmp-usb3-phy";
874 clock-names = "cfg_ahb",
881 reset-names = "phy", "phy_phy";
883 #clock-cells = <0>;
884 clock-output-names = "usb3_phy_pipe_clk_src";
886 #phy-cells = <0>;
887 orientation-switch;
889 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
894 #address-cells = <1>;
895 #size-cells = <0>;
908 remote-endpoint = <&usb_dwc3_ss>;
915 compatible = "qcom,sm6115-snoc";
921 clock-names = "cpu_axi",
925 #interconnect-cells = <2>;
927 clk_virt: interconnect-clk {
928 compatible = "qcom,sm6115-clk-virt";
929 #interconnect-cells = <2>;
932 mmrt_virt: interconnect-mmrt {
933 compatible = "qcom,sm6115-mmrt-virt";
934 #interconnect-cells = <2>;
937 mmnrt_virt: interconnect-mmnrt {
938 compatible = "qcom,sm6115-mmnrt-virt";
939 #interconnect-cells = <2>;
944 compatible = "qcom,sm6115-cnoc";
947 clock-names = "usb_axi";
948 #interconnect-cells = <2>;
952 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
954 #address-cells = <1>;
955 #size-cells = <1>;
957 qusb2_hstx_trim: hstx-trim@25b {
962 gpu_speed_bin: gpu-speed-bin@6006 {
969 compatible = "qcom,prng-ee";
972 clock-names = "core";
976 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
980 operating-points-v2 = <&cpu_bwmon_opp_table>;
984 cpu_bwmon_opp_table: opp-table {
985 compatible = "operating-points-v2";
987 opp-0 {
988 opp-peak-kBps = <(200 * 4 * 1000)>;
991 opp-1 {
992 opp-peak-kBps = <(300 * 4 * 1000)>;
995 opp-2 {
996 opp-peak-kBps = <(451 * 4 * 1000)>;
999 opp-3 {
1000 opp-peak-kBps = <(547 * 4 * 1000)>;
1003 opp-4 {
1004 opp-peak-kBps = <(681 * 4 * 1000)>;
1007 opp-5 {
1008 opp-peak-kBps = <(768 * 4 * 1000)>;
1011 opp-6 {
1012 opp-peak-kBps = <(1017 * 4 * 1000)>;
1015 opp-7 {
1016 opp-peak-kBps = <(1353 * 4 * 1000)>;
1019 opp-8 {
1020 opp-peak-kBps = <(1555 * 4 * 1000)>;
1023 opp-9 {
1024 opp-peak-kBps = <(1804 * 4 * 1000)>;
1030 compatible = "qcom,spmi-pmic-arb";
1036 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1037 interrupt-names = "periph_irq";
1041 #address-cells = <2>;
1042 #size-cells = <0>;
1043 interrupt-controller;
1044 #interrupt-cells = <4>;
1047 tsens0: thermal-sensor@4411000 {
1048 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1054 interrupt-names = "uplow", "critical";
1055 #thermal-sensor-cells = <1>;
1059 compatible = "qcom,sm6115-bimc";
1061 #interconnect-cells = <2>;
1065 compatible = "qcom,rpm-msg-ram";
1070 compatible = "qcom,rpm-stats";
1075 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1079 reg-names = "hc", "cqhci", "ice";
1083 interrupt-names = "hc_irq", "pwr_irq";
1089 clock-names = "iface", "core", "xo", "ice";
1093 power-domains = <&rpmpd SM6115_VDDCX>;
1094 operating-points-v2 = <&sdhc1_opp_table>;
1100 interconnect-names = "sdhc-ddr",
1101 "cpu-sdhc";
1103 bus-width = <8>;
1106 sdhc1_opp_table: opp-table {
1107 compatible = "operating-points-v2";
1109 opp-100000000 {
1110 opp-hz = /bits/ 64 <100000000>;
1111 required-opps = <&rpmpd_opp_low_svs>;
1112 opp-peak-kBps = <250000 133320>;
1113 opp-avg-kBps = <102400 65000>;
1116 opp-192000000 {
1117 opp-hz = /bits/ 64 <192000000>;
1118 required-opps = <&rpmpd_opp_low_svs>;
1119 opp-peak-kBps = <800000 300000>;
1120 opp-avg-kBps = <204800 200000>;
1123 opp-384000000 {
1124 opp-hz = /bits/ 64 <384000000>;
1125 required-opps = <&rpmpd_opp_svs_plus>;
1126 opp-peak-kBps = <800000 300000>;
1127 opp-avg-kBps = <204800 200000>;
1133 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1135 reg-names = "hc";
1139 interrupt-names = "hc_irq", "pwr_irq";
1144 clock-names = "iface", "core", "xo";
1146 power-domains = <&rpmpd SM6115_VDDCX>;
1147 operating-points-v2 = <&sdhc2_opp_table>;
1154 interconnect-names = "sdhc-ddr",
1155 "cpu-sdhc";
1157 bus-width = <4>;
1158 qcom,dll-config = <0x0007642c>;
1159 qcom,ddr-config = <0x80040868>;
1162 sdhc2_opp_table: opp-table {
1163 compatible = "operating-points-v2";
1165 opp-100000000 {
1166 opp-hz = /bits/ 64 <100000000>;
1167 required-opps = <&rpmpd_opp_low_svs>;
1168 opp-peak-kBps = <250000 133320>;
1169 opp-avg-kBps = <261438 150000>;
1172 opp-202000000 {
1173 opp-hz = /bits/ 64 <202000000>;
1174 required-opps = <&rpmpd_opp_nom>;
1175 opp-peak-kBps = <800000 300000>;
1176 opp-avg-kBps = <261438 300000>;
1182 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1184 reg-names = "std", "ice";
1187 phy-names = "ufsphy";
1188 lanes-per-direction = <1>;
1189 #reset-cells = <1>;
1191 reset-names = "rst";
1193 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1204 clock-names = "core_clk",
1213 freq-table-hz = <50000000 200000000>,
1226 compatible = "qcom,sm6115-qmp-ufs-phy";
1232 clock-names = "ref",
1236 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1239 reset-names = "ufsphy";
1241 #phy-cells = <0>;
1246 gpi_dma0: dma-controller@4a00000 {
1247 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1259 dma-channels = <10>;
1260 dma-channel-mask = <0xf>;
1262 #dma-cells = <3>;
1267 compatible = "qcom,geni-se-qup";
1269 clock-names = "m-ahb", "s-ahb";
1272 #address-cells = <2>;
1273 #size-cells = <2>;
1279 compatible = "qcom,geni-i2c";
1281 clock-names = "se";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&qup_i2c0_default>;
1288 dma-names = "tx", "rx";
1295 interconnect-names = "qup-core",
1296 "qup-config",
1297 "qup-memory";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 compatible = "qcom,geni-spi";
1306 clock-names = "se";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_spi0_default>;
1313 dma-names = "tx", "rx";
1320 interconnect-names = "qup-core",
1321 "qup-config",
1322 "qup-memory";
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1329 compatible = "qcom,geni-i2c";
1331 clock-names = "se";
1333 pinctrl-names = "default";
1334 pinctrl-0 = <&qup_i2c1_default>;
1338 dma-names = "tx", "rx";
1345 interconnect-names = "qup-core",
1346 "qup-config",
1347 "qup-memory";
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1354 compatible = "qcom,geni-spi";
1356 clock-names = "se";
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&qup_spi1_default>;
1363 dma-names = "tx", "rx";
1370 interconnect-names = "qup-core",
1371 "qup-config",
1372 "qup-memory";
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1379 compatible = "qcom,geni-i2c";
1381 clock-names = "se";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_i2c2_default>;
1388 dma-names = "tx", "rx";
1395 interconnect-names = "qup-core",
1396 "qup-config",
1397 "qup-memory";
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1404 compatible = "qcom,geni-spi";
1406 clock-names = "se";
1408 pinctrl-names = "default";
1409 pinctrl-0 = <&qup_spi2_default>;
1413 dma-names = "tx", "rx";
1420 interconnect-names = "qup-core",
1421 "qup-config",
1422 "qup-memory";
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1429 compatible = "qcom,geni-i2c";
1431 clock-names = "se";
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&qup_i2c3_default>;
1438 dma-names = "tx", "rx";
1445 interconnect-names = "qup-core",
1446 "qup-config",
1447 "qup-memory";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1454 compatible = "qcom,geni-spi";
1456 clock-names = "se";
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_spi3_default>;
1463 dma-names = "tx", "rx";
1470 interconnect-names = "qup-core",
1471 "qup-config",
1472 "qup-memory";
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1479 compatible = "qcom,geni-uart";
1481 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1483 clock-names = "se";
1484 power-domains = <&rpmpd SM6115_VDDCX>;
1485 operating-points-v2 = <&qup_opp_table>;
1490 interconnect-names = "qup-core",
1491 "qup-config";
1496 compatible = "qcom,geni-i2c";
1498 clock-names = "se";
1500 pinctrl-names = "default";
1501 pinctrl-0 = <&qup_i2c4_default>;
1505 dma-names = "tx", "rx";
1512 interconnect-names = "qup-core",
1513 "qup-config",
1514 "qup-memory";
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1521 compatible = "qcom,geni-spi";
1523 clock-names = "se";
1525 pinctrl-names = "default";
1526 pinctrl-0 = <&qup_spi4_default>;
1530 dma-names = "tx", "rx";
1537 interconnect-names = "qup-core",
1538 "qup-config",
1539 "qup-memory";
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1546 compatible = "qcom,geni-debug-uart";
1548 clock-names = "se";
1555 interconnect-names = "qup-core",
1556 "qup-config";
1561 compatible = "qcom,geni-i2c";
1563 clock-names = "se";
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c5_default>;
1570 dma-names = "tx", "rx";
1577 interconnect-names = "qup-core",
1578 "qup-config",
1579 "qup-memory";
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1586 compatible = "qcom,geni-spi";
1588 clock-names = "se";
1590 pinctrl-names = "default";
1591 pinctrl-0 = <&qup_spi5_default>;
1595 dma-names = "tx", "rx";
1602 interconnect-names = "qup-core",
1603 "qup-config",
1604 "qup-memory";
1605 #address-cells = <1>;
1606 #size-cells = <0>;
1612 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1614 #address-cells = <2>;
1615 #size-cells = <2>;
1624 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1626 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1628 assigned-clock-rates = <19200000>, <66666667>;
1634 interrupt-names = "pwr_event",
1640 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1641 /* TODO: USB<->IPA path */
1646 interconnect-names = "usb-ddr",
1647 "apps-usb";
1652 compatible = "snps,dwc3";
1656 phy-names = "usb2-phy", "usb3-phy";
1660 snps,has-lpm-erratum;
1661 snps,hird-threshold = /bits/ 8 <0x10>;
1663 snps,parkmode-disable-ss-quirk;
1665 usb-role-switch;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1682 remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1690 compatible = "qcom,adreno-610.0", "qcom,adreno";
1692 reg-names = "kgsl_3d0_reg_memory";
1701 clock-names = "core",
1711 operating-points-v2 = <&gpu_opp_table>;
1712 power-domains = <&rpmpd SM6115_VDDCX>;
1715 nvmem-cells = <&gpu_speed_bin>;
1716 nvmem-cell-names = "speed_bin";
1717 #cooling-cells = <2>;
1721 zap-shader {
1722 memory-region = <&pil_gpu_mem>;
1725 gpu_opp_table: opp-table {
1726 compatible = "operating-points-v2";
1728 opp-320000000 {
1729 opp-hz = /bits/ 64 <320000000>;
1730 required-opps = <&rpmpd_opp_low_svs>;
1731 opp-supported-hw = <0x1f>;
1734 opp-465000000 {
1735 opp-hz = /bits/ 64 <465000000>;
1736 required-opps = <&rpmpd_opp_svs>;
1737 opp-supported-hw = <0x1f>;
1740 opp-600000000 {
1741 opp-hz = /bits/ 64 <600000000>;
1742 required-opps = <&rpmpd_opp_svs_plus>;
1743 opp-supported-hw = <0x1f>;
1746 opp-745000000 {
1747 opp-hz = /bits/ 64 <745000000>;
1748 required-opps = <&rpmpd_opp_nom>;
1749 opp-supported-hw = <0xf>;
1752 opp-820000000 {
1753 opp-hz = /bits/ 64 <820000000>;
1754 required-opps = <&rpmpd_opp_nom_plus>;
1755 opp-supported-hw = <0x7>;
1758 opp-900000000 {
1759 opp-hz = /bits/ 64 <900000000>;
1760 required-opps = <&rpmpd_opp_turbo>;
1761 opp-supported-hw = <0x7>;
1765 opp-950000000 {
1766 opp-hz = /bits/ 64 <950000000>;
1767 required-opps = <&rpmpd_opp_turbo_plus>;
1768 opp-supported-hw = <0x4>;
1771 opp-980000000 {
1772 opp-hz = /bits/ 64 <980000000>;
1773 required-opps = <&rpmpd_opp_turbo_plus>;
1774 opp-supported-hw = <0x3>;
1780 compatible = "qcom,adreno-gmu-wrapper";
1782 reg-names = "gmu";
1783 power-domains = <&gpucc GPU_CX_GDSC>,
1785 power-domain-names = "cx", "gx";
1788 gpucc: clock-controller@5990000 {
1789 compatible = "qcom,sm6115-gpucc";
1794 #clock-cells = <1>;
1795 #reset-cells = <1>;
1796 #power-domain-cells = <1>;
1800 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1801 "qcom,smmu-500", "arm,mmu-500";
1816 clock-names = "mem",
1819 power-domains = <&gpucc GPU_CX_GDSC>;
1821 #global-interrupts = <1>;
1822 #iommu-cells = <2>;
1825 mdss: display-subsystem@5e00000 {
1826 compatible = "qcom,sm6115-mdss";
1828 reg-names = "mdss";
1830 power-domains = <&dispcc MDSS_GDSC>;
1837 interrupt-controller;
1838 #interrupt-cells = <1>;
1847 interconnect-names = "mdp0-mem",
1848 "cpu-cfg";
1850 #address-cells = <2>;
1851 #size-cells = <2>;
1856 mdp: display-controller@5e01000 {
1857 compatible = "qcom,sm6115-dpu";
1860 reg-names = "mdp", "vbif";
1868 clock-names = "bus",
1875 operating-points-v2 = <&mdp_opp_table>;
1876 power-domains = <&rpmpd SM6115_VDDCX>;
1878 interrupt-parent = <&mdss>;
1882 #address-cells = <1>;
1883 #size-cells = <0>;
1888 remote-endpoint = <&mdss_dsi0_in>;
1893 mdp_opp_table: opp-table {
1894 compatible = "operating-points-v2";
1896 opp-19200000 {
1897 opp-hz = /bits/ 64 <19200000>;
1898 required-opps = <&rpmpd_opp_min_svs>;
1901 opp-192000000 {
1902 opp-hz = /bits/ 64 <192000000>;
1903 required-opps = <&rpmpd_opp_low_svs>;
1906 opp-256000000 {
1907 opp-hz = /bits/ 64 <256000000>;
1908 required-opps = <&rpmpd_opp_svs>;
1911 opp-307200000 {
1912 opp-hz = /bits/ 64 <307200000>;
1913 required-opps = <&rpmpd_opp_svs_plus>;
1916 opp-384000000 {
1917 opp-hz = /bits/ 64 <384000000>;
1918 required-opps = <&rpmpd_opp_nom>;
1924 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1926 reg-names = "dsi_ctrl";
1928 interrupt-parent = <&mdss>;
1937 clock-names = "byte",
1944 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1946 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1948 operating-points-v2 = <&dsi_opp_table>;
1949 power-domains = <&rpmpd SM6115_VDDCX>;
1952 #address-cells = <1>;
1953 #size-cells = <0>;
1958 #address-cells = <1>;
1959 #size-cells = <0>;
1964 remote-endpoint = <&dpu_intf1_out>;
1975 dsi_opp_table: opp-table {
1976 compatible = "operating-points-v2";
1978 opp-19200000 {
1979 opp-hz = /bits/ 64 <19200000>;
1980 required-opps = <&rpmpd_opp_min_svs>;
1983 opp-164000000 {
1984 opp-hz = /bits/ 64 <164000000>;
1985 required-opps = <&rpmpd_opp_low_svs>;
1988 opp-187500000 {
1989 opp-hz = /bits/ 64 <187500000>;
1990 required-opps = <&rpmpd_opp_svs>;
1996 compatible = "qcom,dsi-phy-14nm-2290";
2000 reg-names = "dsi_phy",
2004 #clock-cells = <1>;
2005 #phy-cells = <0>;
2009 clock-names = "iface", "ref";
2015 dispcc: clock-controller@5f00000 {
2016 compatible = "qcom,sm6115-dispcc";
2023 #clock-cells = <1>;
2024 #reset-cells = <1>;
2025 #power-domain-cells = <1>;
2029 compatible = "qcom,sm6115-mpss-pas";
2032 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
2038 interrupt-names = "wdog", "fatal", "ready", "handover",
2039 "stop-ack", "shutdown-ack";
2042 clock-names = "xo";
2044 power-domains = <&rpmpd SM6115_VDDCX>;
2046 memory-region = <&pil_modem_mem>;
2048 qcom,smem-states = <&modem_smp2p_out 0>;
2049 qcom,smem-state-names = "stop";
2053 glink-edge {
2056 qcom,remote-pid = <1>;
2062 compatible = "arm,coresight-stm", "arm,primecell";
2065 reg-names = "stm-base", "stm-stimulus-base";
2068 clock-names = "apb_pclk";
2072 out-ports {
2075 remote-endpoint = <&funnel_in0_in>;
2082 compatible = "arm,coresight-cti", "arm,primecell";
2086 clock-names = "apb_pclk";
2092 compatible = "arm,coresight-cti", "arm,primecell";
2096 clock-names = "apb_pclk";
2102 compatible = "arm,coresight-cti", "arm,primecell";
2106 clock-names = "apb_pclk";
2112 compatible = "arm,coresight-cti", "arm,primecell";
2116 clock-names = "apb_pclk";
2122 compatible = "arm,coresight-cti", "arm,primecell";
2126 clock-names = "apb_pclk";
2132 compatible = "arm,coresight-cti", "arm,primecell";
2136 clock-names = "apb_pclk";
2142 compatible = "arm,coresight-cti", "arm,primecell";
2146 clock-names = "apb_pclk";
2152 compatible = "arm,coresight-cti", "arm,primecell";
2156 clock-names = "apb_pclk";
2162 compatible = "arm,coresight-cti", "arm,primecell";
2166 clock-names = "apb_pclk";
2172 compatible = "arm,coresight-cti", "arm,primecell";
2176 clock-names = "apb_pclk";
2182 compatible = "arm,coresight-cti", "arm,primecell";
2186 clock-names = "apb_pclk";
2192 compatible = "arm,coresight-cti", "arm,primecell";
2196 clock-names = "apb_pclk";
2202 compatible = "arm,coresight-cti", "arm,primecell";
2206 clock-names = "apb_pclk";
2212 compatible = "arm,coresight-cti", "arm,primecell";
2216 clock-names = "apb_pclk";
2222 compatible = "arm,coresight-cti", "arm,primecell";
2226 clock-names = "apb_pclk";
2232 compatible = "arm,coresight-cti", "arm,primecell";
2236 clock-names = "apb_pclk";
2242 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2246 clock-names = "apb_pclk";
2250 out-ports {
2253 remote-endpoint = <&etr_in>;
2258 in-ports {
2261 remote-endpoint = <&etf_out>;
2268 compatible = "arm,coresight-tmc", "arm,primecell";
2272 clock-names = "apb_pclk";
2276 in-ports {
2279 remote-endpoint = <&merge_funnel_out>;
2284 out-ports {
2287 remote-endpoint = <&replicator_in>;
2294 compatible = "arm,coresight-tmc", "arm,primecell";
2298 clock-names = "apb_pclk";
2302 in-ports {
2305 remote-endpoint = <&replicator_out>;
2312 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2316 clock-names = "apb_pclk";
2320 out-ports {
2323 remote-endpoint = <&merge_funnel_in0>;
2328 in-ports {
2331 remote-endpoint = <&stm_out>;
2338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2342 clock-names = "apb_pclk";
2346 out-ports {
2349 remote-endpoint = <&merge_funnel_in1>;
2354 in-ports {
2357 remote-endpoint = <&funnel_apss1_out>;
2364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2368 clock-names = "apb_pclk";
2372 out-ports {
2375 remote-endpoint = <&etf_in>;
2380 in-ports {
2381 #address-cells = <1>;
2382 #size-cells = <0>;
2387 remote-endpoint = <&funnel_in0_out>;
2394 remote-endpoint = <&funnel_in1_out>;
2401 compatible = "arm,coresight-etm4x", "arm,primecell";
2405 clock-names = "apb_pclk";
2406 arm,coresight-loses-context-with-cpu;
2412 out-ports {
2415 remote-endpoint = <&funnel_apss0_in0>;
2422 compatible = "arm,coresight-etm4x", "arm,primecell";
2426 clock-names = "apb_pclk";
2427 arm,coresight-loses-context-with-cpu;
2433 out-ports {
2436 remote-endpoint = <&funnel_apss0_in1>;
2443 compatible = "arm,coresight-etm4x", "arm,primecell";
2447 clock-names = "apb_pclk";
2448 arm,coresight-loses-context-with-cpu;
2454 out-ports {
2457 remote-endpoint = <&funnel_apss0_in2>;
2464 compatible = "arm,coresight-etm4x", "arm,primecell";
2468 clock-names = "apb_pclk";
2469 arm,coresight-loses-context-with-cpu;
2475 out-ports {
2478 remote-endpoint = <&funnel_apss0_in3>;
2485 compatible = "arm,coresight-etm4x", "arm,primecell";
2489 clock-names = "apb_pclk";
2490 arm,coresight-loses-context-with-cpu;
2496 out-ports {
2499 remote-endpoint = <&funnel_apss0_in4>;
2506 compatible = "arm,coresight-etm4x", "arm,primecell";
2510 clock-names = "apb_pclk";
2511 arm,coresight-loses-context-with-cpu;
2517 out-ports {
2520 remote-endpoint = <&funnel_apss0_in5>;
2527 compatible = "arm,coresight-etm4x", "arm,primecell";
2531 clock-names = "apb_pclk";
2532 arm,coresight-loses-context-with-cpu;
2538 out-ports {
2541 remote-endpoint = <&funnel_apss0_in6>;
2548 compatible = "arm,coresight-etm4x", "arm,primecell";
2552 clock-names = "apb_pclk";
2553 arm,coresight-loses-context-with-cpu;
2559 out-ports {
2562 remote-endpoint = <&funnel_apss0_in7>;
2569 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2573 clock-names = "apb_pclk";
2577 out-ports {
2580 remote-endpoint = <&funnel_apss1_in>;
2585 in-ports {
2586 #address-cells = <1>;
2587 #size-cells = <0>;
2592 remote-endpoint = <&etm0_out>;
2599 remote-endpoint = <&etm1_out>;
2606 remote-endpoint = <&etm2_out>;
2613 remote-endpoint = <&etm3_out>;
2620 remote-endpoint = <&etm4_out>;
2627 remote-endpoint = <&etm5_out>;
2634 remote-endpoint = <&etm6_out>;
2641 remote-endpoint = <&etm7_out>;
2648 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2652 clock-names = "apb_pclk";
2656 out-ports {
2659 remote-endpoint = <&funnel_in1_in>;
2664 in-ports {
2667 remote-endpoint = <&funnel_apss0_out>;
2674 compatible = "qcom,sm6115-adsp-pas";
2677 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2682 interrupt-names = "wdog", "fatal", "ready",
2683 "handover", "stop-ack";
2686 clock-names = "xo";
2688 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2691 memory-region = <&pil_adsp_mem>;
2693 qcom,smem-states = <&adsp_smp2p_out 0>;
2694 qcom,smem-state-names = "stop";
2698 glink-edge {
2701 qcom,remote-pid = <2>;
2706 qcom,glink-channels = "fastrpcglink-apps-dsp";
2708 qcom,non-secure-domain;
2709 #address-cells = <1>;
2710 #size-cells = <0>;
2712 compute-cb@3 {
2713 compatible = "qcom,fastrpc-compute-cb";
2718 compute-cb@4 {
2719 compatible = "qcom,fastrpc-compute-cb";
2724 compute-cb@5 {
2725 compatible = "qcom,fastrpc-compute-cb";
2730 compute-cb@6 {
2731 compatible = "qcom,fastrpc-compute-cb";
2736 compute-cb@7 {
2737 compatible = "qcom,fastrpc-compute-cb";
2746 compatible = "qcom,sm6115-cdsp-pas";
2749 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2754 interrupt-names = "wdog", "fatal", "ready",
2755 "handover", "stop-ack";
2758 clock-names = "xo";
2760 power-domains = <&rpmpd SM6115_VDDCX>;
2762 memory-region = <&pil_cdsp_mem>;
2764 qcom,smem-states = <&cdsp_smp2p_out 0>;
2765 qcom,smem-state-names = "stop";
2769 glink-edge {
2772 qcom,remote-pid = <5>;
2777 qcom,glink-channels = "fastrpcglink-apps-dsp";
2779 qcom,non-secure-domain;
2780 #address-cells = <1>;
2781 #size-cells = <0>;
2783 compute-cb@1 {
2784 compatible = "qcom,fastrpc-compute-cb";
2789 compute-cb@2 {
2790 compatible = "qcom,fastrpc-compute-cb";
2795 compute-cb@3 {
2796 compatible = "qcom,fastrpc-compute-cb";
2801 compute-cb@4 {
2802 compatible = "qcom,fastrpc-compute-cb";
2807 compute-cb@5 {
2808 compatible = "qcom,fastrpc-compute-cb";
2813 compute-cb@6 {
2814 compatible = "qcom,fastrpc-compute-cb";
2825 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2827 #iommu-cells = <2>;
2828 #global-interrupts = <1>;
2898 compatible = "qcom,wcn3990-wifi";
2900 reg-names = "membase";
2901 memory-region = <&wlan_msa_mem>;
2915 qcom,msa-fixed-perm;
2920 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2927 compatible = "qcom,sm6115-apcs-hmss-global",
2928 "qcom,msm8994-apcs-kpss-global";
2931 #mbox-cells = <1>;
2935 compatible = "arm,armv7-timer-mem";
2937 #address-cells = <2>;
2938 #size-cells = <1>;
2940 clock-frequency = <19200000>;
2944 frame-number = <0>;
2951 frame-number = <1>;
2958 frame-number = <2>;
2965 frame-number = <3>;
2972 frame-number = <4>;
2979 frame-number = <5>;
2986 frame-number = <6>;
2992 intc: interrupt-controller@f200000 {
2993 compatible = "arm,gic-v3";
2996 #interrupt-cells = <3>;
2997 interrupt-controller;
2998 interrupt-parent = <&intc>;
2999 #redistributor-regions = <1>;
3000 redistributor-stride = <0x0 0x20000>;
3005 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
3009 reg-names = "freq-domain0", "freq-domain1";
3011 clock-names = "xo", "alternate";
3013 #freq-domain-cells = <1>;
3014 #clock-cells = <1>;
3018 thermal-zones {
3019 mapss-thermal {
3020 thermal-sensors = <&tsens0 0>;
3023 trip-point0 {
3029 trip-point1 {
3037 cdsp-hvx-thermal {
3038 thermal-sensors = <&tsens0 1>;
3041 trip-point0 {
3047 trip-point1 {
3055 wlan-thermal {
3056 thermal-sensors = <&tsens0 2>;
3059 trip-point0 {
3065 trip-point1 {
3073 camera-thermal {
3074 thermal-sensors = <&tsens0 3>;
3077 trip-point0 {
3083 trip-point1 {
3091 video-thermal {
3092 thermal-sensors = <&tsens0 4>;
3095 trip-point0 {
3101 trip-point1 {
3109 modem1-thermal {
3110 thermal-sensors = <&tsens0 5>;
3113 trip-point0 {
3119 trip-point1 {
3127 cpu4-thermal {
3128 thermal-sensors = <&tsens0 6>;
3131 cpu4_alert0: trip-point0 {
3137 cpu4_alert1: trip-point1 {
3143 cpu4_crit: cpu-crit {
3151 cpu5-thermal {
3152 thermal-sensors = <&tsens0 7>;
3155 cpu5_alert0: trip-point0 {
3161 cpu5_alert1: trip-point1 {
3167 cpu5_crit: cpu-crit {
3175 cpu6-thermal {
3176 thermal-sensors = <&tsens0 8>;
3179 cpu6_alert0: trip-point0 {
3185 cpu6_alert1: trip-point1 {
3191 cpu6_crit: cpu-crit {
3199 cpu7-thermal {
3200 thermal-sensors = <&tsens0 9>;
3203 cpu7_alert0: trip-point0 {
3209 cpu7_alert1: trip-point1 {
3215 cpu7_crit: cpu-crit {
3223 cpu45-thermal {
3224 thermal-sensors = <&tsens0 10>;
3227 cpu45_alert0: trip-point0 {
3233 cpu45_alert1: trip-point1 {
3239 cpu45_crit: cpu-crit {
3247 cpu67-thermal {
3248 thermal-sensors = <&tsens0 11>;
3251 cpu67_alert0: trip-point0 {
3257 cpu67_alert1: trip-point1 {
3263 cpu67_crit: cpu-crit {
3271 cpu0123-thermal {
3272 thermal-sensors = <&tsens0 12>;
3275 cpu0123_alert0: trip-point0 {
3281 cpu0123_alert1: trip-point1 {
3287 cpu0123_crit: cpu-crit {
3295 modem0-thermal {
3296 thermal-sensors = <&tsens0 13>;
3299 trip-point0 {
3305 trip-point1 {
3313 display-thermal {
3314 thermal-sensors = <&tsens0 14>;
3317 trip-point0 {
3323 trip-point1 {
3331 gpu-thermal {
3332 polling-delay-passive = <250>;
3334 thermal-sensors = <&tsens0 15>;
3336 cooling-maps {
3339 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3344 gpu_alert0: trip-point0 {
3350 trip-point1 {
3360 compatible = "arm,armv8-timer";