Lines Matching +full:freq +full:- +full:domain1
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
15 #include <dt-bindings/interconnect/qcom,sm6115.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,apr.h>
19 #include <dt-bindings/sound/qcom,q6asm.h>
20 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
21 #include <dt-bindings/thermal/thermal.h>
24 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
32 xo_board: xo-board {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
44 #address-cells = <2>;
45 #size-cells = <0>;
52 capacity-dmips-mhz = <1024>;
53 dynamic-power-coefficient = <100>;
54 enable-method = "psci";
55 next-level-cache = <&l2_0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 power-domains = <&cpu_pd0>;
58 power-domain-names = "psci";
59 l2_0: l2-cache {
61 cache-level = <2>;
62 cache-unified;
71 capacity-dmips-mhz = <1024>;
72 dynamic-power-coefficient = <100>;
73 enable-method = "psci";
74 next-level-cache = <&l2_0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
76 power-domains = <&cpu_pd1>;
77 power-domain-names = "psci";
85 capacity-dmips-mhz = <1024>;
86 dynamic-power-coefficient = <100>;
87 enable-method = "psci";
88 next-level-cache = <&l2_0>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
90 power-domains = <&cpu_pd2>;
91 power-domain-names = "psci";
99 capacity-dmips-mhz = <1024>;
100 dynamic-power-coefficient = <100>;
101 enable-method = "psci";
102 next-level-cache = <&l2_0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
104 power-domains = <&cpu_pd3>;
105 power-domain-names = "psci";
113 enable-method = "psci";
114 capacity-dmips-mhz = <1638>;
115 dynamic-power-coefficient = <282>;
116 next-level-cache = <&l2_1>;
117 qcom,freq-domain = <&cpufreq_hw 1>;
118 power-domains = <&cpu_pd4>;
119 power-domain-names = "psci";
120 l2_1: l2-cache {
122 cache-level = <2>;
123 cache-unified;
132 capacity-dmips-mhz = <1638>;
133 dynamic-power-coefficient = <282>;
134 enable-method = "psci";
135 next-level-cache = <&l2_1>;
136 qcom,freq-domain = <&cpufreq_hw 1>;
137 power-domains = <&cpu_pd5>;
138 power-domain-names = "psci";
146 capacity-dmips-mhz = <1638>;
147 dynamic-power-coefficient = <282>;
148 enable-method = "psci";
149 next-level-cache = <&l2_1>;
150 qcom,freq-domain = <&cpufreq_hw 1>;
151 power-domains = <&cpu_pd6>;
152 power-domain-names = "psci";
160 capacity-dmips-mhz = <1638>;
161 dynamic-power-coefficient = <282>;
162 enable-method = "psci";
163 next-level-cache = <&l2_1>;
164 qcom,freq-domain = <&cpufreq_hw 1>;
165 power-domains = <&cpu_pd7>;
166 power-domain-names = "psci";
169 cpu-map {
207 idle-states {
208 entry-method = "psci";
210 little_cpu_sleep_0: cpu-sleep-0-0 {
211 compatible = "arm,idle-state";
212 idle-state-name = "silver-rail-power-collapse";
213 arm,psci-suspend-param = <0x40000003>;
214 entry-latency-us = <290>;
215 exit-latency-us = <376>;
216 min-residency-us = <1182>;
217 local-timer-stop;
220 big_cpu_sleep_0: cpu-sleep-1-0 {
221 compatible = "arm,idle-state";
222 idle-state-name = "gold-rail-power-collapse";
223 arm,psci-suspend-param = <0x40000003>;
224 entry-latency-us = <297>;
225 exit-latency-us = <324>;
226 min-residency-us = <1110>;
227 local-timer-stop;
231 domain-idle-states {
232 cluster_0_sleep_0: cluster-sleep-0-0 {
234 compatible = "domain-idle-state";
235 arm,psci-suspend-param = <0x40000022>;
236 entry-latency-us = <360>;
237 exit-latency-us = <421>;
238 min-residency-us = <782>;
241 cluster_0_sleep_1: cluster-sleep-0-1 {
243 compatible = "domain-idle-state";
244 arm,psci-suspend-param = <0x41000044>;
245 entry-latency-us = <800>;
246 exit-latency-us = <2118>;
247 min-residency-us = <7376>;
250 cluster_1_sleep_0: cluster-sleep-1-0 {
252 compatible = "domain-idle-state";
253 arm,psci-suspend-param = <0x40000042>;
254 entry-latency-us = <314>;
255 exit-latency-us = <345>;
256 min-residency-us = <660>;
259 cluster_1_sleep_1: cluster-sleep-1-1 {
261 compatible = "domain-idle-state";
262 arm,psci-suspend-param = <0x41000044>;
263 entry-latency-us = <640>;
264 exit-latency-us = <1654>;
265 min-residency-us = <8094>;
272 compatible = "qcom,scm-sm6115", "qcom,scm";
273 #reset-cells = <1>;
285 qup_opp_table: opp-table-qup {
286 compatible = "operating-points-v2";
288 opp-75000000 {
289 opp-hz = /bits/ 64 <75000000>;
290 required-opps = <&rpmpd_opp_low_svs>;
293 opp-100000000 {
294 opp-hz = /bits/ 64 <100000000>;
295 required-opps = <&rpmpd_opp_svs>;
298 opp-128000000 {
299 opp-hz = /bits/ 64 <128000000>;
300 required-opps = <&rpmpd_opp_nom>;
305 compatible = "arm,armv8-pmuv3";
310 compatible = "arm,psci-1.0";
313 cpu_pd0: power-domain-cpu0 {
314 #power-domain-cells = <0>;
315 power-domains = <&cluster_0_pd>;
316 domain-idle-states = <&little_cpu_sleep_0>;
319 cpu_pd1: power-domain-cpu1 {
320 #power-domain-cells = <0>;
321 power-domains = <&cluster_0_pd>;
322 domain-idle-states = <&little_cpu_sleep_0>;
325 cpu_pd2: power-domain-cpu2 {
326 #power-domain-cells = <0>;
327 power-domains = <&cluster_0_pd>;
328 domain-idle-states = <&little_cpu_sleep_0>;
331 cpu_pd3: power-domain-cpu3 {
332 #power-domain-cells = <0>;
333 power-domains = <&cluster_0_pd>;
334 domain-idle-states = <&little_cpu_sleep_0>;
337 cpu_pd4: power-domain-cpu4 {
338 #power-domain-cells = <0>;
339 power-domains = <&cluster_1_pd>;
340 domain-idle-states = <&big_cpu_sleep_0>;
343 cpu_pd5: power-domain-cpu5 {
344 #power-domain-cells = <0>;
345 power-domains = <&cluster_1_pd>;
346 domain-idle-states = <&big_cpu_sleep_0>;
349 cpu_pd6: power-domain-cpu6 {
350 #power-domain-cells = <0>;
351 power-domains = <&cluster_1_pd>;
352 domain-idle-states = <&big_cpu_sleep_0>;
355 cpu_pd7: power-domain-cpu7 {
356 #power-domain-cells = <0>;
357 power-domains = <&cluster_1_pd>;
358 domain-idle-states = <&big_cpu_sleep_0>;
361 cluster_0_pd: power-domain-cpu-cluster0 {
362 #power-domain-cells = <0>;
363 domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>;
366 cluster_1_pd: power-domain-cpu-cluster1 {
367 #power-domain-cells = <0>;
368 domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>;
373 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
375 glink-edge {
376 compatible = "qcom,glink-rpm";
379 qcom,rpm-msg-ram = <&rpm_msg_ram>;
382 rpm_requests: rpm-requests {
383 compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm";
384 qcom,glink-channels = "rpm_requests";
386 rpmcc: clock-controller {
387 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
389 clock-names = "xo";
390 #clock-cells = <1>;
393 rpmpd: power-controller {
394 compatible = "qcom,sm6115-rpmpd";
395 #power-domain-cells = <1>;
396 operating-points-v2 = <&rpmpd_opp_table>;
398 rpmpd_opp_table: opp-table {
399 compatible = "operating-points-v2";
402 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
406 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
410 opp-level = <RPM_SMD_LEVEL_SVS>;
414 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
418 opp-level = <RPM_SMD_LEVEL_NOM>;
422 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
426 opp-level = <RPM_SMD_LEVEL_TURBO>;
430 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
438 reserved_memory: reserved-memory {
439 #address-cells = <2>;
440 #size-cells = <2>;
445 no-map;
450 no-map;
455 no-map;
461 no-map;
464 qcom,rpm-msg-ram = <&rpm_msg_ram>;
469 no-map;
474 no-map;
479 no-map;
484 no-map;
489 no-map;
494 no-map;
499 no-map;
504 no-map;
509 no-map;
514 no-map;
519 no-map;
524 no-map;
528 compatible = "qcom,rmtfs-mem";
530 no-map;
532 qcom,client-id = <1>;
537 smp2p-adsp {
545 qcom,local-pid = <0>;
546 qcom,remote-pid = <2>;
548 adsp_smp2p_out: master-kernel {
549 qcom,entry-name = "master-kernel";
550 #qcom,smem-state-cells = <1>;
553 adsp_smp2p_in: slave-kernel {
554 qcom,entry-name = "slave-kernel";
556 interrupt-controller;
557 #interrupt-cells = <2>;
561 smp2p-cdsp {
569 qcom,local-pid = <0>;
570 qcom,remote-pid = <5>;
572 cdsp_smp2p_out: master-kernel {
573 qcom,entry-name = "master-kernel";
574 #qcom,smem-state-cells = <1>;
577 cdsp_smp2p_in: slave-kernel {
578 qcom,entry-name = "slave-kernel";
580 interrupt-controller;
581 #interrupt-cells = <2>;
585 smp2p-mpss {
593 qcom,local-pid = <0>;
594 qcom,remote-pid = <1>;
596 modem_smp2p_out: master-kernel {
597 qcom,entry-name = "master-kernel";
598 #qcom,smem-state-cells = <1>;
601 modem_smp2p_in: slave-kernel {
602 qcom,entry-name = "slave-kernel";
604 interrupt-controller;
605 #interrupt-cells = <2>;
610 compatible = "simple-bus";
611 #address-cells = <2>;
612 #size-cells = <2>;
614 dma-ranges = <0 0 0 0 0x10 0>;
617 compatible = "qcom,tcsr-mutex";
619 #hwlock-cells = <1>;
623 compatible = "qcom,sm6115-tcsr", "syscon";
628 compatible = "qcom,sm6115-tlmm";
632 reg-names = "west", "south", "east";
634 gpio-controller;
635 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
636 #gpio-cells = <2>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
640 qup_i2c0_default: qup-i2c0-default-state {
643 drive-strength = <2>;
644 bias-pull-up;
647 qup_i2c1_default: qup-i2c1-default-state {
650 drive-strength = <2>;
651 bias-pull-up;
654 qup_i2c2_default: qup-i2c2-default-state {
657 drive-strength = <2>;
658 bias-pull-up;
661 qup_i2c3_default: qup-i2c3-default-state {
664 drive-strength = <2>;
665 bias-pull-up;
668 qup_i2c4_default: qup-i2c4-default-state {
671 drive-strength = <2>;
672 bias-pull-up;
675 qup_i2c5_default: qup-i2c5-default-state {
678 drive-strength = <2>;
679 bias-pull-up;
682 qup_spi0_default: qup-spi0-default-state {
685 drive-strength = <2>;
686 bias-pull-up;
689 qup_spi1_default: qup-spi1-default-state {
692 drive-strength = <2>;
693 bias-pull-up;
696 qup_spi2_default: qup-spi2-default-state {
699 drive-strength = <2>;
700 bias-pull-up;
703 qup_spi3_default: qup-spi3-default-state {
706 drive-strength = <2>;
707 bias-pull-up;
710 qup_spi4_default: qup-spi4-default-state {
713 drive-strength = <2>;
714 bias-pull-up;
717 qup_spi5_default: qup-spi5-default-state {
720 drive-strength = <2>;
721 bias-pull-up;
724 qup_uart4_default: qup-uart4-default-state {
727 drive-strength = <2>;
728 bias-disable;
731 sdc1_state_on: sdc1-on-state {
732 clk-pins {
734 bias-disable;
735 drive-strength = <16>;
738 cmd-pins {
740 bias-pull-up;
741 drive-strength = <10>;
744 data-pins {
746 bias-pull-up;
747 drive-strength = <10>;
750 rclk-pins {
752 bias-pull-down;
756 sdc1_state_off: sdc1-off-state {
757 clk-pins {
759 bias-disable;
760 drive-strength = <2>;
763 cmd-pins {
765 bias-pull-up;
766 drive-strength = <2>;
769 data-pins {
771 bias-pull-up;
772 drive-strength = <2>;
775 rclk-pins {
777 bias-pull-down;
781 sdc2_state_on: sdc2-on-state {
782 clk-pins {
784 bias-disable;
785 drive-strength = <16>;
788 cmd-pins {
790 bias-pull-up;
791 drive-strength = <10>;
794 data-pins {
796 bias-pull-up;
797 drive-strength = <10>;
801 sdc2_state_off: sdc2-off-state {
802 clk-pins {
804 bias-disable;
805 drive-strength = <2>;
808 cmd-pins {
810 bias-pull-up;
811 drive-strength = <2>;
814 data-pins {
816 bias-pull-up;
817 drive-strength = <2>;
823 compatible = "qcom,sm6115-lpass-lpi-pinctrl";
828 clock-names = "audio";
830 gpio-controller;
831 #gpio-cells = <2>;
832 gpio-ranges = <&lpass_tlmm 0 0 19>;
836 gcc: clock-controller@1400000 {
837 compatible = "qcom,gcc-sm6115";
840 clock-names = "bi_tcxo", "sleep_clk";
841 #clock-cells = <1>;
842 #reset-cells = <1>;
843 #power-domain-cells = <1>;
847 compatible = "qcom,sm6115-qusb2-phy";
849 #phy-cells = <0>;
852 clock-names = "cfg_ahb", "ref";
855 nvmem-cells = <&qusb2_hstx_trim>;
860 cryptobam: dma-controller@1b04000 {
861 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
865 clock-names = "bam_clk";
866 #dma-cells = <1>;
868 qcom,controlled-remotely;
877 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
880 clock-names = "core";
883 dma-names = "rx", "tx";
892 compatible = "qcom,sm6115-qmp-usb3-phy";
899 clock-names = "cfg_ahb",
906 reset-names = "phy", "phy_phy";
908 #clock-cells = <0>;
909 clock-output-names = "usb3_phy_pipe_clk_src";
911 #phy-cells = <0>;
912 orientation-switch;
914 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
919 #address-cells = <1>;
920 #size-cells = <0>;
933 remote-endpoint = <&usb_dwc3_ss>;
940 compatible = "qcom,sm6115-snoc";
946 clock-names = "cpu_axi",
950 #interconnect-cells = <2>;
952 clk_virt: interconnect-clk {
953 compatible = "qcom,sm6115-clk-virt";
954 #interconnect-cells = <2>;
957 mmrt_virt: interconnect-mmrt {
958 compatible = "qcom,sm6115-mmrt-virt";
959 #interconnect-cells = <2>;
962 mmnrt_virt: interconnect-mmnrt {
963 compatible = "qcom,sm6115-mmnrt-virt";
964 #interconnect-cells = <2>;
969 compatible = "qcom,sm6115-cnoc";
972 clock-names = "usb_axi";
973 #interconnect-cells = <2>;
977 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
979 #address-cells = <1>;
980 #size-cells = <1>;
982 qusb2_hstx_trim: hstx-trim@25b {
987 gpu_speed_bin: gpu-speed-bin@6006 {
994 compatible = "qcom,prng-ee";
997 clock-names = "core";
1001 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
1005 operating-points-v2 = <&cpu_bwmon_opp_table>;
1009 cpu_bwmon_opp_table: opp-table {
1010 compatible = "operating-points-v2";
1012 opp-0 {
1013 opp-peak-kBps = <(200 * 4 * 1000)>;
1016 opp-1 {
1017 opp-peak-kBps = <(300 * 4 * 1000)>;
1020 opp-2 {
1021 opp-peak-kBps = <(451 * 4 * 1000)>;
1024 opp-3 {
1025 opp-peak-kBps = <(547 * 4 * 1000)>;
1028 opp-4 {
1029 opp-peak-kBps = <(681 * 4 * 1000)>;
1032 opp-5 {
1033 opp-peak-kBps = <(768 * 4 * 1000)>;
1036 opp-6 {
1037 opp-peak-kBps = <(1017 * 4 * 1000)>;
1040 opp-7 {
1041 opp-peak-kBps = <(1353 * 4 * 1000)>;
1044 opp-8 {
1045 opp-peak-kBps = <(1555 * 4 * 1000)>;
1048 opp-9 {
1049 opp-peak-kBps = <(1804 * 4 * 1000)>;
1055 compatible = "qcom,spmi-pmic-arb";
1061 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1062 interrupt-names = "periph_irq";
1066 #address-cells = <2>;
1067 #size-cells = <0>;
1068 interrupt-controller;
1069 #interrupt-cells = <4>;
1072 tsens0: thermal-sensor@4411000 {
1073 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1079 interrupt-names = "uplow", "critical";
1080 #thermal-sensor-cells = <1>;
1084 compatible = "qcom,sm6115-bimc";
1086 #interconnect-cells = <2>;
1090 compatible = "qcom,rpm-msg-ram";
1095 compatible = "qcom,rpm-stats";
1100 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1104 reg-names = "hc", "cqhci", "ice";
1108 interrupt-names = "hc_irq", "pwr_irq";
1114 clock-names = "iface", "core", "xo", "ice";
1118 power-domains = <&rpmpd SM6115_VDDCX>;
1119 operating-points-v2 = <&sdhc1_opp_table>;
1125 interconnect-names = "sdhc-ddr",
1126 "cpu-sdhc";
1128 bus-width = <8>;
1131 sdhc1_opp_table: opp-table {
1132 compatible = "operating-points-v2";
1134 opp-100000000 {
1135 opp-hz = /bits/ 64 <100000000>;
1136 required-opps = <&rpmpd_opp_low_svs>;
1137 opp-peak-kBps = <250000 133320>;
1138 opp-avg-kBps = <102400 65000>;
1141 opp-192000000 {
1142 opp-hz = /bits/ 64 <192000000>;
1143 required-opps = <&rpmpd_opp_low_svs>;
1144 opp-peak-kBps = <800000 300000>;
1145 opp-avg-kBps = <204800 200000>;
1148 opp-384000000 {
1149 opp-hz = /bits/ 64 <384000000>;
1150 required-opps = <&rpmpd_opp_svs_plus>;
1151 opp-peak-kBps = <800000 300000>;
1152 opp-avg-kBps = <204800 200000>;
1158 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1160 reg-names = "hc";
1164 interrupt-names = "hc_irq", "pwr_irq";
1169 clock-names = "iface", "core", "xo";
1171 power-domains = <&rpmpd SM6115_VDDCX>;
1172 operating-points-v2 = <&sdhc2_opp_table>;
1179 interconnect-names = "sdhc-ddr",
1180 "cpu-sdhc";
1182 bus-width = <4>;
1183 qcom,dll-config = <0x0007642c>;
1184 qcom,ddr-config = <0x80040868>;
1187 sdhc2_opp_table: opp-table {
1188 compatible = "operating-points-v2";
1190 opp-100000000 {
1191 opp-hz = /bits/ 64 <100000000>;
1192 required-opps = <&rpmpd_opp_low_svs>;
1193 opp-peak-kBps = <250000 133320>;
1194 opp-avg-kBps = <261438 150000>;
1197 opp-202000000 {
1198 opp-hz = /bits/ 64 <202000000>;
1199 required-opps = <&rpmpd_opp_nom>;
1200 opp-peak-kBps = <800000 300000>;
1201 opp-avg-kBps = <261438 300000>;
1207 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1209 reg-names = "std", "ice";
1212 phy-names = "ufsphy";
1213 lanes-per-direction = <1>;
1214 #reset-cells = <1>;
1216 reset-names = "rst";
1218 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1229 clock-names = "core_clk",
1238 freq-table-hz = <50000000 200000000>,
1251 compatible = "qcom,sm6115-qmp-ufs-phy";
1257 clock-names = "ref",
1261 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1264 reset-names = "ufsphy";
1266 #phy-cells = <0>;
1271 gpi_dma0: dma-controller@4a00000 {
1272 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1284 dma-channels = <10>;
1285 dma-channel-mask = <0xf>;
1287 #dma-cells = <3>;
1292 compatible = "qcom,geni-se-qup";
1294 clock-names = "m-ahb", "s-ahb";
1297 #address-cells = <2>;
1298 #size-cells = <2>;
1304 compatible = "qcom,geni-i2c";
1306 clock-names = "se";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_i2c0_default>;
1313 dma-names = "tx", "rx";
1320 interconnect-names = "qup-core",
1321 "qup-config",
1322 "qup-memory";
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1329 compatible = "qcom,geni-spi";
1331 clock-names = "se";
1333 pinctrl-names = "default";
1334 pinctrl-0 = <&qup_spi0_default>;
1338 dma-names = "tx", "rx";
1345 interconnect-names = "qup-core",
1346 "qup-config",
1347 "qup-memory";
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1354 compatible = "qcom,geni-i2c";
1356 clock-names = "se";
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&qup_i2c1_default>;
1363 dma-names = "tx", "rx";
1370 interconnect-names = "qup-core",
1371 "qup-config",
1372 "qup-memory";
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1379 compatible = "qcom,geni-spi";
1381 clock-names = "se";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_spi1_default>;
1388 dma-names = "tx", "rx";
1395 interconnect-names = "qup-core",
1396 "qup-config",
1397 "qup-memory";
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1404 compatible = "qcom,geni-i2c";
1406 clock-names = "se";
1408 pinctrl-names = "default";
1409 pinctrl-0 = <&qup_i2c2_default>;
1413 dma-names = "tx", "rx";
1420 interconnect-names = "qup-core",
1421 "qup-config",
1422 "qup-memory";
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1429 compatible = "qcom,geni-spi";
1431 clock-names = "se";
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&qup_spi2_default>;
1438 dma-names = "tx", "rx";
1445 interconnect-names = "qup-core",
1446 "qup-config",
1447 "qup-memory";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1454 compatible = "qcom,geni-i2c";
1456 clock-names = "se";
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_i2c3_default>;
1463 dma-names = "tx", "rx";
1470 interconnect-names = "qup-core",
1471 "qup-config",
1472 "qup-memory";
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1479 compatible = "qcom,geni-spi";
1481 clock-names = "se";
1483 pinctrl-names = "default";
1484 pinctrl-0 = <&qup_spi3_default>;
1488 dma-names = "tx", "rx";
1495 interconnect-names = "qup-core",
1496 "qup-config",
1497 "qup-memory";
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1504 compatible = "qcom,geni-uart";
1506 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1508 clock-names = "se";
1509 power-domains = <&rpmpd SM6115_VDDCX>;
1510 operating-points-v2 = <&qup_opp_table>;
1515 interconnect-names = "qup-core",
1516 "qup-config";
1521 compatible = "qcom,geni-i2c";
1523 clock-names = "se";
1525 pinctrl-names = "default";
1526 pinctrl-0 = <&qup_i2c4_default>;
1530 dma-names = "tx", "rx";
1537 interconnect-names = "qup-core",
1538 "qup-config",
1539 "qup-memory";
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1546 compatible = "qcom,geni-spi";
1548 clock-names = "se";
1550 pinctrl-names = "default";
1551 pinctrl-0 = <&qup_spi4_default>;
1555 dma-names = "tx", "rx";
1562 interconnect-names = "qup-core",
1563 "qup-config",
1564 "qup-memory";
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1571 compatible = "qcom,geni-debug-uart";
1573 clock-names = "se";
1575 pinctrl-names = "default";
1576 pinctrl-0 = <&qup_uart4_default>;
1582 interconnect-names = "qup-core",
1583 "qup-config";
1588 compatible = "qcom,geni-i2c";
1590 clock-names = "se";
1592 pinctrl-names = "default";
1593 pinctrl-0 = <&qup_i2c5_default>;
1597 dma-names = "tx", "rx";
1604 interconnect-names = "qup-core",
1605 "qup-config",
1606 "qup-memory";
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1613 compatible = "qcom,geni-spi";
1615 clock-names = "se";
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&qup_spi5_default>;
1622 dma-names = "tx", "rx";
1629 interconnect-names = "qup-core",
1630 "qup-config",
1631 "qup-memory";
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1639 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1641 #address-cells = <2>;
1642 #size-cells = <2>;
1651 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1653 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1655 assigned-clock-rates = <19200000>, <66666667>;
1661 interrupt-names = "pwr_event",
1667 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1668 /* TODO: USB<->IPA path */
1673 interconnect-names = "usb-ddr",
1674 "apps-usb";
1683 phy-names = "usb2-phy", "usb3-phy";
1687 snps,has-lpm-erratum;
1688 snps,hird-threshold = /bits/ 8 <0x10>;
1690 snps,parkmode-disable-ss-quirk;
1692 usb-role-switch;
1695 #address-cells = <1>;
1696 #size-cells = <0>;
1709 remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1717 compatible = "qcom,adreno-610.0", "qcom,adreno";
1719 reg-names = "kgsl_3d0_reg_memory";
1728 clock-names = "core",
1738 operating-points-v2 = <&gpu_opp_table>;
1739 power-domains = <&rpmpd SM6115_VDDCX>;
1742 nvmem-cells = <&gpu_speed_bin>;
1743 nvmem-cell-names = "speed_bin";
1744 #cooling-cells = <2>;
1748 zap-shader {
1749 memory-region = <&pil_gpu_mem>;
1752 gpu_opp_table: opp-table {
1753 compatible = "operating-points-v2";
1755 opp-320000000 {
1756 opp-hz = /bits/ 64 <320000000>;
1757 required-opps = <&rpmpd_opp_low_svs>;
1758 opp-supported-hw = <0x1f>;
1761 opp-465000000 {
1762 opp-hz = /bits/ 64 <465000000>;
1763 required-opps = <&rpmpd_opp_svs>;
1764 opp-supported-hw = <0x1f>;
1767 opp-600000000 {
1768 opp-hz = /bits/ 64 <600000000>;
1769 required-opps = <&rpmpd_opp_svs_plus>;
1770 opp-supported-hw = <0x1f>;
1773 opp-745000000 {
1774 opp-hz = /bits/ 64 <745000000>;
1775 required-opps = <&rpmpd_opp_nom>;
1776 opp-supported-hw = <0xf>;
1779 opp-820000000 {
1780 opp-hz = /bits/ 64 <820000000>;
1781 required-opps = <&rpmpd_opp_nom_plus>;
1782 opp-supported-hw = <0x7>;
1785 opp-900000000 {
1786 opp-hz = /bits/ 64 <900000000>;
1787 required-opps = <&rpmpd_opp_turbo>;
1788 opp-supported-hw = <0x7>;
1792 opp-950000000 {
1793 opp-hz = /bits/ 64 <950000000>;
1794 required-opps = <&rpmpd_opp_turbo_plus>;
1795 opp-supported-hw = <0x4>;
1798 opp-980000000 {
1799 opp-hz = /bits/ 64 <980000000>;
1800 required-opps = <&rpmpd_opp_turbo_plus>;
1801 opp-supported-hw = <0x3>;
1807 compatible = "qcom,adreno-gmu-wrapper";
1809 reg-names = "gmu";
1810 power-domains = <&gpucc GPU_CX_GDSC>,
1812 power-domain-names = "cx", "gx";
1815 gpucc: clock-controller@5990000 {
1816 compatible = "qcom,sm6115-gpucc";
1821 #clock-cells = <1>;
1822 #reset-cells = <1>;
1823 #power-domain-cells = <1>;
1827 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1828 "qcom,smmu-500", "arm,mmu-500";
1843 clock-names = "mem",
1846 power-domains = <&gpucc GPU_CX_GDSC>;
1848 #global-interrupts = <1>;
1849 #iommu-cells = <2>;
1852 mdss: display-subsystem@5e00000 {
1853 compatible = "qcom,sm6115-mdss";
1855 reg-names = "mdss";
1857 power-domains = <&dispcc MDSS_GDSC>;
1864 interrupt-controller;
1865 #interrupt-cells = <1>;
1874 interconnect-names = "mdp0-mem",
1875 "cpu-cfg";
1877 #address-cells = <2>;
1878 #size-cells = <2>;
1883 mdp: display-controller@5e01000 {
1884 compatible = "qcom,sm6115-dpu";
1887 reg-names = "mdp", "vbif";
1895 clock-names = "bus",
1902 operating-points-v2 = <&mdp_opp_table>;
1903 power-domains = <&rpmpd SM6115_VDDCX>;
1905 interrupt-parent = <&mdss>;
1909 #address-cells = <1>;
1910 #size-cells = <0>;
1915 remote-endpoint = <&mdss_dsi0_in>;
1920 mdp_opp_table: opp-table {
1921 compatible = "operating-points-v2";
1923 opp-19200000 {
1924 opp-hz = /bits/ 64 <19200000>;
1925 required-opps = <&rpmpd_opp_min_svs>;
1928 opp-192000000 {
1929 opp-hz = /bits/ 64 <192000000>;
1930 required-opps = <&rpmpd_opp_low_svs>;
1933 opp-256000000 {
1934 opp-hz = /bits/ 64 <256000000>;
1935 required-opps = <&rpmpd_opp_svs>;
1938 opp-307200000 {
1939 opp-hz = /bits/ 64 <307200000>;
1940 required-opps = <&rpmpd_opp_svs_plus>;
1943 opp-384000000 {
1944 opp-hz = /bits/ 64 <384000000>;
1945 required-opps = <&rpmpd_opp_nom>;
1951 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1953 reg-names = "dsi_ctrl";
1955 interrupt-parent = <&mdss>;
1964 clock-names = "byte",
1971 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1973 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1976 operating-points-v2 = <&dsi_opp_table>;
1977 power-domains = <&rpmpd SM6115_VDDCX>;
1980 #address-cells = <1>;
1981 #size-cells = <0>;
1986 #address-cells = <1>;
1987 #size-cells = <0>;
1992 remote-endpoint = <&dpu_intf1_out>;
2003 dsi_opp_table: opp-table {
2004 compatible = "operating-points-v2";
2006 opp-19200000 {
2007 opp-hz = /bits/ 64 <19200000>;
2008 required-opps = <&rpmpd_opp_min_svs>;
2011 opp-164000000 {
2012 opp-hz = /bits/ 64 <164000000>;
2013 required-opps = <&rpmpd_opp_low_svs>;
2016 opp-187500000 {
2017 opp-hz = /bits/ 64 <187500000>;
2018 required-opps = <&rpmpd_opp_svs>;
2024 compatible = "qcom,dsi-phy-14nm-2290";
2028 reg-names = "dsi_phy",
2032 #clock-cells = <1>;
2033 #phy-cells = <0>;
2037 clock-names = "iface", "ref";
2043 dispcc: clock-controller@5f00000 {
2044 compatible = "qcom,sm6115-dispcc";
2051 #clock-cells = <1>;
2052 #reset-cells = <1>;
2053 #power-domain-cells = <1>;
2057 compatible = "qcom,sm6115-mpss-pas";
2060 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
2066 interrupt-names = "wdog", "fatal", "ready", "handover",
2067 "stop-ack", "shutdown-ack";
2070 clock-names = "xo";
2072 power-domains = <&rpmpd SM6115_VDDCX>;
2074 memory-region = <&pil_modem_mem>;
2076 qcom,smem-states = <&modem_smp2p_out 0>;
2077 qcom,smem-state-names = "stop";
2081 glink-edge {
2084 qcom,remote-pid = <1>;
2090 compatible = "arm,coresight-stm", "arm,primecell";
2093 reg-names = "stm-base", "stm-stimulus-base";
2096 clock-names = "apb_pclk";
2100 out-ports {
2103 remote-endpoint = <&funnel_in0_in>;
2110 compatible = "arm,coresight-cti", "arm,primecell";
2114 clock-names = "apb_pclk";
2120 compatible = "arm,coresight-cti", "arm,primecell";
2124 clock-names = "apb_pclk";
2130 compatible = "arm,coresight-cti", "arm,primecell";
2134 clock-names = "apb_pclk";
2140 compatible = "arm,coresight-cti", "arm,primecell";
2144 clock-names = "apb_pclk";
2150 compatible = "arm,coresight-cti", "arm,primecell";
2154 clock-names = "apb_pclk";
2160 compatible = "arm,coresight-cti", "arm,primecell";
2164 clock-names = "apb_pclk";
2170 compatible = "arm,coresight-cti", "arm,primecell";
2174 clock-names = "apb_pclk";
2180 compatible = "arm,coresight-cti", "arm,primecell";
2184 clock-names = "apb_pclk";
2190 compatible = "arm,coresight-cti", "arm,primecell";
2194 clock-names = "apb_pclk";
2200 compatible = "arm,coresight-cti", "arm,primecell";
2204 clock-names = "apb_pclk";
2210 compatible = "arm,coresight-cti", "arm,primecell";
2214 clock-names = "apb_pclk";
2220 compatible = "arm,coresight-cti", "arm,primecell";
2224 clock-names = "apb_pclk";
2230 compatible = "arm,coresight-cti", "arm,primecell";
2234 clock-names = "apb_pclk";
2240 compatible = "arm,coresight-cti", "arm,primecell";
2244 clock-names = "apb_pclk";
2250 compatible = "arm,coresight-cti", "arm,primecell";
2254 clock-names = "apb_pclk";
2260 compatible = "arm,coresight-cti", "arm,primecell";
2264 clock-names = "apb_pclk";
2270 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2274 clock-names = "apb_pclk";
2278 out-ports {
2281 remote-endpoint = <&etr_in>;
2286 in-ports {
2289 remote-endpoint = <&etf_out>;
2296 compatible = "arm,coresight-tmc", "arm,primecell";
2300 clock-names = "apb_pclk";
2304 in-ports {
2307 remote-endpoint = <&merge_funnel_out>;
2312 out-ports {
2315 remote-endpoint = <&replicator_in>;
2322 compatible = "arm,coresight-tmc", "arm,primecell";
2326 clock-names = "apb_pclk";
2330 in-ports {
2333 remote-endpoint = <&replicator_out>;
2340 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2344 clock-names = "apb_pclk";
2348 out-ports {
2351 remote-endpoint = <&merge_funnel_in0>;
2356 in-ports {
2359 remote-endpoint = <&stm_out>;
2366 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2370 clock-names = "apb_pclk";
2374 out-ports {
2377 remote-endpoint = <&merge_funnel_in1>;
2382 in-ports {
2385 remote-endpoint = <&funnel_apss1_out>;
2392 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2396 clock-names = "apb_pclk";
2400 out-ports {
2403 remote-endpoint = <&etf_in>;
2408 in-ports {
2409 #address-cells = <1>;
2410 #size-cells = <0>;
2415 remote-endpoint = <&funnel_in0_out>;
2422 remote-endpoint = <&funnel_in1_out>;
2429 compatible = "arm,coresight-etm4x", "arm,primecell";
2433 clock-names = "apb_pclk";
2434 arm,coresight-loses-context-with-cpu;
2440 out-ports {
2443 remote-endpoint = <&funnel_apss0_in0>;
2450 compatible = "arm,coresight-etm4x", "arm,primecell";
2454 clock-names = "apb_pclk";
2455 arm,coresight-loses-context-with-cpu;
2461 out-ports {
2464 remote-endpoint = <&funnel_apss0_in1>;
2471 compatible = "arm,coresight-etm4x", "arm,primecell";
2475 clock-names = "apb_pclk";
2476 arm,coresight-loses-context-with-cpu;
2482 out-ports {
2485 remote-endpoint = <&funnel_apss0_in2>;
2492 compatible = "arm,coresight-etm4x", "arm,primecell";
2496 clock-names = "apb_pclk";
2497 arm,coresight-loses-context-with-cpu;
2503 out-ports {
2506 remote-endpoint = <&funnel_apss0_in3>;
2513 compatible = "arm,coresight-etm4x", "arm,primecell";
2517 clock-names = "apb_pclk";
2518 arm,coresight-loses-context-with-cpu;
2524 out-ports {
2527 remote-endpoint = <&funnel_apss0_in4>;
2534 compatible = "arm,coresight-etm4x", "arm,primecell";
2538 clock-names = "apb_pclk";
2539 arm,coresight-loses-context-with-cpu;
2545 out-ports {
2548 remote-endpoint = <&funnel_apss0_in5>;
2555 compatible = "arm,coresight-etm4x", "arm,primecell";
2559 clock-names = "apb_pclk";
2560 arm,coresight-loses-context-with-cpu;
2566 out-ports {
2569 remote-endpoint = <&funnel_apss0_in6>;
2576 compatible = "arm,coresight-etm4x", "arm,primecell";
2580 clock-names = "apb_pclk";
2581 arm,coresight-loses-context-with-cpu;
2587 out-ports {
2590 remote-endpoint = <&funnel_apss0_in7>;
2597 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2601 clock-names = "apb_pclk";
2605 out-ports {
2608 remote-endpoint = <&funnel_apss1_in>;
2613 in-ports {
2614 #address-cells = <1>;
2615 #size-cells = <0>;
2620 remote-endpoint = <&etm0_out>;
2627 remote-endpoint = <&etm1_out>;
2634 remote-endpoint = <&etm2_out>;
2641 remote-endpoint = <&etm3_out>;
2648 remote-endpoint = <&etm4_out>;
2655 remote-endpoint = <&etm5_out>;
2662 remote-endpoint = <&etm6_out>;
2669 remote-endpoint = <&etm7_out>;
2676 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2680 clock-names = "apb_pclk";
2684 out-ports {
2687 remote-endpoint = <&funnel_in1_in>;
2692 in-ports {
2695 remote-endpoint = <&funnel_apss0_out>;
2702 compatible = "qcom,sm6115-adsp-pas";
2705 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2710 interrupt-names = "wdog", "fatal", "ready",
2711 "handover", "stop-ack";
2714 clock-names = "xo";
2716 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2719 memory-region = <&pil_adsp_mem>;
2721 qcom,smem-states = <&adsp_smp2p_out 0>;
2722 qcom,smem-state-names = "stop";
2726 glink-edge {
2729 qcom,remote-pid = <2>;
2733 compatible = "qcom,apr-v2";
2734 qcom,glink-channels = "apr_audio_svc";
2736 #address-cells = <1>;
2737 #size-cells = <0>;
2742 qcom,protection-domain = "avs/audio",
2749 qcom,protection-domain = "avs/audio",
2752 compatible = "qcom,q6afe-dais";
2753 #address-cells = <1>;
2754 #size-cells = <0>;
2755 #sound-dai-cells = <1>;
2758 q6afecc: clock-controller {
2759 compatible = "qcom,q6afe-clocks";
2760 #clock-cells = <2>;
2767 qcom,protection-domain = "avs/audio",
2770 compatible = "qcom,q6asm-dais";
2771 #address-cells = <1>;
2772 #size-cells = <0>;
2773 #sound-dai-cells = <1>;
2793 qcom,protection-domain = "avs/audio",
2796 compatible = "qcom,q6adm-routing";
2797 #sound-dai-cells = <0>;
2804 qcom,glink-channels = "fastrpcglink-apps-dsp";
2806 qcom,non-secure-domain;
2807 #address-cells = <1>;
2808 #size-cells = <0>;
2810 compute-cb@3 {
2811 compatible = "qcom,fastrpc-compute-cb";
2816 compute-cb@4 {
2817 compatible = "qcom,fastrpc-compute-cb";
2822 compute-cb@5 {
2823 compatible = "qcom,fastrpc-compute-cb";
2828 compute-cb@6 {
2829 compatible = "qcom,fastrpc-compute-cb";
2834 compute-cb@7 {
2835 compatible = "qcom,fastrpc-compute-cb";
2844 compatible = "qcom,sm6115-cdsp-pas";
2847 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2852 interrupt-names = "wdog", "fatal", "ready",
2853 "handover", "stop-ack";
2856 clock-names = "xo";
2858 power-domains = <&rpmpd SM6115_VDDCX>;
2860 memory-region = <&pil_cdsp_mem>;
2862 qcom,smem-states = <&cdsp_smp2p_out 0>;
2863 qcom,smem-state-names = "stop";
2867 glink-edge {
2870 qcom,remote-pid = <5>;
2875 qcom,glink-channels = "fastrpcglink-apps-dsp";
2877 qcom,non-secure-domain;
2878 #address-cells = <1>;
2879 #size-cells = <0>;
2881 compute-cb@1 {
2882 compatible = "qcom,fastrpc-compute-cb";
2887 compute-cb@2 {
2888 compatible = "qcom,fastrpc-compute-cb";
2893 compute-cb@3 {
2894 compatible = "qcom,fastrpc-compute-cb";
2899 compute-cb@4 {
2900 compatible = "qcom,fastrpc-compute-cb";
2905 compute-cb@5 {
2906 compatible = "qcom,fastrpc-compute-cb";
2911 compute-cb@6 {
2912 compatible = "qcom,fastrpc-compute-cb";
2923 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2925 #iommu-cells = <2>;
2926 #global-interrupts = <1>;
2996 compatible = "qcom,wcn3990-wifi";
2998 reg-names = "membase";
2999 memory-region = <&wlan_msa_mem>;
3013 qcom,msa-fixed-perm;
3018 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
3025 compatible = "qcom,sm6115-apcs-hmss-global",
3026 "qcom,msm8994-apcs-kpss-global";
3029 #mbox-cells = <1>;
3033 compatible = "arm,armv7-timer-mem";
3035 #address-cells = <2>;
3036 #size-cells = <1>;
3038 clock-frequency = <19200000>;
3042 frame-number = <0>;
3049 frame-number = <1>;
3056 frame-number = <2>;
3063 frame-number = <3>;
3070 frame-number = <4>;
3077 frame-number = <5>;
3084 frame-number = <6>;
3090 intc: interrupt-controller@f200000 {
3091 compatible = "arm,gic-v3";
3094 #interrupt-cells = <3>;
3095 interrupt-controller;
3096 interrupt-parent = <&intc>;
3097 #redistributor-regions = <1>;
3098 redistributor-stride = <0x0 0x20000>;
3103 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
3107 reg-names = "freq-domain0", "freq-domain1";
3109 clock-names = "xo", "alternate";
3111 #freq-domain-cells = <1>;
3112 #clock-cells = <1>;
3116 thermal-zones {
3117 mapss-thermal {
3118 thermal-sensors = <&tsens0 0>;
3121 trip-point0 {
3127 trip-point1 {
3135 cdsp-hvx-thermal {
3136 thermal-sensors = <&tsens0 1>;
3139 trip-point0 {
3145 trip-point1 {
3153 wlan-thermal {
3154 thermal-sensors = <&tsens0 2>;
3157 trip-point0 {
3163 trip-point1 {
3171 camera-thermal {
3172 thermal-sensors = <&tsens0 3>;
3175 trip-point0 {
3181 trip-point1 {
3189 video-thermal {
3190 thermal-sensors = <&tsens0 4>;
3193 trip-point0 {
3199 trip-point1 {
3207 modem1-thermal {
3208 thermal-sensors = <&tsens0 5>;
3211 trip-point0 {
3217 trip-point1 {
3225 cpu4-thermal {
3226 thermal-sensors = <&tsens0 6>;
3229 cpu4_alert0: trip-point0 {
3235 cpu4_alert1: trip-point1 {
3241 cpu4_crit: cpu-crit {
3249 cpu5-thermal {
3250 thermal-sensors = <&tsens0 7>;
3253 cpu5_alert0: trip-point0 {
3259 cpu5_alert1: trip-point1 {
3265 cpu5_crit: cpu-crit {
3273 cpu6-thermal {
3274 thermal-sensors = <&tsens0 8>;
3277 cpu6_alert0: trip-point0 {
3283 cpu6_alert1: trip-point1 {
3289 cpu6_crit: cpu-crit {
3297 cpu7-thermal {
3298 thermal-sensors = <&tsens0 9>;
3301 cpu7_alert0: trip-point0 {
3307 cpu7_alert1: trip-point1 {
3313 cpu7_crit: cpu-crit {
3321 cpu45-thermal {
3322 thermal-sensors = <&tsens0 10>;
3325 cpu45_alert0: trip-point0 {
3331 cpu45_alert1: trip-point1 {
3337 cpu45_crit: cpu-crit {
3345 cpu67-thermal {
3346 thermal-sensors = <&tsens0 11>;
3349 cpu67_alert0: trip-point0 {
3355 cpu67_alert1: trip-point1 {
3361 cpu67_crit: cpu-crit {
3369 cpu0123-thermal {
3370 thermal-sensors = <&tsens0 12>;
3373 cpu0123_alert0: trip-point0 {
3379 cpu0123_alert1: trip-point1 {
3385 cpu0123_crit: cpu-crit {
3393 modem0-thermal {
3394 thermal-sensors = <&tsens0 13>;
3397 trip-point0 {
3403 trip-point1 {
3411 display-thermal {
3412 thermal-sensors = <&tsens0 14>;
3415 trip-point0 {
3421 trip-point1 {
3429 gpu-thermal {
3430 polling-delay-passive = <250>;
3432 thermal-sensors = <&tsens0 15>;
3434 cooling-maps {
3437 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3442 gpu_alert0: trip-point0 {
3448 trip-point1 {
3458 compatible = "arm,armv8-timer";