Lines Matching +full:1 +full:c600000
62 cpu1: cpu@1 {
108 clocks = <&cpufreq_hw 1>;
113 qcom,freq-domain = <&cpufreq_hw 1>;
127 clocks = <&cpufreq_hw 1>;
132 qcom,freq-domain = <&cpufreq_hw 1>;
141 clocks = <&cpufreq_hw 1>;
146 qcom,freq-domain = <&cpufreq_hw 1>;
155 clocks = <&cpufreq_hw 1>;
160 qcom,freq-domain = <&cpufreq_hw 1>;
216 big_cpu_sleep_0: cpu-sleep-1-0 {
237 cluster_0_sleep_1: cluster-sleep-0-1 {
246 cluster_1_sleep_0: cluster-sleep-1-0 {
255 cluster_1_sleep_1: cluster-sleep-1-1 {
269 #reset-cells = <1>;
386 #clock-cells = <1>;
391 #power-domain-cells = <1>;
528 qcom,client-id = <1>;
546 #qcom,smem-state-cells = <1>;
570 #qcom,smem-state-cells = <1>;
590 qcom,remote-pid = <1>;
594 #qcom,smem-state-cells = <1>;
615 #hwlock-cells = <1>;
816 #clock-cells = <1>;
817 #reset-cells = <1>;
818 #power-domain-cells = <1>;
835 cryptobam: dma-controller@1b04000 {
841 #dma-cells = <1>;
851 crypto: crypto@1b3a000 {
894 #address-cells = <1>;
904 port@1 {
905 reg = <1>;
951 qfprom@1b40000 {
954 #address-cells = <1>;
955 #size-cells = <1>;
959 bits = <1 4>;
968 rng: rng@1b53000 {
975 pmu@1b8e300 {
991 opp-1 {
1029 spmi_bus: spmi@1c40000 {
1055 #thermal-sensor-cells = <1>;
1188 lanes-per-direction = <1>;
1189 #reset-cells = <1>;
1287 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1298 #address-cells = <1>;
1312 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1323 #address-cells = <1>;
1336 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1337 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1348 #address-cells = <1>;
1361 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1362 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1373 #address-cells = <1>;
1387 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1398 #address-cells = <1>;
1412 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1423 #address-cells = <1>;
1437 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1448 #address-cells = <1>;
1462 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1473 #address-cells = <1>;
1504 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1515 #address-cells = <1>;
1529 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1540 #address-cells = <1>;
1569 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1580 #address-cells = <1>;
1594 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1605 #address-cells = <1>;
1668 #address-cells = <1>;
1678 port@1 {
1679 reg = <1>;
1710 iommus = <&adreno_smmu 0 1>;
1794 #clock-cells = <1>;
1795 #reset-cells = <1>;
1796 #power-domain-cells = <1>;
1821 #global-interrupts = <1>;
1838 #interrupt-cells = <1>;
1882 #address-cells = <1>;
1946 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1952 #address-cells = <1>;
1958 #address-cells = <1>;
1968 port@1 {
1969 reg = <1>;
2004 #clock-cells = <1>;
2021 <&mdss_dsi0_phy 1>,
2023 #clock-cells = <1>;
2024 #reset-cells = <1>;
2025 #power-domain-cells = <1>;
2034 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2056 qcom,remote-pid = <1>;
2381 #address-cells = <1>;
2391 port@1 {
2392 reg = <1>;
2586 #address-cells = <1>;
2596 port@1 {
2597 reg = <1>;
2679 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2709 #address-cells = <1>;
2751 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2780 #address-cells = <1>;
2783 compute-cb@1 {
2785 reg = <1>;
2824 apps_smmu: iommu@c600000 {
2828 #global-interrupts = <1>;
2931 #mbox-cells = <1>;
2938 #size-cells = <1>;
2951 frame-number = <1>;
2999 #redistributor-regions = <1>;
3013 #freq-domain-cells = <1>;
3014 #clock-cells = <1>;
3038 thermal-sensors = <&tsens0 1>;
3361 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,