Lines Matching +full:0 +full:x00d00000
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
47 clocks = <&cpufreq_hw 0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x1>;
66 clocks = <&cpufreq_hw 0>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x2>;
80 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
93 reg = <0x0 0x3>;
94 clocks = <&cpufreq_hw 0>;
99 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0x0 0x100>;
126 reg = <0x0 0x101>;
140 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
206 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
209 arm,psci-suspend-param = <0x40000003>;
216 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
219 arm,psci-suspend-param = <0x40000003>;
228 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
231 arm,psci-suspend-param = <0x40000022>;
237 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
240 arm,psci-suspend-param = <0x41000044>;
246 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
249 arm,psci-suspend-param = <0x40000042>;
258 arm,psci-suspend-param = <0x41000044>;
278 reg = <0 0x80000000 0 0>;
310 #power-domain-cells = <0>;
316 #power-domain-cells = <0>;
322 #power-domain-cells = <0>;
328 #power-domain-cells = <0>;
334 #power-domain-cells = <0>;
340 #power-domain-cells = <0>;
346 #power-domain-cells = <0>;
352 #power-domain-cells = <0>;
358 #power-domain-cells = <0>;
363 #power-domain-cells = <0>;
376 mboxes = <&apcs_glb 0>;
440 reg = <0x0 0x45700000 0x0 0x600000>;
445 reg = <0x0 0x45e00000 0x0 0x140000>;
450 reg = <0x0 0x45fff000 0x0 0x1000>;
456 reg = <0x0 0x46000000 0x0 0x200000>;
464 reg = <0x0 0x46200000 0x0 0x1e00000>;
469 reg = <0x0 0x4ab00000 0x0 0x6900000>;
474 reg = <0x0 0x51400000 0x0 0x500000>;
479 reg = <0x0 0x51900000 0x0 0x100000>;
484 reg = <0x0 0x51a00000 0x0 0x1e00000>;
489 reg = <0x0 0x53800000 0x0 0x2800000>;
494 reg = <0x0 0x56100000 0x0 0x10000>;
499 reg = <0x0 0x56110000 0x0 0x5000>;
504 reg = <0x0 0x56115000 0x0 0x2000>;
509 reg = <0x0 0x5c000000 0x0 0x00f00000>;
514 reg = <0x0 0x5cf00000 0x0 0x0100000>;
519 reg = <0x0 0x60000000 0x0 0x3900000>;
525 reg = <0x0 0x89b01000 0x0 0x200000>;
541 qcom,local-pid = <0>;
565 qcom,local-pid = <0>;
589 qcom,local-pid = <0>;
605 soc: soc@0 {
609 ranges = <0 0 0 0 0x10 0>;
610 dma-ranges = <0 0 0 0 0x10 0>;
614 reg = <0x0 0x00340000 0x0 0x20000>;
620 reg = <0x0 0x003c0000 0x0 0x40000>;
625 reg = <0x0 0x00500000 0x0 0x400000>,
626 <0x0 0x00900000 0x0 0x400000>,
627 <0x0 0x00d00000 0x0 0x400000>;
631 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
813 reg = <0x0 0x01400000 0x0 0x1f0000>;
823 reg = <0x0 0x01613000 0x0 0x180>;
824 #phy-cells = <0>;
837 reg = <0x0 0x01b04000 0x0 0x24000>;
842 qcom,ee = <0>;
844 iommus = <&apps_smmu 0x92 0>,
845 <&apps_smmu 0x94 0x11>,
846 <&apps_smmu 0x96 0x11>,
847 <&apps_smmu 0x98 0x1>,
848 <&apps_smmu 0x9F 0>;
853 reg = <0x0 0x01b3a000 0x0 0x6000>;
859 iommus = <&apps_smmu 0x92 0>,
860 <&apps_smmu 0x94 0x11>,
861 <&apps_smmu 0x96 0x11>,
862 <&apps_smmu 0x98 0x1>,
863 <&apps_smmu 0x9F 0>;
868 reg = <0x0 0x01615000 0x0 0x1000>;
883 #clock-cells = <0>;
886 #phy-cells = <0>;
889 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
895 #size-cells = <0>;
897 port@0 {
898 reg = <0>;
916 reg = <0x0 0x01880000 0x0 0x5f080>;
945 reg = <0x0 0x01900000 0x0 0x6200>;
953 reg = <0x0 0x01b40000 0x0 0x7000>;
958 reg = <0x25b 0x1>;
963 reg = <0x6006 0x2>;
970 reg = <0x0 0x01b53000 0x0 0x1000>;
977 reg = <0x0 0x01b8e300 0x0 0x600>;
987 opp-0 {
1031 reg = <0x0 0x01c40000 0x0 0x1100>,
1032 <0x0 0x01e00000 0x0 0x2000000>,
1033 <0x0 0x03e00000 0x0 0x100000>,
1034 <0x0 0x03f00000 0x0 0xa0000>,
1035 <0x0 0x01c0a000 0x0 0x26000>;
1039 qcom,ee = <0>;
1040 qcom,channel = <0>;
1042 #size-cells = <0>;
1049 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
1050 <0x0 0x04410000 0x0 0x8>; /* SROT */
1060 reg = <0x0 0x04480000 0x0 0x80000>;
1066 reg = <0x0 0x045f0000 0x0 0x7000>;
1071 reg = <0x0 0x04690000 0x0 0x10000>;
1076 reg = <0x0 0x04744000 0x0 0x1000>,
1077 <0x0 0x04745000 0x0 0x1000>,
1078 <0x0 0x04748000 0x0 0x8000>;
1095 iommus = <&apps_smmu 0x00c0 0x0>;
1134 reg = <0x0 0x04784000 0x0 0x1000>;
1148 iommus = <&apps_smmu 0x00a0 0x0>;
1158 qcom,dll-config = <0x0007642c>;
1159 qcom,ddr-config = <0x80040868>;
1183 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1194 iommus = <&apps_smmu 0x100 0>;
1214 <0 0>,
1215 <0 0>,
1217 <0 0>,
1218 <0 0>,
1219 <0 0>,
1227 reg = <0x0 0x04807000 0x0 0x1000>;
1238 resets = <&ufs_mem_hc 0>;
1241 #phy-cells = <0>;
1248 reg = <0x0 0x04a00000 0x0 0x60000>;
1260 dma-channel-mask = <0xf>;
1261 iommus = <&apps_smmu 0xf6 0x0>;
1268 reg = <0x0 0x04ac0000 0x0 0x2000>;
1274 iommus = <&apps_smmu 0xe3 0x0>;
1280 reg = <0x0 0x04a80000 0x0 0x4000>;
1284 pinctrl-0 = <&qup_i2c0_default>;
1286 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1287 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1299 #size-cells = <0>;
1305 reg = <0x0 0x04a80000 0x0 0x4000>;
1309 pinctrl-0 = <&qup_spi0_default>;
1311 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1324 #size-cells = <0>;
1330 reg = <0x0 0x04a84000 0x0 0x4000>;
1334 pinctrl-0 = <&qup_i2c1_default>;
1336 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1349 #size-cells = <0>;
1355 reg = <0x0 0x04a84000 0x0 0x4000>;
1359 pinctrl-0 = <&qup_spi1_default>;
1361 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1374 #size-cells = <0>;
1380 reg = <0x0 0x04a88000 0x0 0x4000>;
1384 pinctrl-0 = <&qup_i2c2_default>;
1386 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1399 #size-cells = <0>;
1405 reg = <0x0 0x04a88000 0x0 0x4000>;
1409 pinctrl-0 = <&qup_spi2_default>;
1411 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1424 #size-cells = <0>;
1430 reg = <0x0 0x04a8c000 0x0 0x4000>;
1434 pinctrl-0 = <&qup_i2c3_default>;
1436 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1449 #size-cells = <0>;
1455 reg = <0x0 0x04a8c000 0x0 0x4000>;
1459 pinctrl-0 = <&qup_spi3_default>;
1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1474 #size-cells = <0>;
1480 reg = <0x0 0x04a8c000 0x0 0x4000>;
1497 reg = <0x0 0x04a90000 0x0 0x4000>;
1501 pinctrl-0 = <&qup_i2c4_default>;
1503 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1516 #size-cells = <0>;
1522 reg = <0x0 0x04a90000 0x0 0x4000>;
1526 pinctrl-0 = <&qup_spi4_default>;
1528 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1541 #size-cells = <0>;
1547 reg = <0x0 0x04a90000 0x0 0x4000>;
1562 reg = <0x0 0x04a94000 0x0 0x4000>;
1566 pinctrl-0 = <&qup_i2c5_default>;
1568 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1581 #size-cells = <0>;
1587 reg = <0x0 0x04a94000 0x0 0x4000>;
1591 pinctrl-0 = <&qup_spi5_default>;
1593 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1606 #size-cells = <0>;
1613 reg = <0x0 0x04ef8800 0x0 0x400>;
1653 reg = <0x0 0x04e00000 0x0 0xcd00>;
1657 iommus = <&apps_smmu 0x120 0x0>;
1661 snps,hird-threshold = /bits/ 8 <0x10>;
1669 #size-cells = <0>;
1671 port@0 {
1672 reg = <0>;
1691 reg = <0x0 0x05900000 0x0 0x40000>;
1710 iommus = <&adreno_smmu 0 1>;
1731 opp-supported-hw = <0x1f>;
1737 opp-supported-hw = <0x1f>;
1743 opp-supported-hw = <0x1f>;
1749 opp-supported-hw = <0xf>;
1755 opp-supported-hw = <0x7>;
1761 opp-supported-hw = <0x7>;
1768 opp-supported-hw = <0x4>;
1774 opp-supported-hw = <0x3>;
1781 reg = <0x0 0x0596a000 0x0 0x30000>;
1790 reg = <0x0 0x05990000 0x0 0x9000>;
1802 reg = <0x0 0x059a0000 0x0 0x10000>;
1827 reg = <0x0 0x05e00000 0x0 0x1000>;
1840 iommus = <&apps_smmu 0x420 0x2>,
1841 <&apps_smmu 0x421 0x0>;
1858 reg = <0x0 0x05e01000 0x0 0x8f000>,
1859 <0x0 0x05eb0000 0x0 0x2008>;
1879 interrupts = <0>;
1883 #size-cells = <0>;
1885 port@0 {
1886 reg = <0>;
1925 reg = <0x0 0x05e94000 0x0 0x400>;
1946 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1953 #size-cells = <0>;
1959 #size-cells = <0>;
1961 port@0 {
1962 reg = <0>;
1997 reg = <0x0 0x05e94400 0x0 0x100>,
1998 <0x0 0x05e94500 0x0 0x300>,
1999 <0x0 0x05e94800 0x0 0x188>;
2005 #phy-cells = <0>;
2017 reg = <0x0 0x05f00000 0 0x20000>;
2020 <&mdss_dsi0_phy 0>,
2030 reg = <0x0 0x06080000 0x0 0x100>;
2033 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2048 qcom,smem-states = <&modem_smp2p_out 0>;
2063 reg = <0x0 0x08002000 0x0 0x1000>,
2064 <0x0 0x0e280000 0x0 0x180000>;
2083 reg = <0x0 0x08010000 0x0 0x1000>;
2093 reg = <0x0 0x08011000 0x0 0x1000>;
2103 reg = <0x0 0x08012000 0x0 0x1000>;
2113 reg = <0x0 0x08013000 0x0 0x1000>;
2123 reg = <0x0 0x08014000 0x0 0x1000>;
2133 reg = <0x0 0x08015000 0x0 0x1000>;
2143 reg = <0x0 0x08016000 0x0 0x1000>;
2153 reg = <0x0 0x08017000 0x0 0x1000>;
2163 reg = <0x0 0x08018000 0x0 0x1000>;
2173 reg = <0x0 0x08019000 0x0 0x1000>;
2183 reg = <0x0 0x0801a000 0x0 0x1000>;
2193 reg = <0x0 0x0801b000 0x0 0x1000>;
2203 reg = <0x0 0x0801c000 0x0 0x1000>;
2213 reg = <0x0 0x0801d000 0x0 0x1000>;
2223 reg = <0x0 0x0801e000 0x0 0x1000>;
2233 reg = <0x0 0x0801f000 0x0 0x1000>;
2243 reg = <0x0 0x08046000 0x0 0x1000>;
2269 reg = <0x0 0x08047000 0x0 0x1000>;
2295 reg = <0x0 0x08048000 0x0 0x1000>;
2313 reg = <0x0 0x08041000 0x0 0x1000>;
2339 reg = <0x0 0x08042000 0x0 0x1000>;
2365 reg = <0x0 0x08045000 0x0 0x1000>;
2382 #size-cells = <0>;
2384 port@0 {
2385 reg = <0>;
2402 reg = <0x0 0x09040000 0x0 0x1000>;
2423 reg = <0x0 0x09140000 0x0 0x1000>;
2444 reg = <0x0 0x09240000 0x0 0x1000>;
2465 reg = <0x0 0x09340000 0x0 0x1000>;
2486 reg = <0x0 0x09440000 0x0 0x1000>;
2507 reg = <0x0 0x09540000 0x0 0x1000>;
2528 reg = <0x0 0x09640000 0x0 0x1000>;
2549 reg = <0x0 0x09740000 0x0 0x1000>;
2570 reg = <0x0 0x09800000 0x0 0x1000>;
2587 #size-cells = <0>;
2589 port@0 {
2590 reg = <0>;
2649 reg = <0x0 0x09810000 0x0 0x1000>;
2675 reg = <0x0 0x0ab00000 0x0 0x100>;
2678 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2693 qcom,smem-states = <&adsp_smp2p_out 0>;
2710 #size-cells = <0>;
2715 iommus = <&apps_smmu 0x01c3 0x0>;
2721 iommus = <&apps_smmu 0x01c4 0x0>;
2727 iommus = <&apps_smmu 0x01c5 0x0>;
2733 iommus = <&apps_smmu 0x01c6 0x0>;
2739 iommus = <&apps_smmu 0x01c7 0x0>;
2747 reg = <0x0 0x0b300000 0x0 0x100000>;
2750 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2764 qcom,smem-states = <&cdsp_smp2p_out 0>;
2781 #size-cells = <0>;
2786 iommus = <&apps_smmu 0x0c01 0x0>;
2792 iommus = <&apps_smmu 0x0c02 0x0>;
2798 iommus = <&apps_smmu 0x0c03 0x0>;
2804 iommus = <&apps_smmu 0x0c04 0x0>;
2810 iommus = <&apps_smmu 0x0c05 0x0>;
2816 iommus = <&apps_smmu 0x0c06 0x0>;
2826 reg = <0x0 0x0c600000 0x0 0x80000>;
2899 reg = <0x0 0x0c800000 0x0 0x800000>;
2914 iommus = <&apps_smmu 0x1a0 0x1>;
2921 reg = <0x0 0x0f017000 0x0 0x1000>;
2929 reg = <0x0 0x0f111000 0x0 0x1000>;
2936 reg = <0x0 0x0f120000 0x0 0x1000>;
2939 ranges = <0x0 0x0 0x0 0x0 0x20000000>;
2943 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
2944 frame-number = <0>;
2950 reg = <0x0 0x0f123000 0x1000>;
2957 reg = <0x0 0x0f124000 0x1000>;
2964 reg = <0x0 0x0f125000 0x1000>;
2971 reg = <0x0 0x0f126000 0x1000>;
2978 reg = <0x0 0x0f127000 0x1000>;
2985 reg = <0x0 0x0f128000 0x1000>;
2994 reg = <0x0 0x0f200000 0x0 0x10000>,
2995 <0x0 0x0f300000 0x0 0x100000>;
3000 redistributor-stride = <0x0 0x20000>;
3006 reg = <0x0 0x0f521000 0x0 0x1000>,
3007 <0x0 0x0f523000 0x0 0x1000>;
3020 thermal-sensors = <&tsens0 0>;
3364 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;