Lines Matching +full:entry +full:- +full:latency +full:- +full:us
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 clock-frequency = <76800000>;
27 #clock-cells = <0>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
33 #clock-cells = <0>;
36 bi_tcxo_div2: bi-tcxo-div2-clk {
37 #clock-cells = <0>;
38 compatible = "fixed-factor-clock";
40 clock-mult = <1>;
41 clock-div = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
51 compatible = "arm,cortex-a55";
54 enable-method = "psci";
55 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_PD0>;
57 power-domain-names = "psci";
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 #cooling-cells = <2>;
61 L2_0: l2-cache {
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&L3_0>;
67 L3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
77 compatible = "arm,cortex-a55";
80 enable-method = "psci";
81 next-level-cache = <&L2_100>;
82 power-domains = <&CPU_PD0>;
83 power-domain-names = "psci";
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 #cooling-cells = <2>;
87 L2_100: l2-cache {
89 cache-level = <2>;
90 cache-unified;
91 next-level-cache = <&L3_0>;
97 compatible = "arm,cortex-a55";
100 enable-method = "psci";
101 next-level-cache = <&L2_200>;
102 power-domains = <&CPU_PD0>;
103 power-domain-names = "psci";
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 #cooling-cells = <2>;
107 L2_200: l2-cache {
109 cache-level = <2>;
110 cache-unified;
111 next-level-cache = <&L3_0>;
117 compatible = "arm,cortex-a55";
120 enable-method = "psci";
121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_PD0>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
127 L2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
137 compatible = "arm,cortex-a55";
140 enable-method = "psci";
141 next-level-cache = <&L2_400>;
142 power-domains = <&CPU_PD0>;
143 power-domain-names = "psci";
144 qcom,freq-domain = <&cpufreq_hw 0>;
145 #cooling-cells = <2>;
147 L2_400: l2-cache {
149 cache-level = <2>;
150 cache-unified;
151 next-level-cache = <&L3_0>;
157 compatible = "arm,cortex-a55";
160 enable-method = "psci";
161 next-level-cache = <&L2_500>;
162 power-domains = <&CPU_PD0>;
163 power-domain-names = "psci";
164 qcom,freq-domain = <&cpufreq_hw 0>;
165 #cooling-cells = <2>;
167 L2_500: l2-cache {
169 cache-level = <2>;
170 cache-unified;
171 next-level-cache = <&L3_0>;
177 compatible = "arm,cortex-a78";
180 enable-method = "psci";
181 next-level-cache = <&L2_600>;
182 power-domains = <&CPU_PD0>;
183 power-domain-names = "psci";
184 qcom,freq-domain = <&cpufreq_hw 1>;
185 #cooling-cells = <2>;
187 L2_600: l2-cache {
189 cache-level = <2>;
190 cache-unified;
191 next-level-cache = <&L3_0>;
197 compatible = "arm,cortex-a78";
200 enable-method = "psci";
201 next-level-cache = <&L2_700>;
202 power-domains = <&CPU_PD0>;
203 power-domain-names = "psci";
204 qcom,freq-domain = <&cpufreq_hw 1>;
205 #cooling-cells = <2>;
207 L2_700: l2-cache {
209 cache-level = <2>;
210 cache-unified;
211 next-level-cache = <&L3_0>;
215 cpu-map {
251 idle-states {
252 entry-method = "psci";
254 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
255 compatible = "arm,idle-state";
256 arm,psci-suspend-param = <0x40000004>;
257 entry-latency-us = <800>;
258 exit-latency-us = <750>;
259 min-residency-us = <4090>;
260 local-timer-stop;
263 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
264 compatible = "arm,idle-state";
265 arm,psci-suspend-param = <0x40000004>;
266 entry-latency-us = <600>;
267 exit-latency-us = <1550>;
268 min-residency-us = <4791>;
269 local-timer-stop;
273 domain-idle-states {
274 CLUSTER_SLEEP_0: cluster-sleep-0 {
275 compatible = "domain-idle-state";
276 arm,psci-suspend-param = <0x41000044>;
277 entry-latency-us = <1050>;
278 exit-latency-us = <2500>;
279 min-residency-us = <5309>;
282 CLUSTER_SLEEP_1: cluster-sleep-1 {
283 compatible = "domain-idle-state";
284 arm,psci-suspend-param = <0x41003344>;
285 entry-latency-us = <1561>;
286 exit-latency-us = <2801>;
287 min-residency-us = <8550>;
298 pmu-a55 {
299 compatible = "arm,cortex-a55-pmu";
303 pmu-a78 {
304 compatible = "arm,cortex-a78-pmu";
309 compatible = "arm,psci-1.0";
312 CPU_PD0: power-domain-cpu0 {
313 #power-domain-cells = <0>;
314 power-domains = <&CLUSTER_PD>;
315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
318 CPU_PD1: power-domain-cpu1 {
319 #power-domain-cells = <0>;
320 power-domains = <&CLUSTER_PD>;
321 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
324 CPU_PD2: power-domain-cpu2 {
325 #power-domain-cells = <0>;
326 power-domains = <&CLUSTER_PD>;
327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 CPU_PD3: power-domain-cpu3 {
331 #power-domain-cells = <0>;
332 power-domains = <&CLUSTER_PD>;
333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 CPU_PD4: power-domain-cpu4 {
337 #power-domain-cells = <0>;
338 power-domains = <&CLUSTER_PD>;
339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
342 CPU_PD5: power-domain-cpu5 {
343 #power-domain-cells = <0>;
344 power-domains = <&CLUSTER_PD>;
345 domain-idle-states = <&BIG_CPU_SLEEP_0>;
348 CPU_PD6: power-domain-cpu6 {
349 #power-domain-cells = <0>;
350 power-domains = <&CLUSTER_PD>;
351 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 CPU_PD7: power-domain-cpu7 {
355 #power-domain-cells = <0>;
356 power-domains = <&CLUSTER_PD>;
357 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 CLUSTER_PD: power-domain-cpu-cluster0 {
361 #power-domain-cells = <0>;
362 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
366 reserved_memory: reserved-memory {
367 #address-cells = <2>;
368 #size-cells = <2>;
371 aop_cmd_db_mem: cmd-db@80860000 {
372 compatible = "qcom,cmd-db";
374 no-map;
379 #address-cells = <2>;
380 #size-cells = <2>;
382 dma-ranges = <0 0 0 0 0x10 0>;
383 compatible = "simple-bus";
385 gcc: clock-controller@100000 {
386 compatible = "qcom,sm4450-gcc";
388 #clock-cells = <1>;
389 #reset-cells = <1>;
390 #power-domain-cells = <1>;
400 compatible = "qcom,geni-se-qup";
405 clock-names = "m-ahb", "s-ahb";
406 #address-cells = <2>;
407 #size-cells = <2>;
411 compatible = "qcom,geni-debug-uart";
414 clock-names = "se";
416 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
417 pinctrl-names = "default";
423 compatible = "qcom,tcsr-mutex";
425 #hwlock-cells = <1>;
428 gpucc: clock-controller@3d90000 {
429 compatible = "qcom,sm4450-gpucc";
434 #clock-cells = <1>;
435 #reset-cells = <1>;
436 #power-domain-cells = <1>;
439 camcc: clock-controller@ade0000 {
440 compatible = "qcom,sm4450-camcc";
444 #clock-cells = <1>;
445 #reset-cells = <1>;
446 #power-domain-cells = <1>;
449 dispcc: clock-controller@af00000 {
450 compatible = "qcom,sm4450-dispcc";
458 #clock-cells = <1>;
459 #reset-cells = <1>;
460 #power-domain-cells = <1>;
463 pdc: interrupt-controller@b220000 {
464 compatible = "qcom,sm4450-pdc", "qcom,pdc";
466 qcom,pdc-ranges = <0 480 94>, <94 494 31>,
468 #interrupt-cells = <2>;
469 interrupt-parent = <&intc>;
470 interrupt-controller;
474 compatible = "qcom,sm4450-tlmm";
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 gpio-ranges = <&tlmm 0 0 137>;
482 wakeup-parent = <&pdc>;
484 qup_uart7_rx: qup-uart7-rx-state {
487 drive-strength = <2>;
488 bias-disable;
491 qup_uart7_tx: qup-uart7-tx-state {
494 drive-strength = <2>;
495 bias-disable;
499 intc: interrupt-controller@17200000 {
500 compatible = "arm,gic-v3";
504 #interrupt-cells = <3>;
505 interrupt-controller;
506 #redistributor-regions = <1>;
507 redistributor-stride = <0x0 0x20000>;
511 compatible = "arm,armv7-timer-mem";
514 #address-cells = <1>;
515 #size-cells = <1>;
520 frame-number = <0>;
527 frame-number = <1>;
534 frame-number = <2>;
541 frame-number = <3>;
548 frame-number = <4>;
555 frame-number = <5>;
562 frame-number = <6>;
569 compatible = "qcom,rpmh-rsc";
573 reg-names = "drv-0", "drv-1", "drv-2";
578 qcom,tcs-offset = <0xd00>;
579 qcom,drv-id = <2>;
580 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
582 power-domains = <&CLUSTER_PD>;
584 apps_bcm_voter: bcm-voter {
585 compatible = "qcom,bcm-voter";
588 rpmhcc: clock-controller {
589 compatible = "qcom,sm4450-rpmh-clk";
590 #clock-cells = <1>;
592 clock-names = "xo";
597 compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss";
600 reg-names = "freq-domain0", "freq-domain1";
602 clock-names = "xo", "alternate";
605 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
606 #freq-domain-cells = <1>;
607 #clock-cells = <1>;
612 compatible = "arm,armv8-timer";