Lines Matching +full:bcm +full:- +full:voter
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
24 interrupt-parent = <&intc>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 clock-frequency = <76800000>;
32 #clock-cells = <0>;
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 clock-frequency = <32000>;
38 #clock-cells = <0>;
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a55";
51 enable-method = "psci";
52 power-domains = <&CPU_PD0>;
53 power-domain-names = "psci";
54 qcom,freq-domain = <&cpufreq_hw 0>;
55 capacity-dmips-mhz = <1024>;
56 dynamic-power-coefficient = <100>;
57 next-level-cache = <&L2_0>;
59 L2_0: l2-cache {
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
66 cache-level = <3>;
67 cache-unified;
74 compatible = "arm,cortex-a55";
77 enable-method = "psci";
78 power-domains = <&CPU_PD1>;
79 power-domain-names = "psci";
80 qcom,freq-domain = <&cpufreq_hw 0>;
81 capacity-dmips-mhz = <1024>;
82 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L2_100>;
85 L2_100: l2-cache {
87 cache-level = <2>;
88 cache-unified;
89 next-level-cache = <&L3_0>;
95 compatible = "arm,cortex-a55";
98 enable-method = "psci";
99 power-domains = <&CPU_PD2>;
100 power-domain-names = "psci";
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 capacity-dmips-mhz = <1024>;
103 dynamic-power-coefficient = <100>;
104 next-level-cache = <&L2_200>;
106 L2_200: l2-cache {
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&L3_0>;
116 compatible = "arm,cortex-a55";
119 enable-method = "psci";
120 power-domains = <&CPU_PD3>;
121 power-domain-names = "psci";
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 capacity-dmips-mhz = <1024>;
124 dynamic-power-coefficient = <100>;
125 next-level-cache = <&L2_300>;
127 L2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
135 cpu-map {
155 idle-states {
156 entry-method = "psci";
158 CPU_OFF: cpu-sleep-0 {
159 compatible = "arm,idle-state";
160 entry-latency-us = <235>;
161 exit-latency-us = <428>;
162 min-residency-us = <1774>;
163 arm,psci-suspend-param = <0x40000003>;
164 local-timer-stop;
167 CPU_RAIL_OFF: cpu-rail-sleep-1 {
168 compatible = "arm,idle-state";
169 entry-latency-us = <800>;
170 exit-latency-us = <750>;
171 min-residency-us = <4090>;
172 arm,psci-suspend-param = <0x40000004>;
173 local-timer-stop;
178 domain-idle-states {
179 CLUSTER_SLEEP_0: cluster-sleep-0 {
180 compatible = "domain-idle-state";
181 arm,psci-suspend-param = <0x41000044>;
182 entry-latency-us = <1050>;
183 exit-latency-us = <2500>;
184 min-residency-us = <5309>;
187 CLUSTER_SLEEP_1: cluster-sleep-1 {
188 compatible = "domain-idle-state";
189 arm,psci-suspend-param = <0x41001344>;
190 entry-latency-us = <2761>;
191 exit-latency-us = <3964>;
192 min-residency-us = <8467>;
195 CLUSTER_SLEEP_2: cluster-sleep-2 {
196 compatible = "domain-idle-state";
197 arm,psci-suspend-param = <0x4100b344>;
198 entry-latency-us = <2793>;
199 exit-latency-us = <4023>;
200 min-residency-us = <9826>;
207 compatible = "qcom,scm-sdx75", "qcom,scm";
211 clk_virt: interconnect-0 {
212 compatible = "qcom,sdx75-clk-virt";
213 #interconnect-cells = <2>;
214 qcom,bcm-voters = <&apps_bcm_voter>;
218 mc_virt: interconnect-1 {
219 compatible = "qcom,sdx75-mc-virt";
220 #interconnect-cells = <2>;
221 qcom,bcm-voters = <&apps_bcm_voter>;
230 compatible = "arm,cortex-a55-pmu";
235 compatible = "arm,psci-1.0";
238 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells = <0>;
240 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
244 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells = <0>;
246 power-domains = <&CLUSTER_PD>;
247 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
250 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells = <0>;
252 power-domains = <&CLUSTER_PD>;
253 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
256 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells = <0>;
258 power-domains = <&CLUSTER_PD>;
259 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
262 CLUSTER_PD: power-domain-cpu-cluster0 {
263 #power-domain-cells = <0>;
264 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
268 reserved-memory {
269 #address-cells = <2>;
270 #size-cells = <2>;
273 gunyah_hyp_mem: gunyah-hyp@80000000 {
275 no-map;
278 hyp_elf_package_mem: hyp-elf-package@80800000 {
280 no-map;
283 access_control_db_mem: access-control-db@81380000 {
285 no-map;
290 no-map;
293 trusted_apps_mem: trusted-apps@81780000 {
295 no-map;
298 xbl_ramdump_mem: xbl-ramdump@87a00000 {
300 no-map;
303 cpucp_fw_mem: cpucp-fw@87c00000 {
305 no-map;
308 xbl_dtlog_mem: xbl-dtlog@87d00000 {
310 no-map;
313 xbl_sc_mem: xbl-sc@87d40000 {
315 no-map;
318 modem_efs_shared_mem: modem-efs-shared@87d80000 {
320 no-map;
323 aop_image_mem: aop-image@87e00000 {
325 no-map;
330 no-map;
333 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
334 compatible = "qcom,cmd-db";
336 no-map;
339 aop_config_mem: aop-config@87f00000 {
341 no-map;
344 ipa_fw_mem: ipa-fw@87f20000 {
346 no-map;
351 no-map;
354 tme_crashdump_mem: tme-crashdump@87f31000 {
356 no-map;
359 tme_log_mem: tme-log@87f71000 {
361 no-map;
364 uefi_log_mem: uefi-log@87f75000 {
366 no-map;
371 no-map;
374 qlink_logging_mem: qlink-logging@88800000 {
376 no-map;
379 audio_heap_mem: audio-heap@88b00000 {
380 compatible = "shared-dma-pool";
382 no-map;
385 mpss_dsm_mem_2: mpss-dsm-2@88f00000 {
387 no-map;
390 mpss_dsm_mem: mpss-dsm@8b400000 {
392 no-map;
395 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
397 no-map;
402 no-map;
405 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
407 no-map;
410 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
412 no-map;
415 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
417 no-map;
421 smp2p-modem {
424 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
430 qcom,local-pid = <0>;
431 qcom,remote-pid = <1>;
433 smp2p_modem_out: master-kernel {
434 qcom,entry-name = "master-kernel";
435 #qcom,smem-state-cells = <1>;
438 smp2p_modem_in: slave-kernel {
439 qcom,entry-name = "slave-kernel";
440 interrupt-controller;
441 #interrupt-cells = <2>;
444 ipa_smp2p_out: ipa-ap-to-modem {
445 qcom,entry-name = "ipa";
446 #qcom,smem-state-cells = <1>;
449 ipa_smp2p_in: ipa-modem-to-ap {
450 qcom,entry-name = "ipa";
451 interrupt-controller;
452 #interrupt-cells = <2>;
458 memory-region = <&smem_mem>;
463 compatible = "simple-bus";
464 #address-cells = <2>;
465 #size-cells = <2>;
467 dma-ranges = <0 0 0 0 0x10 0>;
469 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx75-gcc";
487 #clock-cells = <1>;
488 #reset-cells = <1>;
489 #power-domain-cells = <1>;
493 compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
496 interrupt-controller;
497 #interrupt-cells = <3>;
498 #mbox-cells = <2>;
501 gpi_dma: dma-controller@900000 {
502 compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
504 #dma-cells = <3>;
517 dma-channels = <12>;
518 dma-channel-mask = <0x7f>;
524 compatible = "qcom,geni-se-qup";
528 clock-names = "m-ahb",
529 "s-ahb";
533 interconnect-names = "qup-core";
534 #address-cells = <2>;
535 #size-cells = <2>;
540 compatible = "qcom,geni-i2c";
543 clock-names = "se";
545 #address-cells = <1>;
546 #size-cells = <0>;
547 pinctrl-0 = <&qup_i2c0_data_clk>;
548 pinctrl-names = "default";
555 interconnect-names = "qup-core", "qup-config", "qup-memory";
558 dma-names = "tx", "rx";
563 compatible = "qcom,geni-spi";
566 clock-names = "se";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
571 pinctrl-names = "default";
578 interconnect-names = "qup-core", "qup-config", "qup-memory";
581 dma-names = "tx", "rx";
586 compatible = "qcom,geni-debug-uart";
589 clock-names = "se";
594 interconnect-names = "qup-core",
595 "qup-config";
597 pinctrl-0 = <&qupv3_se1_2uart_active>;
598 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
599 pinctrl-names = "default",
605 compatible = "qcom,geni-i2c";
608 clock-names = "se";
610 #address-cells = <1>;
611 #size-cells = <0>;
612 pinctrl-0 = <&qup_i2c2_data_clk>;
613 pinctrl-names = "default";
620 interconnect-names = "qup-core", "qup-config", "qup-memory";
623 dma-names = "tx", "rx";
628 compatible = "qcom,geni-spi";
631 clock-names = "se";
633 #address-cells = <1>;
634 #size-cells = <0>;
635 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
636 pinctrl-names = "default";
643 interconnect-names = "qup-core", "qup-config", "qup-memory";
646 dma-names = "tx", "rx";
651 compatible = "qcom,geni-i2c";
654 clock-names = "se";
656 #address-cells = <1>;
657 #size-cells = <0>;
658 pinctrl-0 = <&qup_i2c3_data_clk>;
659 pinctrl-names = "default";
666 interconnect-names = "qup-core", "qup-config", "qup-memory";
669 dma-names = "tx", "rx";
674 compatible = "qcom,geni-spi";
677 clock-names = "se";
679 #address-cells = <1>;
680 #size-cells = <0>;
681 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
682 pinctrl-names = "default";
689 interconnect-names = "qup-core", "qup-config", "qup-memory";
692 dma-names = "tx", "rx";
697 compatible = "qcom,geni-uart";
700 clock-names = "se";
702 pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
703 pinctrl-names = "default";
708 interconnect-names = "qup-core", "qup-config";
713 compatible = "qcom,geni-i2c";
716 clock-names = "se";
718 #address-cells = <1>;
719 #size-cells = <0>;
720 pinctrl-0 = <&qup_i2c5_data_clk>;
721 pinctrl-names = "default";
728 interconnect-names = "qup-core", "qup-config", "qup-memory";
731 dma-names = "tx", "rx";
736 compatible = "qcom,geni-i2c";
739 clock-names = "se";
741 #address-cells = <1>;
742 #size-cells = <0>;
743 pinctrl-0 = <&qup_i2c6_data_clk>;
744 pinctrl-names = "default";
751 interconnect-names = "qup-core", "qup-config", "qup-memory";
754 dma-names = "tx", "rx";
759 compatible = "qcom,geni-spi";
762 clock-names = "se";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
767 pinctrl-names = "default";
774 interconnect-names = "qup-core", "qup-config", "qup-memory";
777 dma-names = "tx", "rx";
782 compatible = "qcom,geni-i2c";
785 clock-names = "se";
787 #address-cells = <1>;
788 #size-cells = <0>;
789 pinctrl-0 = <&qup_i2c7_data_clk>;
790 pinctrl-names = "default";
797 interconnect-names = "qup-core", "qup-config", "qup-memory";
800 dma-names = "tx", "rx";
805 compatible = "qcom,geni-spi";
808 clock-names = "se";
810 #address-cells = <1>;
811 #size-cells = <0>;
812 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
813 pinctrl-names = "default";
820 interconnect-names = "qup-core", "qup-config", "qup-memory";
823 dma-names = "tx", "rx";
829 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
831 #phy-cells = <0>;
834 clock-names = "ref";
842 compatible = "qcom,sdx75-qmp-usb3-uni-phy";
849 clock-names = "aux",
854 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
858 reset-names = "phy",
861 #clock-cells = <0>;
862 clock-output-names = "usb3_uni_phy_pipe_clk_src";
864 #phy-cells = <0>;
870 compatible = "qcom,sdx75-system-noc";
872 #interconnect-cells = <2>;
873 qcom,bcm-voters = <&apps_bcm_voter>;
877 compatible = "qcom,sdx75-pcie-anoc";
879 #interconnect-cells = <2>;
880 qcom,bcm-voters = <&apps_bcm_voter>;
884 compatible = "qcom,tcsr-mutex";
886 #hwlock-cells = <1>;
890 compatible = "qcom,sdx75-tcsr", "syscon";
895 compatible = "qcom,sdx75-mpss-pas";
898 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
904 interrupt-names = "wdog",
908 "stop-ack",
909 "shutdown-ack";
912 clock-names = "xo";
914 power-domains = <&rpmhpd RPMHPD_CX>,
916 power-domain-names = "cx",
919 memory-region = <&mpssadsp_mem>, <&q6_mpss_dtb_mem>,
925 qcom,smem-states = <&smp2p_modem_out 0>;
926 qcom,smem-state-names = "stop";
930 glink-edge {
931 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
937 qcom,remote-pid = <1>;
942 compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
947 interrupt-names = "hc_irq",
953 clock-names = "iface",
957 qcom,dll-config = <0x0007442c>;
958 qcom,ddr-config = <0x80040868>;
959 power-domains = <&rpmhpd RPMHPD_CX>;
960 operating-points-v2 = <&sdhc1_opp_table>;
964 interconnect-names = "sdhc-ddr",
965 "cpu-sdhc";
966 bus-width = <4>;
967 dma-coherent;
969 /* Forbid SDR104/SDR50 - broken hw! */
970 sdhci-caps-mask = <0x3 0>;
974 sdhc1_opp_table: opp-table {
975 compatible = "operating-points-v2";
977 opp-100000000 {
978 opp-hz = /bits/ 64 <100000000>;
979 required-opps = <&rpmhpd_opp_low_svs>;
982 opp-384000000 {
983 opp-hz = /bits/ 64 <384000000>;
984 required-opps = <&rpmhpd_opp_nom>;
990 compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
992 #address-cells = <2>;
993 #size-cells = <2>;
1001 clock-names = "cfg_noc",
1007 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1009 assigned-clock-rates = <19200000>, <200000000>;
1011 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1015 interrupt-names = "hs_phy_irq",
1020 power-domains = <&gcc GCC_USB30_GDSC>;
1028 interconnect-names = "usb-ddr",
1029 "apps-usb";
1042 phy-names = "usb2-phy",
1043 "usb3-phy";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1066 pdc: interrupt-controller@b220000 {
1067 compatible = "qcom,sdx75-pdc", "qcom,pdc";
1070 qcom,pdc-ranges = <0 147 52>,
1073 #interrupt-cells = <2>;
1074 interrupt-parent = <&intc>;
1075 interrupt-controller;
1078 aoss_qmp: power-controller@c310000 {
1079 compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
1081 interrupt-parent = <&ipcc>;
1082 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1086 #clock-cells = <0>;
1090 compatible = "qcom,spmi-pmic-arb";
1096 reg-names = "core",
1101 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1102 interrupt-names = "periph_irq";
1105 qcom,bus-id = <0>;
1106 #address-cells = <2>;
1107 #size-cells = <0>;
1108 interrupt-controller;
1109 #interrupt-cells = <4>;
1113 compatible = "qcom,sdx75-tlmm";
1116 gpio-controller;
1117 #gpio-cells = <2>;
1118 gpio-ranges = <&tlmm 0 0 133>;
1119 interrupt-controller;
1120 #interrupt-cells = <2>;
1121 wakeup-parent = <&pdc>;
1123 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
1127 drive-strength = <2>;
1128 bias-pull-up;
1131 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1135 drive-strength = <2>;
1136 bias-pull-up;
1139 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1143 drive-strength = <2>;
1144 bias-pull-up;
1147 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1151 drive-strength = <2>;
1152 bias-pull-up;
1155 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1159 drive-strength = <2>;
1160 bias-pull-up;
1163 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1167 drive-strength = <2>;
1168 bias-pull-up;
1171 qup_spi0_cs: qup-spi0-cs-state {
1174 drive-strength = <6>;
1175 bias-pull-down;
1178 qup_spi0_data_clk: qup-spi0-data-clk-state {
1182 drive-strength = <6>;
1183 bias-pull-down;
1186 qup_spi2_cs: qup-spi2-cs-state {
1189 drive-strength = <6>;
1190 bias-pull-down;
1193 qup_spi2_data_clk: qup-spi2-data-clk-state {
1197 drive-strength = <6>;
1198 bias-pull-down;
1201 qup_spi3_cs: qup-spi3-cs-state {
1204 drive-strength = <6>;
1205 bias-pull-down;
1208 qup_spi3_data_clk: qup-spi3-data-clk-state {
1212 drive-strength = <6>;
1213 bias-pull-down;
1216 qup_spi6_cs: qup-spi6-cs-state {
1219 drive-strength = <6>;
1220 bias-pull-down;
1223 qup_spi6_data_clk: qup-spi6-data-clk-state {
1227 drive-strength = <6>;
1228 bias-pull-down;
1231 qup_spi7_cs: qup-spi7-cs-state {
1234 drive-strength = <6>;
1235 bias-pull-down;
1238 qup_spi7_data_clk: qup-spi7-data-clk-state {
1242 drive-strength = <6>;
1243 bias-pull-down;
1246 qup_uart4_cts_rts: qup-uart4-cts-rts-state {
1250 drive-strength = <2>;
1251 bias-pull-down;
1254 qup_uart4_default: qup-uart4-default-state {
1258 drive-strength = <2>;
1259 bias-pull-up;
1262 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1263 tx-pins {
1266 drive-strength = <2>;
1267 bias-disable;
1270 rx-pins {
1273 drive-strength = <2>;
1274 bias-disable;
1278 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1281 drive-strength = <2>;
1282 bias-pull-down;
1285 sdc1_default: sdc1-default-state {
1286 clk-pins {
1288 drive-strength = <16>;
1289 bias-disable;
1292 cmd-pins {
1294 drive-strength = <10>;
1295 bias-pull-up;
1298 data-pins {
1300 drive-strength = <10>;
1301 bias-pull-up;
1305 sdc1_sleep: sdc1-sleep-state {
1306 clk-pins {
1308 drive-strength = <2>;
1309 bias-disable;
1312 cmd-pins {
1314 drive-strength = <2>;
1315 bias-pull-up;
1318 data-pins {
1320 drive-strength = <2>;
1321 bias-pull-up;
1327 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1329 #iommu-cells = <2>;
1330 #global-interrupts = <2>;
1331 dma-coherent;
1367 intc: interrupt-controller@17200000 {
1368 compatible = "arm,gic-v3";
1369 #interrupt-cells = <3>;
1370 interrupt-controller;
1371 #redistributor-regions = <1>;
1372 redistributor-stride = <0x0 0x20000>;
1379 compatible = "arm,armv7-timer-mem";
1381 #address-cells = <1>;
1382 #size-cells = <1>;
1388 frame-number = <0>;
1395 frame-number = <1>;
1402 frame-number = <2>;
1409 frame-number = <3>;
1416 frame-number = <4>;
1423 frame-number = <5>;
1430 frame-number = <6>;
1438 compatible = "qcom,rpmh-rsc";
1442 reg-names = "drv-0", "drv-1", "drv-2";
1447 power-domains = <&CLUSTER_PD>;
1448 qcom,tcs-offset = <0xd00>;
1449 qcom,drv-id = <2>;
1450 qcom,tcs-config = <ACTIVE_TCS 3>,
1455 apps_bcm_voter: bcm-voter {
1456 compatible = "qcom,bcm-voter";
1459 rpmhcc: clock-controller {
1460 compatible = "qcom,sdx75-rpmh-clk";
1462 clock-names = "xo";
1463 #clock-cells = <1>;
1466 rpmhpd: power-controller {
1467 compatible = "qcom,sdx75-rpmhpd";
1468 #power-domain-cells = <1>;
1469 operating-points-v2 = <&rpmhpd_opp_table>;
1471 rpmhpd_opp_table: opp-table {
1472 compatible = "operating-points-v2";
1474 rpmhpd_opp_ret: opp-16 {
1475 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1478 rpmhpd_opp_min_svs: opp-48 {
1479 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1482 rpmhpd_opp_low_svs: opp-64 {
1483 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1486 rpmhpd_opp_svs: opp-128 {
1487 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1490 rpmhpd_opp_svs_l1: opp-192 {
1491 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1494 rpmhpd_opp_nom: opp-256 {
1495 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1498 rpmhpd_opp_nom_l1: opp-320 {
1499 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1502 rpmhpd_opp_nom_l2: opp-336 {
1503 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1506 rpmhpd_opp_turbo: opp-384 {
1507 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1510 rpmhpd_opp_turbo_l1: opp-416 {
1511 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1518 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1520 reg-names = "freq-domain0";
1523 clock-names = "xo",
1526 interrupt-names = "dcvsh-irq-0";
1527 #freq-domain-cells = <1>;
1528 #clock-cells = <1>;
1532 compatible = "qcom,sdx75-dc-noc";
1534 #interconnect-cells = <2>;
1535 qcom,bcm-voters = <&apps_bcm_voter>;
1539 compatible = "qcom,sdx75-gem-noc";
1541 #interconnect-cells = <2>;
1542 qcom,bcm-voters = <&apps_bcm_voter>;
1547 compatible = "arm,armv8-timer";