Lines Matching refs:gcc
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
617 gcc: clock-controller@100000 { label
618 compatible = "qcom,gcc-sdm670";
659 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
660 <&gcc GCC_SDCC1_APPS_CLK>,
662 <&gcc GCC_SDCC1_ICE_CORE_CLK>,
663 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
742 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
743 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
756 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
777 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
798 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
819 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
840 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
861 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
882 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
903 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
948 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
949 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
962 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
983 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1004 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1025 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1046 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1067 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1088 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1109 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1469 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1470 <&gcc GCC_GPU_CFG_AHB_CLK>;
1490 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1491 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1519 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1520 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1531 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1535 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1550 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1551 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1552 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1553 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1554 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1561 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1562 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1576 power-domains = <&gcc USB30_PRIM_GDSC>;
1578 resets = <&gcc GCC_USB30_PRIM_BCR>;
1717 <&gcc GCC_CAMERA_AHB_CLK>,
1718 <&gcc GCC_CAMERA_AXI_CLK>,
1839 clocks = <&gcc GCC_DISP_AXI_CLK>,
1844 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
2051 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
2052 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
2246 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2257 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;