Lines Matching +full:opp +full:- +full:19200000
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
32 #address-cells = <2>;
33 #size-cells = <0>;
39 enable-method = "psci";
40 capacity-dmips-mhz = <610>;
41 dynamic-power-coefficient = <203>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
43 operating-points-v2 = <&cpu0_opp_table>;
46 power-domains = <&CPU_PD0>;
47 power-domain-names = "psci";
48 next-level-cache = <&L2_0>;
49 L2_0: l2-cache {
51 next-level-cache = <&L3_0>;
52 cache-level = <2>;
53 cache-unified;
54 L3_0: l3-cache {
56 cache-level = <3>;
57 cache-unified;
66 enable-method = "psci";
67 capacity-dmips-mhz = <610>;
68 dynamic-power-coefficient = <203>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
70 operating-points-v2 = <&cpu0_opp_table>;
73 power-domains = <&CPU_PD1>;
74 power-domain-names = "psci";
75 next-level-cache = <&L2_100>;
76 L2_100: l2-cache {
78 cache-level = <2>;
79 cache-unified;
80 next-level-cache = <&L3_0>;
88 enable-method = "psci";
89 capacity-dmips-mhz = <610>;
90 dynamic-power-coefficient = <203>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
92 operating-points-v2 = <&cpu0_opp_table>;
95 power-domains = <&CPU_PD2>;
96 power-domain-names = "psci";
97 next-level-cache = <&L2_200>;
98 L2_200: l2-cache {
100 cache-level = <2>;
101 cache-unified;
102 next-level-cache = <&L3_0>;
110 enable-method = "psci";
111 capacity-dmips-mhz = <610>;
112 dynamic-power-coefficient = <203>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <&cpu0_opp_table>;
117 power-domains = <&CPU_PD3>;
118 power-domain-names = "psci";
119 next-level-cache = <&L2_300>;
120 L2_300: l2-cache {
122 cache-level = <2>;
123 cache-unified;
124 next-level-cache = <&L3_0>;
132 enable-method = "psci";
133 capacity-dmips-mhz = <610>;
134 dynamic-power-coefficient = <203>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
136 operating-points-v2 = <&cpu0_opp_table>;
139 power-domains = <&CPU_PD4>;
140 power-domain-names = "psci";
141 next-level-cache = <&L2_400>;
142 L2_400: l2-cache {
144 cache-level = <2>;
145 cache-unified;
146 next-level-cache = <&L3_0>;
154 enable-method = "psci";
155 capacity-dmips-mhz = <610>;
156 dynamic-power-coefficient = <203>;
157 qcom,freq-domain = <&cpufreq_hw 0>;
158 operating-points-v2 = <&cpu0_opp_table>;
161 power-domains = <&CPU_PD5>;
162 power-domain-names = "psci";
163 next-level-cache = <&L2_500>;
164 L2_500: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
176 enable-method = "psci";
177 capacity-dmips-mhz = <1024>;
178 dynamic-power-coefficient = <393>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 operating-points-v2 = <&cpu6_opp_table>;
183 power-domains = <&CPU_PD6>;
184 power-domain-names = "psci";
185 next-level-cache = <&L2_600>;
186 L2_600: l2-cache {
188 cache-level = <2>;
189 cache-unified;
190 next-level-cache = <&L3_0>;
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <393>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu6_opp_table>;
205 power-domains = <&CPU_PD7>;
206 power-domain-names = "psci";
207 next-level-cache = <&L2_700>;
208 L2_700: l2-cache {
210 cache-level = <2>;
211 cache-unified;
212 next-level-cache = <&L3_0>;
216 cpu-map {
252 idle-states {
253 entry-method = "psci";
255 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
256 compatible = "arm,idle-state";
257 idle-state-name = "little-rail-power-collapse";
258 arm,psci-suspend-param = <0x40000004>;
259 entry-latency-us = <702>;
260 exit-latency-us = <915>;
261 min-residency-us = <1617>;
262 local-timer-stop;
265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
266 compatible = "arm,idle-state";
267 idle-state-name = "big-rail-power-collapse";
268 arm,psci-suspend-param = <0x40000004>;
269 entry-latency-us = <526>;
270 exit-latency-us = <1854>;
271 min-residency-us = <2380>;
272 local-timer-stop;
276 domain-idle-states {
277 CLUSTER_SLEEP_0: cluster-sleep-0 {
278 compatible = "domain-idle-state";
279 arm,psci-suspend-param = <0x4100c244>;
280 entry-latency-us = <3263>;
281 exit-latency-us = <6562>;
282 min-residency-us = <9825>;
289 compatible = "qcom,scm-sdm670", "qcom,scm";
299 cpu0_opp_table: opp-table-cpu0 {
300 compatible = "operating-points-v2";
301 opp-shared;
303 cpu0_opp1: opp-300000000 {
304 opp-hz = /bits/ 64 <300000000>;
305 opp-peak-kBps = <400000 4800000>;
308 cpu0_opp2: opp-576000000 {
309 opp-hz = /bits/ 64 <576000000>;
310 opp-peak-kBps = <400000 4800000>;
313 cpu0_opp3: opp-748800000 {
314 opp-hz = /bits/ 64 <748800000>;
315 opp-peak-kBps = <1200000 4800000>;
318 cpu0_opp4: opp-998400000 {
319 opp-hz = /bits/ 64 <998400000>;
320 opp-peak-kBps = <1804000 8908800>;
323 cpu0_opp5: opp-1209600000 {
324 opp-hz = /bits/ 64 <1209600000>;
325 opp-peak-kBps = <2188000 8908800>;
328 cpu0_opp6: opp-1324800000 {
329 opp-hz = /bits/ 64 <1324800000>;
330 opp-peak-kBps = <2188000 13516800>;
333 cpu0_opp7: opp-1516800000 {
334 opp-hz = /bits/ 64 <1516800000>;
335 opp-peak-kBps = <3072000 15052800>;
338 cpu0_opp8: opp-1612800000 {
339 opp-hz = /bits/ 64 <1612800000>;
340 opp-peak-kBps = <3072000 22118400>;
343 cpu0_opp9: opp-1708800000 {
344 opp-hz = /bits/ 64 <1708800000>;
345 opp-peak-kBps = <4068000 23040000>;
349 cpu6_opp_table: opp-table-cpu6 {
350 compatible = "operating-points-v2";
351 opp-shared;
353 cpu6_opp1: opp-300000000 {
354 opp-hz = /bits/ 64 <300000000>;
355 opp-peak-kBps = <400000 4800000>;
358 cpu6_opp2: opp-652800000 {
359 opp-hz = /bits/ 64 <652800000>;
360 opp-peak-kBps = <400000 4800000>;
363 cpu6_opp3: opp-825600000 {
364 opp-hz = /bits/ 64 <825600000>;
365 opp-peak-kBps = <1200000 4800000>;
368 cpu6_opp4: opp-979200000 {
369 opp-hz = /bits/ 64 <979200000>;
370 opp-peak-kBps = <1200000 4800000>;
373 cpu6_opp5: opp-1132800000 {
374 opp-hz = /bits/ 64 <1132800000>;
375 opp-peak-kBps = <2188000 8908800>;
378 cpu6_opp6: opp-1363200000 {
379 opp-hz = /bits/ 64 <1363200000>;
380 opp-peak-kBps = <4068000 12902400>;
383 cpu6_opp7: opp-1536000000 {
384 opp-hz = /bits/ 64 <1536000000>;
385 opp-peak-kBps = <4068000 12902400>;
388 cpu6_opp8: opp-1747200000 {
389 opp-hz = /bits/ 64 <1747200000>;
390 opp-peak-kBps = <4068000 15052800>;
393 cpu6_opp9: opp-1843200000 {
394 opp-hz = /bits/ 64 <1843200000>;
395 opp-peak-kBps = <4068000 15052800>;
398 cpu6_opp10: opp-1996800000 {
399 opp-hz = /bits/ 64 <1996800000>;
400 opp-peak-kBps = <6220000 19046400>;
404 dsi_opp_table: opp-table-dsi {
405 compatible = "operating-points-v2";
407 opp-19200000 {
408 opp-hz = /bits/ 64 <19200000>;
409 required-opps = <&rpmhpd_opp_min_svs>;
412 opp-180000000 {
413 opp-hz = /bits/ 64 <180000000>;
414 required-opps = <&rpmhpd_opp_low_svs>;
417 opp-275000000 {
418 opp-hz = /bits/ 64 <275000000>;
419 required-opps = <&rpmhpd_opp_svs>;
422 opp-358000000 {
423 opp-hz = /bits/ 64 <358000000>;
424 required-opps = <&rpmhpd_opp_svs_l1>;
429 compatible = "arm,psci-1.0";
432 CPU_PD0: power-domain-cpu0 {
433 #power-domain-cells = <0>;
434 power-domains = <&CLUSTER_PD>;
435 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
438 CPU_PD1: power-domain-cpu1 {
439 #power-domain-cells = <0>;
440 power-domains = <&CLUSTER_PD>;
441 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
444 CPU_PD2: power-domain-cpu2 {
445 #power-domain-cells = <0>;
446 power-domains = <&CLUSTER_PD>;
447 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
450 CPU_PD3: power-domain-cpu3 {
451 #power-domain-cells = <0>;
452 power-domains = <&CLUSTER_PD>;
453 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
456 CPU_PD4: power-domain-cpu4 {
457 #power-domain-cells = <0>;
458 power-domains = <&CLUSTER_PD>;
459 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
462 CPU_PD5: power-domain-cpu5 {
463 #power-domain-cells = <0>;
464 power-domains = <&CLUSTER_PD>;
465 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
468 CPU_PD6: power-domain-cpu6 {
469 #power-domain-cells = <0>;
470 power-domains = <&CLUSTER_PD>;
471 domain-idle-states = <&BIG_CPU_SLEEP_0>;
474 CPU_PD7: power-domain-cpu7 {
475 #power-domain-cells = <0>;
476 power-domains = <&CLUSTER_PD>;
477 domain-idle-states = <&BIG_CPU_SLEEP_0>;
480 CLUSTER_PD: power-domain-cluster {
481 #power-domain-cells = <0>;
482 domain-idle-states = <&CLUSTER_SLEEP_0>;
486 reserved-memory {
487 #address-cells = <2>;
488 #size-cells = <2>;
491 hyp_mem: hyp-mem@85700000 {
493 no-map;
496 xbl_mem: xbl-mem@85e00000 {
498 no-map;
501 aop_mem: aop-mem@85fc0000 {
503 no-map;
506 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
507 compatible = "qcom,cmd-db";
509 no-map;
515 no-map;
521 no-map;
524 camera_mem: camera-mem@8ab00000 {
526 no-map;
531 no-map;
536 no-map;
539 wlan_msa_mem: wlan-msa@93300000 {
541 no-map;
546 no-map;
551 no-map;
556 no-map;
559 ipa_fw_mem: ipa-fw@95c00000 {
561 no-map;
564 ipa_gsi_mem: ipa-gsi@95c10000 {
566 no-map;
571 no-map;
576 no-map;
581 no-map;
586 compatible = "arm,armv8-timer";
594 #address-cells = <2>;
595 #size-cells = <2>;
597 dma-ranges = <0 0 0 0 0x10 0>;
598 compatible = "simple-bus";
600 gcc: clock-controller@100000 {
601 compatible = "qcom,gcc-sdm670";
606 clock-names = "bi_tcxo",
609 #clock-cells = <1>;
610 #reset-cells = <1>;
611 #power-domain-cells = <1>;
615 compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
617 #address-cells = <1>;
618 #size-cells = <1>;
620 qusb2_hstx_trim: hstx-trim@1eb {
627 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
631 reg-names = "hc", "cqhci", "ice";
635 interrupt-names = "hc_irq", "pwr_irq";
642 clock-names = "iface", "core", "xo", "ice", "bus";
645 interconnect-names = "sdhc-ddr", "cpu-sdhc";
646 operating-points-v2 = <&sdhc1_opp_table>;
650 pinctrl-names = "default", "sleep";
651 pinctrl-0 = <&sdc1_state_on>;
652 pinctrl-1 = <&sdc1_state_off>;
653 power-domains = <&rpmhpd SDM670_CX>;
655 bus-width = <8>;
656 non-removable;
660 sdhc1_opp_table: opp-table {
661 compatible = "operating-points-v2";
663 opp-20000000 {
664 opp-hz = /bits/ 64 <20000000>;
665 required-opps = <&rpmhpd_opp_min_svs>;
666 opp-peak-kBps = <80000 80000>;
667 opp-avg-kBps = <52286 80000>;
670 opp-50000000 {
671 opp-hz = /bits/ 64 <50000000>;
672 required-opps = <&rpmhpd_opp_low_svs>;
673 opp-peak-kBps = <200000 100000>;
674 opp-avg-kBps = <130718 100000>;
677 opp-100000000 {
678 opp-hz = /bits/ 64 <100000000>;
679 required-opps = <&rpmhpd_opp_svs>;
680 opp-peak-kBps = <200000 130000>;
681 opp-avg-kBps = <130718 130000>;
684 opp-384000000 {
685 opp-hz = /bits/ 64 <384000000>;
686 required-opps = <&rpmhpd_opp_nom>;
687 opp-peak-kBps = <4096000 4096000>;
688 opp-avg-kBps = <1338562 1338562>;
693 gpi_dma0: dma-controller@800000 {
694 #dma-cells = <3>;
695 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
710 dma-channels = <13>;
711 dma-channel-mask = <0xfa>;
717 compatible = "qcom,geni-se-qup";
719 clock-names = "m-ahb", "s-ahb";
723 #address-cells = <2>;
724 #size-cells = <2>;
727 interconnect-names = "qup-core";
731 compatible = "qcom,geni-i2c";
733 clock-names = "se";
735 pinctrl-names = "default";
736 pinctrl-0 = <&qup_i2c0_default>;
738 #address-cells = <1>;
739 #size-cells = <0>;
740 power-domains = <&rpmhpd SDM670_CX>;
744 interconnect-names = "qup-core", "qup-config", "qup-memory";
747 dma-names = "tx", "rx";
752 compatible = "qcom,geni-i2c";
754 clock-names = "se";
756 pinctrl-names = "default";
757 pinctrl-0 = <&qup_i2c1_default>;
759 #address-cells = <1>;
760 #size-cells = <0>;
761 power-domains = <&rpmhpd SDM670_CX>;
765 interconnect-names = "qup-core", "qup-config", "qup-memory";
768 dma-names = "tx", "rx";
773 compatible = "qcom,geni-i2c";
775 clock-names = "se";
777 pinctrl-names = "default";
778 pinctrl-0 = <&qup_i2c2_default>;
780 #address-cells = <1>;
781 #size-cells = <0>;
782 power-domains = <&rpmhpd SDM670_CX>;
786 interconnect-names = "qup-core", "qup-config", "qup-memory";
789 dma-names = "tx", "rx";
794 compatible = "qcom,geni-i2c";
796 clock-names = "se";
798 pinctrl-names = "default";
799 pinctrl-0 = <&qup_i2c3_default>;
801 #address-cells = <1>;
802 #size-cells = <0>;
803 power-domains = <&rpmhpd SDM670_CX>;
807 interconnect-names = "qup-core", "qup-config", "qup-memory";
810 dma-names = "tx", "rx";
815 compatible = "qcom,geni-i2c";
817 clock-names = "se";
819 pinctrl-names = "default";
820 pinctrl-0 = <&qup_i2c4_default>;
822 #address-cells = <1>;
823 #size-cells = <0>;
824 power-domains = <&rpmhpd SDM670_CX>;
828 interconnect-names = "qup-core", "qup-config", "qup-memory";
831 dma-names = "tx", "rx";
836 compatible = "qcom,geni-i2c";
838 clock-names = "se";
840 pinctrl-names = "default";
841 pinctrl-0 = <&qup_i2c5_default>;
843 #address-cells = <1>;
844 #size-cells = <0>;
845 power-domains = <&rpmhpd SDM670_CX>;
849 interconnect-names = "qup-core", "qup-config", "qup-memory";
852 dma-names = "tx", "rx";
857 compatible = "qcom,geni-i2c";
859 clock-names = "se";
861 pinctrl-names = "default";
862 pinctrl-0 = <&qup_i2c6_default>;
864 #address-cells = <1>;
865 #size-cells = <0>;
866 power-domains = <&rpmhpd SDM670_CX>;
870 interconnect-names = "qup-core", "qup-config", "qup-memory";
873 dma-names = "tx", "rx";
878 compatible = "qcom,geni-i2c";
880 clock-names = "se";
882 pinctrl-names = "default";
883 pinctrl-0 = <&qup_i2c7_default>;
885 #address-cells = <1>;
886 #size-cells = <0>;
887 power-domains = <&rpmhpd SDM670_CX>;
891 interconnect-names = "qup-core", "qup-config", "qup-memory";
894 dma-names = "tx", "rx";
899 gpi_dma1: dma-controller@a00000 {
900 #dma-cells = <3>;
901 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
916 dma-channels = <13>;
917 dma-channel-mask = <0xfa>;
923 compatible = "qcom,geni-se-qup";
925 clock-names = "m-ahb", "s-ahb";
929 #address-cells = <2>;
930 #size-cells = <2>;
933 interconnect-names = "qup-core";
937 compatible = "qcom,geni-i2c";
939 clock-names = "se";
941 pinctrl-names = "default";
942 pinctrl-0 = <&qup_i2c8_default>;
944 #address-cells = <1>;
945 #size-cells = <0>;
946 power-domains = <&rpmhpd SDM670_CX>;
950 interconnect-names = "qup-core", "qup-config", "qup-memory";
953 dma-names = "tx", "rx";
958 compatible = "qcom,geni-i2c";
960 clock-names = "se";
962 pinctrl-names = "default";
963 pinctrl-0 = <&qup_i2c9_default>;
965 #address-cells = <1>;
966 #size-cells = <0>;
967 power-domains = <&rpmhpd SDM670_CX>;
971 interconnect-names = "qup-core", "qup-config", "qup-memory";
974 dma-names = "tx", "rx";
979 compatible = "qcom,geni-i2c";
981 clock-names = "se";
983 pinctrl-names = "default";
984 pinctrl-0 = <&qup_i2c10_default>;
986 #address-cells = <1>;
987 #size-cells = <0>;
988 power-domains = <&rpmhpd SDM670_CX>;
992 interconnect-names = "qup-core", "qup-config", "qup-memory";
995 dma-names = "tx", "rx";
1000 compatible = "qcom,geni-i2c";
1002 clock-names = "se";
1004 pinctrl-names = "default";
1005 pinctrl-0 = <&qup_i2c11_default>;
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1009 power-domains = <&rpmhpd SDM670_CX>;
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1016 dma-names = "tx", "rx";
1021 compatible = "qcom,geni-i2c";
1023 clock-names = "se";
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&qup_i2c12_default>;
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 power-domains = <&rpmhpd SDM670_CX>;
1034 interconnect-names = "qup-core", "qup-config", "qup-memory";
1037 dma-names = "tx", "rx";
1042 compatible = "qcom,geni-i2c";
1044 clock-names = "se";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&qup_i2c13_default>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051 power-domains = <&rpmhpd SDM670_CX>;
1055 interconnect-names = "qup-core", "qup-config", "qup-memory";
1058 dma-names = "tx", "rx";
1063 compatible = "qcom,geni-i2c";
1065 clock-names = "se";
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&qup_i2c14_default>;
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072 power-domains = <&rpmhpd SDM670_CX>;
1076 interconnect-names = "qup-core", "qup-config", "qup-memory";
1079 dma-names = "tx", "rx";
1084 compatible = "qcom,geni-i2c";
1086 clock-names = "se";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&qup_i2c15_default>;
1091 #address-cells = <1>;
1092 #size-cells = <0>;
1093 power-domains = <&rpmhpd SDM670_CX>;
1097 interconnect-names = "qup-core", "qup-config", "qup-memory";
1100 dma-names = "tx", "rx";
1106 compatible = "qcom,sdm670-mem-noc";
1108 #interconnect-cells = <2>;
1109 qcom,bcm-voters = <&apps_bcm_voter>;
1113 compatible = "qcom,sdm670-dc-noc";
1115 #interconnect-cells = <2>;
1116 qcom,bcm-voters = <&apps_bcm_voter>;
1120 compatible = "qcom,sdm670-config-noc";
1122 #interconnect-cells = <2>;
1123 qcom,bcm-voters = <&apps_bcm_voter>;
1127 compatible = "qcom,sdm670-system-noc";
1129 #interconnect-cells = <2>;
1130 qcom,bcm-voters = <&apps_bcm_voter>;
1134 compatible = "qcom,sdm670-aggre1-noc";
1136 #interconnect-cells = <2>;
1137 qcom,bcm-voters = <&apps_bcm_voter>;
1141 compatible = "qcom,sdm670-aggre2-noc";
1143 #interconnect-cells = <2>;
1144 qcom,bcm-voters = <&apps_bcm_voter>;
1148 compatible = "qcom,sdm670-mmss-noc";
1150 #interconnect-cells = <2>;
1151 qcom,bcm-voters = <&apps_bcm_voter>;
1155 compatible = "qcom,tcsr-mutex";
1157 #hwlock-cells = <1>;
1161 compatible = "qcom,sdm670-tlmm";
1164 gpio-controller;
1165 #gpio-cells = <2>;
1166 interrupt-controller;
1167 #interrupt-cells = <2>;
1168 gpio-ranges = <&tlmm 0 0 151>;
1169 wakeup-parent = <&pdc>;
1171 qup_i2c0_default: qup-i2c0-default-state {
1176 qup_i2c1_default: qup-i2c1-default-state {
1181 qup_i2c2_default: qup-i2c2-default-state {
1186 qup_i2c3_default: qup-i2c3-default-state {
1191 qup_i2c4_default: qup-i2c4-default-state {
1196 qup_i2c5_default: qup-i2c5-default-state {
1201 qup_i2c6_default: qup-i2c6-default-state {
1206 qup_i2c7_default: qup-i2c7-default-state {
1211 qup_i2c8_default: qup-i2c8-default-state {
1216 qup_i2c9_default: qup-i2c9-default-state {
1221 qup_i2c10_default: qup-i2c10-default-state {
1226 qup_i2c11_default: qup-i2c11-default-state {
1231 qup_i2c12_default: qup-i2c12-default-state {
1236 qup_i2c13_default: qup-i2c13-default-state {
1241 qup_i2c14_default: qup-i2c14-default-state {
1246 qup_i2c15_default: qup-i2c15-default-state {
1251 sdc1_state_on: sdc1-on-state {
1252 clk-pins {
1254 bias-disable;
1255 drive-strength = <16>;
1258 cmd-pins {
1260 bias-pull-up;
1261 drive-strength = <10>;
1264 data-pins {
1266 bias-pull-up;
1267 drive-strength = <10>;
1270 rclk-pins {
1272 bias-pull-down;
1276 sdc1_state_off: sdc1-off-state {
1277 clk-pins {
1279 bias-disable;
1280 drive-strength = <2>;
1283 cmd-pins {
1285 bias-pull-up;
1286 drive-strength = <2>;
1289 data-pins {
1291 bias-pull-up;
1292 drive-strength = <2>;
1295 rclk-pins {
1297 bias-pull-down;
1303 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1305 #phy-cells = <0>;
1309 clock-names = "cfg_ahb", "ref";
1313 nvmem-cells = <&qusb2_hstx_trim>;
1319 compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1321 #address-cells = <2>;
1322 #size-cells = <2>;
1324 dma-ranges;
1331 clock-names = "cfg_noc",
1337 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1339 assigned-clock-rates = <19200000>, <150000000>;
1341 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1346 interrupt-names = "pwr_event",
1352 power-domains = <&gcc USB30_PRIM_GDSC>;
1358 interconnect-names = "usb-ddr", "apps-usb";
1370 phy-names = "usb2-phy";
1374 pdc: interrupt-controller@b220000 {
1375 compatible = "qcom,sdm670-pdc", "qcom,pdc";
1377 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1380 #interrupt-cells = <2>;
1381 interrupt-parent = <&intc>;
1382 interrupt-controller;
1386 compatible = "qcom,spmi-pmic-arb";
1392 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1393 interrupt-names = "periph_irq";
1397 #address-cells = <2>;
1398 #size-cells = <0>;
1399 interrupt-controller;
1400 #interrupt-cells = <4>;
1403 mdss: display-subsystem@ae00000 {
1404 compatible = "qcom,sdm670-mdss";
1406 reg-names = "mdss";
1408 power-domains = <&dispcc MDSS_GDSC>;
1412 clock-names = "iface", "core";
1415 interrupt-controller;
1416 #interrupt-cells = <1>;
1420 interconnect-names = "mdp0-mem", "mdp1-mem";
1425 #address-cells = <2>;
1426 #size-cells = <2>;
1431 mdss_mdp: display-controller@ae01000 {
1432 compatible = "qcom,sdm670-dpu";
1435 reg-names = "mdp", "vbif";
1442 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
1444 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1445 assigned-clock-rates = <19200000>;
1446 operating-points-v2 = <&mdp_opp_table>;
1447 power-domains = <&rpmhpd SDM670_CX>;
1449 interrupt-parent = <&mdss>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1459 remote-endpoint = <&mdss_dsi0_in>;
1466 remote-endpoint = <&mdss_dsi1_in>;
1471 mdp_opp_table: opp-table {
1472 compatible = "operating-points-v2";
1474 opp-19200000 {
1475 opp-hz = /bits/ 64 <19200000>;
1476 required-opps = <&rpmhpd_opp_min_svs>;
1479 opp-171428571 {
1480 opp-hz = /bits/ 64 <171428571>;
1481 required-opps = <&rpmhpd_opp_low_svs>;
1484 opp-358000000 {
1485 opp-hz = /bits/ 64 <358000000>;
1486 required-opps = <&rpmhpd_opp_svs_l1>;
1489 opp-430000000 {
1490 opp-hz = /bits/ 64 <430000000>;
1491 required-opps = <&rpmhpd_opp_nom>;
1497 compatible = "qcom,sdm670-dsi-ctrl",
1498 "qcom,mdss-dsi-ctrl";
1500 reg-names = "dsi_ctrl";
1502 interrupt-parent = <&mdss>;
1511 clock-names = "byte",
1517 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1519 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1522 operating-points-v2 = <&dsi_opp_table>;
1523 power-domains = <&rpmhpd SDM670_CX>;
1527 #address-cells = <1>;
1528 #size-cells = <0>;
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1539 remote-endpoint = <&dpu_intf0_out>;
1552 compatible = "qcom,dsi-phy-10nm";
1556 reg-names = "dsi_phy",
1560 #clock-cells = <1>;
1561 #phy-cells = <0>;
1565 clock-names = "iface", "ref";
1571 compatible = "qcom,sdm670-dsi-ctrl",
1572 "qcom,mdss-dsi-ctrl";
1574 reg-names = "dsi_ctrl";
1576 interrupt-parent = <&mdss>;
1585 clock-names = "byte",
1591 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
1593 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1595 operating-points-v2 = <&dsi_opp_table>;
1596 power-domains = <&rpmhpd SDM670_CX>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1606 #address-cells = <1>;
1607 #size-cells = <0>;
1612 remote-endpoint = <&dpu_intf1_out>;
1625 compatible = "qcom,dsi-phy-10nm";
1629 reg-names = "dsi_phy",
1633 #clock-cells = <1>;
1634 #phy-cells = <0>;
1638 clock-names = "iface", "ref";
1644 dispcc: clock-controller@af00000 {
1645 compatible = "qcom,sdm845-dispcc";
1656 clock-names = "bi_tcxo",
1665 #clock-cells = <1>;
1666 #reset-cells = <1>;
1667 #power-domain-cells = <1>;
1671 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1673 #iommu-cells = <2>;
1674 #global-interrupts = <1>;
1743 compatible = "qcom,sdm670-gladiator-noc";
1745 #interconnect-cells = <2>;
1746 qcom,bcm-voters = <&apps_bcm_voter>;
1750 compatible = "qcom,rpmh-rsc";
1754 reg-names = "drv-0", "drv-1", "drv-2";
1759 qcom,tcs-offset = <0xd00>;
1760 qcom,drv-id = <2>;
1761 qcom,tcs-config = <ACTIVE_TCS 2>,
1765 power-domains = <&CLUSTER_PD>;
1767 apps_bcm_voter: bcm-voter {
1768 compatible = "qcom,bcm-voter";
1771 rpmhcc: clock-controller {
1772 compatible = "qcom,sdm670-rpmh-clk";
1773 #clock-cells = <1>;
1774 clock-names = "xo";
1778 rpmhpd: power-controller {
1779 compatible = "qcom,sdm670-rpmhpd";
1780 #power-domain-cells = <1>;
1781 operating-points-v2 = <&rpmhpd_opp_table>;
1783 rpmhpd_opp_table: opp-table {
1784 compatible = "operating-points-v2";
1787 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1791 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1795 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1799 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1803 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1807 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1811 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1815 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1819 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1823 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1829 intc: interrupt-controller@17a00000 {
1830 compatible = "arm,gic-v3";
1833 interrupt-controller;
1835 #interrupt-cells = <3>;
1839 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
1843 clock-names = "xo", "alternate";
1845 #interconnect-cells = <1>;
1849 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw";
1851 reg-names = "freq-domain0", "freq-domain1";
1854 clock-names = "xo", "alternate";
1856 #freq-domain-cells = <1>;