Lines Matching +full:0 +full:x0c40a000
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
87 reg = <0x0 0x200>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x300>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
131 reg = <0x0 0x400>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
153 reg = <0x0 0x500>;
157 qcom,freq-domain = <&cpufreq_hw 0>;
175 reg = <0x0 0x600>;
197 reg = <0x0 0x700>;
255 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
258 arm,psci-suspend-param = <0x40000004>;
265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
268 arm,psci-suspend-param = <0x40000004>;
277 CLUSTER_SLEEP_0: cluster-sleep-0 {
279 arm,psci-suspend-param = <0x4100c244>;
296 reg = <0x0 0x80000000 0x0 0x0>;
433 #power-domain-cells = <0>;
439 #power-domain-cells = <0>;
445 #power-domain-cells = <0>;
451 #power-domain-cells = <0>;
457 #power-domain-cells = <0>;
463 #power-domain-cells = <0>;
469 #power-domain-cells = <0>;
475 #power-domain-cells = <0>;
481 #power-domain-cells = <0>;
492 reg = <0 0x85700000 0 0x600000>;
497 reg = <0 0x85e00000 0 0x100000>;
502 reg = <0 0x85fc0000 0 0x20000>;
508 reg = <0 0x85fe0000 0 0x20000>;
514 reg = <0 0x86000000 0 0x200000>;
520 reg = <0 0x86200000 0 0x2d00000>;
525 reg = <0 0x8ab00000 0 0x500000>;
530 reg = <0 0x8b000000 0 0x7e00000>;
535 reg = <0 0x92e00000 0 0x500000>;
540 reg = <0 0x93300000 0 0x100000>;
545 reg = <0 0x93400000 0 0x800000>;
550 reg = <0 0x93c00000 0 0x200000>;
555 reg = <0 0x93e00000 0 0x1e00000>;
560 reg = <0 0x95c00000 0 0x10000>;
565 reg = <0 0x95c10000 0 0x5000>;
570 reg = <0 0x95c15000 0 0x2000>;
575 reg = <0 0x97b00000 0 0x100000>;
580 reg = <0 0x9e400000 0 0x1400000>;
590 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
593 soc: soc@0 {
596 ranges = <0 0 0 0 0x10 0>;
597 dma-ranges = <0 0 0 0 0x10 0>;
602 reg = <0 0x00100000 0 0x1f0000>;
616 reg = <0 0x00784000 0 0x1000>;
621 reg = <0x1eb 0x1>;
628 reg = <0 0x007c4000 0 0x1000>,
629 <0 0x007c5000 0 0x1000>,
630 <0 0x007c8000 0 0x8000>;
643 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
644 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
648 iommus = <&apps_smmu 0x140 0xf>;
651 pinctrl-0 = <&sdc1_state_on>;
696 reg = <0 0x00800000 0 0x60000>;
711 dma-channel-mask = <0xfa>;
712 iommus = <&apps_smmu 0x16 0x0>;
718 reg = <0 0x008c0000 0 0x6000>;
722 iommus = <&apps_smmu 0x3 0x0>;
726 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
732 reg = <0 0x00880000 0 0x4000>;
736 pinctrl-0 = <&qup_i2c0_default>;
739 #size-cells = <0>;
741 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
742 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
743 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
745 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
746 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
753 reg = <0 0x00884000 0 0x4000>;
757 pinctrl-0 = <&qup_i2c1_default>;
760 #size-cells = <0>;
762 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
763 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
764 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
766 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
774 reg = <0 0x00888000 0 0x4000>;
778 pinctrl-0 = <&qup_i2c2_default>;
781 #size-cells = <0>;
783 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
784 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
785 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
787 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
795 reg = <0 0x0088c000 0 0x4000>;
799 pinctrl-0 = <&qup_i2c3_default>;
802 #size-cells = <0>;
804 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
805 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
806 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
808 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
816 reg = <0 0x00890000 0 0x4000>;
820 pinctrl-0 = <&qup_i2c4_default>;
823 #size-cells = <0>;
825 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
826 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
827 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
829 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
837 reg = <0 0x00894000 0 0x4000>;
841 pinctrl-0 = <&qup_i2c5_default>;
844 #size-cells = <0>;
846 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
847 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
848 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
850 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
858 reg = <0 0x00898000 0 0x4000>;
862 pinctrl-0 = <&qup_i2c6_default>;
865 #size-cells = <0>;
867 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
868 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
869 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
871 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
879 reg = <0 0x0089c000 0 0x4000>;
883 pinctrl-0 = <&qup_i2c7_default>;
886 #size-cells = <0>;
888 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
889 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
890 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
892 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
902 reg = <0 0x00a00000 0 0x60000>;
917 dma-channel-mask = <0xfa>;
918 iommus = <&apps_smmu 0x6d6 0x0>;
924 reg = <0 0x00ac0000 0 0x6000>;
928 iommus = <&apps_smmu 0x6c3 0x0>;
932 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
938 reg = <0 0x00a80000 0 0x4000>;
942 pinctrl-0 = <&qup_i2c8_default>;
945 #size-cells = <0>;
947 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
948 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
949 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
951 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
952 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
959 reg = <0 0x00a84000 0 0x4000>;
963 pinctrl-0 = <&qup_i2c9_default>;
966 #size-cells = <0>;
968 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
969 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
970 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
972 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
980 reg = <0 0x00a88000 0 0x4000>;
984 pinctrl-0 = <&qup_i2c10_default>;
987 #size-cells = <0>;
989 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
990 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
991 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
993 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1001 reg = <0 0x00a8c000 0 0x4000>;
1005 pinctrl-0 = <&qup_i2c11_default>;
1008 #size-cells = <0>;
1010 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1011 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1012 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1014 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1022 reg = <0 0x00a90000 0 0x4000>;
1026 pinctrl-0 = <&qup_i2c12_default>;
1029 #size-cells = <0>;
1031 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1032 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1033 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1035 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1043 reg = <0 0x00a94000 0 0x4000>;
1047 pinctrl-0 = <&qup_i2c13_default>;
1050 #size-cells = <0>;
1052 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1053 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1054 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1056 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1064 reg = <0 0x00a98000 0 0x4000>;
1068 pinctrl-0 = <&qup_i2c14_default>;
1071 #size-cells = <0>;
1073 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1074 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1075 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1077 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1085 reg = <0 0x00a9c000 0 0x4000>;
1089 pinctrl-0 = <&qup_i2c15_default>;
1092 #size-cells = <0>;
1094 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1095 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1096 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1098 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1107 reg = <0 0x01380000 0 0x27200>;
1114 reg = <0 0x014e0000 0 0x400>;
1121 reg = <0 0x01500000 0 0x5080>;
1128 reg = <0 0x01620000 0 0x18080>;
1135 reg = <0 0x016e0000 0 0x15080>;
1142 reg = <0 0x01700000 0 0x1f300>;
1149 reg = <0 0x01740000 0 0x1c100>;
1156 reg = <0 0x01f40000 0 0x20000>;
1162 reg = <0 0x03400000 0 0xc00000>;
1168 gpio-ranges = <&tlmm 0 0 151>;
1304 reg = <0 0x088e2000 0 0x400>;
1305 #phy-cells = <0>;
1320 reg = <0 0x0a6f8800 0 0x400>;
1356 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1357 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1364 reg = <0 0x0a600000 0 0xcd00>;
1366 iommus = <&apps_smmu 0x740 0>;
1376 reg = <0 0x0b220000 0 0x30000>;
1377 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1387 reg = <0 0x0c440000 0 0x1100>,
1388 <0 0x0c600000 0 0x2000000>,
1389 <0 0x0e600000 0 0x100000>,
1390 <0 0x0e700000 0 0xa0000>,
1391 <0 0x0c40a000 0 0x26000>;
1395 qcom,ee = <0>;
1396 qcom,channel = <0>;
1398 #size-cells = <0>;
1405 reg = <0 0x0ae00000 0 0x1000>;
1418 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
1419 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
1422 iommus = <&apps_smmu 0x880 0x8>,
1423 <&apps_smmu 0xc80 0x8>;
1433 reg = <0 0x0ae01000 0 0x8f000>,
1434 <0 0x0aeb0000 0 0x2008>;
1450 interrupts = <0>;
1454 #size-cells = <0>;
1456 port@0 {
1457 reg = <0>;
1499 reg = <0 0x0ae94000 0 0x400>;
1519 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1528 #size-cells = <0>;
1534 #size-cells = <0>;
1536 port@0 {
1537 reg = <0>;
1553 reg = <0 0x0ae94400 0 0x200>,
1554 <0 0x0ae94600 0 0x280>,
1555 <0 0x0ae94a00 0 0x1e0>;
1561 #phy-cells = <0>;
1573 reg = <0 0x0ae96000 0 0x400>;
1593 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1601 #size-cells = <0>;
1607 #size-cells = <0>;
1609 port@0 {
1610 reg = <0>;
1626 reg = <0 0x0ae96400 0 0x200>,
1627 <0 0x0ae96600 0 0x280>,
1628 <0 0x0ae96a00 0 0x10e>;
1634 #phy-cells = <0>;
1646 reg = <0 0x0af00000 0 0x10000>;
1650 <&mdss_dsi0_phy 0>,
1652 <&mdss_dsi1_phy 0>,
1654 <0>,
1655 <0>;
1672 reg = <0 0x15000000 0 0x80000>;
1744 reg = <0 0x17900000 0 0xd080>;
1751 reg = <0 0x179c0000 0 0x10000>,
1752 <0 0x179d0000 0 0x10000>,
1753 <0 0x179e0000 0 0x10000>;
1754 reg-names = "drv-0", "drv-1", "drv-2";
1759 qcom,tcs-offset = <0xd00>;
1831 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1832 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1840 reg = <0 0x17d41000 0 0x1400>;
1850 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;