Lines Matching +full:0 +full:x0ad00000
37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x300>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
148 reg = <0x0 0x400>;
152 qcom,freq-domain = <&cpufreq_hw 0>;
170 reg = <0x0 0x500>;
174 qcom,freq-domain = <&cpufreq_hw 0>;
192 reg = <0x0 0x600>;
214 reg = <0x0 0x700>;
272 little_cpu_sleep_0: cpu-sleep-0-0 {
275 arm,psci-suspend-param = <0x40000004>;
282 big_cpu_sleep_0: cpu-sleep-1-0 {
285 arm,psci-suspend-param = <0x40000004>;
294 cluster_sleep_0: cluster-sleep-0 {
296 arm,psci-suspend-param = <0x4100c244>;
313 reg = <0x0 0x80000000 0x0 0x0>;
450 #power-domain-cells = <0>;
456 #power-domain-cells = <0>;
462 #power-domain-cells = <0>;
468 #power-domain-cells = <0>;
474 #power-domain-cells = <0>;
480 #power-domain-cells = <0>;
486 #power-domain-cells = <0>;
492 #power-domain-cells = <0>;
498 #power-domain-cells = <0>;
509 reg = <0 0x85700000 0 0x600000>;
514 reg = <0 0x85e00000 0 0x100000>;
519 reg = <0 0x85fc0000 0 0x20000>;
525 reg = <0 0x85fe0000 0 0x20000>;
531 reg = <0 0x86000000 0 0x200000>;
537 reg = <0 0x86200000 0 0x2d00000>;
542 reg = <0 0x8ab00000 0 0x500000>;
547 reg = <0 0x8b000000 0 0x7e00000>;
552 reg = <0 0x92e00000 0 0x500000>;
557 reg = <0 0x93300000 0 0x100000>;
562 reg = <0 0x93400000 0 0x800000>;
567 reg = <0 0x93c00000 0 0x200000>;
572 reg = <0 0x93e00000 0 0x1e00000>;
577 reg = <0 0x95c00000 0 0x10000>;
582 reg = <0 0x95c10000 0 0x5000>;
587 reg = <0 0x95c15000 0 0x2000>;
592 reg = <0 0x97b00000 0 0x100000>;
597 reg = <0 0x9e400000 0 0x1400000>;
607 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
610 soc: soc@0 {
613 ranges = <0 0 0 0 0x10 0>;
614 dma-ranges = <0 0 0 0 0x10 0>;
619 reg = <0 0x00100000 0 0x1f0000>;
633 reg = <0 0x00784000 0 0x1000>;
638 reg = <0x1a2 0x2>;
643 reg = <0x1eb 0x1>;
650 reg = <0 0x007c4000 0 0x1000>,
651 <0 0x007c5000 0 0x1000>,
652 <0 0x007c8000 0 0x8000>;
665 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
666 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
670 iommus = <&apps_smmu 0x140 0xf>;
673 pinctrl-0 = <&sdc1_state_on>;
718 reg = <0 0x00800000 0 0x60000>;
733 dma-channel-mask = <0xfa>;
734 iommus = <&apps_smmu 0x16 0x0>;
740 reg = <0 0x008c0000 0 0x6000>;
744 iommus = <&apps_smmu 0x3 0x0>;
748 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
754 reg = <0 0x00880000 0 0x4000>;
758 pinctrl-0 = <&qup_i2c0_default>;
761 #size-cells = <0>;
763 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
764 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
765 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
767 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
768 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
775 reg = <0 0x00884000 0 0x4000>;
779 pinctrl-0 = <&qup_i2c1_default>;
782 #size-cells = <0>;
784 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
785 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
786 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
788 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
796 reg = <0 0x00888000 0 0x4000>;
800 pinctrl-0 = <&qup_i2c2_default>;
803 #size-cells = <0>;
805 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
806 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
807 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
809 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
817 reg = <0 0x0088c000 0 0x4000>;
821 pinctrl-0 = <&qup_i2c3_default>;
824 #size-cells = <0>;
826 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
827 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
828 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
830 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
838 reg = <0 0x00890000 0 0x4000>;
842 pinctrl-0 = <&qup_i2c4_default>;
845 #size-cells = <0>;
847 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
848 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
849 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
851 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
859 reg = <0 0x00894000 0 0x4000>;
863 pinctrl-0 = <&qup_i2c5_default>;
866 #size-cells = <0>;
868 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
869 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
870 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
872 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
880 reg = <0 0x00898000 0 0x4000>;
884 pinctrl-0 = <&qup_i2c6_default>;
887 #size-cells = <0>;
889 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
890 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
891 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
893 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
901 reg = <0 0x0089c000 0 0x4000>;
905 pinctrl-0 = <&qup_i2c7_default>;
908 #size-cells = <0>;
910 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
911 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
912 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
914 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
924 reg = <0 0x00a00000 0 0x60000>;
939 dma-channel-mask = <0xfa>;
940 iommus = <&apps_smmu 0x6d6 0x0>;
946 reg = <0 0x00ac0000 0 0x6000>;
950 iommus = <&apps_smmu 0x6c3 0x0>;
954 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
960 reg = <0 0x00a80000 0 0x4000>;
964 pinctrl-0 = <&qup_i2c8_default>;
967 #size-cells = <0>;
969 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
970 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
971 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
973 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
974 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
981 reg = <0 0x00a84000 0 0x4000>;
985 pinctrl-0 = <&qup_i2c9_default>;
988 #size-cells = <0>;
990 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
991 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
992 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
994 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1002 reg = <0 0x00a88000 0 0x4000>;
1006 pinctrl-0 = <&qup_i2c10_default>;
1009 #size-cells = <0>;
1011 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1012 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1013 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1015 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1023 reg = <0 0x00a8c000 0 0x4000>;
1027 pinctrl-0 = <&qup_i2c11_default>;
1030 #size-cells = <0>;
1032 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1033 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1034 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1036 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1044 reg = <0 0x00a90000 0 0x4000>;
1048 pinctrl-0 = <&qup_i2c12_default>;
1051 #size-cells = <0>;
1053 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1054 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1055 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1057 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1065 reg = <0 0x00a94000 0 0x4000>;
1069 pinctrl-0 = <&qup_i2c13_default>;
1072 #size-cells = <0>;
1074 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1075 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1076 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1078 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1086 reg = <0 0x00a98000 0 0x4000>;
1090 pinctrl-0 = <&qup_i2c14_default>;
1093 #size-cells = <0>;
1095 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1096 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1097 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1099 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1107 reg = <0 0x00a9c000 0 0x4000>;
1111 pinctrl-0 = <&qup_i2c15_default>;
1114 #size-cells = <0>;
1116 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1117 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1118 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1120 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1129 reg = <0 0x01380000 0 0x27200>;
1136 reg = <0 0x014e0000 0 0x400>;
1143 reg = <0 0x01500000 0 0x5080>;
1150 reg = <0 0x01620000 0 0x18080>;
1157 reg = <0 0x016e0000 0 0x15080>;
1164 reg = <0 0x01700000 0 0x1f300>;
1171 reg = <0 0x01740000 0 0x1c100>;
1178 reg = <0 0x01f40000 0 0x20000>;
1184 reg = <0 0x03400000 0 0xc00000>;
1190 gpio-ranges = <&tlmm 0 0 151>;
1355 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;
1365 iommus = <&adreno_smmu 0>;
1371 interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>;
1386 opp-supported-hw = <0x8>;
1393 opp-supported-hw = <0x8>;
1400 opp-supported-hw = <0x4>;
1407 opp-supported-hw = <0xc>;
1414 opp-supported-hw = <0xc>;
1421 opp-supported-hw = <0x2>;
1428 opp-supported-hw = <0xf>;
1435 opp-supported-hw = <0xf>;
1442 opp-supported-hw = <0xf>;
1449 opp-supported-hw = <0xf>;
1456 reg = <0 0x05040000 0 0x10000>;
1479 reg = <0 0x0506a000 0 0x30000>,
1480 <0 0x0b280000 0 0x10000>,
1481 <0 0x0b480000 0 0x10000>;
1514 reg = <0 0x05090000 0 0x9000>;
1528 reg = <0 0x088e2000 0 0x400>;
1529 #phy-cells = <0>;
1544 reg = <0 0x0a6f8800 0 0x400>;
1580 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1581 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1588 reg = <0 0x0a600000 0 0xcd00>;
1590 iommus = <&apps_smmu 0x740 0>;
1600 reg = <0 0x0b220000 0 0x30000>;
1601 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1611 reg = <0 0x0c440000 0 0x1100>,
1612 <0 0x0c600000 0 0x2000000>,
1613 <0 0x0e600000 0 0x100000>,
1614 <0 0x0e700000 0 0xa0000>,
1615 <0 0x0c40a000 0 0x26000>;
1619 qcom,ee = <0>;
1620 qcom,channel = <0>;
1622 #size-cells = <0>;
1630 #size-cells = <0>;
1632 reg = <0 0x0ac4a000 0 0x4000>;
1646 pinctrl-0 = <&cci0_default &cci1_default>;
1651 cci_i2c0: i2c-bus@0 {
1652 reg = <0>;
1655 #size-cells = <0>;
1662 #size-cells = <0>;
1668 reg = <0 0x0acb3000 0 0x1000>,
1669 <0 0x0acba000 0 0x1000>,
1670 <0 0x0acc8000 0 0x1000>,
1671 <0 0x0ac65000 0 0x1000>,
1672 <0 0x0ac66000 0 0x1000>,
1673 <0 0x0ac67000 0 0x1000>,
1674 <0 0x0acaf000 0 0x4000>,
1675 <0 0x0acb6000 0 0x4000>,
1676 <0 0x0acc4000 0 0x4000>;
1751 iommus = <&apps_smmu 0x808 0x0>,
1752 <&apps_smmu 0x810 0x8>,
1753 <&apps_smmu 0xc08 0x0>,
1754 <&apps_smmu 0xc10 0x8>;
1767 #size-cells = <0>;
1769 port@0 {
1770 reg = <0>;
1797 reg = <0 0x0ad00000 0 0x10000>;
1807 reg = <0 0x0ae00000 0 0x1000>;
1820 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
1821 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
1824 iommus = <&apps_smmu 0x880 0x8>,
1825 <&apps_smmu 0xc80 0x8>;
1835 reg = <0 0x0ae01000 0 0x8f000>,
1836 <0 0x0aeb0000 0 0x3000>;
1852 interrupts = <0>;
1856 #size-cells = <0>;
1858 port@0 {
1859 reg = <0>;
1901 reg = <0 0x0ae94000 0 0x400>;
1930 #size-cells = <0>;
1936 #size-cells = <0>;
1938 port@0 {
1939 reg = <0>;
1955 reg = <0 0x0ae94400 0 0x200>,
1956 <0 0x0ae94600 0 0x280>,
1957 <0 0x0ae94a00 0 0x1e0>;
1963 #phy-cells = <0>;
1975 reg = <0 0x0ae96000 0 0x400>;
2004 #size-cells = <0>;
2010 #size-cells = <0>;
2012 port@0 {
2013 reg = <0>;
2029 reg = <0 0x0ae96400 0 0x200>,
2030 <0 0x0ae96600 0 0x280>,
2031 <0 0x0ae96a00 0 0x10e>;
2037 #phy-cells = <0>;
2049 reg = <0 0x0af00000 0 0x10000>;
2057 <0>,
2058 <0>;
2075 reg = <0 0x15000000 0 0x80000>;
2148 reg = <0 0x17900000 0 0xd080>;
2155 reg = <0 0x179c0000 0 0x10000>,
2156 <0 0x179d0000 0 0x10000>,
2157 <0 0x179e0000 0 0x10000>;
2158 reg-names = "drv-0", "drv-1", "drv-2";
2163 qcom,tcs-offset = <0xd00>;
2235 reg = <0 0x17a00000 0 0x10000>, /* GICD */
2236 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
2244 reg = <0 0x17d41000 0 0x1400>;
2254 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;