Lines Matching +full:smp2p +full:- +full:mpss
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
9 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
10 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/interconnect/qcom,sdm660.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/soc/qcom,apr.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <19200000>;
38 clock-output-names = "xo_board";
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <32764>;
45 clock-output-names = "sleep_clk";
50 #address-cells = <2>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 cpu-idle-states = <&perf_cpu_sleep_0
63 capacity-dmips-mhz = <1126>;
64 #cooling-cells = <2>;
65 next-level-cache = <&l2_1>;
66 l2_1: l2-cache {
68 cache-level = <2>;
69 cache-unified;
75 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 cpu-idle-states = <&perf_cpu_sleep_0
83 capacity-dmips-mhz = <1126>;
84 #cooling-cells = <2>;
85 next-level-cache = <&l2_1>;
90 compatible = "arm,cortex-a53";
92 enable-method = "psci";
93 cpu-idle-states = <&perf_cpu_sleep_0
98 capacity-dmips-mhz = <1126>;
99 #cooling-cells = <2>;
100 next-level-cache = <&l2_1>;
105 compatible = "arm,cortex-a53";
107 enable-method = "psci";
108 cpu-idle-states = <&perf_cpu_sleep_0
113 capacity-dmips-mhz = <1126>;
114 #cooling-cells = <2>;
115 next-level-cache = <&l2_1>;
120 compatible = "arm,cortex-a53";
122 enable-method = "psci";
123 cpu-idle-states = <&pwr_cpu_sleep_0
128 capacity-dmips-mhz = <1024>;
129 #cooling-cells = <2>;
130 next-level-cache = <&l2_0>;
131 l2_0: l2-cache {
133 cache-level = <2>;
134 cache-unified;
140 compatible = "arm,cortex-a53";
142 enable-method = "psci";
143 cpu-idle-states = <&pwr_cpu_sleep_0
148 capacity-dmips-mhz = <1024>;
149 #cooling-cells = <2>;
150 next-level-cache = <&l2_0>;
155 compatible = "arm,cortex-a53";
157 enable-method = "psci";
158 cpu-idle-states = <&pwr_cpu_sleep_0
163 capacity-dmips-mhz = <1024>;
164 #cooling-cells = <2>;
165 next-level-cache = <&l2_0>;
170 compatible = "arm,cortex-a53";
172 enable-method = "psci";
173 cpu-idle-states = <&pwr_cpu_sleep_0
178 capacity-dmips-mhz = <1024>;
179 #cooling-cells = <2>;
180 next-level-cache = <&l2_0>;
183 cpu-map {
221 idle-states {
222 entry-method = "psci";
224 pwr_cpu_sleep_0: cpu-sleep-0-0 {
225 compatible = "arm,idle-state";
226 idle-state-name = "pwr-retention";
227 arm,psci-suspend-param = <0x40000002>;
228 entry-latency-us = <338>;
229 exit-latency-us = <423>;
230 min-residency-us = <200>;
233 pwr_cpu_sleep_1: cpu-sleep-0-1 {
234 compatible = "arm,idle-state";
235 idle-state-name = "pwr-power-collapse";
236 arm,psci-suspend-param = <0x40000003>;
237 entry-latency-us = <515>;
238 exit-latency-us = <1821>;
239 min-residency-us = <1000>;
240 local-timer-stop;
243 perf_cpu_sleep_0: cpu-sleep-1-0 {
244 compatible = "arm,idle-state";
245 idle-state-name = "perf-retention";
246 arm,psci-suspend-param = <0x40000002>;
247 entry-latency-us = <154>;
248 exit-latency-us = <87>;
249 min-residency-us = <200>;
252 perf_cpu_sleep_1: cpu-sleep-1-1 {
253 compatible = "arm,idle-state";
254 idle-state-name = "perf-power-collapse";
255 arm,psci-suspend-param = <0x40000003>;
256 entry-latency-us = <262>;
257 exit-latency-us = <301>;
258 min-residency-us = <1000>;
259 local-timer-stop;
262 pwr_cluster_sleep_0: cluster-sleep-0-0 {
263 compatible = "arm,idle-state";
264 idle-state-name = "pwr-cluster-dynamic-retention";
265 arm,psci-suspend-param = <0x400000F2>;
266 entry-latency-us = <284>;
267 exit-latency-us = <384>;
268 min-residency-us = <9987>;
269 local-timer-stop;
272 pwr_cluster_sleep_1: cluster-sleep-0-1 {
273 compatible = "arm,idle-state";
274 idle-state-name = "pwr-cluster-retention";
275 arm,psci-suspend-param = <0x400000F3>;
276 entry-latency-us = <338>;
277 exit-latency-us = <423>;
278 min-residency-us = <9987>;
279 local-timer-stop;
282 pwr_cluster_sleep_2: cluster-sleep-0-2 {
283 compatible = "arm,idle-state";
284 idle-state-name = "pwr-cluster-retention";
285 arm,psci-suspend-param = <0x400000F4>;
286 entry-latency-us = <515>;
287 exit-latency-us = <1821>;
288 min-residency-us = <9987>;
289 local-timer-stop;
292 perf_cluster_sleep_0: cluster-sleep-1-0 {
293 compatible = "arm,idle-state";
294 idle-state-name = "perf-cluster-dynamic-retention";
295 arm,psci-suspend-param = <0x400000F2>;
296 entry-latency-us = <272>;
297 exit-latency-us = <329>;
298 min-residency-us = <9987>;
299 local-timer-stop;
302 perf_cluster_sleep_1: cluster-sleep-1-1 {
303 compatible = "arm,idle-state";
304 idle-state-name = "perf-cluster-retention";
305 arm,psci-suspend-param = <0x400000F3>;
306 entry-latency-us = <332>;
307 exit-latency-us = <368>;
308 min-residency-us = <9987>;
309 local-timer-stop;
312 perf_cluster_sleep_2: cluster-sleep-1-2 {
313 compatible = "arm,idle-state";
314 idle-state-name = "perf-cluster-retention";
315 arm,psci-suspend-param = <0x400000F4>;
316 entry-latency-us = <545>;
317 exit-latency-us = <1609>;
318 min-residency-us = <9987>;
319 local-timer-stop;
326 compatible = "qcom,scm-msm8998", "qcom,scm";
336 dsi_opp_table: opp-table-dsi {
337 compatible = "operating-points-v2";
339 opp-131250000 {
340 opp-hz = /bits/ 64 <131250000>;
341 required-opps = <&rpmpd_opp_svs>;
344 opp-210000000 {
345 opp-hz = /bits/ 64 <210000000>;
346 required-opps = <&rpmpd_opp_svs_plus>;
349 opp-262500000 {
350 opp-hz = /bits/ 64 <262500000>;
351 required-opps = <&rpmpd_opp_nom>;
356 compatible = "arm,armv8-pmuv3";
361 compatible = "arm,psci-1.0";
366 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
368 glink-edge {
369 compatible = "qcom,glink-rpm";
372 qcom,rpm-msg-ram = <&rpm_msg_ram>;
375 rpm_requests: rpm-requests {
376 compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm";
377 qcom,glink-channels = "rpm_requests";
379 rpmcc: clock-controller {
380 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
381 #clock-cells = <1>;
384 rpmpd: power-controller {
385 compatible = "qcom,sdm660-rpmpd";
386 #power-domain-cells = <1>;
387 operating-points-v2 = <&rpmpd_opp_table>;
389 rpmpd_opp_table: opp-table {
390 compatible = "operating-points-v2";
393 opp-level = <RPM_SMD_LEVEL_RETENTION>;
397 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
401 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
405 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
409 opp-level = <RPM_SMD_LEVEL_SVS>;
413 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
417 opp-level = <RPM_SMD_LEVEL_NOM>;
421 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
425 opp-level = <RPM_SMD_LEVEL_TURBO>;
433 reserved-memory {
434 #address-cells = <2>;
435 #size-cells = <2>;
438 wlan_msa_guard: wlan-msa-guard@85600000 {
440 no-map;
443 wlan_msa_mem: wlan-msa-mem@85700000 {
445 no-map;
448 qhee_code: qhee-code@85800000 {
450 no-map;
454 compatible = "qcom,rmtfs-mem";
456 no-map;
458 qcom,client-id = <1>;
462 smem_region: smem-mem@86000000 {
464 no-map;
469 no-map;
472 mpss_region: mpss@8ac00000 {
474 no-map;
479 no-map;
484 no-map;
489 no-map;
494 no-map;
497 adsp_mem: adsp-region@f6000000 {
499 no-map;
502 qseecom_mem: qseecom-region@f6800000 {
504 no-map;
508 compatible = "shared-dma-pool";
510 no-map;
513 mdata_mem: mpss-metadata {
514 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
516 no-map;
522 memory-region = <&smem_region>;
526 smp2p-adsp {
527 compatible = "qcom,smp2p";
531 qcom,local-pid = <0>;
532 qcom,remote-pid = <2>;
534 adsp_smp2p_out: master-kernel {
535 qcom,entry-name = "master-kernel";
536 #qcom,smem-state-cells = <1>;
539 adsp_smp2p_in: slave-kernel {
540 qcom,entry-name = "slave-kernel";
541 interrupt-controller;
542 #interrupt-cells = <2>;
546 smp2p-mpss {
547 compatible = "qcom,smp2p";
551 qcom,local-pid = <0>;
552 qcom,remote-pid = <1>;
554 modem_smp2p_out: master-kernel {
555 qcom,entry-name = "master-kernel";
556 #qcom,smem-state-cells = <1>;
559 modem_smp2p_in: slave-kernel {
560 qcom,entry-name = "slave-kernel";
561 interrupt-controller;
562 #interrupt-cells = <2>;
567 #address-cells = <1>;
568 #size-cells = <1>;
570 compatible = "simple-bus";
572 gcc: clock-controller@100000 {
573 compatible = "qcom,gcc-sdm630";
574 #clock-cells = <1>;
575 #reset-cells = <1>;
576 #power-domain-cells = <1>;
579 clock-names = "xo", "sleep_clk";
585 compatible = "qcom,rpm-msg-ram";
590 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
592 #address-cells = <1>;
593 #size-cells = <1>;
595 qusb2_hstx_trim: hstx-trim@240 {
600 gpu_speed_bin: gpu-speed-bin@41a0 {
607 compatible = "qcom,prng-ee";
610 clock-names = "core";
614 compatible = "qcom,sdm660-bimc";
616 #interconnect-cells = <1>;
625 compatible = "qcom,sdm660-cnoc";
627 #interconnect-cells = <1>;
631 compatible = "qcom,sdm660-snoc";
633 #interconnect-cells = <1>;
637 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
639 #global-interrupts = <2>;
640 #iommu-cells = <1>;
678 compatible = "qcom,sdm660-a2noc";
680 #interconnect-cells = <1>;
681 clock-names = "ipa",
694 compatible = "qcom,sdm660-mnoc";
696 #interconnect-cells = <1>;
697 clock-names = "iface";
701 tsens: thermal-sensor@10ae000 {
702 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
708 interrupt-names = "uplow", "critical";
709 #thermal-sensor-cells = <1>;
713 compatible = "qcom,tcsr-mutex";
715 #hwlock-cells = <1>;
719 compatible = "qcom,sdm630-tcsr", "syscon";
724 compatible = "qcom,sdm630-pinctrl";
728 reg-names = "south", "center", "north";
730 gpio-controller;
731 gpio-ranges = <&tlmm 0 0 114>;
732 #gpio-cells = <2>;
733 interrupt-controller;
734 #interrupt-cells = <2>;
736 blsp1_uart1_default: blsp1-uart1-default-state {
739 drive-strength = <2>;
740 bias-disable;
743 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
746 drive-strength = <2>;
747 bias-disable;
750 blsp1_uart2_default: blsp1-uart2-default-state {
753 drive-strength = <2>;
754 bias-disable;
757 blsp2_uart1_default: blsp2-uart1-active-state {
758 tx-rts-pins {
761 drive-strength = <2>;
762 bias-disable;
765 rx-pins {
772 drive-strength = <2>;
773 bias-pull-up;
776 cts-pins {
780 drive-strength = <2>;
781 bias-pull-down;
785 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
786 tx-pins {
789 drive-strength = <2>;
790 bias-pull-up;
793 rx-cts-rts-pins {
796 drive-strength = <2>;
797 bias-disable;
801 i2c1_default: i2c1-default-state {
804 drive-strength = <2>;
805 bias-disable;
808 i2c1_sleep: i2c1-sleep-state {
811 drive-strength = <2>;
812 bias-pull-up;
815 i2c2_default: i2c2-default-state {
818 drive-strength = <2>;
819 bias-disable;
822 i2c2_sleep: i2c2-sleep-state {
825 drive-strength = <2>;
826 bias-pull-up;
829 i2c3_default: i2c3-default-state {
832 drive-strength = <2>;
833 bias-disable;
836 i2c3_sleep: i2c3-sleep-state {
839 drive-strength = <2>;
840 bias-pull-up;
843 i2c4_default: i2c4-default-state {
846 drive-strength = <2>;
847 bias-disable;
850 i2c4_sleep: i2c4-sleep-state {
853 drive-strength = <2>;
854 bias-pull-up;
857 i2c5_default: i2c5-default-state {
860 drive-strength = <2>;
861 bias-disable;
864 i2c5_sleep: i2c5-sleep-state {
867 drive-strength = <2>;
868 bias-pull-up;
871 i2c6_default: i2c6-default-state {
874 drive-strength = <2>;
875 bias-disable;
878 i2c6_sleep: i2c6-sleep-state {
881 drive-strength = <2>;
882 bias-pull-up;
885 i2c7_default: i2c7-default-state {
888 drive-strength = <2>;
889 bias-disable;
892 i2c7_sleep: i2c7-sleep-state {
895 drive-strength = <2>;
896 bias-pull-up;
899 i2c8_default: i2c8-default-state {
902 drive-strength = <2>;
903 bias-disable;
906 i2c8_sleep: i2c8-sleep-state {
909 drive-strength = <2>;
910 bias-pull-up;
913 cci0_default: cci0-default-state {
916 bias-pull-up;
917 drive-strength = <2>;
920 cci1_default: cci1-default-state {
923 bias-pull-up;
924 drive-strength = <2>;
927 sdc1_state_on: sdc1-on-state {
928 clk-pins {
930 bias-disable;
931 drive-strength = <16>;
934 cmd-pins {
936 bias-pull-up;
937 drive-strength = <10>;
940 data-pins {
942 bias-pull-up;
943 drive-strength = <10>;
946 rclk-pins {
948 bias-pull-down;
952 sdc1_state_off: sdc1-off-state {
953 clk-pins {
955 bias-disable;
956 drive-strength = <2>;
959 cmd-pins {
961 bias-pull-up;
962 drive-strength = <2>;
965 data-pins {
967 bias-pull-up;
968 drive-strength = <2>;
971 rclk-pins {
973 bias-pull-down;
977 sdc2_state_on: sdc2-on-state {
978 clk-pins {
980 bias-disable;
981 drive-strength = <16>;
984 cmd-pins {
986 bias-pull-up;
987 drive-strength = <10>;
990 data-pins {
992 bias-pull-up;
993 drive-strength = <10>;
997 sdc2_state_off: sdc2-off-state {
998 clk-pins {
1000 bias-disable;
1001 drive-strength = <2>;
1004 cmd-pins {
1006 bias-pull-up;
1007 drive-strength = <2>;
1010 data-pins {
1012 bias-pull-up;
1013 drive-strength = <2>;
1019 compatible = "qcom,sdm660-mss-pil";
1021 reg-names = "qdsp6", "rmb";
1023 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1029 interrupt-names = "wdog",
1033 "stop-ack",
1034 "shutdown-ack";
1044 clock-names = "iface",
1053 qcom,smem-states = <&modem_smp2p_out 0>;
1054 qcom,smem-state-names = "stop";
1057 reset-names = "mss_restart";
1059 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1061 power-domains = <&rpmpd SDM660_VDDCX>,
1063 power-domain-names = "cx", "mx";
1065 memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>;
1069 glink-edge {
1072 qcom,remote-pid = <1>;
1078 compatible = "qcom,adreno-508.0", "qcom,adreno";
1081 reg-names = "kgsl_3d0_reg_memory";
1092 clock-names = "iface",
1099 power-domains = <&rpmpd SDM660_VDDMX>;
1102 nvmem-cells = <&gpu_speed_bin>;
1103 nvmem-cell-names = "speed_bin";
1106 interconnect-names = "gfx-mem";
1108 operating-points-v2 = <&gpu_sdm630_opp_table>;
1109 #cooling-cells = <2>;
1113 gpu_sdm630_opp_table: opp-table {
1114 compatible = "operating-points-v2";
1115 opp-775000000 {
1116 opp-hz = /bits/ 64 <775000000>;
1117 opp-level = <RPM_SMD_LEVEL_TURBO>;
1118 opp-peak-kBps = <5412000>;
1119 opp-supported-hw = <0xa2>;
1121 opp-647000000 {
1122 opp-hz = /bits/ 64 <647000000>;
1123 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1124 opp-peak-kBps = <4068000>;
1125 opp-supported-hw = <0xff>;
1127 opp-588000000 {
1128 opp-hz = /bits/ 64 <588000000>;
1129 opp-level = <RPM_SMD_LEVEL_NOM>;
1130 opp-peak-kBps = <3072000>;
1131 opp-supported-hw = <0xff>;
1133 opp-465000000 {
1134 opp-hz = /bits/ 64 <465000000>;
1135 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1136 opp-peak-kBps = <2724000>;
1137 opp-supported-hw = <0xff>;
1139 opp-370000000 {
1140 opp-hz = /bits/ 64 <370000000>;
1141 opp-level = <RPM_SMD_LEVEL_SVS>;
1142 opp-peak-kBps = <2188000>;
1143 opp-supported-hw = <0xff>;
1145 opp-240000000 {
1146 opp-hz = /bits/ 64 <240000000>;
1147 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1148 opp-peak-kBps = <1648000>;
1149 opp-supported-hw = <0xff>;
1151 opp-160000000 {
1152 opp-hz = /bits/ 64 <160000000>;
1153 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1154 opp-peak-kBps = <1200000>;
1155 opp-supported-hw = <0xff>;
1159 adreno_gpu_zap: zap-shader {
1160 memory-region = <&zap_shader_region>;
1165 compatible = "qcom,sdm630-smmu-v2",
1166 "qcom,adreno-smmu", "qcom,smmu-v2";
1176 power-domains = <&gpucc GPU_GX_GDSC>;
1180 clock-names = "iface",
1183 #global-interrupts = <2>;
1184 #iommu-cells = <1>;
1200 gpucc: clock-controller@5065000 {
1201 compatible = "qcom,gpucc-sdm630";
1202 #clock-cells = <1>;
1203 #reset-cells = <1>;
1204 #power-domain-cells = <1>;
1210 clock-names = "xo",
1216 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1218 #iommu-cells = <1>;
1220 #global-interrupts = <2>;
1245 compatible = "qcom,rpm-stats";
1250 compatible = "qcom,spmi-pmic-arb";
1256 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1257 interrupt-names = "periph_irq";
1261 #address-cells = <2>;
1262 #size-cells = <0>;
1263 interrupt-controller;
1264 #interrupt-cells = <4>;
1268 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1280 clock-names = "cfg_noc",
1286 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1288 assigned-clock-rates = <19200000>, <120000000>;
1294 interrupt-names = "pwr_event",
1299 power-domains = <&gcc USB_30_GDSC>;
1309 snps,parkmode-disable-ss-quirk;
1310 snps,dis-u1-entry-quirk;
1311 snps,dis-u2-entry-quirk;
1314 phy-names = "usb2-phy", "usb3-phy";
1315 snps,hird-threshold = /bits/ 8 <0>;
1320 compatible = "qcom,sdm660-qmp-usb3-phy";
1327 clock-names = "aux",
1331 clock-output-names = "usb3_phy_pipe_clk_src";
1332 #clock-cells = <0>;
1333 #phy-cells = <0>;
1337 reset-names = "phy",
1340 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
1346 compatible = "qcom,sdm660-qusb2-phy";
1348 #phy-cells = <0>;
1352 clock-names = "cfg_ahb", "ref";
1355 nvmem-cells = <&qusb2_hstx_trim>;
1360 compatible = "qcom,sdm660-qusb2-phy";
1362 #phy-cells = <0>;
1366 clock-names = "cfg_ahb", "ref";
1369 nvmem-cells = <&qusb2_hstx_trim>;
1374 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1376 reg-names = "hc";
1380 interrupt-names = "hc_irq", "pwr_irq";
1382 bus-width = <4>;
1387 clock-names = "iface", "core", "xo";
1393 interconnect-names = "sdhc-ddr","cpu-sdhc";
1394 operating-points-v2 = <&sdhc2_opp_table>;
1396 pinctrl-names = "default", "sleep";
1397 pinctrl-0 = <&sdc2_state_on>;
1398 pinctrl-1 = <&sdc2_state_off>;
1399 power-domains = <&rpmpd SDM660_VDDCX>;
1403 sdhc2_opp_table: opp-table {
1404 compatible = "operating-points-v2";
1406 opp-50000000 {
1407 opp-hz = /bits/ 64 <50000000>;
1408 required-opps = <&rpmpd_opp_low_svs>;
1409 opp-peak-kBps = <200000 140000>;
1410 opp-avg-kBps = <130718 133320>;
1412 opp-100000000 {
1413 opp-hz = /bits/ 64 <100000000>;
1414 required-opps = <&rpmpd_opp_svs>;
1415 opp-peak-kBps = <250000 160000>;
1416 opp-avg-kBps = <196078 150000>;
1418 opp-200000000 {
1419 opp-hz = /bits/ 64 <200000000>;
1420 required-opps = <&rpmpd_opp_nom>;
1421 opp-peak-kBps = <4096000 4096000>;
1422 opp-avg-kBps = <1338562 1338562>;
1428 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1432 reg-names = "hc", "cqhci", "ice";
1436 interrupt-names = "hc_irq", "pwr_irq";
1442 clock-names = "iface", "core", "xo", "ice";
1448 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1449 operating-points-v2 = <&sdhc1_opp_table>;
1450 pinctrl-names = "default", "sleep";
1451 pinctrl-0 = <&sdc1_state_on>;
1452 pinctrl-1 = <&sdc1_state_off>;
1453 power-domains = <&rpmpd SDM660_VDDCX>;
1455 bus-width = <8>;
1456 non-removable;
1460 sdhc1_opp_table: opp-table {
1461 compatible = "operating-points-v2";
1463 opp-50000000 {
1464 opp-hz = /bits/ 64 <50000000>;
1465 required-opps = <&rpmpd_opp_low_svs>;
1466 opp-peak-kBps = <200000 140000>;
1467 opp-avg-kBps = <130718 133320>;
1469 opp-100000000 {
1470 opp-hz = /bits/ 64 <100000000>;
1471 required-opps = <&rpmpd_opp_svs>;
1472 opp-peak-kBps = <250000 160000>;
1473 opp-avg-kBps = <196078 150000>;
1475 opp-384000000 {
1476 opp-hz = /bits/ 64 <384000000>;
1477 required-opps = <&rpmpd_opp_nom>;
1478 opp-peak-kBps = <4096000 4096000>;
1479 opp-avg-kBps = <1338562 1338562>;
1485 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1488 #address-cells = <1>;
1489 #size-cells = <1>;
1496 clock-names = "cfg_noc", "core",
1499 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1501 assigned-clock-rates = <19200000>, <60000000>;
1506 interrupt-names = "pwr_event",
1510 qcom,select-utmi-as-pipe-clk;
1520 snps,dis-u1-entry-quirk;
1521 snps,dis-u2-entry-quirk;
1523 /* This is the HS-only host */
1524 maximum-speed = "high-speed";
1526 phy-names = "usb2-phy";
1527 snps,hird-threshold = /bits/ 8 <0>;
1531 mmcc: clock-controller@c8c0000 {
1532 compatible = "qcom,mmcc-sdm630";
1534 #clock-cells = <1>;
1535 #reset-cells = <1>;
1536 #power-domain-cells = <1>;
1537 clock-names = "xo",
1559 mdss: display-subsystem@c900000 {
1563 reg-names = "mdss_phys", "vbif_phys";
1565 power-domains = <&mmcc MDSS_GDSC>;
1571 clock-names = "iface",
1578 interrupt-controller;
1579 #interrupt-cells = <1>;
1581 #address-cells = <1>;
1582 #size-cells = <1>;
1586 mdp: display-controller@c901000 {
1587 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1589 reg-names = "mdp_phys";
1591 interrupt-parent = <&mdss>;
1594 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1596 assigned-clock-rates = <300000000>,
1602 clock-names = "iface",
1610 interconnect-names = "mdp0-mem",
1611 "mdp1-mem",
1612 "rotator-mem";
1614 operating-points-v2 = <&mdp_opp_table>;
1615 power-domains = <&rpmpd SDM660_VDDCX>;
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1624 remote-endpoint = <&mdss_dsi0_in>;
1629 mdp_opp_table: opp-table {
1630 compatible = "operating-points-v2";
1632 opp-150000000 {
1633 opp-hz = /bits/ 64 <150000000>;
1634 opp-peak-kBps = <320000 320000 76800>;
1635 required-opps = <&rpmpd_opp_low_svs>;
1637 opp-275000000 {
1638 opp-hz = /bits/ 64 <275000000>;
1639 opp-peak-kBps = <6400000 6400000 160000>;
1640 required-opps = <&rpmpd_opp_svs>;
1642 opp-300000000 {
1643 opp-hz = /bits/ 64 <300000000>;
1644 opp-peak-kBps = <6400000 6400000 190000>;
1645 required-opps = <&rpmpd_opp_svs_plus>;
1647 opp-330000000 {
1648 opp-hz = /bits/ 64 <330000000>;
1649 opp-peak-kBps = <6400000 6400000 240000>;
1650 required-opps = <&rpmpd_opp_nom>;
1652 opp-412500000 {
1653 opp-hz = /bits/ 64 <412500000>;
1654 opp-peak-kBps = <6400000 6400000 320000>;
1655 required-opps = <&rpmpd_opp_turbo>;
1661 compatible = "qcom,sdm660-dsi-ctrl",
1662 "qcom,mdss-dsi-ctrl";
1664 reg-names = "dsi_ctrl";
1666 operating-points-v2 = <&dsi_opp_table>;
1667 power-domains = <&rpmpd SDM660_VDDCX>;
1669 interrupt-parent = <&mdss>;
1672 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1674 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1686 clock-names = "mdp_core",
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1707 remote-endpoint = <&mdp5_intf1_out>;
1720 compatible = "qcom,dsi-phy-14nm-660";
1724 reg-names = "dsi_phy",
1728 #clock-cells = <1>;
1729 #phy-cells = <0>;
1732 clock-names = "iface", "ref";
1737 blsp1_dma: dma-controller@c144000 {
1738 compatible = "qcom,bam-v1.7.0";
1742 clock-names = "bam_clk";
1743 #dma-cells = <1>;
1745 qcom,controlled-remotely;
1746 num-channels = <18>;
1747 qcom,num-ees = <4>;
1751 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1756 clock-names = "core", "iface";
1758 dma-names = "tx", "rx";
1759 pinctrl-names = "default", "sleep";
1760 pinctrl-0 = <&blsp1_uart1_default>;
1761 pinctrl-1 = <&blsp1_uart1_sleep>;
1766 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1771 clock-names = "core", "iface";
1773 dma-names = "tx", "rx";
1774 pinctrl-names = "default";
1775 pinctrl-0 = <&blsp1_uart2_default>;
1780 compatible = "qcom,i2c-qup-v2.2.1";
1786 clock-names = "core", "iface";
1787 clock-frequency = <400000>;
1789 dma-names = "tx", "rx";
1791 pinctrl-names = "default", "sleep";
1792 pinctrl-0 = <&i2c1_default>;
1793 pinctrl-1 = <&i2c1_sleep>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1800 compatible = "qcom,i2c-qup-v2.2.1";
1806 clock-names = "core", "iface";
1807 clock-frequency = <400000>;
1809 dma-names = "tx", "rx";
1811 pinctrl-names = "default", "sleep";
1812 pinctrl-0 = <&i2c2_default>;
1813 pinctrl-1 = <&i2c2_sleep>;
1814 #address-cells = <1>;
1815 #size-cells = <0>;
1820 compatible = "qcom,i2c-qup-v2.2.1";
1826 clock-names = "core", "iface";
1827 clock-frequency = <400000>;
1829 dma-names = "tx", "rx";
1831 pinctrl-names = "default", "sleep";
1832 pinctrl-0 = <&i2c3_default>;
1833 pinctrl-1 = <&i2c3_sleep>;
1834 #address-cells = <1>;
1835 #size-cells = <0>;
1840 compatible = "qcom,i2c-qup-v2.2.1";
1846 clock-names = "core", "iface";
1847 clock-frequency = <400000>;
1849 dma-names = "tx", "rx";
1851 pinctrl-names = "default", "sleep";
1852 pinctrl-0 = <&i2c4_default>;
1853 pinctrl-1 = <&i2c4_sleep>;
1854 #address-cells = <1>;
1855 #size-cells = <0>;
1859 blsp2_dma: dma-controller@c184000 {
1860 compatible = "qcom,bam-v1.7.0";
1864 clock-names = "bam_clk";
1865 #dma-cells = <1>;
1867 qcom,controlled-remotely;
1868 num-channels = <18>;
1869 qcom,num-ees = <4>;
1873 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1878 clock-names = "core", "iface";
1880 dma-names = "tx", "rx";
1881 pinctrl-names = "default", "sleep";
1882 pinctrl-0 = <&blsp2_uart1_default>;
1883 pinctrl-1 = <&blsp2_uart1_sleep>;
1888 compatible = "qcom,i2c-qup-v2.2.1";
1894 clock-names = "core", "iface";
1895 clock-frequency = <400000>;
1897 dma-names = "tx", "rx";
1899 pinctrl-names = "default", "sleep";
1900 pinctrl-0 = <&i2c5_default>;
1901 pinctrl-1 = <&i2c5_sleep>;
1902 #address-cells = <1>;
1903 #size-cells = <0>;
1908 compatible = "qcom,i2c-qup-v2.2.1";
1914 clock-names = "core", "iface";
1915 clock-frequency = <400000>;
1917 dma-names = "tx", "rx";
1919 pinctrl-names = "default", "sleep";
1920 pinctrl-0 = <&i2c6_default>;
1921 pinctrl-1 = <&i2c6_sleep>;
1922 #address-cells = <1>;
1923 #size-cells = <0>;
1928 compatible = "qcom,i2c-qup-v2.2.1";
1934 clock-names = "core", "iface";
1935 clock-frequency = <400000>;
1937 dma-names = "tx", "rx";
1939 pinctrl-names = "default", "sleep";
1940 pinctrl-0 = <&i2c7_default>;
1941 pinctrl-1 = <&i2c7_sleep>;
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1948 compatible = "qcom,i2c-qup-v2.2.1";
1954 clock-names = "core", "iface";
1955 clock-frequency = <400000>;
1957 dma-names = "tx", "rx";
1959 pinctrl-names = "default", "sleep";
1960 pinctrl-0 = <&i2c8_default>;
1961 pinctrl-1 = <&i2c8_sleep>;
1962 #address-cells = <1>;
1963 #size-cells = <0>;
1968 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1971 #address-cells = <1>;
1972 #size-cells = <1>;
1976 pil-reloc@94c {
1977 compatible = "qcom,pil-reloc-info";
1983 compatible = "qcom,sdm660-camss";
1998 reg-names = "csi_clk_mux",
2022 interrupt-names = "csid0",
2074 clock-names = "ahb",
2117 interconnect-names = "vfe-mem";
2122 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2133 compatible = "qcom,msm8996-cci";
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2139 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2141 assigned-clock-rates = <80800000>, <37500000>;
2146 clock-names = "camss_top_ahb",
2151 pinctrl-names = "default";
2152 pinctrl-0 = <&cci0_default &cci1_default>;
2153 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2156 cci_i2c0: i2c-bus@0 {
2158 clock-frequency = <400000>;
2159 #address-cells = <1>;
2160 #size-cells = <0>;
2163 cci_i2c1: i2c-bus@1 {
2165 clock-frequency = <400000>;
2166 #address-cells = <1>;
2167 #size-cells = <0>;
2171 venus: video-codec@cc00000 {
2172 compatible = "qcom,sdm660-venus";
2178 clock-names = "core", "iface", "bus", "bus_throttle";
2181 interconnect-names = "cpu-cfg", "video-mem";
2203 memory-region = <&venus_region>;
2204 power-domains = <&mmcc VENUS_GDSC>;
2207 video-decoder {
2208 compatible = "venus-decoder";
2210 clock-names = "vcodec0_core";
2211 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2214 video-encoder {
2215 compatible = "venus-encoder";
2217 clock-names = "vcodec0_core";
2218 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2223 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2229 clock-names = "iface-mm", "iface-smmu",
2230 "bus-smmu";
2231 #global-interrupts = <2>;
2232 #iommu-cells = <1>;
2267 compatible = "qcom,sdm660-adsp-pas";
2270 interrupts-extended =
2276 interrupt-names = "wdog", "fatal", "ready",
2277 "handover", "stop-ack";
2280 clock-names = "xo";
2282 memory-region = <&adsp_region>;
2283 power-domains = <&rpmpd SDM660_VDDCX>;
2284 power-domain-names = "cx";
2286 qcom,smem-states = <&adsp_smp2p_out 0>;
2287 qcom,smem-state-names = "stop";
2289 glink-edge {
2294 qcom,remote-pid = <2>;
2297 compatible = "qcom,apr-v2";
2298 qcom,glink-channels = "apr_audio_svc";
2300 #address-cells = <1>;
2301 #size-cells = <0>;
2312 compatible = "qcom,q6afe-dais";
2313 #address-cells = <1>;
2314 #size-cells = <0>;
2315 #sound-dai-cells = <1>;
2323 compatible = "qcom,q6asm-dais";
2324 #address-cells = <1>;
2325 #size-cells = <0>;
2326 #sound-dai-cells = <1>;
2335 compatible = "qcom,q6adm-routing";
2336 #sound-dai-cells = <0>;
2344 compatible = "qcom,sdm660-gnoc";
2346 #interconnect-cells = <1>;
2350 compatible = "qcom,sdm660-apcs-hmss-global",
2351 "qcom,msm8994-apcs-kpss-global";
2354 #mbox-cells = <1>;
2358 #address-cells = <1>;
2359 #size-cells = <1>;
2361 compatible = "arm,armv7-timer-mem";
2363 clock-frequency = <19200000>;
2366 frame-number = <0>;
2374 frame-number = <1>;
2381 frame-number = <2>;
2388 frame-number = <3>;
2395 frame-number = <4>;
2402 frame-number = <5>;
2409 frame-number = <6>;
2416 intc: interrupt-controller@17a00000 {
2417 compatible = "arm,gic-v3";
2420 #interrupt-cells = <3>;
2421 #address-cells = <1>;
2422 #size-cells = <1>;
2424 interrupt-controller;
2425 #redistributor-regions = <1>;
2426 redistributor-stride = <0x0 0x20000>;
2431 compatible = "qcom,wcn3990-wifi";
2433 reg-names = "membase";
2434 memory-region = <&wlan_msa_mem>;
2436 clock-names = "cxo_ref_clk_pin";
2452 qcom,snoc-host-cap-8bit-quirk;
2453 qcom,no-msa-ready-indicator;
2461 thermal-zones {
2462 aoss-thermal {
2463 polling-delay-passive = <250>;
2465 thermal-sensors = <&tsens 0>;
2468 aoss_alert0: trip-point0 {
2476 cpuss0-thermal {
2477 polling-delay-passive = <250>;
2479 thermal-sensors = <&tsens 1>;
2482 cpuss0_alert0: trip-point0 {
2490 cpuss1-thermal {
2491 polling-delay-passive = <250>;
2493 thermal-sensors = <&tsens 2>;
2496 cpuss1_alert0: trip-point0 {
2504 cpu0-thermal {
2505 polling-delay-passive = <250>;
2507 thermal-sensors = <&tsens 3>;
2510 cpu0_alert0: trip-point0 {
2516 cpu0_crit: cpu-crit {
2524 cpu1-thermal {
2525 polling-delay-passive = <250>;
2527 thermal-sensors = <&tsens 4>;
2530 cpu1_alert0: trip-point0 {
2536 cpu1_crit: cpu-crit {
2544 cpu2-thermal {
2545 polling-delay-passive = <250>;
2547 thermal-sensors = <&tsens 5>;
2550 cpu2_alert0: trip-point0 {
2556 cpu2_crit: cpu-crit {
2564 cpu3-thermal {
2565 polling-delay-passive = <250>;
2567 thermal-sensors = <&tsens 6>;
2570 cpu3_alert0: trip-point0 {
2576 cpu3_crit: cpu-crit {
2590 pwr-cluster-thermal {
2591 polling-delay-passive = <250>;
2593 thermal-sensors = <&tsens 7>;
2596 pwr_cluster_alert0: trip-point0 {
2602 pwr_cluster_crit: cpu-crit {
2610 gpu-thermal {
2611 polling-delay-passive = <250>;
2613 thermal-sensors = <&tsens 8>;
2615 cooling-maps {
2618 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2623 gpu_alert0: trip-point0 {
2629 trip-point1 {
2635 trip-point2 {
2645 compatible = "arm,armv8-timer";