Lines Matching +full:q6afe +full:- +full:clocks
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/soc/qcom,apr.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
32 clocks {
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <19200000>;
37 clock-output-names = "xo_board";
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32764>;
44 clock-output-names = "sleep_clk";
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 cpu-idle-states = <&PERF_CPU_SLEEP_0
62 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>;
64 next-level-cache = <&L2_1>;
65 L2_1: l2-cache {
67 cache-level = <2>;
68 cache-unified;
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 cpu-idle-states = <&PERF_CPU_SLEEP_0
82 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>;
84 next-level-cache = <&L2_1>;
89 compatible = "arm,cortex-a53";
91 enable-method = "psci";
92 cpu-idle-states = <&PERF_CPU_SLEEP_0
97 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>;
99 next-level-cache = <&L2_1>;
104 compatible = "arm,cortex-a53";
106 enable-method = "psci";
107 cpu-idle-states = <&PERF_CPU_SLEEP_0
112 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>;
114 next-level-cache = <&L2_1>;
119 compatible = "arm,cortex-a53";
121 enable-method = "psci";
122 cpu-idle-states = <&PWR_CPU_SLEEP_0
127 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>;
129 next-level-cache = <&L2_0>;
130 L2_0: l2-cache {
132 cache-level = <2>;
133 cache-unified;
139 compatible = "arm,cortex-a53";
141 enable-method = "psci";
142 cpu-idle-states = <&PWR_CPU_SLEEP_0
147 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>;
149 next-level-cache = <&L2_0>;
154 compatible = "arm,cortex-a53";
156 enable-method = "psci";
157 cpu-idle-states = <&PWR_CPU_SLEEP_0
162 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>;
164 next-level-cache = <&L2_0>;
169 compatible = "arm,cortex-a53";
171 enable-method = "psci";
172 cpu-idle-states = <&PWR_CPU_SLEEP_0
177 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>;
179 next-level-cache = <&L2_0>;
182 cpu-map {
220 idle-states {
221 entry-method = "psci";
223 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 compatible = "arm,idle-state";
225 idle-state-name = "pwr-retention";
226 arm,psci-suspend-param = <0x40000002>;
227 entry-latency-us = <338>;
228 exit-latency-us = <423>;
229 min-residency-us = <200>;
232 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 compatible = "arm,idle-state";
234 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspend-param = <0x40000003>;
236 entry-latency-us = <515>;
237 exit-latency-us = <1821>;
238 min-residency-us = <1000>;
239 local-timer-stop;
242 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 compatible = "arm,idle-state";
244 idle-state-name = "perf-retention";
245 arm,psci-suspend-param = <0x40000002>;
246 entry-latency-us = <154>;
247 exit-latency-us = <87>;
248 min-residency-us = <200>;
251 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
252 compatible = "arm,idle-state";
253 idle-state-name = "perf-power-collapse";
254 arm,psci-suspend-param = <0x40000003>;
255 entry-latency-us = <262>;
256 exit-latency-us = <301>;
257 min-residency-us = <1000>;
258 local-timer-stop;
261 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 compatible = "arm,idle-state";
263 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency-us = <284>;
266 exit-latency-us = <384>;
267 min-residency-us = <9987>;
268 local-timer-stop;
271 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 compatible = "arm,idle-state";
273 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency-us = <338>;
276 exit-latency-us = <423>;
277 min-residency-us = <9987>;
278 local-timer-stop;
281 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 compatible = "arm,idle-state";
283 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency-us = <515>;
286 exit-latency-us = <1821>;
287 min-residency-us = <9987>;
288 local-timer-stop;
291 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency-us = <272>;
296 exit-latency-us = <329>;
297 min-residency-us = <9987>;
298 local-timer-stop;
301 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
302 compatible = "arm,idle-state";
303 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency-us = <332>;
306 exit-latency-us = <368>;
307 min-residency-us = <9987>;
308 local-timer-stop;
311 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
312 compatible = "arm,idle-state";
313 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency-us = <545>;
316 exit-latency-us = <1609>;
317 min-residency-us = <9987>;
318 local-timer-stop;
325 compatible = "qcom,scm-msm8998", "qcom,scm";
335 dsi_opp_table: opp-table-dsi {
336 compatible = "operating-points-v2";
338 opp-131250000 {
339 opp-hz = /bits/ 64 <131250000>;
340 required-opps = <&rpmpd_opp_svs>;
343 opp-210000000 {
344 opp-hz = /bits/ 64 <210000000>;
345 required-opps = <&rpmpd_opp_svs_plus>;
348 opp-262500000 {
349 opp-hz = /bits/ 64 <262500000>;
350 required-opps = <&rpmpd_opp_nom>;
355 compatible = "arm,armv8-pmuv3";
360 compatible = "arm,psci-1.0";
365 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
367 glink-edge {
368 compatible = "qcom,glink-rpm";
371 qcom,rpm-msg-ram = <&rpm_msg_ram>;
374 rpm_requests: rpm-requests {
375 compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm";
376 qcom,glink-channels = "rpm_requests";
378 rpmcc: clock-controller {
379 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
380 #clock-cells = <1>;
383 rpmpd: power-controller {
384 compatible = "qcom,sdm660-rpmpd";
385 #power-domain-cells = <1>;
386 operating-points-v2 = <&rpmpd_opp_table>;
388 rpmpd_opp_table: opp-table {
389 compatible = "operating-points-v2";
392 opp-level = <RPM_SMD_LEVEL_RETENTION>;
396 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
400 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
404 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
408 opp-level = <RPM_SMD_LEVEL_SVS>;
412 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
416 opp-level = <RPM_SMD_LEVEL_NOM>;
420 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
424 opp-level = <RPM_SMD_LEVEL_TURBO>;
432 reserved-memory {
433 #address-cells = <2>;
434 #size-cells = <2>;
437 wlan_msa_guard: wlan-msa-guard@85600000 {
439 no-map;
442 wlan_msa_mem: wlan-msa-mem@85700000 {
444 no-map;
447 qhee_code: qhee-code@85800000 {
449 no-map;
453 compatible = "qcom,rmtfs-mem";
455 no-map;
457 qcom,client-id = <1>;
461 smem_region: smem-mem@86000000 {
463 no-map;
468 no-map;
473 no-map;
478 no-map;
483 no-map;
488 no-map;
493 no-map;
496 adsp_mem: adsp-region@f6000000 {
498 no-map;
501 qseecom_mem: qseecom-region@f6800000 {
503 no-map;
507 compatible = "shared-dma-pool";
509 no-map;
515 memory-region = <&smem_region>;
519 smp2p-adsp {
524 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>;
527 adsp_smp2p_out: master-kernel {
528 qcom,entry-name = "master-kernel";
529 #qcom,smem-state-cells = <1>;
532 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "slave-kernel";
534 interrupt-controller;
535 #interrupt-cells = <2>;
539 smp2p-mpss {
544 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>;
547 modem_smp2p_out: master-kernel {
548 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells = <1>;
552 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "slave-kernel";
554 interrupt-controller;
555 #interrupt-cells = <2>;
560 #address-cells = <1>;
561 #size-cells = <1>;
563 compatible = "simple-bus";
565 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>;
568 #reset-cells = <1>;
569 #power-domain-cells = <1>;
572 clock-names = "xo", "sleep_clk";
573 clocks = <&xo_board>,
578 compatible = "qcom,rpm-msg-ram";
583 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
585 #address-cells = <1>;
586 #size-cells = <1>;
588 qusb2_hstx_trim: hstx-trim@240 {
593 gpu_speed_bin: gpu-speed-bin@41a0 {
600 compatible = "qcom,prng-ee";
602 clocks = <&gcc GCC_PRNG_AHB_CLK>;
603 clock-names = "core";
607 compatible = "qcom,sdm660-bimc";
609 #interconnect-cells = <1>;
618 compatible = "qcom,sdm660-cnoc";
620 #interconnect-cells = <1>;
624 compatible = "qcom,sdm660-snoc";
626 #interconnect-cells = <1>;
630 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
632 #global-interrupts = <2>;
633 #iommu-cells = <1>;
673 compatible = "qcom,sdm660-a2noc";
675 #interconnect-cells = <1>;
676 clock-names = "ipa",
681 clocks = <&rpmcc RPM_SMD_IPA_CLK>,
689 compatible = "qcom,sdm660-mnoc";
691 #interconnect-cells = <1>;
692 clock-names = "iface";
693 clocks = <&mmcc AHB_CLK_SRC>;
696 tsens: thermal-sensor@10ae000 {
697 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
703 interrupt-names = "uplow", "critical";
704 #thermal-sensor-cells = <1>;
708 compatible = "qcom,tcsr-mutex";
710 #hwlock-cells = <1>;
714 compatible = "qcom,sdm630-tcsr", "syscon";
719 compatible = "qcom,sdm630-pinctrl";
723 reg-names = "south", "center", "north";
725 gpio-controller;
726 gpio-ranges = <&tlmm 0 0 114>;
727 #gpio-cells = <2>;
728 interrupt-controller;
729 #interrupt-cells = <2>;
731 blsp1_uart1_default: blsp1-uart1-default-state {
734 drive-strength = <2>;
735 bias-disable;
738 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
741 drive-strength = <2>;
742 bias-disable;
745 blsp1_uart2_default: blsp1-uart2-default-state {
748 drive-strength = <2>;
749 bias-disable;
752 blsp2_uart1_default: blsp2-uart1-active-state {
753 tx-rts-pins {
756 drive-strength = <2>;
757 bias-disable;
760 rx-pins {
767 drive-strength = <2>;
768 bias-pull-up;
771 cts-pins {
775 drive-strength = <2>;
776 bias-pull-down;
780 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
781 tx-pins {
784 drive-strength = <2>;
785 bias-pull-up;
788 rx-cts-rts-pins {
791 drive-strength = <2>;
792 bias-disable;
796 i2c1_default: i2c1-default-state {
799 drive-strength = <2>;
800 bias-disable;
803 i2c1_sleep: i2c1-sleep-state {
806 drive-strength = <2>;
807 bias-pull-up;
810 i2c2_default: i2c2-default-state {
813 drive-strength = <2>;
814 bias-disable;
817 i2c2_sleep: i2c2-sleep-state {
820 drive-strength = <2>;
821 bias-pull-up;
824 i2c3_default: i2c3-default-state {
827 drive-strength = <2>;
828 bias-disable;
831 i2c3_sleep: i2c3-sleep-state {
834 drive-strength = <2>;
835 bias-pull-up;
838 i2c4_default: i2c4-default-state {
841 drive-strength = <2>;
842 bias-disable;
845 i2c4_sleep: i2c4-sleep-state {
848 drive-strength = <2>;
849 bias-pull-up;
852 i2c5_default: i2c5-default-state {
855 drive-strength = <2>;
856 bias-disable;
859 i2c5_sleep: i2c5-sleep-state {
862 drive-strength = <2>;
863 bias-pull-up;
866 i2c6_default: i2c6-default-state {
869 drive-strength = <2>;
870 bias-disable;
873 i2c6_sleep: i2c6-sleep-state {
876 drive-strength = <2>;
877 bias-pull-up;
880 i2c7_default: i2c7-default-state {
883 drive-strength = <2>;
884 bias-disable;
887 i2c7_sleep: i2c7-sleep-state {
890 drive-strength = <2>;
891 bias-pull-up;
894 i2c8_default: i2c8-default-state {
897 drive-strength = <2>;
898 bias-disable;
901 i2c8_sleep: i2c8-sleep-state {
904 drive-strength = <2>;
905 bias-pull-up;
908 cci0_default: cci0-default-state {
911 bias-pull-up;
912 drive-strength = <2>;
915 cci1_default: cci1-default-state {
918 bias-pull-up;
919 drive-strength = <2>;
922 sdc1_state_on: sdc1-on-state {
923 clk-pins {
925 bias-disable;
926 drive-strength = <16>;
929 cmd-pins {
931 bias-pull-up;
932 drive-strength = <10>;
935 data-pins {
937 bias-pull-up;
938 drive-strength = <10>;
941 rclk-pins {
943 bias-pull-down;
947 sdc1_state_off: sdc1-off-state {
948 clk-pins {
950 bias-disable;
951 drive-strength = <2>;
954 cmd-pins {
956 bias-pull-up;
957 drive-strength = <2>;
960 data-pins {
962 bias-pull-up;
963 drive-strength = <2>;
966 rclk-pins {
968 bias-pull-down;
972 sdc2_state_on: sdc2-on-state {
973 clk-pins {
975 bias-disable;
976 drive-strength = <16>;
979 cmd-pins {
981 bias-pull-up;
982 drive-strength = <10>;
985 data-pins {
987 bias-pull-up;
988 drive-strength = <10>;
992 sdc2_state_off: sdc2-off-state {
993 clk-pins {
995 bias-disable;
996 drive-strength = <2>;
999 cmd-pins {
1001 bias-pull-up;
1002 drive-strength = <2>;
1005 data-pins {
1007 bias-pull-up;
1008 drive-strength = <2>;
1014 compatible = "qcom,sdm660-mss-pil";
1016 reg-names = "qdsp6", "rmb";
1018 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1024 interrupt-names = "wdog",
1028 "stop-ack",
1029 "shutdown-ack";
1031 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1039 clock-names = "iface",
1048 qcom,smem-states = <&modem_smp2p_out 0>;
1049 qcom,smem-state-names = "stop";
1052 reset-names = "mss_restart";
1054 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1056 power-domains = <&rpmpd SDM660_VDDCX>,
1058 power-domain-names = "cx", "mx";
1060 memory-region = <&mba_region>, <&mpss_region>;
1064 glink-edge {
1067 qcom,remote-pid = <1>;
1073 compatible = "qcom,adreno-508.0", "qcom,adreno";
1076 reg-names = "kgsl_3d0_reg_memory";
1080 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1087 clock-names = "iface",
1094 power-domains = <&rpmpd SDM660_VDDMX>;
1097 nvmem-cells = <&gpu_speed_bin>;
1098 nvmem-cell-names = "speed_bin";
1101 interconnect-names = "gfx-mem";
1103 operating-points-v2 = <&gpu_sdm630_opp_table>;
1104 #cooling-cells = <2>;
1108 gpu_sdm630_opp_table: opp-table {
1109 compatible = "operating-points-v2";
1110 opp-775000000 {
1111 opp-hz = /bits/ 64 <775000000>;
1112 opp-level = <RPM_SMD_LEVEL_TURBO>;
1113 opp-peak-kBps = <5412000>;
1114 opp-supported-hw = <0xa2>;
1116 opp-647000000 {
1117 opp-hz = /bits/ 64 <647000000>;
1118 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1119 opp-peak-kBps = <4068000>;
1120 opp-supported-hw = <0xff>;
1122 opp-588000000 {
1123 opp-hz = /bits/ 64 <588000000>;
1124 opp-level = <RPM_SMD_LEVEL_NOM>;
1125 opp-peak-kBps = <3072000>;
1126 opp-supported-hw = <0xff>;
1128 opp-465000000 {
1129 opp-hz = /bits/ 64 <465000000>;
1130 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1131 opp-peak-kBps = <2724000>;
1132 opp-supported-hw = <0xff>;
1134 opp-370000000 {
1135 opp-hz = /bits/ 64 <370000000>;
1136 opp-level = <RPM_SMD_LEVEL_SVS>;
1137 opp-peak-kBps = <2188000>;
1138 opp-supported-hw = <0xff>;
1140 opp-240000000 {
1141 opp-hz = /bits/ 64 <240000000>;
1142 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1143 opp-peak-kBps = <1648000>;
1144 opp-supported-hw = <0xff>;
1146 opp-160000000 {
1147 opp-hz = /bits/ 64 <160000000>;
1148 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1149 opp-peak-kBps = <1200000>;
1150 opp-supported-hw = <0xff>;
1156 compatible = "qcom,sdm630-smmu-v2",
1157 "qcom,adreno-smmu", "qcom,smmu-v2";
1167 power-domains = <&gpucc GPU_GX_GDSC>;
1168 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1171 clock-names = "iface",
1174 #global-interrupts = <2>;
1175 #iommu-cells = <1>;
1193 gpucc: clock-controller@5065000 {
1194 compatible = "qcom,gpucc-sdm630";
1195 #clock-cells = <1>;
1196 #reset-cells = <1>;
1197 #power-domain-cells = <1>;
1200 clocks = <&xo_board>,
1203 clock-names = "xo",
1210 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1212 #iommu-cells = <1>;
1214 #global-interrupts = <2>;
1241 compatible = "qcom,rpm-stats";
1246 compatible = "qcom,spmi-pmic-arb";
1252 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1253 interrupt-names = "periph_irq";
1257 #address-cells = <2>;
1258 #size-cells = <0>;
1259 interrupt-controller;
1260 #interrupt-cells = <4>;
1264 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1267 #address-cells = <1>;
1268 #size-cells = <1>;
1271 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1276 clock-names = "cfg_noc",
1282 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1284 assigned-clock-rates = <19200000>, <120000000>;
1290 interrupt-names = "pwr_event",
1295 power-domains = <&gcc USB_30_GDSC>;
1305 snps,parkmode-disable-ss-quirk;
1308 phy-names = "usb2-phy", "usb3-phy";
1309 snps,hird-threshold = /bits/ 8 <0>;
1314 compatible = "qcom,sdm660-qmp-usb3-phy";
1317 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1321 clock-names = "aux",
1325 clock-output-names = "usb3_phy_pipe_clk_src";
1326 #clock-cells = <0>;
1327 #phy-cells = <0>;
1331 reset-names = "phy",
1334 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
1340 compatible = "qcom,sdm660-qusb2-phy";
1342 #phy-cells = <0>;
1344 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1346 clock-names = "cfg_ahb", "ref";
1349 nvmem-cells = <&qusb2_hstx_trim>;
1354 compatible = "qcom,sdm660-qusb2-phy";
1356 #phy-cells = <0>;
1358 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1360 clock-names = "cfg_ahb", "ref";
1363 nvmem-cells = <&qusb2_hstx_trim>;
1368 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1370 reg-names = "hc";
1374 interrupt-names = "hc_irq", "pwr_irq";
1376 bus-width = <4>;
1378 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1381 clock-names = "iface", "core", "xo";
1386 interconnect-names = "sdhc-ddr","cpu-sdhc";
1387 operating-points-v2 = <&sdhc2_opp_table>;
1389 pinctrl-names = "default", "sleep";
1390 pinctrl-0 = <&sdc2_state_on>;
1391 pinctrl-1 = <&sdc2_state_off>;
1392 power-domains = <&rpmpd SDM660_VDDCX>;
1396 sdhc2_opp_table: opp-table {
1397 compatible = "operating-points-v2";
1399 opp-50000000 {
1400 opp-hz = /bits/ 64 <50000000>;
1401 required-opps = <&rpmpd_opp_low_svs>;
1402 opp-peak-kBps = <200000 140000>;
1403 opp-avg-kBps = <130718 133320>;
1405 opp-100000000 {
1406 opp-hz = /bits/ 64 <100000000>;
1407 required-opps = <&rpmpd_opp_svs>;
1408 opp-peak-kBps = <250000 160000>;
1409 opp-avg-kBps = <196078 150000>;
1411 opp-200000000 {
1412 opp-hz = /bits/ 64 <200000000>;
1413 required-opps = <&rpmpd_opp_nom>;
1414 opp-peak-kBps = <4096000 4096000>;
1415 opp-avg-kBps = <1338562 1338562>;
1421 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1425 reg-names = "hc", "cqhci", "ice";
1429 interrupt-names = "hc_irq", "pwr_irq";
1431 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1435 clock-names = "iface", "core", "xo", "ice";
1439 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1440 operating-points-v2 = <&sdhc1_opp_table>;
1441 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&sdc1_state_on>;
1443 pinctrl-1 = <&sdc1_state_off>;
1444 power-domains = <&rpmpd SDM660_VDDCX>;
1446 bus-width = <8>;
1447 non-removable;
1451 sdhc1_opp_table: opp-table {
1452 compatible = "operating-points-v2";
1454 opp-50000000 {
1455 opp-hz = /bits/ 64 <50000000>;
1456 required-opps = <&rpmpd_opp_low_svs>;
1457 opp-peak-kBps = <200000 140000>;
1458 opp-avg-kBps = <130718 133320>;
1460 opp-100000000 {
1461 opp-hz = /bits/ 64 <100000000>;
1462 required-opps = <&rpmpd_opp_svs>;
1463 opp-peak-kBps = <250000 160000>;
1464 opp-avg-kBps = <196078 150000>;
1466 opp-384000000 {
1467 opp-hz = /bits/ 64 <384000000>;
1468 required-opps = <&rpmpd_opp_nom>;
1469 opp-peak-kBps = <4096000 4096000>;
1470 opp-avg-kBps = <1338562 1338562>;
1476 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1479 #address-cells = <1>;
1480 #size-cells = <1>;
1483 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1487 clock-names = "cfg_noc", "core",
1490 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1492 assigned-clock-rates = <19200000>, <60000000>;
1497 interrupt-names = "pwr_event",
1501 qcom,select-utmi-as-pipe-clk;
1512 /* This is the HS-only host */
1513 maximum-speed = "high-speed";
1515 phy-names = "usb2-phy";
1516 snps,hird-threshold = /bits/ 8 <0>;
1520 mmcc: clock-controller@c8c0000 {
1521 compatible = "qcom,mmcc-sdm630";
1523 #clock-cells = <1>;
1524 #reset-cells = <1>;
1525 #power-domain-cells = <1>;
1526 clock-names = "xo",
1536 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1548 mdss: display-subsystem@c900000 {
1552 reg-names = "mdss_phys", "vbif_phys";
1554 power-domains = <&mmcc MDSS_GDSC>;
1556 clocks = <&mmcc MDSS_AHB_CLK>,
1560 clock-names = "iface",
1567 interrupt-controller;
1568 #interrupt-cells = <1>;
1570 #address-cells = <1>;
1571 #size-cells = <1>;
1575 mdp: display-controller@c901000 {
1576 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1578 reg-names = "mdp_phys";
1580 interrupt-parent = <&mdss>;
1583 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1585 assigned-clock-rates = <300000000>,
1587 clocks = <&mmcc MDSS_AHB_CLK>,
1591 clock-names = "iface",
1599 interconnect-names = "mdp0-mem",
1600 "mdp1-mem",
1601 "rotator-mem";
1603 operating-points-v2 = <&mdp_opp_table>;
1604 power-domains = <&rpmpd SDM660_VDDCX>;
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1613 remote-endpoint = <&mdss_dsi0_in>;
1618 mdp_opp_table: opp-table {
1619 compatible = "operating-points-v2";
1621 opp-150000000 {
1622 opp-hz = /bits/ 64 <150000000>;
1623 opp-peak-kBps = <320000 320000 76800>;
1624 required-opps = <&rpmpd_opp_low_svs>;
1626 opp-275000000 {
1627 opp-hz = /bits/ 64 <275000000>;
1628 opp-peak-kBps = <6400000 6400000 160000>;
1629 required-opps = <&rpmpd_opp_svs>;
1631 opp-300000000 {
1632 opp-hz = /bits/ 64 <300000000>;
1633 opp-peak-kBps = <6400000 6400000 190000>;
1634 required-opps = <&rpmpd_opp_svs_plus>;
1636 opp-330000000 {
1637 opp-hz = /bits/ 64 <330000000>;
1638 opp-peak-kBps = <6400000 6400000 240000>;
1639 required-opps = <&rpmpd_opp_nom>;
1641 opp-412500000 {
1642 opp-hz = /bits/ 64 <412500000>;
1643 opp-peak-kBps = <6400000 6400000 320000>;
1644 required-opps = <&rpmpd_opp_turbo>;
1650 compatible = "qcom,sdm660-dsi-ctrl",
1651 "qcom,mdss-dsi-ctrl";
1653 reg-names = "dsi_ctrl";
1655 operating-points-v2 = <&dsi_opp_table>;
1656 power-domains = <&rpmpd SDM660_VDDCX>;
1658 interrupt-parent = <&mdss>;
1661 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1663 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1666 clocks = <&mmcc MDSS_MDP_CLK>,
1675 clock-names = "mdp_core",
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1696 remote-endpoint = <&mdp5_intf1_out>;
1709 compatible = "qcom,dsi-phy-14nm-660";
1713 reg-names = "dsi_phy",
1717 #clock-cells = <1>;
1718 #phy-cells = <0>;
1720 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1721 clock-names = "iface", "ref";
1726 blsp1_dma: dma-controller@c144000 {
1727 compatible = "qcom,bam-v1.7.0";
1730 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1731 clock-names = "bam_clk";
1732 #dma-cells = <1>;
1734 qcom,controlled-remotely;
1735 num-channels = <18>;
1736 qcom,num-ees = <4>;
1740 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1743 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1745 clock-names = "core", "iface";
1747 dma-names = "tx", "rx";
1748 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&blsp1_uart1_default>;
1750 pinctrl-1 = <&blsp1_uart1_sleep>;
1755 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1758 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1760 clock-names = "core", "iface";
1762 dma-names = "tx", "rx";
1763 pinctrl-names = "default";
1764 pinctrl-0 = <&blsp1_uart2_default>;
1769 compatible = "qcom,i2c-qup-v2.2.1";
1773 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1775 clock-names = "core", "iface";
1776 clock-frequency = <400000>;
1778 dma-names = "tx", "rx";
1780 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c1_default>;
1782 pinctrl-1 = <&i2c1_sleep>;
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1789 compatible = "qcom,i2c-qup-v2.2.1";
1793 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1795 clock-names = "core", "iface";
1796 clock-frequency = <400000>;
1798 dma-names = "tx", "rx";
1800 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c2_default>;
1802 pinctrl-1 = <&i2c2_sleep>;
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1809 compatible = "qcom,i2c-qup-v2.2.1";
1813 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1815 clock-names = "core", "iface";
1816 clock-frequency = <400000>;
1818 dma-names = "tx", "rx";
1820 pinctrl-names = "default", "sleep";
1821 pinctrl-0 = <&i2c3_default>;
1822 pinctrl-1 = <&i2c3_sleep>;
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1829 compatible = "qcom,i2c-qup-v2.2.1";
1833 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1835 clock-names = "core", "iface";
1836 clock-frequency = <400000>;
1838 dma-names = "tx", "rx";
1840 pinctrl-names = "default", "sleep";
1841 pinctrl-0 = <&i2c4_default>;
1842 pinctrl-1 = <&i2c4_sleep>;
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1848 blsp2_dma: dma-controller@c184000 {
1849 compatible = "qcom,bam-v1.7.0";
1852 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1853 clock-names = "bam_clk";
1854 #dma-cells = <1>;
1856 qcom,controlled-remotely;
1857 num-channels = <18>;
1858 qcom,num-ees = <4>;
1862 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1865 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1867 clock-names = "core", "iface";
1869 dma-names = "tx", "rx";
1870 pinctrl-names = "default", "sleep";
1871 pinctrl-0 = <&blsp2_uart1_default>;
1872 pinctrl-1 = <&blsp2_uart1_sleep>;
1877 compatible = "qcom,i2c-qup-v2.2.1";
1881 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1883 clock-names = "core", "iface";
1884 clock-frequency = <400000>;
1886 dma-names = "tx", "rx";
1888 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&i2c5_default>;
1890 pinctrl-1 = <&i2c5_sleep>;
1891 #address-cells = <1>;
1892 #size-cells = <0>;
1897 compatible = "qcom,i2c-qup-v2.2.1";
1901 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1903 clock-names = "core", "iface";
1904 clock-frequency = <400000>;
1906 dma-names = "tx", "rx";
1908 pinctrl-names = "default", "sleep";
1909 pinctrl-0 = <&i2c6_default>;
1910 pinctrl-1 = <&i2c6_sleep>;
1911 #address-cells = <1>;
1912 #size-cells = <0>;
1917 compatible = "qcom,i2c-qup-v2.2.1";
1921 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1923 clock-names = "core", "iface";
1924 clock-frequency = <400000>;
1926 dma-names = "tx", "rx";
1928 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&i2c7_default>;
1930 pinctrl-1 = <&i2c7_sleep>;
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1937 compatible = "qcom,i2c-qup-v2.2.1";
1941 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1943 clock-names = "core", "iface";
1944 clock-frequency = <400000>;
1946 dma-names = "tx", "rx";
1948 pinctrl-names = "default", "sleep";
1949 pinctrl-0 = <&i2c8_default>;
1950 pinctrl-1 = <&i2c8_sleep>;
1951 #address-cells = <1>;
1952 #size-cells = <0>;
1957 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1960 #address-cells = <1>;
1961 #size-cells = <1>;
1965 pil-reloc@94c {
1966 compatible = "qcom,pil-reloc-info";
1972 compatible = "qcom,sdm660-camss";
1987 reg-names = "csi_clk_mux",
2011 interrupt-names = "csid0",
2021 clocks = <&mmcc CAMSS_AHB_CLK>,
2063 clock-names = "ahb",
2106 interconnect-names = "vfe-mem";
2111 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2116 #address-cells = <1>;
2117 #size-cells = <0>;
2122 compatible = "qcom,msm8996-cci";
2123 #address-cells = <1>;
2124 #size-cells = <0>;
2128 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2130 assigned-clock-rates = <80800000>, <37500000>;
2131 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2135 clock-names = "camss_top_ahb",
2140 pinctrl-names = "default";
2141 pinctrl-0 = <&cci0_default &cci1_default>;
2142 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2145 cci_i2c0: i2c-bus@0 {
2147 clock-frequency = <400000>;
2148 #address-cells = <1>;
2149 #size-cells = <0>;
2152 cci_i2c1: i2c-bus@1 {
2154 clock-frequency = <400000>;
2155 #address-cells = <1>;
2156 #size-cells = <0>;
2160 venus: video-codec@cc00000 {
2161 compatible = "qcom,sdm660-venus";
2163 clocks = <&mmcc VIDEO_CORE_CLK>,
2167 clock-names = "core", "iface", "bus", "bus_throttle";
2170 interconnect-names = "cpu-cfg", "video-mem";
2192 memory-region = <&venus_region>;
2193 power-domains = <&mmcc VENUS_GDSC>;
2196 video-decoder {
2197 compatible = "venus-decoder";
2198 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2199 clock-names = "vcodec0_core";
2200 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2203 video-encoder {
2204 compatible = "venus-encoder";
2205 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2206 clock-names = "vcodec0_core";
2207 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2212 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2215 clocks = <&mmcc MNOC_AHB_CLK>,
2218 clock-names = "iface-mm", "iface-smmu",
2219 "bus-smmu";
2220 #global-interrupts = <2>;
2221 #iommu-cells = <1>;
2256 compatible = "qcom,sdm660-adsp-pas";
2259 interrupts-extended =
2265 interrupt-names = "wdog", "fatal", "ready",
2266 "handover", "stop-ack";
2268 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2269 clock-names = "xo";
2271 memory-region = <&adsp_region>;
2272 power-domains = <&rpmpd SDM660_VDDCX>;
2273 power-domain-names = "cx";
2275 qcom,smem-states = <&adsp_smp2p_out 0>;
2276 qcom,smem-state-names = "stop";
2278 glink-edge {
2283 qcom,remote-pid = <2>;
2286 compatible = "qcom,apr-v2";
2287 qcom,glink-channels = "apr_audio_svc";
2289 #address-cells = <1>;
2290 #size-cells = <0>;
2297 q6afe: service@4 { label
2298 compatible = "qcom,q6afe";
2301 compatible = "qcom,q6afe-dais";
2302 #address-cells = <1>;
2303 #size-cells = <0>;
2304 #sound-dai-cells = <1>;
2312 compatible = "qcom,q6asm-dais";
2313 #address-cells = <1>;
2314 #size-cells = <0>;
2315 #sound-dai-cells = <1>;
2324 compatible = "qcom,q6adm-routing";
2325 #sound-dai-cells = <0>;
2333 compatible = "qcom,sdm660-gnoc";
2335 #interconnect-cells = <1>;
2339 compatible = "qcom,sdm660-apcs-hmss-global",
2340 "qcom,msm8994-apcs-kpss-global";
2343 #mbox-cells = <1>;
2347 #address-cells = <1>;
2348 #size-cells = <1>;
2350 compatible = "arm,armv7-timer-mem";
2352 clock-frequency = <19200000>;
2355 frame-number = <0>;
2363 frame-number = <1>;
2370 frame-number = <2>;
2377 frame-number = <3>;
2384 frame-number = <4>;
2391 frame-number = <5>;
2398 frame-number = <6>;
2405 intc: interrupt-controller@17a00000 {
2406 compatible = "arm,gic-v3";
2409 #interrupt-cells = <3>;
2410 #address-cells = <1>;
2411 #size-cells = <1>;
2413 interrupt-controller;
2414 #redistributor-regions = <1>;
2415 redistributor-stride = <0x0 0x20000>;
2423 thermal-zones {
2424 aoss-thermal {
2425 polling-delay-passive = <250>;
2427 thermal-sensors = <&tsens 0>;
2430 aoss_alert0: trip-point0 {
2438 cpuss0-thermal {
2439 polling-delay-passive = <250>;
2441 thermal-sensors = <&tsens 1>;
2444 cpuss0_alert0: trip-point0 {
2452 cpuss1-thermal {
2453 polling-delay-passive = <250>;
2455 thermal-sensors = <&tsens 2>;
2458 cpuss1_alert0: trip-point0 {
2466 cpu0-thermal {
2467 polling-delay-passive = <250>;
2469 thermal-sensors = <&tsens 3>;
2472 cpu0_alert0: trip-point0 {
2478 cpu0_crit: cpu-crit {
2486 cpu1-thermal {
2487 polling-delay-passive = <250>;
2489 thermal-sensors = <&tsens 4>;
2492 cpu1_alert0: trip-point0 {
2498 cpu1_crit: cpu-crit {
2506 cpu2-thermal {
2507 polling-delay-passive = <250>;
2509 thermal-sensors = <&tsens 5>;
2512 cpu2_alert0: trip-point0 {
2518 cpu2_crit: cpu-crit {
2526 cpu3-thermal {
2527 polling-delay-passive = <250>;
2529 thermal-sensors = <&tsens 6>;
2532 cpu3_alert0: trip-point0 {
2538 cpu3_crit: cpu-crit {
2552 pwr-cluster-thermal {
2553 polling-delay-passive = <250>;
2555 thermal-sensors = <&tsens 7>;
2558 pwr_cluster_alert0: trip-point0 {
2564 pwr_cluster_crit: cpu-crit {
2572 gpu-thermal {
2573 polling-delay-passive = <250>;
2575 thermal-sensors = <&tsens 8>;
2577 cooling-maps {
2580 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2585 gpu_alert0: trip-point0 {
2591 trip-point1 {
2597 trip-point2 {
2607 compatible = "arm,armv8-timer";