Lines Matching +full:msm8998 +full:- +full:pinctrl
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/soc/qcom,apr.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <19200000>;
37 clock-output-names = "xo_board";
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32764>;
44 clock-output-names = "sleep_clk";
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 cpu-idle-states = <&perf_cpu_sleep_0
62 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>;
64 next-level-cache = <&l2_1>;
65 l2_1: l2-cache {
67 cache-level = <2>;
68 cache-unified;
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 cpu-idle-states = <&perf_cpu_sleep_0
82 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>;
84 next-level-cache = <&l2_1>;
89 compatible = "arm,cortex-a53";
91 enable-method = "psci";
92 cpu-idle-states = <&perf_cpu_sleep_0
97 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>;
99 next-level-cache = <&l2_1>;
104 compatible = "arm,cortex-a53";
106 enable-method = "psci";
107 cpu-idle-states = <&perf_cpu_sleep_0
112 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>;
114 next-level-cache = <&l2_1>;
119 compatible = "arm,cortex-a53";
121 enable-method = "psci";
122 cpu-idle-states = <&pwr_cpu_sleep_0
127 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>;
129 next-level-cache = <&l2_0>;
130 l2_0: l2-cache {
132 cache-level = <2>;
133 cache-unified;
139 compatible = "arm,cortex-a53";
141 enable-method = "psci";
142 cpu-idle-states = <&pwr_cpu_sleep_0
147 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>;
149 next-level-cache = <&l2_0>;
154 compatible = "arm,cortex-a53";
156 enable-method = "psci";
157 cpu-idle-states = <&pwr_cpu_sleep_0
162 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>;
164 next-level-cache = <&l2_0>;
169 compatible = "arm,cortex-a53";
171 enable-method = "psci";
172 cpu-idle-states = <&pwr_cpu_sleep_0
177 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>;
179 next-level-cache = <&l2_0>;
182 cpu-map {
220 idle-states {
221 entry-method = "psci";
223 pwr_cpu_sleep_0: cpu-sleep-0-0 {
224 compatible = "arm,idle-state";
225 idle-state-name = "pwr-retention";
226 arm,psci-suspend-param = <0x40000002>;
227 entry-latency-us = <338>;
228 exit-latency-us = <423>;
229 min-residency-us = <200>;
232 pwr_cpu_sleep_1: cpu-sleep-0-1 {
233 compatible = "arm,idle-state";
234 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspend-param = <0x40000003>;
236 entry-latency-us = <515>;
237 exit-latency-us = <1821>;
238 min-residency-us = <1000>;
239 local-timer-stop;
242 perf_cpu_sleep_0: cpu-sleep-1-0 {
243 compatible = "arm,idle-state";
244 idle-state-name = "perf-retention";
245 arm,psci-suspend-param = <0x40000002>;
246 entry-latency-us = <154>;
247 exit-latency-us = <87>;
248 min-residency-us = <200>;
251 perf_cpu_sleep_1: cpu-sleep-1-1 {
252 compatible = "arm,idle-state";
253 idle-state-name = "perf-power-collapse";
254 arm,psci-suspend-param = <0x40000003>;
255 entry-latency-us = <262>;
256 exit-latency-us = <301>;
257 min-residency-us = <1000>;
258 local-timer-stop;
261 pwr_cluster_sleep_0: cluster-sleep-0-0 {
262 compatible = "arm,idle-state";
263 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency-us = <284>;
266 exit-latency-us = <384>;
267 min-residency-us = <9987>;
268 local-timer-stop;
271 pwr_cluster_sleep_1: cluster-sleep-0-1 {
272 compatible = "arm,idle-state";
273 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency-us = <338>;
276 exit-latency-us = <423>;
277 min-residency-us = <9987>;
278 local-timer-stop;
281 pwr_cluster_sleep_2: cluster-sleep-0-2 {
282 compatible = "arm,idle-state";
283 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency-us = <515>;
286 exit-latency-us = <1821>;
287 min-residency-us = <9987>;
288 local-timer-stop;
291 perf_cluster_sleep_0: cluster-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency-us = <272>;
296 exit-latency-us = <329>;
297 min-residency-us = <9987>;
298 local-timer-stop;
301 perf_cluster_sleep_1: cluster-sleep-1-1 {
302 compatible = "arm,idle-state";
303 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency-us = <332>;
306 exit-latency-us = <368>;
307 min-residency-us = <9987>;
308 local-timer-stop;
311 perf_cluster_sleep_2: cluster-sleep-1-2 {
312 compatible = "arm,idle-state";
313 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency-us = <545>;
316 exit-latency-us = <1609>;
317 min-residency-us = <9987>;
318 local-timer-stop;
325 compatible = "qcom,scm-msm8998", "qcom,scm";
335 dsi_opp_table: opp-table-dsi {
336 compatible = "operating-points-v2";
338 opp-131250000 {
339 opp-hz = /bits/ 64 <131250000>;
340 required-opps = <&rpmpd_opp_svs>;
343 opp-210000000 {
344 opp-hz = /bits/ 64 <210000000>;
345 required-opps = <&rpmpd_opp_svs_plus>;
348 opp-262500000 {
349 opp-hz = /bits/ 64 <262500000>;
350 required-opps = <&rpmpd_opp_nom>;
355 compatible = "arm,armv8-pmuv3";
360 compatible = "arm,psci-1.0";
365 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
367 glink-edge {
368 compatible = "qcom,glink-rpm";
371 qcom,rpm-msg-ram = <&rpm_msg_ram>;
374 rpm_requests: rpm-requests {
375 compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm";
376 qcom,glink-channels = "rpm_requests";
378 rpmcc: clock-controller {
379 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
380 #clock-cells = <1>;
383 rpmpd: power-controller {
384 compatible = "qcom,sdm660-rpmpd";
385 #power-domain-cells = <1>;
386 operating-points-v2 = <&rpmpd_opp_table>;
388 rpmpd_opp_table: opp-table {
389 compatible = "operating-points-v2";
392 opp-level = <RPM_SMD_LEVEL_RETENTION>;
396 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
400 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
404 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
408 opp-level = <RPM_SMD_LEVEL_SVS>;
412 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
416 opp-level = <RPM_SMD_LEVEL_NOM>;
420 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
424 opp-level = <RPM_SMD_LEVEL_TURBO>;
432 reserved-memory {
433 #address-cells = <2>;
434 #size-cells = <2>;
437 wlan_msa_guard: wlan-msa-guard@85600000 {
439 no-map;
442 wlan_msa_mem: wlan-msa-mem@85700000 {
444 no-map;
447 qhee_code: qhee-code@85800000 {
449 no-map;
453 compatible = "qcom,rmtfs-mem";
455 no-map;
457 qcom,client-id = <1>;
461 smem_region: smem-mem@86000000 {
463 no-map;
468 no-map;
473 no-map;
478 no-map;
483 no-map;
488 no-map;
493 no-map;
496 adsp_mem: adsp-region@f6000000 {
498 no-map;
501 qseecom_mem: qseecom-region@f6800000 {
503 no-map;
507 compatible = "shared-dma-pool";
509 no-map;
515 memory-region = <&smem_region>;
519 smp2p-adsp {
524 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>;
527 adsp_smp2p_out: master-kernel {
528 qcom,entry-name = "master-kernel";
529 #qcom,smem-state-cells = <1>;
532 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "slave-kernel";
534 interrupt-controller;
535 #interrupt-cells = <2>;
539 smp2p-mpss {
544 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>;
547 modem_smp2p_out: master-kernel {
548 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells = <1>;
552 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "slave-kernel";
554 interrupt-controller;
555 #interrupt-cells = <2>;
560 #address-cells = <1>;
561 #size-cells = <1>;
563 compatible = "simple-bus";
565 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>;
568 #reset-cells = <1>;
569 #power-domain-cells = <1>;
572 clock-names = "xo", "sleep_clk";
578 compatible = "qcom,rpm-msg-ram";
583 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
585 #address-cells = <1>;
586 #size-cells = <1>;
588 qusb2_hstx_trim: hstx-trim@240 {
593 gpu_speed_bin: gpu-speed-bin@41a0 {
600 compatible = "qcom,prng-ee";
603 clock-names = "core";
607 compatible = "qcom,sdm660-bimc";
609 #interconnect-cells = <1>;
618 compatible = "qcom,sdm660-cnoc";
620 #interconnect-cells = <1>;
624 compatible = "qcom,sdm660-snoc";
626 #interconnect-cells = <1>;
630 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
632 #global-interrupts = <2>;
633 #iommu-cells = <1>;
671 compatible = "qcom,sdm660-a2noc";
673 #interconnect-cells = <1>;
674 clock-names = "ipa",
687 compatible = "qcom,sdm660-mnoc";
689 #interconnect-cells = <1>;
690 clock-names = "iface";
694 tsens: thermal-sensor@10ae000 {
695 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
701 interrupt-names = "uplow", "critical";
702 #thermal-sensor-cells = <1>;
706 compatible = "qcom,tcsr-mutex";
708 #hwlock-cells = <1>;
712 compatible = "qcom,sdm630-tcsr", "syscon";
716 tlmm: pinctrl@3100000 {
717 compatible = "qcom,sdm630-pinctrl";
721 reg-names = "south", "center", "north";
723 gpio-controller;
724 gpio-ranges = <&tlmm 0 0 114>;
725 #gpio-cells = <2>;
726 interrupt-controller;
727 #interrupt-cells = <2>;
729 blsp1_uart1_default: blsp1-uart1-default-state {
732 drive-strength = <2>;
733 bias-disable;
736 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
739 drive-strength = <2>;
740 bias-disable;
743 blsp1_uart2_default: blsp1-uart2-default-state {
746 drive-strength = <2>;
747 bias-disable;
750 blsp2_uart1_default: blsp2-uart1-active-state {
751 tx-rts-pins {
754 drive-strength = <2>;
755 bias-disable;
758 rx-pins {
765 drive-strength = <2>;
766 bias-pull-up;
769 cts-pins {
773 drive-strength = <2>;
774 bias-pull-down;
778 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
779 tx-pins {
782 drive-strength = <2>;
783 bias-pull-up;
786 rx-cts-rts-pins {
789 drive-strength = <2>;
790 bias-disable;
794 i2c1_default: i2c1-default-state {
797 drive-strength = <2>;
798 bias-disable;
801 i2c1_sleep: i2c1-sleep-state {
804 drive-strength = <2>;
805 bias-pull-up;
808 i2c2_default: i2c2-default-state {
811 drive-strength = <2>;
812 bias-disable;
815 i2c2_sleep: i2c2-sleep-state {
818 drive-strength = <2>;
819 bias-pull-up;
822 i2c3_default: i2c3-default-state {
825 drive-strength = <2>;
826 bias-disable;
829 i2c3_sleep: i2c3-sleep-state {
832 drive-strength = <2>;
833 bias-pull-up;
836 i2c4_default: i2c4-default-state {
839 drive-strength = <2>;
840 bias-disable;
843 i2c4_sleep: i2c4-sleep-state {
846 drive-strength = <2>;
847 bias-pull-up;
850 i2c5_default: i2c5-default-state {
853 drive-strength = <2>;
854 bias-disable;
857 i2c5_sleep: i2c5-sleep-state {
860 drive-strength = <2>;
861 bias-pull-up;
864 i2c6_default: i2c6-default-state {
867 drive-strength = <2>;
868 bias-disable;
871 i2c6_sleep: i2c6-sleep-state {
874 drive-strength = <2>;
875 bias-pull-up;
878 i2c7_default: i2c7-default-state {
881 drive-strength = <2>;
882 bias-disable;
885 i2c7_sleep: i2c7-sleep-state {
888 drive-strength = <2>;
889 bias-pull-up;
892 i2c8_default: i2c8-default-state {
895 drive-strength = <2>;
896 bias-disable;
899 i2c8_sleep: i2c8-sleep-state {
902 drive-strength = <2>;
903 bias-pull-up;
906 cci0_default: cci0-default-state {
909 bias-pull-up;
910 drive-strength = <2>;
913 cci1_default: cci1-default-state {
916 bias-pull-up;
917 drive-strength = <2>;
920 sdc1_state_on: sdc1-on-state {
921 clk-pins {
923 bias-disable;
924 drive-strength = <16>;
927 cmd-pins {
929 bias-pull-up;
930 drive-strength = <10>;
933 data-pins {
935 bias-pull-up;
936 drive-strength = <10>;
939 rclk-pins {
941 bias-pull-down;
945 sdc1_state_off: sdc1-off-state {
946 clk-pins {
948 bias-disable;
949 drive-strength = <2>;
952 cmd-pins {
954 bias-pull-up;
955 drive-strength = <2>;
958 data-pins {
960 bias-pull-up;
961 drive-strength = <2>;
964 rclk-pins {
966 bias-pull-down;
970 sdc2_state_on: sdc2-on-state {
971 clk-pins {
973 bias-disable;
974 drive-strength = <16>;
977 cmd-pins {
979 bias-pull-up;
980 drive-strength = <10>;
983 data-pins {
985 bias-pull-up;
986 drive-strength = <10>;
990 sdc2_state_off: sdc2-off-state {
991 clk-pins {
993 bias-disable;
994 drive-strength = <2>;
997 cmd-pins {
999 bias-pull-up;
1000 drive-strength = <2>;
1003 data-pins {
1005 bias-pull-up;
1006 drive-strength = <2>;
1012 compatible = "qcom,sdm660-mss-pil";
1014 reg-names = "qdsp6", "rmb";
1016 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1022 interrupt-names = "wdog",
1026 "stop-ack",
1027 "shutdown-ack";
1037 clock-names = "iface",
1046 qcom,smem-states = <&modem_smp2p_out 0>;
1047 qcom,smem-state-names = "stop";
1050 reset-names = "mss_restart";
1052 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1054 power-domains = <&rpmpd SDM660_VDDCX>,
1056 power-domain-names = "cx", "mx";
1058 memory-region = <&mba_region>, <&mpss_region>;
1062 glink-edge {
1065 qcom,remote-pid = <1>;
1071 compatible = "qcom,adreno-508.0", "qcom,adreno";
1074 reg-names = "kgsl_3d0_reg_memory";
1085 clock-names = "iface",
1092 power-domains = <&rpmpd SDM660_VDDMX>;
1095 nvmem-cells = <&gpu_speed_bin>;
1096 nvmem-cell-names = "speed_bin";
1099 interconnect-names = "gfx-mem";
1101 operating-points-v2 = <&gpu_sdm630_opp_table>;
1102 #cooling-cells = <2>;
1106 gpu_sdm630_opp_table: opp-table {
1107 compatible = "operating-points-v2";
1108 opp-775000000 {
1109 opp-hz = /bits/ 64 <775000000>;
1110 opp-level = <RPM_SMD_LEVEL_TURBO>;
1111 opp-peak-kBps = <5412000>;
1112 opp-supported-hw = <0xa2>;
1114 opp-647000000 {
1115 opp-hz = /bits/ 64 <647000000>;
1116 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1117 opp-peak-kBps = <4068000>;
1118 opp-supported-hw = <0xff>;
1120 opp-588000000 {
1121 opp-hz = /bits/ 64 <588000000>;
1122 opp-level = <RPM_SMD_LEVEL_NOM>;
1123 opp-peak-kBps = <3072000>;
1124 opp-supported-hw = <0xff>;
1126 opp-465000000 {
1127 opp-hz = /bits/ 64 <465000000>;
1128 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1129 opp-peak-kBps = <2724000>;
1130 opp-supported-hw = <0xff>;
1132 opp-370000000 {
1133 opp-hz = /bits/ 64 <370000000>;
1134 opp-level = <RPM_SMD_LEVEL_SVS>;
1135 opp-peak-kBps = <2188000>;
1136 opp-supported-hw = <0xff>;
1138 opp-240000000 {
1139 opp-hz = /bits/ 64 <240000000>;
1140 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1141 opp-peak-kBps = <1648000>;
1142 opp-supported-hw = <0xff>;
1144 opp-160000000 {
1145 opp-hz = /bits/ 64 <160000000>;
1146 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1147 opp-peak-kBps = <1200000>;
1148 opp-supported-hw = <0xff>;
1152 adreno_gpu_zap: zap-shader {
1153 memory-region = <&zap_shader_region>;
1158 compatible = "qcom,sdm630-smmu-v2",
1159 "qcom,adreno-smmu", "qcom,smmu-v2";
1169 power-domains = <&gpucc GPU_GX_GDSC>;
1173 clock-names = "iface",
1176 #global-interrupts = <2>;
1177 #iommu-cells = <1>;
1193 gpucc: clock-controller@5065000 {
1194 compatible = "qcom,gpucc-sdm630";
1195 #clock-cells = <1>;
1196 #reset-cells = <1>;
1197 #power-domain-cells = <1>;
1203 clock-names = "xo",
1209 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1211 #iommu-cells = <1>;
1213 #global-interrupts = <2>;
1238 compatible = "qcom,rpm-stats";
1243 compatible = "qcom,spmi-pmic-arb";
1249 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1250 interrupt-names = "periph_irq";
1254 #address-cells = <2>;
1255 #size-cells = <0>;
1256 interrupt-controller;
1257 #interrupt-cells = <4>;
1261 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1264 #address-cells = <1>;
1265 #size-cells = <1>;
1273 clock-names = "cfg_noc",
1279 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1281 assigned-clock-rates = <19200000>, <120000000>;
1287 interrupt-names = "pwr_event",
1292 power-domains = <&gcc USB_30_GDSC>;
1302 snps,parkmode-disable-ss-quirk;
1305 phy-names = "usb2-phy", "usb3-phy";
1306 snps,hird-threshold = /bits/ 8 <0>;
1311 compatible = "qcom,sdm660-qmp-usb3-phy";
1318 clock-names = "aux",
1322 clock-output-names = "usb3_phy_pipe_clk_src";
1323 #clock-cells = <0>;
1324 #phy-cells = <0>;
1328 reset-names = "phy",
1331 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
1337 compatible = "qcom,sdm660-qusb2-phy";
1339 #phy-cells = <0>;
1343 clock-names = "cfg_ahb", "ref";
1346 nvmem-cells = <&qusb2_hstx_trim>;
1351 compatible = "qcom,sdm660-qusb2-phy";
1353 #phy-cells = <0>;
1357 clock-names = "cfg_ahb", "ref";
1360 nvmem-cells = <&qusb2_hstx_trim>;
1365 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1367 reg-names = "hc";
1371 interrupt-names = "hc_irq", "pwr_irq";
1373 bus-width = <4>;
1378 clock-names = "iface", "core", "xo";
1383 interconnect-names = "sdhc-ddr","cpu-sdhc";
1384 operating-points-v2 = <&sdhc2_opp_table>;
1386 pinctrl-names = "default", "sleep";
1387 pinctrl-0 = <&sdc2_state_on>;
1388 pinctrl-1 = <&sdc2_state_off>;
1389 power-domains = <&rpmpd SDM660_VDDCX>;
1393 sdhc2_opp_table: opp-table {
1394 compatible = "operating-points-v2";
1396 opp-50000000 {
1397 opp-hz = /bits/ 64 <50000000>;
1398 required-opps = <&rpmpd_opp_low_svs>;
1399 opp-peak-kBps = <200000 140000>;
1400 opp-avg-kBps = <130718 133320>;
1402 opp-100000000 {
1403 opp-hz = /bits/ 64 <100000000>;
1404 required-opps = <&rpmpd_opp_svs>;
1405 opp-peak-kBps = <250000 160000>;
1406 opp-avg-kBps = <196078 150000>;
1408 opp-200000000 {
1409 opp-hz = /bits/ 64 <200000000>;
1410 required-opps = <&rpmpd_opp_nom>;
1411 opp-peak-kBps = <4096000 4096000>;
1412 opp-avg-kBps = <1338562 1338562>;
1418 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1422 reg-names = "hc", "cqhci", "ice";
1426 interrupt-names = "hc_irq", "pwr_irq";
1432 clock-names = "iface", "core", "xo", "ice";
1436 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1437 operating-points-v2 = <&sdhc1_opp_table>;
1438 pinctrl-names = "default", "sleep";
1439 pinctrl-0 = <&sdc1_state_on>;
1440 pinctrl-1 = <&sdc1_state_off>;
1441 power-domains = <&rpmpd SDM660_VDDCX>;
1443 bus-width = <8>;
1444 non-removable;
1448 sdhc1_opp_table: opp-table {
1449 compatible = "operating-points-v2";
1451 opp-50000000 {
1452 opp-hz = /bits/ 64 <50000000>;
1453 required-opps = <&rpmpd_opp_low_svs>;
1454 opp-peak-kBps = <200000 140000>;
1455 opp-avg-kBps = <130718 133320>;
1457 opp-100000000 {
1458 opp-hz = /bits/ 64 <100000000>;
1459 required-opps = <&rpmpd_opp_svs>;
1460 opp-peak-kBps = <250000 160000>;
1461 opp-avg-kBps = <196078 150000>;
1463 opp-384000000 {
1464 opp-hz = /bits/ 64 <384000000>;
1465 required-opps = <&rpmpd_opp_nom>;
1466 opp-peak-kBps = <4096000 4096000>;
1467 opp-avg-kBps = <1338562 1338562>;
1473 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1476 #address-cells = <1>;
1477 #size-cells = <1>;
1484 clock-names = "cfg_noc", "core",
1487 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1489 assigned-clock-rates = <19200000>, <60000000>;
1494 interrupt-names = "pwr_event",
1498 qcom,select-utmi-as-pipe-clk;
1509 /* This is the HS-only host */
1510 maximum-speed = "high-speed";
1512 phy-names = "usb2-phy";
1513 snps,hird-threshold = /bits/ 8 <0>;
1517 mmcc: clock-controller@c8c0000 {
1518 compatible = "qcom,mmcc-sdm630";
1520 #clock-cells = <1>;
1521 #reset-cells = <1>;
1522 #power-domain-cells = <1>;
1523 clock-names = "xo",
1545 mdss: display-subsystem@c900000 {
1549 reg-names = "mdss_phys", "vbif_phys";
1551 power-domains = <&mmcc MDSS_GDSC>;
1557 clock-names = "iface",
1564 interrupt-controller;
1565 #interrupt-cells = <1>;
1567 #address-cells = <1>;
1568 #size-cells = <1>;
1572 mdp: display-controller@c901000 {
1573 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1575 reg-names = "mdp_phys";
1577 interrupt-parent = <&mdss>;
1580 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1582 assigned-clock-rates = <300000000>,
1588 clock-names = "iface",
1596 interconnect-names = "mdp0-mem",
1597 "mdp1-mem",
1598 "rotator-mem";
1600 operating-points-v2 = <&mdp_opp_table>;
1601 power-domains = <&rpmpd SDM660_VDDCX>;
1604 #address-cells = <1>;
1605 #size-cells = <0>;
1610 remote-endpoint = <&mdss_dsi0_in>;
1615 mdp_opp_table: opp-table {
1616 compatible = "operating-points-v2";
1618 opp-150000000 {
1619 opp-hz = /bits/ 64 <150000000>;
1620 opp-peak-kBps = <320000 320000 76800>;
1621 required-opps = <&rpmpd_opp_low_svs>;
1623 opp-275000000 {
1624 opp-hz = /bits/ 64 <275000000>;
1625 opp-peak-kBps = <6400000 6400000 160000>;
1626 required-opps = <&rpmpd_opp_svs>;
1628 opp-300000000 {
1629 opp-hz = /bits/ 64 <300000000>;
1630 opp-peak-kBps = <6400000 6400000 190000>;
1631 required-opps = <&rpmpd_opp_svs_plus>;
1633 opp-330000000 {
1634 opp-hz = /bits/ 64 <330000000>;
1635 opp-peak-kBps = <6400000 6400000 240000>;
1636 required-opps = <&rpmpd_opp_nom>;
1638 opp-412500000 {
1639 opp-hz = /bits/ 64 <412500000>;
1640 opp-peak-kBps = <6400000 6400000 320000>;
1641 required-opps = <&rpmpd_opp_turbo>;
1647 compatible = "qcom,sdm660-dsi-ctrl",
1648 "qcom,mdss-dsi-ctrl";
1650 reg-names = "dsi_ctrl";
1652 operating-points-v2 = <&dsi_opp_table>;
1653 power-domains = <&rpmpd SDM660_VDDCX>;
1655 interrupt-parent = <&mdss>;
1658 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1660 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1672 clock-names = "mdp_core",
1687 #address-cells = <1>;
1688 #size-cells = <0>;
1693 remote-endpoint = <&mdp5_intf1_out>;
1706 compatible = "qcom,dsi-phy-14nm-660";
1710 reg-names = "dsi_phy",
1714 #clock-cells = <1>;
1715 #phy-cells = <0>;
1718 clock-names = "iface", "ref";
1723 blsp1_dma: dma-controller@c144000 {
1724 compatible = "qcom,bam-v1.7.0";
1728 clock-names = "bam_clk";
1729 #dma-cells = <1>;
1731 qcom,controlled-remotely;
1732 num-channels = <18>;
1733 qcom,num-ees = <4>;
1737 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1742 clock-names = "core", "iface";
1744 dma-names = "tx", "rx";
1745 pinctrl-names = "default", "sleep";
1746 pinctrl-0 = <&blsp1_uart1_default>;
1747 pinctrl-1 = <&blsp1_uart1_sleep>;
1752 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1757 clock-names = "core", "iface";
1759 dma-names = "tx", "rx";
1760 pinctrl-names = "default";
1761 pinctrl-0 = <&blsp1_uart2_default>;
1766 compatible = "qcom,i2c-qup-v2.2.1";
1772 clock-names = "core", "iface";
1773 clock-frequency = <400000>;
1775 dma-names = "tx", "rx";
1777 pinctrl-names = "default", "sleep";
1778 pinctrl-0 = <&i2c1_default>;
1779 pinctrl-1 = <&i2c1_sleep>;
1780 #address-cells = <1>;
1781 #size-cells = <0>;
1786 compatible = "qcom,i2c-qup-v2.2.1";
1792 clock-names = "core", "iface";
1793 clock-frequency = <400000>;
1795 dma-names = "tx", "rx";
1797 pinctrl-names = "default", "sleep";
1798 pinctrl-0 = <&i2c2_default>;
1799 pinctrl-1 = <&i2c2_sleep>;
1800 #address-cells = <1>;
1801 #size-cells = <0>;
1806 compatible = "qcom,i2c-qup-v2.2.1";
1812 clock-names = "core", "iface";
1813 clock-frequency = <400000>;
1815 dma-names = "tx", "rx";
1817 pinctrl-names = "default", "sleep";
1818 pinctrl-0 = <&i2c3_default>;
1819 pinctrl-1 = <&i2c3_sleep>;
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1826 compatible = "qcom,i2c-qup-v2.2.1";
1832 clock-names = "core", "iface";
1833 clock-frequency = <400000>;
1835 dma-names = "tx", "rx";
1837 pinctrl-names = "default", "sleep";
1838 pinctrl-0 = <&i2c4_default>;
1839 pinctrl-1 = <&i2c4_sleep>;
1840 #address-cells = <1>;
1841 #size-cells = <0>;
1845 blsp2_dma: dma-controller@c184000 {
1846 compatible = "qcom,bam-v1.7.0";
1850 clock-names = "bam_clk";
1851 #dma-cells = <1>;
1853 qcom,controlled-remotely;
1854 num-channels = <18>;
1855 qcom,num-ees = <4>;
1859 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1864 clock-names = "core", "iface";
1866 dma-names = "tx", "rx";
1867 pinctrl-names = "default", "sleep";
1868 pinctrl-0 = <&blsp2_uart1_default>;
1869 pinctrl-1 = <&blsp2_uart1_sleep>;
1874 compatible = "qcom,i2c-qup-v2.2.1";
1880 clock-names = "core", "iface";
1881 clock-frequency = <400000>;
1883 dma-names = "tx", "rx";
1885 pinctrl-names = "default", "sleep";
1886 pinctrl-0 = <&i2c5_default>;
1887 pinctrl-1 = <&i2c5_sleep>;
1888 #address-cells = <1>;
1889 #size-cells = <0>;
1894 compatible = "qcom,i2c-qup-v2.2.1";
1900 clock-names = "core", "iface";
1901 clock-frequency = <400000>;
1903 dma-names = "tx", "rx";
1905 pinctrl-names = "default", "sleep";
1906 pinctrl-0 = <&i2c6_default>;
1907 pinctrl-1 = <&i2c6_sleep>;
1908 #address-cells = <1>;
1909 #size-cells = <0>;
1914 compatible = "qcom,i2c-qup-v2.2.1";
1920 clock-names = "core", "iface";
1921 clock-frequency = <400000>;
1923 dma-names = "tx", "rx";
1925 pinctrl-names = "default", "sleep";
1926 pinctrl-0 = <&i2c7_default>;
1927 pinctrl-1 = <&i2c7_sleep>;
1928 #address-cells = <1>;
1929 #size-cells = <0>;
1934 compatible = "qcom,i2c-qup-v2.2.1";
1940 clock-names = "core", "iface";
1941 clock-frequency = <400000>;
1943 dma-names = "tx", "rx";
1945 pinctrl-names = "default", "sleep";
1946 pinctrl-0 = <&i2c8_default>;
1947 pinctrl-1 = <&i2c8_sleep>;
1948 #address-cells = <1>;
1949 #size-cells = <0>;
1954 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1957 #address-cells = <1>;
1958 #size-cells = <1>;
1962 pil-reloc@94c {
1963 compatible = "qcom,pil-reloc-info";
1969 compatible = "qcom,sdm660-camss";
1984 reg-names = "csi_clk_mux",
2008 interrupt-names = "csid0",
2060 clock-names = "ahb",
2103 interconnect-names = "vfe-mem";
2108 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2113 #address-cells = <1>;
2114 #size-cells = <0>;
2119 compatible = "qcom,msm8996-cci";
2120 #address-cells = <1>;
2121 #size-cells = <0>;
2125 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2127 assigned-clock-rates = <80800000>, <37500000>;
2132 clock-names = "camss_top_ahb",
2137 pinctrl-names = "default";
2138 pinctrl-0 = <&cci0_default &cci1_default>;
2139 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2142 cci_i2c0: i2c-bus@0 {
2144 clock-frequency = <400000>;
2145 #address-cells = <1>;
2146 #size-cells = <0>;
2149 cci_i2c1: i2c-bus@1 {
2151 clock-frequency = <400000>;
2152 #address-cells = <1>;
2153 #size-cells = <0>;
2157 venus: video-codec@cc00000 {
2158 compatible = "qcom,sdm660-venus";
2164 clock-names = "core", "iface", "bus", "bus_throttle";
2167 interconnect-names = "cpu-cfg", "video-mem";
2189 memory-region = <&venus_region>;
2190 power-domains = <&mmcc VENUS_GDSC>;
2193 video-decoder {
2194 compatible = "venus-decoder";
2196 clock-names = "vcodec0_core";
2197 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2200 video-encoder {
2201 compatible = "venus-encoder";
2203 clock-names = "vcodec0_core";
2204 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2209 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2215 clock-names = "iface-mm", "iface-smmu",
2216 "bus-smmu";
2217 #global-interrupts = <2>;
2218 #iommu-cells = <1>;
2253 compatible = "qcom,sdm660-adsp-pas";
2256 interrupts-extended =
2262 interrupt-names = "wdog", "fatal", "ready",
2263 "handover", "stop-ack";
2266 clock-names = "xo";
2268 memory-region = <&adsp_region>;
2269 power-domains = <&rpmpd SDM660_VDDCX>;
2270 power-domain-names = "cx";
2272 qcom,smem-states = <&adsp_smp2p_out 0>;
2273 qcom,smem-state-names = "stop";
2275 glink-edge {
2280 qcom,remote-pid = <2>;
2283 compatible = "qcom,apr-v2";
2284 qcom,glink-channels = "apr_audio_svc";
2286 #address-cells = <1>;
2287 #size-cells = <0>;
2298 compatible = "qcom,q6afe-dais";
2299 #address-cells = <1>;
2300 #size-cells = <0>;
2301 #sound-dai-cells = <1>;
2309 compatible = "qcom,q6asm-dais";
2310 #address-cells = <1>;
2311 #size-cells = <0>;
2312 #sound-dai-cells = <1>;
2321 compatible = "qcom,q6adm-routing";
2322 #sound-dai-cells = <0>;
2330 compatible = "qcom,sdm660-gnoc";
2332 #interconnect-cells = <1>;
2336 compatible = "qcom,sdm660-apcs-hmss-global",
2337 "qcom,msm8994-apcs-kpss-global";
2340 #mbox-cells = <1>;
2344 #address-cells = <1>;
2345 #size-cells = <1>;
2347 compatible = "arm,armv7-timer-mem";
2349 clock-frequency = <19200000>;
2352 frame-number = <0>;
2360 frame-number = <1>;
2367 frame-number = <2>;
2374 frame-number = <3>;
2381 frame-number = <4>;
2388 frame-number = <5>;
2395 frame-number = <6>;
2402 intc: interrupt-controller@17a00000 {
2403 compatible = "arm,gic-v3";
2406 #interrupt-cells = <3>;
2407 #address-cells = <1>;
2408 #size-cells = <1>;
2410 interrupt-controller;
2411 #redistributor-regions = <1>;
2412 redistributor-stride = <0x0 0x20000>;
2417 compatible = "qcom,wcn3990-wifi";
2419 reg-names = "membase";
2420 memory-region = <&wlan_msa_mem>;
2422 clock-names = "cxo_ref_clk_pin";
2438 qcom,snoc-host-cap-8bit-quirk;
2439 qcom,no-msa-ready-indicator;
2447 thermal-zones {
2448 aoss-thermal {
2449 polling-delay-passive = <250>;
2451 thermal-sensors = <&tsens 0>;
2454 aoss_alert0: trip-point0 {
2462 cpuss0-thermal {
2463 polling-delay-passive = <250>;
2465 thermal-sensors = <&tsens 1>;
2468 cpuss0_alert0: trip-point0 {
2476 cpuss1-thermal {
2477 polling-delay-passive = <250>;
2479 thermal-sensors = <&tsens 2>;
2482 cpuss1_alert0: trip-point0 {
2490 cpu0-thermal {
2491 polling-delay-passive = <250>;
2493 thermal-sensors = <&tsens 3>;
2496 cpu0_alert0: trip-point0 {
2502 cpu0_crit: cpu-crit {
2510 cpu1-thermal {
2511 polling-delay-passive = <250>;
2513 thermal-sensors = <&tsens 4>;
2516 cpu1_alert0: trip-point0 {
2522 cpu1_crit: cpu-crit {
2530 cpu2-thermal {
2531 polling-delay-passive = <250>;
2533 thermal-sensors = <&tsens 5>;
2536 cpu2_alert0: trip-point0 {
2542 cpu2_crit: cpu-crit {
2550 cpu3-thermal {
2551 polling-delay-passive = <250>;
2553 thermal-sensors = <&tsens 6>;
2556 cpu3_alert0: trip-point0 {
2562 cpu3_crit: cpu-crit {
2576 pwr-cluster-thermal {
2577 polling-delay-passive = <250>;
2579 thermal-sensors = <&tsens 7>;
2582 pwr_cluster_alert0: trip-point0 {
2588 pwr_cluster_crit: cpu-crit {
2596 gpu-thermal {
2597 polling-delay-passive = <250>;
2599 thermal-sensors = <&tsens 8>;
2601 cooling-maps {
2604 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2609 gpu_alert0: trip-point0 {
2615 trip-point1 {
2621 trip-point2 {
2631 compatible = "arm,armv8-timer";