Lines Matching +full:0 +full:x94000
35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
55 reg = <0x0 0x100>;
75 reg = <0x0 0x101>;
90 reg = <0x0 0x102>;
105 reg = <0x0 0x103>;
117 cpu4: cpu@0 {
120 reg = <0x0 0x0>;
140 reg = <0x0 0x1>;
155 reg = <0x0 0x2>;
170 reg = <0x0 0x3>;
223 pwr_cpu_sleep_0: cpu-sleep-0-0 {
226 arm,psci-suspend-param = <0x40000002>;
232 pwr_cpu_sleep_1: cpu-sleep-0-1 {
235 arm,psci-suspend-param = <0x40000003>;
242 perf_cpu_sleep_0: cpu-sleep-1-0 {
245 arm,psci-suspend-param = <0x40000002>;
254 arm,psci-suspend-param = <0x40000003>;
261 pwr_cluster_sleep_0: cluster-sleep-0-0 {
264 arm,psci-suspend-param = <0x400000F2>;
271 pwr_cluster_sleep_1: cluster-sleep-0-1 {
274 arm,psci-suspend-param = <0x400000F3>;
281 pwr_cluster_sleep_2: cluster-sleep-0-2 {
284 arm,psci-suspend-param = <0x400000F4>;
291 perf_cluster_sleep_0: cluster-sleep-1-0 {
294 arm,psci-suspend-param = <0x400000F2>;
304 arm,psci-suspend-param = <0x400000F3>;
314 arm,psci-suspend-param = <0x400000F4>;
332 reg = <0x0 0x80000000 0x0 0x0>;
372 mboxes = <&apcs_glb 0>;
438 reg = <0x0 0x85600000 0x0 0x100000>;
443 reg = <0x0 0x85700000 0x0 0x100000>;
448 reg = <0x0 0x85800000 0x0 0x600000>;
454 reg = <0x0 0x85e00000 0x0 0x200000>;
462 reg = <0 0x86000000 0 0x200000>;
467 reg = <0x0 0x86200000 0x0 0x3300000>;
472 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
477 reg = <0x0 0x92a00000 0x0 0x1e00000>;
482 reg = <0x0 0x94800000 0x0 0x200000>;
487 reg = <0x0 0x94a00000 0x0 0x100000>;
492 reg = <0x0 0x9f800000 0x0 0x800000>;
497 reg = <0x0 0xf6000000 0x0 0x800000>;
502 reg = <0x0 0xf6800000 0x0 0x1400000>;
508 reg = <0x0 0xfed00000 0x0 0xa00000>;
524 qcom,local-pid = <0>;
544 qcom,local-pid = <0>;
559 soc@0 {
562 ranges = <0 0 0 0xffffffff>;
570 reg = <0x00100000 0x94000>;
579 reg = <0x00778000 0x7000>;
584 reg = <0x00780000 0x621c>;
589 reg = <0x243 0x1>;
594 reg = <0x41a2 0x1>;
601 reg = <0x00793000 0x1000>;
608 reg = <0x01008000 0x78000>;
614 reg = <0x010ac000 0x4>;
619 reg = <0x01500000 0x10000>;
625 reg = <0x01626000 0x7090>;
631 reg = <0x016c0000 0x40000>;
672 reg = <0x01704000 0xc100>;
688 reg = <0x01745000 0xa010>;
696 reg = <0x010ae000 0x1000>, /* TM */
697 <0x010ad000 0x1000>; /* SROT */
707 reg = <0x01f40000 0x20000>;
713 reg = <0x01f60000 0x20000>;
718 reg = <0x03100000 0x400000>,
719 <0x03500000 0x400000>,
720 <0x03900000 0x400000>;
724 gpio-ranges = <&tlmm 0 0 114>;
1013 reg = <0x04080000 0x100>, <0x04180000 0x40>;
1017 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1046 qcom,smem-states = <&modem_smp2p_out 0>;
1052 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1073 reg = <0x05000000 0x40000>;
1093 iommus = <&kgsl_smmu 0>;
1112 opp-supported-hw = <0xa2>;
1118 opp-supported-hw = <0xff>;
1124 opp-supported-hw = <0xff>;
1130 opp-supported-hw = <0xff>;
1136 opp-supported-hw = <0xff>;
1142 opp-supported-hw = <0xff>;
1148 opp-supported-hw = <0xff>;
1160 reg = <0x05040000 0x10000>;
1198 reg = <0x05065000 0x9038>;
1210 reg = <0x05100000 0x40000>;
1239 reg = <0x00290000 0x10000>;
1244 reg = <0x0800f000 0x1000>,
1245 <0x08400000 0x1000000>,
1246 <0x09400000 0x1000000>,
1247 <0x0a400000 0x220000>,
1248 <0x0800a000 0x3000>;
1252 qcom,ee = <0>;
1253 qcom,channel = <0>;
1255 #size-cells = <0>;
1262 reg = <0x0a8f8800 0x400>;
1298 reg = <0x0a800000 0xc8d0>;
1306 snps,hird-threshold = /bits/ 8 <0>;
1312 reg = <0x0c010000 0x1000>;
1323 #clock-cells = <0>;
1324 #phy-cells = <0>;
1331 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
1338 reg = <0x0c012000 0x180>;
1339 #phy-cells = <0>;
1352 reg = <0x0c014000 0x180>;
1353 #phy-cells = <0>;
1366 reg = <0x0c084000 0x1000>;
1382 <&gnoc 0 &cnoc 28>;
1387 pinctrl-0 = <&sdc2_state_on>;
1419 reg = <0x0c0c4000 0x1000>,
1420 <0x0c0c5000 0x1000>,
1421 <0x0c0c8000 0x8000>;
1435 <&gnoc 0 &cnoc 27>;
1439 pinctrl-0 = <&sdc1_state_on>;
1474 reg = <0x0c2f8800 0x400>;
1504 reg = <0x0c200000 0xc8d0>;
1513 snps,hird-threshold = /bits/ 8 <0>;
1519 reg = <0x0c8c0000 0x40000>;
1538 <&mdss_dsi0_phy 0>,
1539 <0>,
1540 <0>,
1541 <0>,
1542 <0>;
1547 reg = <0x0c900000 0x1000>,
1548 <0x0c9b0000 0x1040>;
1574 reg = <0x0c901000 0x89000>;
1578 interrupts = <0>;
1595 <&gnoc 0 &mnoc 17>;
1599 iommus = <&mmss_smmu 0>;
1605 #size-cells = <0>;
1607 port@0 {
1608 reg = <0>;
1649 reg = <0x0c994000 0x400>;
1660 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1688 #size-cells = <0>;
1690 port@0 {
1691 reg = <0>;
1707 reg = <0x0c994400 0x100>,
1708 <0x0c994500 0x300>,
1709 <0x0c994800 0x188>;
1715 #phy-cells = <0>;
1725 reg = <0x0c144000 0x1f000>;
1730 qcom,ee = <0>;
1738 reg = <0x0c16f000 0x200>;
1743 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1746 pinctrl-0 = <&blsp1_uart1_default>;
1753 reg = <0x0c170000 0x1000>;
1761 pinctrl-0 = <&blsp1_uart2_default>;
1767 reg = <0x0c175000 0x600>;
1778 pinctrl-0 = <&i2c1_default>;
1781 #size-cells = <0>;
1787 reg = <0x0c176000 0x600>;
1798 pinctrl-0 = <&i2c2_default>;
1801 #size-cells = <0>;
1807 reg = <0x0c177000 0x600>;
1818 pinctrl-0 = <&i2c3_default>;
1821 #size-cells = <0>;
1827 reg = <0x0c178000 0x600>;
1838 pinctrl-0 = <&i2c4_default>;
1841 #size-cells = <0>;
1847 reg = <0x0c184000 0x1f000>;
1852 qcom,ee = <0>;
1860 reg = <0x0c1af000 0x200>;
1865 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1868 pinctrl-0 = <&blsp2_uart1_default>;
1875 reg = <0x0c1b5000 0x600>;
1886 pinctrl-0 = <&i2c5_default>;
1889 #size-cells = <0>;
1895 reg = <0x0c1b6000 0x600>;
1906 pinctrl-0 = <&i2c6_default>;
1909 #size-cells = <0>;
1915 reg = <0x0c1b7000 0x600>;
1926 pinctrl-0 = <&i2c7_default>;
1929 #size-cells = <0>;
1935 reg = <0x0c1b8000 0x600>;
1946 pinctrl-0 = <&i2c8_default>;
1949 #size-cells = <0>;
1955 reg = <0x146bf000 0x1000>;
1960 ranges = <0 0x146bf000 0x1000>;
1964 reg = <0x94c 0xc8>;
1970 reg = <0x0ca00020 0x10>,
1971 <0x0ca30000 0x100>,
1972 <0x0ca30400 0x100>,
1973 <0x0ca30800 0x100>,
1974 <0x0ca30c00 0x100>,
1975 <0x0c824000 0x1000>,
1976 <0x0ca00120 0x4>,
1977 <0x0c825000 0x1000>,
1978 <0x0ca00124 0x4>,
1979 <0x0c826000 0x1000>,
1980 <0x0ca00128 0x4>,
1981 <0x0ca31000 0x500>,
1982 <0x0ca10000 0x1000>,
1983 <0x0ca14000 0x1000>;
2104 iommus = <&mmss_smmu 0xc00>,
2105 <&mmss_smmu 0xc01>,
2106 <&mmss_smmu 0xc02>,
2107 <&mmss_smmu 0xc03>;
2114 #size-cells = <0>;
2121 #size-cells = <0>;
2122 reg = <0x0ca0c000 0x1000>;
2138 pinctrl-0 = <&cci0_default &cci1_default>;
2142 cci_i2c0: i2c-bus@0 {
2143 reg = <0>;
2146 #size-cells = <0>;
2153 #size-cells = <0>;
2159 reg = <0x0cc00000 0xff000>;
2165 interconnects = <&gnoc 0 &mnoc 13>,
2169 iommus = <&mmss_smmu 0x400>,
2170 <&mmss_smmu 0x401>,
2171 <&mmss_smmu 0x40a>,
2172 <&mmss_smmu 0x407>,
2173 <&mmss_smmu 0x40e>,
2174 <&mmss_smmu 0x40f>,
2175 <&mmss_smmu 0x408>,
2176 <&mmss_smmu 0x409>,
2177 <&mmss_smmu 0x40b>,
2178 <&mmss_smmu 0x40c>,
2179 <&mmss_smmu 0x40d>,
2180 <&mmss_smmu 0x410>,
2181 <&mmss_smmu 0x421>,
2182 <&mmss_smmu 0x428>,
2183 <&mmss_smmu 0x429>,
2184 <&mmss_smmu 0x42b>,
2185 <&mmss_smmu 0x42c>,
2186 <&mmss_smmu 0x42d>,
2187 <&mmss_smmu 0x411>,
2188 <&mmss_smmu 0x431>;
2210 reg = <0x0cd00000 0x40000>;
2254 reg = <0x15700000 0x4040>;
2258 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2272 qcom,smem-states = <&adsp_smp2p_out 0>;
2287 #size-cells = <0>;
2300 #size-cells = <0>;
2311 #size-cells = <0>;
2322 #sound-dai-cells = <0>;
2331 reg = <0x17900000 0xe000>;
2338 reg = <0x17911000 0x1000>;
2348 reg = <0x17920000 0x1000>;
2352 frame-number = <0>;
2355 reg = <0x17921000 0x1000>,
2356 <0x17922000 0x1000>;
2362 reg = <0x17923000 0x1000>;
2369 reg = <0x17924000 0x1000>;
2376 reg = <0x17925000 0x1000>;
2383 reg = <0x17926000 0x1000>;
2390 reg = <0x17927000 0x1000>;
2397 reg = <0x17928000 0x1000>;
2404 reg = <0x17a00000 0x10000>, /* GICD */
2405 <0x17b00000 0x100000>; /* GICR * 8 */
2412 redistributor-stride = <0x0 0x20000>;
2418 reg = <0x18800000 0x800000>;
2436 iommus = <&anoc2_smmu 0x1a00>,
2437 <&anoc2_smmu 0x1a01>;
2451 thermal-sensors = <&tsens 0>;
2635 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;