Lines Matching refs:gcc
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
834 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
835 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
836 <&gcc GCC_EMAC0_PTP_CLK>,
837 <&gcc GCC_EMAC0_RGMII_CLK>;
848 power-domains = <&gcc EMAC_0_GDSC>;
858 gcc: clock-controller@100000 { label
859 compatible = "qcom,gcc-sc8280xp";
950 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
951 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
966 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
988 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1010 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1032 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1052 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1068 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1090 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1110 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1152 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1174 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1196 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1217 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1240 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1263 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1284 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1307 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1328 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1376 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1377 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1393 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1414 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1437 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1458 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1481 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1502 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1522 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1539 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1560 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1581 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1604 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1627 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1648 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1671 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1692 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1736 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1783 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1784 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1799 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1821 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1843 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1865 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1887 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1909 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1931 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1953 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1975 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1997 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2019 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2041 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2063 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2085 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2107 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2129 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2190 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
2191 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
2192 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
2193 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
2194 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
2195 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2196 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2197 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
2198 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
2209 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
2216 resets = <&gcc GCC_PCIE_4_BCR>;
2219 power-domains = <&gcc PCIE_4_GDSC>;
2242 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
2243 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
2244 <&gcc GCC_PCIE_4_CLKREF_CLK>,
2245 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
2246 <&gcc GCC_PCIE_4_PIPE_CLK>,
2247 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
2251 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
2254 power-domains = <&gcc PCIE_4_GDSC>;
2256 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
2303 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
2304 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
2305 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
2306 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
2307 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
2308 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2309 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2310 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2320 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
2327 resets = <&gcc GCC_PCIE_3B_BCR>;
2330 power-domains = <&gcc PCIE_3B_GDSC>;
2353 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
2354 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
2355 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2356 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
2357 <&gcc GCC_PCIE_3B_PIPE_CLK>,
2358 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
2362 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
2365 power-domains = <&gcc PCIE_3B_GDSC>;
2367 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
2414 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2415 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2416 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
2417 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
2418 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2420 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2421 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2431 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2438 resets = <&gcc GCC_PCIE_3A_BCR>;
2441 power-domains = <&gcc PCIE_3A_GDSC>;
2465 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2466 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2467 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2468 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2469 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2470 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2474 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2477 power-domains = <&gcc PCIE_3A_GDSC>;
2479 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2528 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2529 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2530 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2531 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2532 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2533 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2534 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2535 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2545 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2552 resets = <&gcc GCC_PCIE_2B_BCR>;
2555 power-domains = <&gcc PCIE_2B_GDSC>;
2578 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2579 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2580 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2581 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2582 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2583 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2587 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2590 power-domains = <&gcc PCIE_2B_GDSC>;
2592 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2639 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2640 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2641 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2642 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2643 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2644 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2645 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2646 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2656 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2663 resets = <&gcc GCC_PCIE_2A_BCR>;
2666 power-domains = <&gcc PCIE_2A_GDSC>;
2690 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2691 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2692 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2693 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2694 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2695 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2699 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2702 power-domains = <&gcc PCIE_2A_GDSC>;
2704 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2726 resets = <&gcc GCC_UFS_PHY_BCR>;
2729 power-domains = <&gcc UFS_PHY_GDSC>;
2735 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2736 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2737 <&gcc GCC_UFS_PHY_AHB_CLK>,
2738 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2739 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2740 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2741 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2742 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2767 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2768 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
2773 power-domains = <&gcc UFS_PHY_GDSC>;
2792 resets = <&gcc GCC_UFS_CARD_BCR>;
2795 power-domains = <&gcc UFS_CARD_GDSC>;
2800 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2801 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2802 <&gcc GCC_UFS_CARD_AHB_CLK>,
2803 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2804 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2805 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2806 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2807 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2832 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
2833 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
2838 power-domains = <&gcc UFS_CARD_GDSC>;
3442 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3443 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3480 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3481 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3513 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3514 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3540 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3541 <&gcc GCC_SDCC2_APPS_CLK>,
3544 resets = <&gcc GCC_SDCC2_BCR>;
3581 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3592 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
3594 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
3605 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
3607 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
3618 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
3620 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
3631 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
3633 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
3644 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3645 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3646 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3647 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3650 power-domains = <&gcc USB30_PRIM_GDSC>;
3652 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3653 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3691 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3692 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
3693 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3694 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
3697 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
3698 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
3701 power-domains = <&gcc USB30_MP_GDSC>;
3715 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3716 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
3717 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3718 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
3721 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
3722 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
3725 power-domains = <&gcc USB30_MP_GDSC>;
3750 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3759 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3760 <&gcc GCC_USB4_CLKREF_CLK>,
3761 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3762 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3765 power-domains = <&gcc USB30_SEC_GDSC>;
3767 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3768 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3949 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
3950 <&gcc GCC_USB30_MP_MASTER_CLK>,
3951 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
3952 <&gcc GCC_USB30_MP_SLEEP_CLK>,
3953 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3954 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3955 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3956 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3957 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3961 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3962 <&gcc GCC_USB30_MP_MASTER_CLK>;
3994 power-domains = <&gcc USB30_MP_GDSC>;
3997 resets = <&gcc GCC_USB30_MP_BCR>;
4033 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4034 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4035 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4036 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4037 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4038 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4039 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
4040 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
4041 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4045 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4046 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4060 power-domains = <&gcc USB30_PRIM_GDSC>;
4063 resets = <&gcc GCC_USB30_PRIM_BCR>;
4112 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4113 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4114 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4115 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4116 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4117 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4118 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
4119 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
4120 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4124 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4125 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4139 power-domains = <&gcc USB30_SEC_GDSC>;
4142 resets = <&gcc GCC_USB30_SEC_BCR>;
4481 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4482 <&gcc GCC_CAMERA_SF_AXI_CLK>;
4585 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4601 clocks = <&gcc GCC_DISP_AHB_CLK>,
4629 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4630 <&gcc GCC_DISP_SF_AXI_CLK>,
5072 clocks = <&gcc GCC_DISP_AHB_CLK>,
5752 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5769 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5951 clocks = <&gcc GCC_DISP_AHB_CLK>,
5980 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5981 <&gcc GCC_DISP_SF_AXI_CLK>,
6418 clocks = <&gcc GCC_DISP_AHB_CLK>,
6448 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
6449 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
6450 <&gcc GCC_EMAC1_PTP_CLK>,
6451 <&gcc GCC_EMAC1_RGMII_CLK>;
6462 power-domains = <&gcc EMAC_1_GDSC>;