Lines Matching +full:q6apm +full:- +full:lpass +full:- +full:dais
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32764>;
44 #address-cells = <2>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a78c";
52 enable-method = "psci";
53 capacity-dmips-mhz = <981>;
54 dynamic-power-coefficient = <549>;
55 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_PD0>;
57 power-domain-names = "psci";
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = <&cpu0_opp_table>;
61 #cooling-cells = <2>;
62 L2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&L3_0>;
67 L3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
77 compatible = "arm,cortex-a78c";
80 enable-method = "psci";
81 capacity-dmips-mhz = <981>;
82 dynamic-power-coefficient = <549>;
83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = <&cpu0_opp_table>;
89 #cooling-cells = <2>;
90 L2_100: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&L3_0>;
100 compatible = "arm,cortex-a78c";
103 enable-method = "psci";
104 capacity-dmips-mhz = <981>;
105 dynamic-power-coefficient = <549>;
106 next-level-cache = <&L2_200>;
107 power-domains = <&CPU_PD2>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
112 #cooling-cells = <2>;
113 L2_200: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&L3_0>;
123 compatible = "arm,cortex-a78c";
126 enable-method = "psci";
127 capacity-dmips-mhz = <981>;
128 dynamic-power-coefficient = <549>;
129 next-level-cache = <&L2_300>;
130 power-domains = <&CPU_PD3>;
131 power-domain-names = "psci";
132 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = <&cpu0_opp_table>;
135 #cooling-cells = <2>;
136 L2_300: l2-cache {
138 cache-level = <2>;
139 cache-unified;
140 next-level-cache = <&L3_0>;
146 compatible = "arm,cortex-x1c";
149 enable-method = "psci";
150 capacity-dmips-mhz = <1024>;
151 dynamic-power-coefficient = <590>;
152 next-level-cache = <&L2_400>;
153 power-domains = <&CPU_PD4>;
154 power-domain-names = "psci";
155 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = <&cpu4_opp_table>;
158 #cooling-cells = <2>;
159 L2_400: l2-cache {
161 cache-level = <2>;
162 cache-unified;
163 next-level-cache = <&L3_0>;
169 compatible = "arm,cortex-x1c";
172 enable-method = "psci";
173 capacity-dmips-mhz = <1024>;
174 dynamic-power-coefficient = <590>;
175 next-level-cache = <&L2_500>;
176 power-domains = <&CPU_PD5>;
177 power-domain-names = "psci";
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
181 #cooling-cells = <2>;
182 L2_500: l2-cache {
184 cache-level = <2>;
185 cache-unified;
186 next-level-cache = <&L3_0>;
192 compatible = "arm,cortex-x1c";
195 enable-method = "psci";
196 capacity-dmips-mhz = <1024>;
197 dynamic-power-coefficient = <590>;
198 next-level-cache = <&L2_600>;
199 power-domains = <&CPU_PD6>;
200 power-domain-names = "psci";
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
204 #cooling-cells = <2>;
205 L2_600: l2-cache {
207 cache-level = <2>;
208 cache-unified;
209 next-level-cache = <&L3_0>;
215 compatible = "arm,cortex-x1c";
218 enable-method = "psci";
219 capacity-dmips-mhz = <1024>;
220 dynamic-power-coefficient = <590>;
221 next-level-cache = <&L2_700>;
222 power-domains = <&CPU_PD7>;
223 power-domain-names = "psci";
224 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = <&cpu4_opp_table>;
227 #cooling-cells = <2>;
228 L2_700: l2-cache {
230 cache-level = <2>;
231 cache-unified;
232 next-level-cache = <&L3_0>;
236 cpu-map {
272 idle-states {
273 entry-method = "psci";
275 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
276 compatible = "arm,idle-state";
277 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspend-param = <0x40000004>;
279 entry-latency-us = <355>;
280 exit-latency-us = <909>;
281 min-residency-us = <3934>;
282 local-timer-stop;
285 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286 compatible = "arm,idle-state";
287 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspend-param = <0x40000004>;
289 entry-latency-us = <241>;
290 exit-latency-us = <1461>;
291 min-residency-us = <4488>;
292 local-timer-stop;
296 domain-idle-states {
297 CLUSTER_SLEEP_0: cluster-sleep-0 {
298 compatible = "domain-idle-state";
299 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency-us = <3263>;
301 exit-latency-us = <6562>;
302 min-residency-us = <9987>;
309 compatible = "qcom,scm-sc8280xp", "qcom,scm";
311 qcom,dload-mode = <&tcsr 0x13000>;
315 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_voter>;
321 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_voter>;
327 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_voter>;
333 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_voter>;
339 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_voter>;
345 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_voter>;
351 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_voter>;
357 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_voter>;
363 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_voter>;
369 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_voter>;
375 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
381 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_voter>;
393 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points-v2";
395 opp-shared;
397 opp-300000000 {
398 opp-hz = /bits/ 64 <300000000>;
399 opp-peak-kBps = <(300000 * 32)>;
401 opp-403200000 {
402 opp-hz = /bits/ 64 <403200000>;
403 opp-peak-kBps = <(384000 * 32)>;
405 opp-499200000 {
406 opp-hz = /bits/ 64 <499200000>;
407 opp-peak-kBps = <(480000 * 32)>;
409 opp-595200000 {
410 opp-hz = /bits/ 64 <595200000>;
411 opp-peak-kBps = <(576000 * 32)>;
413 opp-691200000 {
414 opp-hz = /bits/ 64 <691200000>;
415 opp-peak-kBps = <(672000 * 32)>;
417 opp-806400000 {
418 opp-hz = /bits/ 64 <806400000>;
419 opp-peak-kBps = <(768000 * 32)>;
421 opp-902400000 {
422 opp-hz = /bits/ 64 <902400000>;
423 opp-peak-kBps = <(864000 * 32)>;
425 opp-1017600000 {
426 opp-hz = /bits/ 64 <1017600000>;
427 opp-peak-kBps = <(960000 * 32)>;
429 opp-1113600000 {
430 opp-hz = /bits/ 64 <1113600000>;
431 opp-peak-kBps = <(1075200 * 32)>;
433 opp-1209600000 {
434 opp-hz = /bits/ 64 <1209600000>;
435 opp-peak-kBps = <(1171200 * 32)>;
437 opp-1324800000 {
438 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <(1267200 * 32)>;
441 opp-1440000000 {
442 opp-hz = /bits/ 64 <1440000000>;
443 opp-peak-kBps = <(1363200 * 32)>;
445 opp-1555200000 {
446 opp-hz = /bits/ 64 <1555200000>;
447 opp-peak-kBps = <(1536000 * 32)>;
449 opp-1670400000 {
450 opp-hz = /bits/ 64 <1670400000>;
451 opp-peak-kBps = <(1612800 * 32)>;
453 opp-1785600000 {
454 opp-hz = /bits/ 64 <1785600000>;
455 opp-peak-kBps = <(1689600 * 32)>;
457 opp-1881600000 {
458 opp-hz = /bits/ 64 <1881600000>;
459 opp-peak-kBps = <(1689600 * 32)>;
461 opp-1996800000 {
462 opp-hz = /bits/ 64 <1996800000>;
463 opp-peak-kBps = <(1689600 * 32)>;
465 opp-2112000000 {
466 opp-hz = /bits/ 64 <2112000000>;
467 opp-peak-kBps = <(1689600 * 32)>;
469 opp-2227200000 {
470 opp-hz = /bits/ 64 <2227200000>;
471 opp-peak-kBps = <(1689600 * 32)>;
473 opp-2342400000 {
474 opp-hz = /bits/ 64 <2342400000>;
475 opp-peak-kBps = <(1689600 * 32)>;
477 opp-2438400000 {
478 opp-hz = /bits/ 64 <2438400000>;
479 opp-peak-kBps = <(1689600 * 32)>;
483 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points-v2";
485 opp-shared;
487 opp-825600000 {
488 opp-hz = /bits/ 64 <825600000>;
489 opp-peak-kBps = <(768000 * 32)>;
491 opp-940800000 {
492 opp-hz = /bits/ 64 <940800000>;
493 opp-peak-kBps = <(864000 * 32)>;
495 opp-1056000000 {
496 opp-hz = /bits/ 64 <1056000000>;
497 opp-peak-kBps = <(960000 * 32)>;
499 opp-1171200000 {
500 opp-hz = /bits/ 64 <1171200000>;
501 opp-peak-kBps = <(1171200 * 32)>;
503 opp-1286400000 {
504 opp-hz = /bits/ 64 <1286400000>;
505 opp-peak-kBps = <(1267200 * 32)>;
507 opp-1401600000 {
508 opp-hz = /bits/ 64 <1401600000>;
509 opp-peak-kBps = <(1363200 * 32)>;
511 opp-1516800000 {
512 opp-hz = /bits/ 64 <1516800000>;
513 opp-peak-kBps = <(1459200 * 32)>;
515 opp-1632000000 {
516 opp-hz = /bits/ 64 <1632000000>;
517 opp-peak-kBps = <(1612800 * 32)>;
519 opp-1747200000 {
520 opp-hz = /bits/ 64 <1747200000>;
521 opp-peak-kBps = <(1689600 * 32)>;
523 opp-1862400000 {
524 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <(1689600 * 32)>;
527 opp-1977600000 {
528 opp-hz = /bits/ 64 <1977600000>;
529 opp-peak-kBps = <(1689600 * 32)>;
531 opp-2073600000 {
532 opp-hz = /bits/ 64 <2073600000>;
533 opp-peak-kBps = <(1689600 * 32)>;
535 opp-2169600000 {
536 opp-hz = /bits/ 64 <2169600000>;
537 opp-peak-kBps = <(1689600 * 32)>;
539 opp-2284800000 {
540 opp-hz = /bits/ 64 <2284800000>;
541 opp-peak-kBps = <(1689600 * 32)>;
543 opp-2400000000 {
544 opp-hz = /bits/ 64 <2400000000>;
545 opp-peak-kBps = <(1689600 * 32)>;
547 opp-2496000000 {
548 opp-hz = /bits/ 64 <2496000000>;
549 opp-peak-kBps = <(1689600 * 32)>;
551 opp-2592000000 {
552 opp-hz = /bits/ 64 <2592000000>;
553 opp-peak-kBps = <(1689600 * 32)>;
555 opp-2688000000 {
556 opp-hz = /bits/ 64 <2688000000>;
557 opp-peak-kBps = <(1689600 * 32)>;
559 opp-2803200000 {
560 opp-hz = /bits/ 64 <2803200000>;
561 opp-peak-kBps = <(1689600 * 32)>;
563 opp-2899200000 {
564 opp-hz = /bits/ 64 <2899200000>;
565 opp-peak-kBps = <(1689600 * 32)>;
567 opp-2995200000 {
568 opp-hz = /bits/ 64 <2995200000>;
569 opp-peak-kBps = <(1689600 * 32)>;
573 qup_opp_table_100mhz: opp-table-qup100mhz {
574 compatible = "operating-points-v2";
576 opp-75000000 {
577 opp-hz = /bits/ 64 <75000000>;
578 required-opps = <&rpmhpd_opp_low_svs>;
581 opp-100000000 {
582 opp-hz = /bits/ 64 <100000000>;
583 required-opps = <&rpmhpd_opp_svs>;
588 compatible = "arm,armv8-pmuv3";
593 compatible = "arm,psci-1.0";
596 CPU_PD0: power-domain-cpu0 {
597 #power-domain-cells = <0>;
598 power-domains = <&CLUSTER_PD>;
599 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
602 CPU_PD1: power-domain-cpu1 {
603 #power-domain-cells = <0>;
604 power-domains = <&CLUSTER_PD>;
605 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
608 CPU_PD2: power-domain-cpu2 {
609 #power-domain-cells = <0>;
610 power-domains = <&CLUSTER_PD>;
611 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
614 CPU_PD3: power-domain-cpu3 {
615 #power-domain-cells = <0>;
616 power-domains = <&CLUSTER_PD>;
617 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
620 CPU_PD4: power-domain-cpu4 {
621 #power-domain-cells = <0>;
622 power-domains = <&CLUSTER_PD>;
623 domain-idle-states = <&BIG_CPU_SLEEP_0>;
626 CPU_PD5: power-domain-cpu5 {
627 #power-domain-cells = <0>;
628 power-domains = <&CLUSTER_PD>;
629 domain-idle-states = <&BIG_CPU_SLEEP_0>;
632 CPU_PD6: power-domain-cpu6 {
633 #power-domain-cells = <0>;
634 power-domains = <&CLUSTER_PD>;
635 domain-idle-states = <&BIG_CPU_SLEEP_0>;
638 CPU_PD7: power-domain-cpu7 {
639 #power-domain-cells = <0>;
640 power-domains = <&CLUSTER_PD>;
641 domain-idle-states = <&BIG_CPU_SLEEP_0>;
644 CLUSTER_PD: power-domain-cpu-cluster0 {
645 #power-domain-cells = <0>;
646 domain-idle-states = <&CLUSTER_SLEEP_0>;
650 reserved-memory {
651 #address-cells = <2>;
652 #size-cells = <2>;
655 reserved-region@80000000 {
657 no-map;
660 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd-db";
663 no-map;
666 reserved-region@80880000 {
668 no-map;
671 smem_mem: smem-region@80900000 {
674 no-map;
678 reserved-region@80b00000 {
680 no-map;
683 reserved-region@83b00000 {
685 no-map;
688 reserved-region@85b00000 {
690 no-map;
693 pil_adsp_mem: adsp-region@86c00000 {
695 no-map;
698 pil_nsp0_mem: cdsp0-region@8a100000 {
700 no-map;
703 pil_nsp1_mem: cdsp1-region@8c600000 {
705 no-map;
708 reserved-region@aeb00000 {
710 no-map;
714 smp2p-adsp {
717 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>;
726 smp2p_adsp_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
731 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
738 smp2p-nsp0 {
741 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>;
750 smp2p_nsp0_out: master-kernel {
751 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells = <1>;
755 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "slave-kernel";
757 interrupt-controller;
758 #interrupt-cells = <2>;
762 smp2p-nsp1 {
765 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
771 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>;
774 smp2p_nsp1_out: master-kernel {
775 qcom,entry-name = "master-kernel";
776 #qcom,smem-state-cells = <1>;
779 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "slave-kernel";
781 interrupt-controller;
782 #interrupt-cells = <2>;
787 compatible = "simple-bus";
788 #address-cells = <2>;
789 #size-cells = <2>;
791 dma-ranges = <0 0 0 0 0x10 0>;
794 compatible = "qcom,sc8280xp-ethqos";
797 reg-names = "stmmaceth", "rgmii";
803 clock-names = "stmmaceth",
810 interrupt-names = "macirq", "eth_lpi";
813 power-domains = <&gcc EMAC_0_GDSC>;
817 rx-fifo-depth = <4096>;
818 tx-fifo-depth = <4096>;
823 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc-sc8280xp";
826 #clock-cells = <1>;
827 #reset-cells = <1>;
828 #power-domain-cells = <1>;
862 power-domains = <&rpmhpd SC8280XP_CX>;
866 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
869 interrupt-controller;
870 #interrupt-cells = <3>;
871 #mbox-cells = <2>;
875 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom";
877 #address-cells = <1>;
878 #size-cells = <1>;
880 gpu_speed_bin: gpu-speed-bin@18b {
887 compatible = "qcom,geni-se-qup";
891 clock-names = "m-ahb", "s-ahb";
894 #address-cells = <2>;
895 #size-cells = <2>;
901 compatible = "qcom,geni-i2c";
903 #address-cells = <1>;
904 #size-cells = <0>;
906 clock-names = "se";
908 power-domains = <&rpmhpd SC8280XP_CX>;
912 interconnect-names = "qup-core", "qup-config", "qup-memory";
917 compatible = "qcom,geni-spi";
919 #address-cells = <1>;
920 #size-cells = <0>;
922 clock-names = "se";
924 power-domains = <&rpmhpd SC8280XP_CX>;
928 interconnect-names = "qup-core", "qup-config", "qup-memory";
933 compatible = "qcom,geni-i2c";
935 #address-cells = <1>;
936 #size-cells = <0>;
938 clock-names = "se";
940 power-domains = <&rpmhpd SC8280XP_CX>;
944 interconnect-names = "qup-core", "qup-config", "qup-memory";
949 compatible = "qcom,geni-spi";
951 #address-cells = <1>;
952 #size-cells = <0>;
954 clock-names = "se";
956 power-domains = <&rpmhpd SC8280XP_CX>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
965 compatible = "qcom,geni-uart";
968 clock-names = "se";
970 operating-points-v2 = <&qup_opp_table_100mhz>;
971 power-domains = <&rpmhpd SC8280XP_CX>;
974 interconnect-names = "qup-core", "qup-config";
979 compatible = "qcom,geni-i2c";
981 #address-cells = <1>;
982 #size-cells = <0>;
984 clock-names = "se";
986 power-domains = <&rpmhpd SC8280XP_CX>;
990 interconnect-names = "qup-core", "qup-config", "qup-memory";
995 compatible = "qcom,geni-spi";
997 #address-cells = <1>;
998 #size-cells = <0>;
1000 clock-names = "se";
1002 power-domains = <&rpmhpd SC8280XP_CX>;
1006 interconnect-names = "qup-core", "qup-config", "qup-memory";
1011 compatible = "qcom,geni-i2c";
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1016 clock-names = "se";
1018 power-domains = <&rpmhpd SC8280XP_CX>;
1022 interconnect-names = "qup-core", "qup-config", "qup-memory";
1027 compatible = "qcom,geni-spi";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1032 clock-names = "se";
1034 power-domains = <&rpmhpd SC8280XP_CX>;
1038 interconnect-names = "qup-core", "qup-config", "qup-memory";
1043 compatible = "qcom,geni-i2c";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1048 clock-names = "se";
1050 power-domains = <&rpmhpd SC8280XP_CX>;
1054 interconnect-names = "qup-core", "qup-config", "qup-memory";
1059 compatible = "qcom,geni-spi";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1064 clock-names = "se";
1066 power-domains = <&rpmhpd SC8280XP_CX>;
1070 interconnect-names = "qup-core", "qup-config", "qup-memory";
1075 compatible = "qcom,geni-i2c";
1077 clock-names = "se";
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 power-domains = <&rpmhpd SC8280XP_CX>;
1086 interconnect-names = "qup-core", "qup-config", "qup-memory";
1091 compatible = "qcom,geni-spi";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1096 clock-names = "se";
1098 power-domains = <&rpmhpd SC8280XP_CX>;
1102 interconnect-names = "qup-core", "qup-config", "qup-memory";
1107 compatible = "qcom,geni-i2c";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 clock-names = "se";
1114 power-domains = <&rpmhpd SC8280XP_CX>;
1118 interconnect-names = "qup-core", "qup-config", "qup-memory";
1123 compatible = "qcom,geni-spi";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1128 clock-names = "se";
1130 power-domains = <&rpmhpd SC8280XP_CX>;
1134 interconnect-names = "qup-core", "qup-config", "qup-memory";
1139 compatible = "qcom,geni-i2c";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 clock-names = "se";
1146 power-domains = <&rpmhpd SC8280XP_CX>;
1150 interconnect-names = "qup-core", "qup-config", "qup-memory";
1155 compatible = "qcom,geni-spi";
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1160 clock-names = "se";
1162 power-domains = <&rpmhpd SC8280XP_CX>;
1166 interconnect-names = "qup-core", "qup-config", "qup-memory";
1172 compatible = "qcom,geni-se-qup";
1176 clock-names = "m-ahb", "s-ahb";
1179 #address-cells = <2>;
1180 #size-cells = <2>;
1186 compatible = "qcom,geni-i2c";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1190 clock-names = "se";
1193 power-domains = <&rpmhpd SC8280XP_CX>;
1197 interconnect-names = "qup-core", "qup-config", "qup-memory";
1202 compatible = "qcom,geni-spi";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1207 clock-names = "se";
1209 power-domains = <&rpmhpd SC8280XP_CX>;
1213 interconnect-names = "qup-core", "qup-config", "qup-memory";
1218 compatible = "qcom,geni-i2c";
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1222 clock-names = "se";
1225 power-domains = <&rpmhpd SC8280XP_CX>;
1229 interconnect-names = "qup-core", "qup-config", "qup-memory";
1234 compatible = "qcom,geni-spi";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1239 clock-names = "se";
1241 power-domains = <&rpmhpd SC8280XP_CX>;
1245 interconnect-names = "qup-core", "qup-config", "qup-memory";
1250 compatible = "qcom,geni-i2c";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 clock-names = "se";
1257 power-domains = <&rpmhpd SC8280XP_CX>;
1261 interconnect-names = "qup-core", "qup-config", "qup-memory";
1266 compatible = "qcom,geni-spi";
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1271 clock-names = "se";
1273 power-domains = <&rpmhpd SC8280XP_CX>;
1277 interconnect-names = "qup-core", "qup-config", "qup-memory";
1282 compatible = "qcom,geni-uart";
1285 clock-names = "se";
1287 operating-points-v2 = <&qup_opp_table_100mhz>;
1288 power-domains = <&rpmhpd SC8280XP_CX>;
1291 interconnect-names = "qup-core", "qup-config";
1296 compatible = "qcom,geni-i2c";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1300 clock-names = "se";
1303 power-domains = <&rpmhpd SC8280XP_CX>;
1307 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 compatible = "qcom,geni-spi";
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1317 clock-names = "se";
1319 power-domains = <&rpmhpd SC8280XP_CX>;
1323 interconnect-names = "qup-core", "qup-config", "qup-memory";
1328 compatible = "qcom,geni-i2c";
1330 clock-names = "se";
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1335 power-domains = <&rpmhpd SC8280XP_CX>;
1339 interconnect-names = "qup-core", "qup-config", "qup-memory";
1344 compatible = "qcom,geni-spi";
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1349 clock-names = "se";
1351 power-domains = <&rpmhpd SC8280XP_CX>;
1355 interconnect-names = "qup-core", "qup-config", "qup-memory";
1360 compatible = "qcom,geni-i2c";
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 clock-names = "se";
1367 power-domains = <&rpmhpd SC8280XP_CX>;
1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1376 compatible = "qcom,geni-spi";
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1381 clock-names = "se";
1383 power-domains = <&rpmhpd SC8280XP_CX>;
1387 interconnect-names = "qup-core", "qup-config", "qup-memory";
1392 compatible = "qcom,geni-i2c";
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396 clock-names = "se";
1399 power-domains = <&rpmhpd SC8280XP_CX>;
1403 interconnect-names = "qup-core", "qup-config", "qup-memory";
1408 compatible = "qcom,geni-spi";
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1413 clock-names = "se";
1415 power-domains = <&rpmhpd SC8280XP_CX>;
1419 interconnect-names = "qup-core", "qup-config", "qup-memory";
1424 compatible = "qcom,geni-i2c";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428 clock-names = "se";
1431 power-domains = <&rpmhpd SC8280XP_CX>;
1435 interconnect-names = "qup-core", "qup-config", "qup-memory";
1440 compatible = "qcom,geni-spi";
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1445 clock-names = "se";
1447 power-domains = <&rpmhpd SC8280XP_CX>;
1451 interconnect-names = "qup-core", "qup-config", "qup-memory";
1457 compatible = "qcom,geni-se-qup";
1461 clock-names = "m-ahb", "s-ahb";
1464 #address-cells = <2>;
1465 #size-cells = <2>;
1471 compatible = "qcom,geni-i2c";
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1476 clock-names = "se";
1478 power-domains = <&rpmhpd SC8280XP_CX>;
1482 interconnect-names = "qup-core", "qup-config", "qup-memory";
1487 compatible = "qcom,geni-spi";
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1492 clock-names = "se";
1494 power-domains = <&rpmhpd SC8280XP_CX>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1503 compatible = "qcom,geni-i2c";
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1508 clock-names = "se";
1510 power-domains = <&rpmhpd SC8280XP_CX>;
1514 interconnect-names = "qup-core", "qup-config", "qup-memory";
1519 compatible = "qcom,geni-spi";
1521 #address-cells = <1>;
1522 #size-cells = <0>;
1524 clock-names = "se";
1526 power-domains = <&rpmhpd SC8280XP_CX>;
1530 interconnect-names = "qup-core", "qup-config", "qup-memory";
1535 compatible = "qcom,geni-i2c";
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1540 clock-names = "se";
1542 power-domains = <&rpmhpd SC8280XP_CX>;
1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1551 compatible = "qcom,geni-spi";
1553 #address-cells = <1>;
1554 #size-cells = <0>;
1556 clock-names = "se";
1558 power-domains = <&rpmhpd SC8280XP_CX>;
1562 interconnect-names = "qup-core", "qup-config", "qup-memory";
1567 compatible = "qcom,geni-i2c";
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1572 clock-names = "se";
1574 power-domains = <&rpmhpd SC8280XP_CX>;
1578 interconnect-names = "qup-core", "qup-config", "qup-memory";
1583 compatible = "qcom,geni-spi";
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1588 clock-names = "se";
1590 power-domains = <&rpmhpd SC8280XP_CX>;
1594 interconnect-names = "qup-core", "qup-config", "qup-memory";
1599 compatible = "qcom,geni-i2c";
1601 #address-cells = <1>;
1602 #size-cells = <0>;
1604 clock-names = "se";
1606 power-domains = <&rpmhpd SC8280XP_CX>;
1610 interconnect-names = "qup-core", "qup-config", "qup-memory";
1615 compatible = "qcom,geni-spi";
1617 #address-cells = <1>;
1618 #size-cells = <0>;
1620 clock-names = "se";
1622 power-domains = <&rpmhpd SC8280XP_CX>;
1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1631 compatible = "qcom,geni-i2c";
1633 #address-cells = <1>;
1634 #size-cells = <0>;
1636 clock-names = "se";
1638 power-domains = <&rpmhpd SC8280XP_CX>;
1642 interconnect-names = "qup-core", "qup-config", "qup-memory";
1647 compatible = "qcom,geni-spi";
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1652 clock-names = "se";
1654 power-domains = <&rpmhpd SC8280XP_CX>;
1658 interconnect-names = "qup-core", "qup-config", "qup-memory";
1663 compatible = "qcom,geni-i2c";
1665 #address-cells = <1>;
1666 #size-cells = <0>;
1668 clock-names = "se";
1670 power-domains = <&rpmhpd SC8280XP_CX>;
1674 interconnect-names = "qup-core", "qup-config", "qup-memory";
1679 compatible = "qcom,geni-spi";
1681 #address-cells = <1>;
1682 #size-cells = <0>;
1684 clock-names = "se";
1686 power-domains = <&rpmhpd SC8280XP_CX>;
1690 interconnect-names = "qup-core", "qup-config", "qup-memory";
1695 compatible = "qcom,geni-i2c";
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1700 clock-names = "se";
1702 power-domains = <&rpmhpd SC8280XP_CX>;
1706 interconnect-names = "qup-core", "qup-config", "qup-memory";
1711 compatible = "qcom,geni-spi";
1713 #address-cells = <1>;
1714 #size-cells = <0>;
1716 clock-names = "se";
1718 power-domains = <&rpmhpd SC8280XP_CX>;
1722 interconnect-names = "qup-core", "qup-config", "qup-memory";
1728 compatible = "qcom,prng-ee";
1731 clock-names = "core";
1736 compatible = "qcom,pcie-sc8280xp";
1743 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1744 #address-cells = <3>;
1745 #size-cells = <2>;
1748 bus-range = <0x00 0xff>;
1750 dma-coherent;
1752 linux,pci-domain = <6>;
1753 num-lanes = <1>;
1755 msi-map = <0x0 &its 0xe0000 0x10000>;
1761 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1763 #interrupt-cells = <1>;
1764 interrupt-map-mask = <0 0 0 0x7>;
1765 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1779 clock-names = "aux",
1789 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1790 assigned-clock-rates = <19200000>;
1794 interconnect-names = "pcie-mem", "cpu-pcie";
1797 reset-names = "pci";
1799 power-domains = <&gcc PCIE_4_GDSC>;
1800 required-opps = <&rpmhpd_opp_nom>;
1803 phy-names = "pciephy";
1810 bus-range = <0x01 0xff>;
1812 #address-cells = <3>;
1813 #size-cells = <2>;
1819 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1828 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1831 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1832 assigned-clock-rates = <100000000>;
1834 power-domains = <&gcc PCIE_4_GDSC>;
1837 reset-names = "phy";
1839 #clock-cells = <0>;
1840 clock-output-names = "pcie_4_pipe_clk";
1842 #phy-cells = <0>;
1849 compatible = "qcom,pcie-sc8280xp";
1856 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1857 #address-cells = <3>;
1858 #size-cells = <2>;
1861 bus-range = <0x00 0xff>;
1863 dma-coherent;
1865 linux,pci-domain = <5>;
1866 num-lanes = <2>;
1868 msi-map = <0x0 &its 0xd0000 0x10000>;
1874 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1876 #interrupt-cells = <1>;
1877 interrupt-map-mask = <0 0 0 0x7>;
1878 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1891 clock-names = "aux",
1900 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1901 assigned-clock-rates = <19200000>;
1905 interconnect-names = "pcie-mem", "cpu-pcie";
1908 reset-names = "pci";
1910 power-domains = <&gcc PCIE_3B_GDSC>;
1911 required-opps = <&rpmhpd_opp_nom>;
1914 phy-names = "pciephy";
1921 bus-range = <0x01 0xff>;
1923 #address-cells = <3>;
1924 #size-cells = <2>;
1930 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1939 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1942 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1943 assigned-clock-rates = <100000000>;
1945 power-domains = <&gcc PCIE_3B_GDSC>;
1948 reset-names = "phy";
1950 #clock-cells = <0>;
1951 clock-output-names = "pcie_3b_pipe_clk";
1953 #phy-cells = <0>;
1960 compatible = "qcom,pcie-sc8280xp";
1967 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1968 #address-cells = <3>;
1969 #size-cells = <2>;
1972 bus-range = <0x00 0xff>;
1974 dma-coherent;
1976 linux,pci-domain = <4>;
1977 num-lanes = <4>;
1979 msi-map = <0x0 &its 0xc0000 0x10000>;
1985 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1987 #interrupt-cells = <1>;
1988 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
2002 clock-names = "aux",
2011 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2012 assigned-clock-rates = <19200000>;
2016 interconnect-names = "pcie-mem", "cpu-pcie";
2019 reset-names = "pci";
2021 power-domains = <&gcc PCIE_3A_GDSC>;
2022 required-opps = <&rpmhpd_opp_nom>;
2025 phy-names = "pciephy";
2032 bus-range = <0x01 0xff>;
2034 #address-cells = <3>;
2035 #size-cells = <2>;
2041 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2051 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2054 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2055 assigned-clock-rates = <100000000>;
2057 power-domains = <&gcc PCIE_3A_GDSC>;
2060 reset-names = "phy";
2062 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2064 #clock-cells = <0>;
2065 clock-output-names = "pcie_3a_pipe_clk";
2067 #phy-cells = <0>;
2074 compatible = "qcom,pcie-sc8280xp";
2081 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2082 #address-cells = <3>;
2083 #size-cells = <2>;
2086 bus-range = <0x00 0xff>;
2088 dma-coherent;
2090 linux,pci-domain = <3>;
2091 num-lanes = <2>;
2093 msi-map = <0x0 &its 0xb0000 0x10000>;
2099 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2101 #interrupt-cells = <1>;
2102 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2116 clock-names = "aux",
2125 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2126 assigned-clock-rates = <19200000>;
2130 interconnect-names = "pcie-mem", "cpu-pcie";
2133 reset-names = "pci";
2135 power-domains = <&gcc PCIE_2B_GDSC>;
2136 required-opps = <&rpmhpd_opp_nom>;
2139 phy-names = "pciephy";
2146 bus-range = <0x01 0xff>;
2148 #address-cells = <3>;
2149 #size-cells = <2>;
2155 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2164 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2167 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2168 assigned-clock-rates = <100000000>;
2170 power-domains = <&gcc PCIE_2B_GDSC>;
2173 reset-names = "phy";
2175 #clock-cells = <0>;
2176 clock-output-names = "pcie_2b_pipe_clk";
2178 #phy-cells = <0>;
2185 compatible = "qcom,pcie-sc8280xp";
2192 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2193 #address-cells = <3>;
2194 #size-cells = <2>;
2197 bus-range = <0x00 0xff>;
2199 dma-coherent;
2201 linux,pci-domain = <2>;
2202 num-lanes = <4>;
2204 msi-map = <0x0 &its 0xa0000 0x10000>;
2210 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2212 #interrupt-cells = <1>;
2213 interrupt-map-mask = <0 0 0 0x7>;
2214 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2227 clock-names = "aux",
2236 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2237 assigned-clock-rates = <19200000>;
2241 interconnect-names = "pcie-mem", "cpu-pcie";
2244 reset-names = "pci";
2246 power-domains = <&gcc PCIE_2A_GDSC>;
2247 required-opps = <&rpmhpd_opp_nom>;
2250 phy-names = "pciephy";
2257 bus-range = <0x01 0xff>;
2259 #address-cells = <3>;
2260 #size-cells = <2>;
2266 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2276 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2279 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2280 assigned-clock-rates = <100000000>;
2282 power-domains = <&gcc PCIE_2A_GDSC>;
2285 reset-names = "phy";
2287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2289 #clock-cells = <0>;
2290 clock-output-names = "pcie_2a_pipe_clk";
2292 #phy-cells = <0>;
2298 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2299 "jedec,ufs-2.0";
2303 phy-names = "ufsphy";
2304 lanes-per-direction = <2>;
2305 #reset-cells = <1>;
2307 reset-names = "rst";
2309 power-domains = <&gcc UFS_PHY_GDSC>;
2310 required-opps = <&rpmhpd_opp_nom>;
2313 dma-coherent;
2323 clock-names = "core_clk",
2331 freq-table-hz = <75000000 300000000>,
2343 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2349 clock-names = "ref",
2353 power-domains = <&gcc UFS_PHY_GDSC>;
2356 reset-names = "ufsphy";
2358 #phy-cells = <0>;
2364 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2365 "jedec,ufs-2.0";
2369 phy-names = "ufsphy";
2370 lanes-per-direction = <2>;
2371 #reset-cells = <1>;
2373 reset-names = "rst";
2375 power-domains = <&gcc UFS_CARD_GDSC>;
2378 dma-coherent;
2388 clock-names = "core_clk",
2396 freq-table-hz = <75000000 300000000>,
2408 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2414 clock-names = "ref",
2418 power-domains = <&gcc UFS_CARD_GDSC>;
2421 reset-names = "ufsphy";
2423 #phy-cells = <0>;
2429 compatible = "qcom,tcsr-mutex";
2431 #hwlock-cells = <1>;
2435 compatible = "qcom,sc8280xp-tcsr", "syscon";
2440 compatible = "qcom,adreno-690.0", "qcom,adreno";
2445 reg-names = "kgsl_3d0_reg_memory",
2450 operating-points-v2 = <&gpu_opp_table>;
2454 interconnect-names = "gfx-mem";
2455 #cooling-cells = <2>;
2459 gpu_opp_table: opp-table {
2460 compatible = "operating-points-v2";
2462 opp-270000000 {
2463 opp-hz = /bits/ 64 <270000000>;
2464 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2465 opp-peak-kBps = <451000>;
2468 opp-410000000 {
2469 opp-hz = /bits/ 64 <410000000>;
2470 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2471 opp-peak-kBps = <1555000>;
2474 opp-500000000 {
2475 opp-hz = /bits/ 64 <500000000>;
2476 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2477 opp-peak-kBps = <1555000>;
2480 opp-547000000 {
2481 opp-hz = /bits/ 64 <547000000>;
2482 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2483 opp-peak-kBps = <1555000>;
2486 opp-606000000 {
2487 opp-hz = /bits/ 64 <606000000>;
2488 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2489 opp-peak-kBps = <2736000>;
2492 opp-640000000 {
2493 opp-hz = /bits/ 64 <640000000>;
2494 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2495 opp-peak-kBps = <2736000>;
2498 opp-655000000 {
2499 opp-hz = /bits/ 64 <655000000>;
2500 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2501 opp-peak-kBps = <2736000>;
2504 opp-690000000 {
2505 opp-hz = /bits/ 64 <690000000>;
2506 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2507 opp-peak-kBps = <2736000>;
2513 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2517 reg-names = "gmu", "rscc", "gmu_pdc";
2520 interrupt-names = "hfi", "gmu";
2528 clock-names = "gmu",
2535 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2537 power-domain-names = "cx",
2540 operating-points-v2 = <&gmu_opp_table>;
2542 gmu_opp_table: opp-table {
2543 compatible = "operating-points-v2";
2545 opp-200000000 {
2546 opp-hz = /bits/ 64 <200000000>;
2547 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2550 opp-500000000 {
2551 opp-hz = /bits/ 64 <500000000>;
2552 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2557 gpucc: clock-controller@3d90000 {
2558 compatible = "qcom,sc8280xp-gpucc";
2563 clock-names = "bi_tcxo",
2567 power-domains = <&rpmhpd SC8280XP_GFX>;
2568 #clock-cells = <1>;
2569 #reset-cells = <1>;
2570 #power-domain-cells = <1>;
2574 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2575 "qcom,smmu-500", "arm,mmu-500";
2577 #iommu-cells = <2>;
2578 #global-interrupts = <2>;
2601 clock-names = "gcc_gpu_memnoc_gfx_clk",
2609 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2610 dma-coherent;
2614 compatible = "qcom,sc8280xp-usb-hs-phy",
2615 "qcom,usb-snps-hs-5nm-phy";
2618 clock-names = "ref";
2621 #phy-cells = <0>;
2627 compatible = "qcom,sc8280xp-usb-hs-phy",
2628 "qcom,usb-snps-hs-5nm-phy";
2631 clock-names = "ref";
2634 #phy-cells = <0>;
2640 compatible = "qcom,sc8280xp-usb-hs-phy",
2641 "qcom,usb-snps-hs-5nm-phy";
2644 clock-names = "ref";
2647 #phy-cells = <0>;
2653 compatible = "qcom,sc8280xp-usb-hs-phy",
2654 "qcom,usb-snps-hs-5nm-phy";
2657 clock-names = "ref";
2660 #phy-cells = <0>;
2666 compatible = "qcom,sc8280xp-usb-hs-phy",
2667 "qcom,usb-snps-hs-5nm-phy";
2670 clock-names = "ref";
2673 #phy-cells = <0>;
2679 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2686 clock-names = "aux", "ref", "com_aux", "pipe";
2690 reset-names = "phy", "phy_phy";
2692 power-domains = <&gcc USB30_MP_GDSC>;
2694 #clock-cells = <0>;
2695 clock-output-names = "usb2_phy0_pipe_clk";
2697 #phy-cells = <0>;
2703 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2710 clock-names = "aux", "ref", "com_aux", "pipe";
2714 reset-names = "phy", "phy_phy";
2716 power-domains = <&gcc USB30_MP_GDSC>;
2718 #clock-cells = <0>;
2719 clock-output-names = "usb2_phy1_pipe_clk";
2721 #phy-cells = <0>;
2727 compatible = "qcom,sc8280xp-adsp-pas";
2730 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2736 interrupt-names = "wdog", "fatal", "ready",
2737 "handover", "stop-ack", "shutdown-ack";
2740 clock-names = "xo";
2742 power-domains = <&rpmhpd SC8280XP_LCX>,
2744 power-domain-names = "lcx", "lmx";
2746 memory-region = <&pil_adsp_mem>;
2750 qcom,smem-states = <&smp2p_adsp_out 0>;
2751 qcom,smem-state-names = "stop";
2755 remoteproc_adsp_glink: glink-edge {
2756 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2762 label = "lpass";
2763 qcom,remote-pid = <2>;
2767 qcom,glink-channels = "adsp_apps";
2770 #address-cells = <1>;
2771 #size-cells = <0>;
2773 q6apm: service@1 { label
2774 compatible = "qcom,q6apm";
2776 #sound-dai-cells = <0>;
2777 qcom,protection-domain = "avs/audio",
2779 q6apmdai: dais {
2780 compatible = "qcom,q6apm-dais";
2785 compatible = "qcom,q6apm-lpass-dais";
2786 #sound-dai-cells = <1>;
2793 qcom,protection-domain = "avs/audio",
2795 q6prmcc: clock-controller {
2796 compatible = "qcom,q6prm-lpass-clocks";
2797 #clock-cells = <2>;
2805 compatible = "qcom,sc8280xp-lpass-rx-macro";
2812 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2813 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2815 assigned-clock-rates = <19200000>, <19200000>;
2817 clock-output-names = "mclk";
2818 #clock-cells = <0>;
2819 #sound-dai-cells = <1>;
2821 pinctrl-names = "default";
2822 pinctrl-0 = <&rx_swr_default>;
2828 compatible = "qcom,soundwire-v1.6.0";
2832 clock-names = "iface";
2834 reset-names = "swr_audio_cgcr";
2837 qcom,din-ports = <0>;
2838 qcom,dout-ports = <5>;
2840 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2841 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2842 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2843 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2844 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2845 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2846 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2847 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2848 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2850 #sound-dai-cells = <1>;
2851 #address-cells = <2>;
2852 #size-cells = <0>;
2858 compatible = "qcom,sc8280xp-lpass-tx-macro";
2860 pinctrl-names = "default";
2861 pinctrl-0 = <&tx_swr_default>;
2868 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2869 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2871 assigned-clock-rates = <19200000>, <19200000>;
2872 clock-output-names = "mclk";
2874 #clock-cells = <0>;
2875 #sound-dai-cells = <1>;
2881 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2888 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2889 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2891 assigned-clock-rates = <19200000>, <19200000>;
2893 #clock-cells = <0>;
2894 clock-output-names = "mclk";
2895 #sound-dai-cells = <1>;
2897 pinctrl-names = "default";
2898 pinctrl-0 = <&wsa_swr_default>;
2905 compatible = "qcom,soundwire-v1.6.0";
2908 clock-names = "iface";
2910 reset-names = "swr_audio_cgcr";
2913 qcom,din-ports = <2>;
2914 qcom,dout-ports = <6>;
2916 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2917 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2918 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2919 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2920 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2921 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2922 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2923 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2924 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2926 #sound-dai-cells = <1>;
2927 #address-cells = <2>;
2928 #size-cells = <0>;
2933 lpass_audiocc: clock-controller@32a9000 {
2934 compatible = "qcom,sc8280xp-lpassaudiocc";
2936 #clock-cells = <1>;
2937 #reset-cells = <1>;
2941 compatible = "qcom,soundwire-v1.6.0";
2945 interrupt-names = "core", "wakeup";
2948 clock-names = "iface";
2950 reset-names = "swr_audio_cgcr";
2952 #sound-dai-cells = <1>;
2953 #address-cells = <2>;
2954 #size-cells = <0>;
2956 qcom,din-ports = <4>;
2957 qcom,dout-ports = <0>;
2958 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2959 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2960 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2961 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2965 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2966 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2972 compatible = "qcom,sc8280xp-lpass-va-macro";
2978 clock-names = "mclk", "macro", "dcodec", "npl";
2979 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2980 assigned-clock-rates = <19200000>;
2982 #clock-cells = <0>;
2983 clock-output-names = "fsgen";
2984 #sound-dai-cells = <1>;
2990 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2993 gpio-controller;
2994 #gpio-cells = <2>;
2995 gpio-ranges = <&lpass_tlmm 0 0 19>;
2999 clock-names = "core", "audio";
3003 tx_swr_default: tx-swr-default-state {
3004 clk-pins {
3007 drive-strength = <2>;
3008 slew-rate = <1>;
3009 bias-disable;
3012 data-pins {
3015 drive-strength = <2>;
3016 slew-rate = <1>;
3017 bias-bus-hold;
3021 rx_swr_default: rx-swr-default-state {
3022 clk-pins {
3025 drive-strength = <2>;
3026 slew-rate = <1>;
3027 bias-disable;
3030 data-pins {
3033 drive-strength = <2>;
3034 slew-rate = <1>;
3035 bias-bus-hold;
3039 dmic01_default: dmic01-default-state {
3040 clk-pins {
3043 drive-strength = <8>;
3044 output-high;
3047 data-pins {
3050 drive-strength = <8>;
3051 input-enable;
3055 dmic01_sleep: dmic01-sleep-state {
3056 clk-pins {
3059 drive-strength = <2>;
3060 bias-disable;
3061 output-low;
3064 data-pins {
3067 drive-strength = <2>;
3068 bias-pull-down;
3069 input-enable;
3073 dmic23_default: dmic23-default-state {
3074 clk-pins {
3077 drive-strength = <8>;
3078 output-high;
3081 data-pins {
3084 drive-strength = <8>;
3085 input-enable;
3089 dmic23_sleep: dmic23-sleep-state {
3090 clk-pins {
3093 drive-strength = <2>;
3094 bias-disable;
3095 output-low;
3098 data-pins {
3101 drive-strength = <2>;
3102 bias-pull-down;
3103 input-enable;
3107 wsa_swr_default: wsa-swr-default-state {
3108 clk-pins {
3111 drive-strength = <2>;
3112 slew-rate = <1>;
3113 bias-disable;
3116 data-pins {
3119 drive-strength = <2>;
3120 slew-rate = <1>;
3121 bias-bus-hold;
3125 wsa2_swr_default: wsa2-swr-default-state {
3126 clk-pins {
3129 drive-strength = <2>;
3130 slew-rate = <1>;
3131 bias-disable;
3134 data-pins {
3137 drive-strength = <2>;
3138 slew-rate = <1>;
3139 bias-bus-hold;
3144 lpasscc: clock-controller@33e0000 {
3145 compatible = "qcom,sc8280xp-lpasscc";
3147 #clock-cells = <1>;
3148 #reset-cells = <1>;
3152 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3157 interrupt-names = "hc_irq", "pwr_irq";
3162 clock-names = "iface", "core", "xo";
3166 interconnect-names = "sdhc-ddr","cpu-sdhc";
3168 power-domains = <&rpmhpd SC8280XP_CX>;
3169 operating-points-v2 = <&sdc2_opp_table>;
3170 bus-width = <4>;
3171 dma-coherent;
3175 sdc2_opp_table: opp-table {
3176 compatible = "operating-points-v2";
3178 opp-100000000 {
3179 opp-hz = /bits/ 64 <100000000>;
3180 required-opps = <&rpmhpd_opp_low_svs>;
3181 opp-peak-kBps = <1800000 400000>;
3182 opp-avg-kBps = <100000 0>;
3185 opp-202000000 {
3186 opp-hz = /bits/ 64 <202000000>;
3187 required-opps = <&rpmhpd_opp_svs_l1>;
3188 opp-peak-kBps = <5400000 1600000>;
3189 opp-avg-kBps = <200000 0>;
3195 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3202 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3204 power-domains = <&gcc USB30_PRIM_GDSC>;
3208 reset-names = "phy", "common";
3210 #clock-cells = <1>;
3211 #phy-cells = <1>;
3216 #address-cells = <1>;
3217 #size-cells = <0>;
3229 remote-endpoint = <&usb_0_dwc3_ss>;
3242 compatible = "qcom,sc8280xp-usb-hs-phy",
3243 "qcom,usb-snps-hs-5nm-phy";
3245 #phy-cells = <0>;
3248 clock-names = "ref";
3256 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3263 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3265 power-domains = <&gcc USB30_SEC_GDSC>;
3269 reset-names = "phy", "common";
3271 #clock-cells = <1>;
3272 #phy-cells = <1>;
3277 #address-cells = <1>;
3278 #size-cells = <0>;
3290 remote-endpoint = <&usb_1_dwc3_ss>;
3303 compatible = "qcom,sc8280xp-dp-phy";
3311 clock-names = "aux", "cfg_ahb";
3312 power-domains = <&rpmhpd SC8280XP_MX>;
3314 #clock-cells = <1>;
3315 #phy-cells = <0>;
3321 compatible = "qcom,sc8280xp-dp-phy";
3329 clock-names = "aux", "cfg_ahb";
3330 power-domains = <&rpmhpd SC8280XP_MX>;
3332 #clock-cells = <1>;
3333 #phy-cells = <0>;
3339 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3346 operating-points-v2 = <&llcc_bwmon_opp_table>;
3348 llcc_bwmon_opp_table: opp-table {
3349 compatible = "operating-points-v2";
3351 opp-0 {
3352 opp-peak-kBps = <762000>;
3354 opp-1 {
3355 opp-peak-kBps = <1720000>;
3357 opp-2 {
3358 opp-peak-kBps = <2086000>;
3360 opp-3 {
3361 opp-peak-kBps = <2597000>;
3363 opp-4 {
3364 opp-peak-kBps = <2929000>;
3366 opp-5 {
3367 opp-peak-kBps = <3879000>;
3369 opp-6 {
3370 opp-peak-kBps = <5161000>;
3372 opp-7 {
3373 opp-peak-kBps = <5931000>;
3375 opp-8 {
3376 opp-peak-kBps = <6515000>;
3378 opp-9 {
3379 opp-peak-kBps = <7980000>;
3381 opp-10 {
3382 opp-peak-kBps = <8136000>;
3384 opp-11 {
3385 opp-peak-kBps = <10437000>;
3387 opp-12 {
3388 opp-peak-kBps = <12191000>;
3394 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3400 operating-points-v2 = <&cpu_bwmon_opp_table>;
3402 cpu_bwmon_opp_table: opp-table {
3403 compatible = "operating-points-v2";
3405 opp-0 {
3406 opp-peak-kBps = <2288000>;
3408 opp-1 {
3409 opp-peak-kBps = <4577000>;
3411 opp-2 {
3412 opp-peak-kBps = <7110000>;
3414 opp-3 {
3415 opp-peak-kBps = <9155000>;
3417 opp-4 {
3418 opp-peak-kBps = <12298000>;
3420 opp-5 {
3421 opp-peak-kBps = <14236000>;
3423 opp-6 {
3424 opp-peak-kBps = <15258001>;
3429 system-cache-controller@9200000 {
3430 compatible = "qcom,sc8280xp-llcc";
3436 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3443 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
3445 #address-cells = <2>;
3446 #size-cells = <2>;
3458 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3461 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3463 assigned-clock-rates = <19200000>, <200000000>;
3465 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3484 interrupt-names = "pwr_event_1", "pwr_event_2",
3494 power-domains = <&gcc USB30_MP_GDSC>;
3495 required-opps = <&rpmhpd_opp_nom>;
3501 interconnect-names = "usb-ddr", "apps-usb";
3503 wakeup-source;
3516 phy-names = "usb2-0", "usb3-0",
3517 "usb2-1", "usb3-1",
3518 "usb2-2",
3519 "usb2-3";
3525 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3527 #address-cells = <2>;
3528 #size-cells = <2>;
3540 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3543 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3545 assigned-clock-rates = <19200000>, <200000000>;
3547 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3552 interrupt-names = "pwr_event",
3558 power-domains = <&gcc USB30_PRIM_GDSC>;
3559 required-opps = <&rpmhpd_opp_nom>;
3565 interconnect-names = "usb-ddr", "apps-usb";
3567 wakeup-source;
3577 phy-names = "usb2-phy", "usb3-phy";
3580 #address-cells = <1>;
3581 #size-cells = <0>;
3594 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
3602 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3604 #address-cells = <2>;
3605 #size-cells = <2>;
3617 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3620 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3622 assigned-clock-rates = <19200000>, <200000000>;
3624 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3629 interrupt-names = "pwr_event",
3635 power-domains = <&gcc USB30_SEC_GDSC>;
3636 required-opps = <&rpmhpd_opp_nom>;
3642 interconnect-names = "usb-ddr", "apps-usb";
3644 wakeup-source;
3654 phy-names = "usb2-phy", "usb3-phy";
3657 #address-cells = <1>;
3658 #size-cells = <0>;
3671 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3679 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3688 clock-names = "camnoc_axi",
3693 power-domains = <&camcc TITAN_TOP_GDSC>;
3695 pinctrl-0 = <&cci0_default>;
3696 pinctrl-1 = <&cci0_sleep>;
3697 pinctrl-names = "default", "sleep";
3699 #address-cells = <1>;
3700 #size-cells = <0>;
3704 cci0_i2c0: i2c-bus@0 {
3706 clock-frequency = <1000000>;
3707 #address-cells = <1>;
3708 #size-cells = <0>;
3711 cci0_i2c1: i2c-bus@1 {
3713 clock-frequency = <1000000>;
3714 #address-cells = <1>;
3715 #size-cells = <0>;
3720 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3729 clock-names = "camnoc_axi",
3734 power-domains = <&camcc TITAN_TOP_GDSC>;
3736 pinctrl-0 = <&cci1_default>;
3737 pinctrl-1 = <&cci1_sleep>;
3738 pinctrl-names = "default", "sleep";
3740 #address-cells = <1>;
3741 #size-cells = <0>;
3745 cci1_i2c0: i2c-bus@0 {
3747 clock-frequency = <1000000>;
3748 #address-cells = <1>;
3749 #size-cells = <0>;
3752 cci1_i2c1: i2c-bus@1 {
3754 clock-frequency = <1000000>;
3755 #address-cells = <1>;
3756 #size-cells = <0>;
3761 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3770 clock-names = "camnoc_axi",
3774 power-domains = <&camcc TITAN_TOP_GDSC>;
3776 pinctrl-0 = <&cci2_default>;
3777 pinctrl-1 = <&cci2_sleep>;
3778 pinctrl-names = "default", "sleep";
3780 #address-cells = <1>;
3781 #size-cells = <0>;
3785 cci2_i2c0: i2c-bus@0 {
3787 clock-frequency = <1000000>;
3788 #address-cells = <1>;
3789 #size-cells = <0>;
3792 cci2_i2c1: i2c-bus@1 {
3794 clock-frequency = <1000000>;
3795 #address-cells = <1>;
3796 #size-cells = <0>;
3801 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3810 clock-names = "camnoc_axi",
3815 power-domains = <&camcc TITAN_TOP_GDSC>;
3817 pinctrl-0 = <&cci3_default>;
3818 pinctrl-1 = <&cci3_sleep>;
3819 pinctrl-names = "default", "sleep";
3821 #address-cells = <1>;
3822 #size-cells = <0>;
3826 cci3_i2c0: i2c-bus@0 {
3828 clock-frequency = <1000000>;
3829 #address-cells = <1>;
3830 #size-cells = <0>;
3833 cci3_i2c1: i2c-bus@1 {
3835 clock-frequency = <1000000>;
3836 #address-cells = <1>;
3837 #size-cells = <0>;
3842 compatible = "qcom,sc8280xp-camss";
3864 reg-names = "csiphy2",
3905 interrupt-names = "csid1_lite",
3926 power-domains = <&camcc IFE_0_GDSC>,
3931 power-domain-names = "ife0",
3977 clock-names = "camnoc_axi",
4039 interconnect-names = "cam_ahb",
4047 #address-cells = <1>;
4048 #size-cells = <0>;
4052 #address-cells = <1>;
4053 #size-cells = <0>;
4058 #address-cells = <1>;
4059 #size-cells = <0>;
4064 #address-cells = <1>;
4065 #size-cells = <0>;
4070 #address-cells = <1>;
4071 #size-cells = <0>;
4076 camcc: clock-controller@ad00000 {
4077 compatible = "qcom,sc8280xp-camcc";
4083 power-domains = <&rpmhpd SC8280XP_MMCX>;
4084 required-opps = <&rpmhpd_opp_low_svs>;
4085 #clock-cells = <1>;
4086 #reset-cells = <1>;
4087 #power-domain-cells = <1>;
4090 mdss0: display-subsystem@ae00000 {
4091 compatible = "qcom,sc8280xp-mdss";
4093 reg-names = "mdss";
4098 clock-names = "iface",
4104 interconnect-names = "mdp0-mem", "mdp1-mem";
4106 power-domains = <&dispcc0 MDSS_GDSC>;
4109 interrupt-controller;
4110 #interrupt-cells = <1>;
4111 #address-cells = <2>;
4112 #size-cells = <2>;
4117 mdss0_mdp: display-controller@ae01000 {
4118 compatible = "qcom,sc8280xp-dpu";
4121 reg-names = "mdp", "vbif";
4129 clock-names = "bus",
4135 interrupt-parent = <&mdss0>;
4137 power-domains = <&rpmhpd SC8280XP_MMCX>;
4139 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4140 assigned-clock-rates = <19200000>;
4141 operating-points-v2 = <&mdss0_mdp_opp_table>;
4144 #address-cells = <1>;
4145 #size-cells = <0>;
4150 remote-endpoint = <&mdss0_dp0_in>;
4157 remote-endpoint = <&mdss0_dp1_in>;
4164 remote-endpoint = <&mdss0_dp3_in>;
4171 remote-endpoint = <&mdss0_dp2_in>;
4176 mdss0_mdp_opp_table: opp-table {
4177 compatible = "operating-points-v2";
4179 opp-200000000 {
4180 opp-hz = /bits/ 64 <200000000>;
4181 required-opps = <&rpmhpd_opp_low_svs>;
4184 opp-300000000 {
4185 opp-hz = /bits/ 64 <300000000>;
4186 required-opps = <&rpmhpd_opp_svs>;
4189 opp-375000000 {
4190 opp-hz = /bits/ 64 <375000000>;
4191 required-opps = <&rpmhpd_opp_svs_l1>;
4194 opp-500000000 {
4195 opp-hz = /bits/ 64 <500000000>;
4196 required-opps = <&rpmhpd_opp_nom>;
4198 opp-600000000 {
4199 opp-hz = /bits/ 64 <600000000>;
4200 required-opps = <&rpmhpd_opp_turbo_l1>;
4205 mdss0_dp0: displayport-controller@ae90000 {
4206 compatible = "qcom,sc8280xp-dp";
4212 interrupt-parent = <&mdss0>;
4219 clock-names = "core_iface", "core_aux",
4224 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4226 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4230 phy-names = "dp";
4232 #sound-dai-cells = <0>;
4234 operating-points-v2 = <&mdss0_dp0_opp_table>;
4235 power-domains = <&rpmhpd SC8280XP_MMCX>;
4240 #address-cells = <1>;
4241 #size-cells = <0>;
4247 remote-endpoint = <&mdss0_intf0_out>;
4259 mdss0_dp0_opp_table: opp-table {
4260 compatible = "operating-points-v2";
4262 opp-160000000 {
4263 opp-hz = /bits/ 64 <160000000>;
4264 required-opps = <&rpmhpd_opp_low_svs>;
4267 opp-270000000 {
4268 opp-hz = /bits/ 64 <270000000>;
4269 required-opps = <&rpmhpd_opp_svs>;
4272 opp-540000000 {
4273 opp-hz = /bits/ 64 <540000000>;
4274 required-opps = <&rpmhpd_opp_svs_l1>;
4277 opp-810000000 {
4278 opp-hz = /bits/ 64 <810000000>;
4279 required-opps = <&rpmhpd_opp_nom>;
4284 mdss0_dp1: displayport-controller@ae98000 {
4285 compatible = "qcom,sc8280xp-dp";
4291 interrupt-parent = <&mdss0>;
4298 clock-names = "core_iface", "core_aux",
4302 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4304 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4308 phy-names = "dp";
4310 #sound-dai-cells = <0>;
4312 operating-points-v2 = <&mdss0_dp1_opp_table>;
4313 power-domains = <&rpmhpd SC8280XP_MMCX>;
4318 #address-cells = <1>;
4319 #size-cells = <0>;
4325 remote-endpoint = <&mdss0_intf4_out>;
4337 mdss0_dp1_opp_table: opp-table {
4338 compatible = "operating-points-v2";
4340 opp-160000000 {
4341 opp-hz = /bits/ 64 <160000000>;
4342 required-opps = <&rpmhpd_opp_low_svs>;
4345 opp-270000000 {
4346 opp-hz = /bits/ 64 <270000000>;
4347 required-opps = <&rpmhpd_opp_svs>;
4350 opp-540000000 {
4351 opp-hz = /bits/ 64 <540000000>;
4352 required-opps = <&rpmhpd_opp_svs_l1>;
4355 opp-810000000 {
4356 opp-hz = /bits/ 64 <810000000>;
4357 required-opps = <&rpmhpd_opp_nom>;
4362 mdss0_dp2: displayport-controller@ae9a000 {
4363 compatible = "qcom,sc8280xp-dp";
4375 clock-names = "core_iface", "core_aux",
4378 interrupt-parent = <&mdss0>;
4381 phy-names = "dp";
4382 power-domains = <&rpmhpd SC8280XP_MMCX>;
4384 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4386 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4387 operating-points-v2 = <&mdss0_dp2_opp_table>;
4389 #sound-dai-cells = <0>;
4394 #address-cells = <1>;
4395 #size-cells = <0>;
4400 remote-endpoint = <&mdss0_intf6_out>;
4409 mdss0_dp2_opp_table: opp-table {
4410 compatible = "operating-points-v2";
4412 opp-160000000 {
4413 opp-hz = /bits/ 64 <160000000>;
4414 required-opps = <&rpmhpd_opp_low_svs>;
4417 opp-270000000 {
4418 opp-hz = /bits/ 64 <270000000>;
4419 required-opps = <&rpmhpd_opp_svs>;
4422 opp-540000000 {
4423 opp-hz = /bits/ 64 <540000000>;
4424 required-opps = <&rpmhpd_opp_svs_l1>;
4427 opp-810000000 {
4428 opp-hz = /bits/ 64 <810000000>;
4429 required-opps = <&rpmhpd_opp_nom>;
4434 mdss0_dp3: displayport-controller@aea0000 {
4435 compatible = "qcom,sc8280xp-dp";
4447 clock-names = "core_iface", "core_aux",
4450 interrupt-parent = <&mdss0>;
4453 phy-names = "dp";
4454 power-domains = <&rpmhpd SC8280XP_MMCX>;
4456 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4458 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4459 operating-points-v2 = <&mdss0_dp3_opp_table>;
4461 #sound-dai-cells = <0>;
4466 #address-cells = <1>;
4467 #size-cells = <0>;
4472 remote-endpoint = <&mdss0_intf5_out>;
4481 mdss0_dp3_opp_table: opp-table {
4482 compatible = "operating-points-v2";
4484 opp-160000000 {
4485 opp-hz = /bits/ 64 <160000000>;
4486 required-opps = <&rpmhpd_opp_low_svs>;
4489 opp-270000000 {
4490 opp-hz = /bits/ 64 <270000000>;
4491 required-opps = <&rpmhpd_opp_svs>;
4494 opp-540000000 {
4495 opp-hz = /bits/ 64 <540000000>;
4496 required-opps = <&rpmhpd_opp_svs_l1>;
4499 opp-810000000 {
4500 opp-hz = /bits/ 64 <810000000>;
4501 required-opps = <&rpmhpd_opp_nom>;
4508 compatible = "qcom,sc8280xp-dp-phy";
4516 clock-names = "aux", "cfg_ahb";
4517 power-domains = <&rpmhpd SC8280XP_MX>;
4519 #clock-cells = <1>;
4520 #phy-cells = <0>;
4526 compatible = "qcom,sc8280xp-dp-phy";
4534 clock-names = "aux", "cfg_ahb";
4535 power-domains = <&rpmhpd SC8280XP_MX>;
4537 #clock-cells = <1>;
4538 #phy-cells = <0>;
4543 dispcc0: clock-controller@af00000 {
4544 compatible = "qcom,sc8280xp-dispcc0";
4562 power-domains = <&rpmhpd SC8280XP_MMCX>;
4564 #clock-cells = <1>;
4565 #power-domain-cells = <1>;
4566 #reset-cells = <1>;
4571 pdc: interrupt-controller@b220000 {
4572 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4574 qcom,pdc-ranges = <0 480 40>,
4631 #interrupt-cells = <2>;
4632 interrupt-parent = <&intc>;
4633 interrupt-controller;
4636 tsens2: thermal-sensor@c251000 {
4637 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4641 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
4643 interrupt-names = "uplow", "critical";
4644 #thermal-sensor-cells = <1>;
4647 tsens3: thermal-sensor@c252000 {
4648 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4652 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
4654 interrupt-names = "uplow", "critical";
4655 #thermal-sensor-cells = <1>;
4658 tsens0: thermal-sensor@c263000 {
4659 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4663 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4665 interrupt-names = "uplow", "critical";
4666 #thermal-sensor-cells = <1>;
4676 tsens1: thermal-sensor@c265000 {
4677 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4681 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4683 interrupt-names = "uplow", "critical";
4684 #thermal-sensor-cells = <1>;
4687 aoss_qmp: power-management@c300000 {
4688 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4690 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4693 #clock-cells = <0>;
4697 compatible = "qcom,rpmh-stats";
4703 compatible = "qcom,spmi-pmic-arb";
4709 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4710 interrupt-names = "periph_irq";
4711 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4714 #address-cells = <2>;
4715 #size-cells = <0>;
4716 interrupt-controller;
4717 #interrupt-cells = <4>;
4721 compatible = "qcom,sc8280xp-tlmm";
4724 gpio-controller;
4725 #gpio-cells = <2>;
4726 interrupt-controller;
4727 #interrupt-cells = <2>;
4728 gpio-ranges = <&tlmm 0 0 230>;
4729 wakeup-parent = <&pdc>;
4731 cci0_default: cci0-default-state {
4732 cci0_i2c0_default: cci0-i2c0-default-pins {
4736 drive-strength = <2>;
4737 bias-pull-up;
4740 cci0_i2c1_default: cci0-i2c1-default-pins {
4744 drive-strength = <2>;
4745 bias-pull-up;
4749 cci0_sleep: cci0-sleep-state {
4750 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4754 drive-strength = <2>;
4755 bias-pull-down;
4758 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4762 drive-strength = <2>;
4763 bias-pull-down;
4767 cci1_default: cci1-default-state {
4768 cci1_i2c0_default: cci1-i2c0-default-pins {
4772 drive-strength = <2>;
4773 bias-pull-up;
4776 cci1_i2c1_default: cci1-i2c1-default-pins {
4780 drive-strength = <2>;
4781 bias-pull-up;
4785 cci1_sleep: cci1-sleep-state {
4786 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4790 drive-strength = <2>;
4791 bias-pull-down;
4794 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4798 drive-strength = <2>;
4799 bias-pull-down;
4803 cci2_default: cci2-default-state {
4804 cci2_i2c0_default: cci2-i2c0-default-pins {
4808 drive-strength = <2>;
4809 bias-pull-up;
4812 cci2_i2c1_default: cci2-i2c1-default-pins {
4816 drive-strength = <2>;
4817 bias-pull-up;
4821 cci2_sleep: cci2-sleep-state {
4822 cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
4826 drive-strength = <2>;
4827 bias-pull-down;
4830 cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
4834 drive-strength = <2>;
4835 bias-pull-down;
4839 cci3_default: cci3-default-state {
4840 cci3_i2c0_default: cci3-i2c0-default-pins {
4844 drive-strength = <2>;
4845 bias-pull-up;
4848 cci3_i2c1_default: cci3-i2c1-default-pins {
4852 drive-strength = <2>;
4853 bias-pull-up;
4857 cci3_sleep: cci3-sleep-state {
4858 cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
4862 drive-strength = <2>;
4863 bias-pull-down;
4866 cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
4870 drive-strength = <2>;
4871 bias-pull-down;
4877 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4879 #iommu-cells = <2>;
4880 #global-interrupts = <2>;
5013 intc: interrupt-controller@17a00000 {
5014 compatible = "arm,gic-v3";
5015 interrupt-controller;
5016 #interrupt-cells = <3>;
5020 #redistributor-regions = <1>;
5021 redistributor-stride = <0 0x20000>;
5023 #address-cells = <2>;
5024 #size-cells = <2>;
5027 its: msi-controller@17a40000 {
5028 compatible = "arm,gic-v3-its";
5030 msi-controller;
5031 #msi-cells = <1>;
5036 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5043 compatible = "arm,armv7-timer-mem";
5045 #address-cells = <1>;
5046 #size-cells = <1>;
5050 frame-number = <0>;
5058 frame-number = <1>;
5065 frame-number = <2>;
5072 frame-number = <3>;
5079 frame-number = <4>;
5086 frame-number = <5>;
5093 frame-number = <6>;
5101 compatible = "qcom,rpmh-rsc";
5105 reg-names = "drv-0", "drv-1", "drv-2";
5109 qcom,tcs-offset = <0xd00>;
5110 qcom,drv-id = <2>;
5111 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5114 power-domains = <&CLUSTER_PD>;
5116 apps_bcm_voter: bcm-voter {
5117 compatible = "qcom,bcm-voter";
5120 rpmhcc: clock-controller {
5121 compatible = "qcom,sc8280xp-rpmh-clk";
5122 #clock-cells = <1>;
5123 clock-names = "xo";
5127 rpmhpd: power-controller {
5128 compatible = "qcom,sc8280xp-rpmhpd";
5129 #power-domain-cells = <1>;
5130 operating-points-v2 = <&rpmhpd_opp_table>;
5132 rpmhpd_opp_table: opp-table {
5133 compatible = "operating-points-v2";
5136 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5140 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5144 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5148 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5152 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5156 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5160 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5164 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5168 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5172 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5179 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5183 clock-names = "xo", "alternate";
5185 #interconnect-cells = <1>;
5189 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5192 reg-names = "freq-domain0", "freq-domain1";
5196 interrupt-names = "dcvsh-irq-0",
5197 "dcvsh-irq-1";
5200 clock-names = "xo", "alternate";
5202 #freq-domain-cells = <1>;
5203 #clock-cells = <1>;
5207 compatible = "qcom,sc8280xp-nsp0-pas";
5210 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5215 interrupt-names = "wdog", "fatal", "ready",
5216 "handover", "stop-ack";
5219 clock-names = "xo";
5221 power-domains = <&rpmhpd SC8280XP_NSP>;
5222 power-domain-names = "nsp";
5224 memory-region = <&pil_nsp0_mem>;
5226 qcom,smem-states = <&smp2p_nsp0_out 0>;
5227 qcom,smem-state-names = "stop";
5233 glink-edge {
5234 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5241 qcom,remote-pid = <5>;
5245 qcom,glink-channels = "fastrpcglink-apps-dsp";
5247 #address-cells = <1>;
5248 #size-cells = <0>;
5250 compute-cb@1 {
5251 compatible = "qcom,fastrpc-compute-cb";
5256 compute-cb@2 {
5257 compatible = "qcom,fastrpc-compute-cb";
5262 compute-cb@3 {
5263 compatible = "qcom,fastrpc-compute-cb";
5268 compute-cb@4 {
5269 compatible = "qcom,fastrpc-compute-cb";
5274 compute-cb@5 {
5275 compatible = "qcom,fastrpc-compute-cb";
5280 compute-cb@6 {
5281 compatible = "qcom,fastrpc-compute-cb";
5286 compute-cb@7 {
5287 compatible = "qcom,fastrpc-compute-cb";
5292 compute-cb@8 {
5293 compatible = "qcom,fastrpc-compute-cb";
5298 compute-cb@9 {
5299 compatible = "qcom,fastrpc-compute-cb";
5304 compute-cb@10 {
5305 compatible = "qcom,fastrpc-compute-cb";
5310 compute-cb@11 {
5311 compatible = "qcom,fastrpc-compute-cb";
5316 compute-cb@12 {
5317 compatible = "qcom,fastrpc-compute-cb";
5322 compute-cb@13 {
5323 compatible = "qcom,fastrpc-compute-cb";
5328 compute-cb@14 {
5329 compatible = "qcom,fastrpc-compute-cb";
5338 compatible = "qcom,sc8280xp-nsp1-pas";
5341 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5346 interrupt-names = "wdog", "fatal", "ready",
5347 "handover", "stop-ack";
5350 clock-names = "xo";
5352 power-domains = <&rpmhpd SC8280XP_NSP>;
5353 power-domain-names = "nsp";
5355 memory-region = <&pil_nsp1_mem>;
5357 qcom,smem-states = <&smp2p_nsp1_out 0>;
5358 qcom,smem-state-names = "stop";
5364 glink-edge {
5365 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5372 qcom,remote-pid = <12>;
5376 mdss1: display-subsystem@22000000 {
5377 compatible = "qcom,sc8280xp-mdss";
5379 reg-names = "mdss";
5384 clock-names = "iface",
5389 interconnect-names = "mdp0-mem", "mdp1-mem";
5393 power-domains = <&dispcc1 MDSS_GDSC>;
5396 interrupt-controller;
5397 #interrupt-cells = <1>;
5398 #address-cells = <2>;
5399 #size-cells = <2>;
5404 mdss1_mdp: display-controller@22001000 {
5405 compatible = "qcom,sc8280xp-dpu";
5408 reg-names = "mdp", "vbif";
5416 clock-names = "bus",
5422 interrupt-parent = <&mdss1>;
5424 power-domains = <&rpmhpd SC8280XP_MMCX>;
5426 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5427 assigned-clock-rates = <19200000>;
5428 operating-points-v2 = <&mdss1_mdp_opp_table>;
5431 #address-cells = <1>;
5432 #size-cells = <0>;
5437 remote-endpoint = <&mdss1_dp0_in>;
5444 remote-endpoint = <&mdss1_dp1_in>;
5451 remote-endpoint = <&mdss1_dp3_in>;
5458 remote-endpoint = <&mdss1_dp2_in>;
5463 mdss1_mdp_opp_table: opp-table {
5464 compatible = "operating-points-v2";
5466 opp-200000000 {
5467 opp-hz = /bits/ 64 <200000000>;
5468 required-opps = <&rpmhpd_opp_low_svs>;
5471 opp-300000000 {
5472 opp-hz = /bits/ 64 <300000000>;
5473 required-opps = <&rpmhpd_opp_svs>;
5476 opp-375000000 {
5477 opp-hz = /bits/ 64 <375000000>;
5478 required-opps = <&rpmhpd_opp_svs_l1>;
5481 opp-500000000 {
5482 opp-hz = /bits/ 64 <500000000>;
5483 required-opps = <&rpmhpd_opp_nom>;
5485 opp-600000000 {
5486 opp-hz = /bits/ 64 <600000000>;
5487 required-opps = <&rpmhpd_opp_turbo_l1>;
5492 mdss1_dp0: displayport-controller@22090000 {
5493 compatible = "qcom,sc8280xp-dp";
5505 clock-names = "core_iface", "core_aux",
5508 interrupt-parent = <&mdss1>;
5511 phy-names = "dp";
5512 power-domains = <&rpmhpd SC8280XP_MMCX>;
5514 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5516 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5517 operating-points-v2 = <&mdss1_dp0_opp_table>;
5519 #sound-dai-cells = <0>;
5524 #address-cells = <1>;
5525 #size-cells = <0>;
5530 remote-endpoint = <&mdss1_intf0_out>;
5539 mdss1_dp0_opp_table: opp-table {
5540 compatible = "operating-points-v2";
5542 opp-160000000 {
5543 opp-hz = /bits/ 64 <160000000>;
5544 required-opps = <&rpmhpd_opp_low_svs>;
5547 opp-270000000 {
5548 opp-hz = /bits/ 64 <270000000>;
5549 required-opps = <&rpmhpd_opp_svs>;
5552 opp-540000000 {
5553 opp-hz = /bits/ 64 <540000000>;
5554 required-opps = <&rpmhpd_opp_svs_l1>;
5557 opp-810000000 {
5558 opp-hz = /bits/ 64 <810000000>;
5559 required-opps = <&rpmhpd_opp_nom>;
5564 mdss1_dp1: displayport-controller@22098000 {
5565 compatible = "qcom,sc8280xp-dp";
5577 clock-names = "core_iface", "core_aux",
5580 interrupt-parent = <&mdss1>;
5583 phy-names = "dp";
5584 power-domains = <&rpmhpd SC8280XP_MMCX>;
5586 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5588 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5589 operating-points-v2 = <&mdss1_dp1_opp_table>;
5591 #sound-dai-cells = <0>;
5596 #address-cells = <1>;
5597 #size-cells = <0>;
5602 remote-endpoint = <&mdss1_intf4_out>;
5611 mdss1_dp1_opp_table: opp-table {
5612 compatible = "operating-points-v2";
5614 opp-160000000 {
5615 opp-hz = /bits/ 64 <160000000>;
5616 required-opps = <&rpmhpd_opp_low_svs>;
5619 opp-270000000 {
5620 opp-hz = /bits/ 64 <270000000>;
5621 required-opps = <&rpmhpd_opp_svs>;
5624 opp-540000000 {
5625 opp-hz = /bits/ 64 <540000000>;
5626 required-opps = <&rpmhpd_opp_svs_l1>;
5629 opp-810000000 {
5630 opp-hz = /bits/ 64 <810000000>;
5631 required-opps = <&rpmhpd_opp_nom>;
5636 mdss1_dp2: displayport-controller@2209a000 {
5637 compatible = "qcom,sc8280xp-dp";
5649 clock-names = "core_iface", "core_aux",
5652 interrupt-parent = <&mdss1>;
5655 phy-names = "dp";
5656 power-domains = <&rpmhpd SC8280XP_MMCX>;
5658 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5660 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5661 operating-points-v2 = <&mdss1_dp2_opp_table>;
5663 #sound-dai-cells = <0>;
5668 #address-cells = <1>;
5669 #size-cells = <0>;
5674 remote-endpoint = <&mdss1_intf6_out>;
5683 mdss1_dp2_opp_table: opp-table {
5684 compatible = "operating-points-v2";
5686 opp-160000000 {
5687 opp-hz = /bits/ 64 <160000000>;
5688 required-opps = <&rpmhpd_opp_low_svs>;
5691 opp-270000000 {
5692 opp-hz = /bits/ 64 <270000000>;
5693 required-opps = <&rpmhpd_opp_svs>;
5696 opp-540000000 {
5697 opp-hz = /bits/ 64 <540000000>;
5698 required-opps = <&rpmhpd_opp_svs_l1>;
5701 opp-810000000 {
5702 opp-hz = /bits/ 64 <810000000>;
5703 required-opps = <&rpmhpd_opp_nom>;
5708 mdss1_dp3: displayport-controller@220a0000 {
5709 compatible = "qcom,sc8280xp-dp";
5721 clock-names = "core_iface", "core_aux",
5724 interrupt-parent = <&mdss1>;
5727 phy-names = "dp";
5728 power-domains = <&rpmhpd SC8280XP_MMCX>;
5730 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5732 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5733 operating-points-v2 = <&mdss1_dp3_opp_table>;
5735 #sound-dai-cells = <0>;
5740 #address-cells = <1>;
5741 #size-cells = <0>;
5746 remote-endpoint = <&mdss1_intf5_out>;
5755 mdss1_dp3_opp_table: opp-table {
5756 compatible = "operating-points-v2";
5758 opp-160000000 {
5759 opp-hz = /bits/ 64 <160000000>;
5760 required-opps = <&rpmhpd_opp_low_svs>;
5763 opp-270000000 {
5764 opp-hz = /bits/ 64 <270000000>;
5765 required-opps = <&rpmhpd_opp_svs>;
5768 opp-540000000 {
5769 opp-hz = /bits/ 64 <540000000>;
5770 required-opps = <&rpmhpd_opp_svs_l1>;
5773 opp-810000000 {
5774 opp-hz = /bits/ 64 <810000000>;
5775 required-opps = <&rpmhpd_opp_nom>;
5782 compatible = "qcom,sc8280xp-dp-phy";
5790 clock-names = "aux", "cfg_ahb";
5791 power-domains = <&rpmhpd SC8280XP_MX>;
5793 #clock-cells = <1>;
5794 #phy-cells = <0>;
5800 compatible = "qcom,sc8280xp-dp-phy";
5808 clock-names = "aux", "cfg_ahb";
5809 power-domains = <&rpmhpd SC8280XP_MX>;
5811 #clock-cells = <1>;
5812 #phy-cells = <0>;
5817 dispcc1: clock-controller@22100000 {
5818 compatible = "qcom,sc8280xp-dispcc1";
5836 power-domains = <&rpmhpd SC8280XP_MMCX>;
5838 #clock-cells = <1>;
5839 #power-domain-cells = <1>;
5840 #reset-cells = <1>;
5846 compatible = "qcom,sc8280xp-ethqos";
5849 reg-names = "stmmaceth", "rgmii";
5855 clock-names = "stmmaceth",
5862 interrupt-names = "macirq", "eth_lpi";
5865 power-domains = <&gcc EMAC_1_GDSC>;
5869 rx-fifo-depth = <4096>;
5870 tx-fifo-depth = <4096>;
5879 thermal-zones {
5880 cpu0-thermal {
5881 polling-delay-passive = <250>;
5883 thermal-sensors = <&tsens0 1>;
5886 cpu-crit {
5894 cpu1-thermal {
5895 polling-delay-passive = <250>;
5897 thermal-sensors = <&tsens0 2>;
5900 cpu-crit {
5908 cpu2-thermal {
5909 polling-delay-passive = <250>;
5911 thermal-sensors = <&tsens0 3>;
5914 cpu-crit {
5922 cpu3-thermal {
5923 polling-delay-passive = <250>;
5925 thermal-sensors = <&tsens0 4>;
5928 cpu-crit {
5936 cpu4-thermal {
5937 polling-delay-passive = <250>;
5939 thermal-sensors = <&tsens0 5>;
5942 cpu-crit {
5950 cpu5-thermal {
5951 polling-delay-passive = <250>;
5953 thermal-sensors = <&tsens0 6>;
5956 cpu-crit {
5964 cpu6-thermal {
5965 polling-delay-passive = <250>;
5967 thermal-sensors = <&tsens0 7>;
5970 cpu-crit {
5978 cpu7-thermal {
5979 polling-delay-passive = <250>;
5981 thermal-sensors = <&tsens0 8>;
5984 cpu-crit {
5992 cluster0-thermal {
5993 polling-delay-passive = <250>;
5995 thermal-sensors = <&tsens0 9>;
5998 cpu-crit {
6006 gpu-thermal {
6007 polling-delay-passive = <250>;
6009 thermal-sensors = <&tsens2 2>;
6011 cooling-maps {
6014 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6019 gpu_alert0: trip-point0 {
6025 trip-point1 {
6033 mem-thermal {
6034 polling-delay-passive = <250>;
6036 thermal-sensors = <&tsens1 15>;
6039 trip-point0 {
6049 compatible = "arm,armv8-timer";