Lines Matching +full:opp +full:- +full:810000000
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32764>;
44 #address-cells = <2>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a78c";
52 enable-method = "psci";
53 capacity-dmips-mhz = <981>;
54 dynamic-power-coefficient = <549>;
55 next-level-cache = <&l2_0>;
56 power-domains = <&cpu_pd0>;
57 power-domain-names = "psci";
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = <&cpu0_opp_table>;
61 #cooling-cells = <2>;
62 l2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&l3_0>;
67 l3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
77 compatible = "arm,cortex-a78c";
80 enable-method = "psci";
81 capacity-dmips-mhz = <981>;
82 dynamic-power-coefficient = <549>;
83 next-level-cache = <&l2_100>;
84 power-domains = <&cpu_pd1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = <&cpu0_opp_table>;
89 #cooling-cells = <2>;
90 l2_100: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
100 compatible = "arm,cortex-a78c";
103 enable-method = "psci";
104 capacity-dmips-mhz = <981>;
105 dynamic-power-coefficient = <549>;
106 next-level-cache = <&l2_200>;
107 power-domains = <&cpu_pd2>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
112 #cooling-cells = <2>;
113 l2_200: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&l3_0>;
123 compatible = "arm,cortex-a78c";
126 enable-method = "psci";
127 capacity-dmips-mhz = <981>;
128 dynamic-power-coefficient = <549>;
129 next-level-cache = <&l2_300>;
130 power-domains = <&cpu_pd3>;
131 power-domain-names = "psci";
132 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = <&cpu0_opp_table>;
135 #cooling-cells = <2>;
136 l2_300: l2-cache {
138 cache-level = <2>;
139 cache-unified;
140 next-level-cache = <&l3_0>;
146 compatible = "arm,cortex-x1c";
149 enable-method = "psci";
150 capacity-dmips-mhz = <1024>;
151 dynamic-power-coefficient = <590>;
152 next-level-cache = <&l2_400>;
153 power-domains = <&cpu_pd4>;
154 power-domain-names = "psci";
155 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = <&cpu4_opp_table>;
158 #cooling-cells = <2>;
159 l2_400: l2-cache {
161 cache-level = <2>;
162 cache-unified;
163 next-level-cache = <&l3_0>;
169 compatible = "arm,cortex-x1c";
172 enable-method = "psci";
173 capacity-dmips-mhz = <1024>;
174 dynamic-power-coefficient = <590>;
175 next-level-cache = <&l2_500>;
176 power-domains = <&cpu_pd5>;
177 power-domain-names = "psci";
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
181 #cooling-cells = <2>;
182 l2_500: l2-cache {
184 cache-level = <2>;
185 cache-unified;
186 next-level-cache = <&l3_0>;
192 compatible = "arm,cortex-x1c";
195 enable-method = "psci";
196 capacity-dmips-mhz = <1024>;
197 dynamic-power-coefficient = <590>;
198 next-level-cache = <&l2_600>;
199 power-domains = <&cpu_pd6>;
200 power-domain-names = "psci";
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
204 #cooling-cells = <2>;
205 l2_600: l2-cache {
207 cache-level = <2>;
208 cache-unified;
209 next-level-cache = <&l3_0>;
215 compatible = "arm,cortex-x1c";
218 enable-method = "psci";
219 capacity-dmips-mhz = <1024>;
220 dynamic-power-coefficient = <590>;
221 next-level-cache = <&l2_700>;
222 power-domains = <&cpu_pd7>;
223 power-domain-names = "psci";
224 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = <&cpu4_opp_table>;
227 #cooling-cells = <2>;
228 l2_700: l2-cache {
230 cache-level = <2>;
231 cache-unified;
232 next-level-cache = <&l3_0>;
236 cpu-map {
272 idle-states {
273 entry-method = "psci";
275 little_cpu_sleep_0: cpu-sleep-0-0 {
276 compatible = "arm,idle-state";
277 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspend-param = <0x40000004>;
279 entry-latency-us = <355>;
280 exit-latency-us = <909>;
281 min-residency-us = <3934>;
282 local-timer-stop;
285 big_cpu_sleep_0: cpu-sleep-1-0 {
286 compatible = "arm,idle-state";
287 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspend-param = <0x40000004>;
289 entry-latency-us = <241>;
290 exit-latency-us = <1461>;
291 min-residency-us = <4488>;
292 local-timer-stop;
296 domain-idle-states {
297 cluster_sleep_0: cluster-sleep-0 {
298 compatible = "domain-idle-state";
299 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency-us = <3263>;
301 exit-latency-us = <6562>;
302 min-residency-us = <9987>;
309 compatible = "qcom,scm-sc8280xp", "qcom,scm";
311 qcom,dload-mode = <&tcsr 0x13000>;
315 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_voter>;
321 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_voter>;
327 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_voter>;
333 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_voter>;
339 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_voter>;
345 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_voter>;
351 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_voter>;
357 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_voter>;
363 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_voter>;
369 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_voter>;
375 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
381 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_voter>;
393 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points-v2";
395 opp-shared;
397 opp-300000000 {
398 opp-hz = /bits/ 64 <300000000>;
399 opp-peak-kBps = <(300000 * 32)>;
401 opp-403200000 {
402 opp-hz = /bits/ 64 <403200000>;
403 opp-peak-kBps = <(384000 * 32)>;
405 opp-499200000 {
406 opp-hz = /bits/ 64 <499200000>;
407 opp-peak-kBps = <(480000 * 32)>;
409 opp-595200000 {
410 opp-hz = /bits/ 64 <595200000>;
411 opp-peak-kBps = <(576000 * 32)>;
413 opp-691200000 {
414 opp-hz = /bits/ 64 <691200000>;
415 opp-peak-kBps = <(672000 * 32)>;
417 opp-806400000 {
418 opp-hz = /bits/ 64 <806400000>;
419 opp-peak-kBps = <(768000 * 32)>;
421 opp-902400000 {
422 opp-hz = /bits/ 64 <902400000>;
423 opp-peak-kBps = <(864000 * 32)>;
425 opp-1017600000 {
426 opp-hz = /bits/ 64 <1017600000>;
427 opp-peak-kBps = <(960000 * 32)>;
429 opp-1113600000 {
430 opp-hz = /bits/ 64 <1113600000>;
431 opp-peak-kBps = <(1075200 * 32)>;
433 opp-1209600000 {
434 opp-hz = /bits/ 64 <1209600000>;
435 opp-peak-kBps = <(1171200 * 32)>;
437 opp-1324800000 {
438 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <(1267200 * 32)>;
441 opp-1440000000 {
442 opp-hz = /bits/ 64 <1440000000>;
443 opp-peak-kBps = <(1363200 * 32)>;
445 opp-1555200000 {
446 opp-hz = /bits/ 64 <1555200000>;
447 opp-peak-kBps = <(1536000 * 32)>;
449 opp-1670400000 {
450 opp-hz = /bits/ 64 <1670400000>;
451 opp-peak-kBps = <(1612800 * 32)>;
453 opp-1785600000 {
454 opp-hz = /bits/ 64 <1785600000>;
455 opp-peak-kBps = <(1689600 * 32)>;
457 opp-1881600000 {
458 opp-hz = /bits/ 64 <1881600000>;
459 opp-peak-kBps = <(1689600 * 32)>;
461 opp-1996800000 {
462 opp-hz = /bits/ 64 <1996800000>;
463 opp-peak-kBps = <(1689600 * 32)>;
465 opp-2112000000 {
466 opp-hz = /bits/ 64 <2112000000>;
467 opp-peak-kBps = <(1689600 * 32)>;
469 opp-2227200000 {
470 opp-hz = /bits/ 64 <2227200000>;
471 opp-peak-kBps = <(1689600 * 32)>;
473 opp-2342400000 {
474 opp-hz = /bits/ 64 <2342400000>;
475 opp-peak-kBps = <(1689600 * 32)>;
477 opp-2438400000 {
478 opp-hz = /bits/ 64 <2438400000>;
479 opp-peak-kBps = <(1689600 * 32)>;
483 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points-v2";
485 opp-shared;
487 opp-825600000 {
488 opp-hz = /bits/ 64 <825600000>;
489 opp-peak-kBps = <(768000 * 32)>;
491 opp-940800000 {
492 opp-hz = /bits/ 64 <940800000>;
493 opp-peak-kBps = <(864000 * 32)>;
495 opp-1056000000 {
496 opp-hz = /bits/ 64 <1056000000>;
497 opp-peak-kBps = <(960000 * 32)>;
499 opp-1171200000 {
500 opp-hz = /bits/ 64 <1171200000>;
501 opp-peak-kBps = <(1171200 * 32)>;
503 opp-1286400000 {
504 opp-hz = /bits/ 64 <1286400000>;
505 opp-peak-kBps = <(1267200 * 32)>;
507 opp-1401600000 {
508 opp-hz = /bits/ 64 <1401600000>;
509 opp-peak-kBps = <(1363200 * 32)>;
511 opp-1516800000 {
512 opp-hz = /bits/ 64 <1516800000>;
513 opp-peak-kBps = <(1459200 * 32)>;
515 opp-1632000000 {
516 opp-hz = /bits/ 64 <1632000000>;
517 opp-peak-kBps = <(1612800 * 32)>;
519 opp-1747200000 {
520 opp-hz = /bits/ 64 <1747200000>;
521 opp-peak-kBps = <(1689600 * 32)>;
523 opp-1862400000 {
524 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <(1689600 * 32)>;
527 opp-1977600000 {
528 opp-hz = /bits/ 64 <1977600000>;
529 opp-peak-kBps = <(1689600 * 32)>;
531 opp-2073600000 {
532 opp-hz = /bits/ 64 <2073600000>;
533 opp-peak-kBps = <(1689600 * 32)>;
535 opp-2169600000 {
536 opp-hz = /bits/ 64 <2169600000>;
537 opp-peak-kBps = <(1689600 * 32)>;
539 opp-2284800000 {
540 opp-hz = /bits/ 64 <2284800000>;
541 opp-peak-kBps = <(1689600 * 32)>;
543 opp-2400000000 {
544 opp-hz = /bits/ 64 <2400000000>;
545 opp-peak-kBps = <(1689600 * 32)>;
547 opp-2496000000 {
548 opp-hz = /bits/ 64 <2496000000>;
549 opp-peak-kBps = <(1689600 * 32)>;
551 opp-2592000000 {
552 opp-hz = /bits/ 64 <2592000000>;
553 opp-peak-kBps = <(1689600 * 32)>;
555 opp-2688000000 {
556 opp-hz = /bits/ 64 <2688000000>;
557 opp-peak-kBps = <(1689600 * 32)>;
559 opp-2803200000 {
560 opp-hz = /bits/ 64 <2803200000>;
561 opp-peak-kBps = <(1689600 * 32)>;
563 opp-2899200000 {
564 opp-hz = /bits/ 64 <2899200000>;
565 opp-peak-kBps = <(1689600 * 32)>;
567 opp-2995200000 {
568 opp-hz = /bits/ 64 <2995200000>;
569 opp-peak-kBps = <(1689600 * 32)>;
573 qup_opp_table_100mhz: opp-table-qup100mhz {
574 compatible = "operating-points-v2";
576 opp-75000000 {
577 opp-hz = /bits/ 64 <75000000>;
578 required-opps = <&rpmhpd_opp_low_svs>;
581 opp-100000000 {
582 opp-hz = /bits/ 64 <100000000>;
583 required-opps = <&rpmhpd_opp_svs>;
588 compatible = "arm,armv8-pmuv3";
593 compatible = "arm,psci-1.0";
596 cpu_pd0: power-domain-cpu0 {
597 #power-domain-cells = <0>;
598 power-domains = <&cluster_pd>;
599 domain-idle-states = <&little_cpu_sleep_0>;
602 cpu_pd1: power-domain-cpu1 {
603 #power-domain-cells = <0>;
604 power-domains = <&cluster_pd>;
605 domain-idle-states = <&little_cpu_sleep_0>;
608 cpu_pd2: power-domain-cpu2 {
609 #power-domain-cells = <0>;
610 power-domains = <&cluster_pd>;
611 domain-idle-states = <&little_cpu_sleep_0>;
614 cpu_pd3: power-domain-cpu3 {
615 #power-domain-cells = <0>;
616 power-domains = <&cluster_pd>;
617 domain-idle-states = <&little_cpu_sleep_0>;
620 cpu_pd4: power-domain-cpu4 {
621 #power-domain-cells = <0>;
622 power-domains = <&cluster_pd>;
623 domain-idle-states = <&big_cpu_sleep_0>;
626 cpu_pd5: power-domain-cpu5 {
627 #power-domain-cells = <0>;
628 power-domains = <&cluster_pd>;
629 domain-idle-states = <&big_cpu_sleep_0>;
632 cpu_pd6: power-domain-cpu6 {
633 #power-domain-cells = <0>;
634 power-domains = <&cluster_pd>;
635 domain-idle-states = <&big_cpu_sleep_0>;
638 cpu_pd7: power-domain-cpu7 {
639 #power-domain-cells = <0>;
640 power-domains = <&cluster_pd>;
641 domain-idle-states = <&big_cpu_sleep_0>;
644 cluster_pd: power-domain-cpu-cluster0 {
645 #power-domain-cells = <0>;
646 domain-idle-states = <&cluster_sleep_0>;
650 reserved-memory {
651 #address-cells = <2>;
652 #size-cells = <2>;
655 reserved-region@80000000 {
657 no-map;
660 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd-db";
663 no-map;
666 reserved-region@80880000 {
668 no-map;
671 smem_mem: smem-region@80900000 {
674 no-map;
678 reserved-region@80b00000 {
680 no-map;
683 reserved-region@83b00000 {
685 no-map;
688 reserved-region@85b00000 {
690 no-map;
693 pil_adsp_mem: adsp-region@86c00000 {
695 no-map;
698 pil_slpi_mem: slpi-region@88c00000 {
700 no-map;
703 pil_nsp0_mem: cdsp0-region@8a100000 {
705 no-map;
708 pil_nsp1_mem: cdsp1-region@8c600000 {
710 no-map;
713 reserved-region@aeb00000 {
715 no-map;
719 smp2p-adsp {
722 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
728 qcom,local-pid = <0>;
729 qcom,remote-pid = <2>;
731 smp2p_adsp_out: master-kernel {
732 qcom,entry-name = "master-kernel";
733 #qcom,smem-state-cells = <1>;
736 smp2p_adsp_in: slave-kernel {
737 qcom,entry-name = "slave-kernel";
738 interrupt-controller;
739 #interrupt-cells = <2>;
743 smp2p-nsp0 {
746 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
752 qcom,local-pid = <0>;
753 qcom,remote-pid = <5>;
755 smp2p_nsp0_out: master-kernel {
756 qcom,entry-name = "master-kernel";
757 #qcom,smem-state-cells = <1>;
760 smp2p_nsp0_in: slave-kernel {
761 qcom,entry-name = "slave-kernel";
762 interrupt-controller;
763 #interrupt-cells = <2>;
767 smp2p-nsp1 {
770 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
776 qcom,local-pid = <0>;
777 qcom,remote-pid = <12>;
779 smp2p_nsp1_out: master-kernel {
780 qcom,entry-name = "master-kernel";
781 #qcom,smem-state-cells = <1>;
784 smp2p_nsp1_in: slave-kernel {
785 qcom,entry-name = "slave-kernel";
786 interrupt-controller;
787 #interrupt-cells = <2>;
791 smp2p-slpi {
794 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
800 qcom,local-pid = <0>;
801 qcom,remote-pid = <3>;
803 smp2p_slpi_out: master-kernel {
804 qcom,entry-name = "master-kernel";
805 #qcom,smem-state-cells = <1>;
808 smp2p_slpi_in: slave-kernel {
809 qcom,entry-name = "slave-kernel";
810 interrupt-controller;
811 #interrupt-cells = <2>;
816 compatible = "simple-bus";
817 #address-cells = <2>;
818 #size-cells = <2>;
820 dma-ranges = <0 0 0 0 0x10 0>;
823 compatible = "qcom,sc8280xp-ethqos";
826 reg-names = "stmmaceth", "rgmii";
832 clock-names = "stmmaceth",
839 interrupt-names = "macirq", "eth_lpi";
842 power-domains = <&gcc EMAC_0_GDSC>;
846 rx-fifo-depth = <4096>;
847 tx-fifo-depth = <4096>;
852 gcc: clock-controller@100000 {
853 compatible = "qcom,gcc-sc8280xp";
855 #clock-cells = <1>;
856 #reset-cells = <1>;
857 #power-domain-cells = <1>;
891 power-domains = <&rpmhpd SC8280XP_CX>;
895 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
898 interrupt-controller;
899 #interrupt-cells = <3>;
900 #mbox-cells = <2>;
904 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom";
906 #address-cells = <1>;
907 #size-cells = <1>;
909 gpu_speed_bin: gpu-speed-bin@18b {
916 compatible = "qcom,geni-se-qup";
920 clock-names = "m-ahb", "s-ahb";
923 #address-cells = <2>;
924 #size-cells = <2>;
930 compatible = "qcom,geni-i2c";
932 #address-cells = <1>;
933 #size-cells = <0>;
935 clock-names = "se";
937 power-domains = <&rpmhpd SC8280XP_CX>;
941 interconnect-names = "qup-core", "qup-config", "qup-memory";
946 compatible = "qcom,geni-spi";
948 #address-cells = <1>;
949 #size-cells = <0>;
951 clock-names = "se";
953 power-domains = <&rpmhpd SC8280XP_CX>;
957 interconnect-names = "qup-core", "qup-config", "qup-memory";
962 compatible = "qcom,geni-i2c";
964 #address-cells = <1>;
965 #size-cells = <0>;
967 clock-names = "se";
969 power-domains = <&rpmhpd SC8280XP_CX>;
973 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 compatible = "qcom,geni-spi";
980 #address-cells = <1>;
981 #size-cells = <0>;
983 clock-names = "se";
985 power-domains = <&rpmhpd SC8280XP_CX>;
989 interconnect-names = "qup-core", "qup-config", "qup-memory";
994 compatible = "qcom,geni-uart";
997 clock-names = "se";
999 operating-points-v2 = <&qup_opp_table_100mhz>;
1000 power-domains = <&rpmhpd SC8280XP_CX>;
1003 interconnect-names = "qup-core", "qup-config";
1008 compatible = "qcom,geni-i2c";
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1013 clock-names = "se";
1015 power-domains = <&rpmhpd SC8280XP_CX>;
1019 interconnect-names = "qup-core", "qup-config", "qup-memory";
1024 compatible = "qcom,geni-spi";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1029 clock-names = "se";
1031 power-domains = <&rpmhpd SC8280XP_CX>;
1035 interconnect-names = "qup-core", "qup-config", "qup-memory";
1040 compatible = "qcom,geni-uart";
1043 clock-names = "se";
1045 operating-points-v2 = <&qup_opp_table_100mhz>;
1046 power-domains = <&rpmhpd SC8280XP_CX>;
1049 interconnect-names = "qup-core", "qup-config";
1051 pinctrl-0 = <&qup_uart18_default>;
1052 pinctrl-names = "default";
1058 compatible = "qcom,geni-i2c";
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1063 clock-names = "se";
1065 power-domains = <&rpmhpd SC8280XP_CX>;
1069 interconnect-names = "qup-core", "qup-config", "qup-memory";
1074 compatible = "qcom,geni-spi";
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1079 clock-names = "se";
1081 power-domains = <&rpmhpd SC8280XP_CX>;
1085 interconnect-names = "qup-core", "qup-config", "qup-memory";
1090 compatible = "qcom,geni-i2c";
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1095 clock-names = "se";
1097 power-domains = <&rpmhpd SC8280XP_CX>;
1101 interconnect-names = "qup-core", "qup-config", "qup-memory";
1106 compatible = "qcom,geni-spi";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1111 clock-names = "se";
1113 power-domains = <&rpmhpd SC8280XP_CX>;
1117 interconnect-names = "qup-core", "qup-config", "qup-memory";
1122 compatible = "qcom,geni-i2c";
1124 clock-names = "se";
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129 power-domains = <&rpmhpd SC8280XP_CX>;
1133 interconnect-names = "qup-core", "qup-config", "qup-memory";
1138 compatible = "qcom,geni-spi";
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1143 clock-names = "se";
1145 power-domains = <&rpmhpd SC8280XP_CX>;
1149 interconnect-names = "qup-core", "qup-config", "qup-memory";
1154 compatible = "qcom,geni-i2c";
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1158 clock-names = "se";
1161 power-domains = <&rpmhpd SC8280XP_CX>;
1165 interconnect-names = "qup-core", "qup-config", "qup-memory";
1170 compatible = "qcom,geni-spi";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1175 clock-names = "se";
1177 power-domains = <&rpmhpd SC8280XP_CX>;
1181 interconnect-names = "qup-core", "qup-config", "qup-memory";
1186 compatible = "qcom,geni-i2c";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1190 clock-names = "se";
1193 power-domains = <&rpmhpd SC8280XP_CX>;
1197 interconnect-names = "qup-core", "qup-config", "qup-memory";
1202 compatible = "qcom,geni-spi";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1207 clock-names = "se";
1209 power-domains = <&rpmhpd SC8280XP_CX>;
1213 interconnect-names = "qup-core", "qup-config", "qup-memory";
1219 compatible = "qcom,geni-se-qup";
1223 clock-names = "m-ahb", "s-ahb";
1226 #address-cells = <2>;
1227 #size-cells = <2>;
1233 compatible = "qcom,geni-i2c";
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1237 clock-names = "se";
1240 power-domains = <&rpmhpd SC8280XP_CX>;
1244 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 compatible = "qcom,geni-spi";
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1254 clock-names = "se";
1256 power-domains = <&rpmhpd SC8280XP_CX>;
1260 interconnect-names = "qup-core", "qup-config", "qup-memory";
1265 compatible = "qcom,geni-i2c";
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1269 clock-names = "se";
1272 power-domains = <&rpmhpd SC8280XP_CX>;
1276 interconnect-names = "qup-core", "qup-config", "qup-memory";
1281 compatible = "qcom,geni-spi";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1286 clock-names = "se";
1288 power-domains = <&rpmhpd SC8280XP_CX>;
1292 interconnect-names = "qup-core", "qup-config", "qup-memory";
1297 compatible = "qcom,geni-i2c";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1301 clock-names = "se";
1304 power-domains = <&rpmhpd SC8280XP_CX>;
1308 interconnect-names = "qup-core", "qup-config", "qup-memory";
1313 compatible = "qcom,geni-spi";
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1318 clock-names = "se";
1320 power-domains = <&rpmhpd SC8280XP_CX>;
1324 interconnect-names = "qup-core", "qup-config", "qup-memory";
1329 compatible = "qcom,geni-uart";
1332 clock-names = "se";
1334 operating-points-v2 = <&qup_opp_table_100mhz>;
1335 power-domains = <&rpmhpd SC8280XP_CX>;
1338 interconnect-names = "qup-core", "qup-config";
1343 compatible = "qcom,geni-i2c";
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1347 clock-names = "se";
1350 power-domains = <&rpmhpd SC8280XP_CX>;
1354 interconnect-names = "qup-core", "qup-config", "qup-memory";
1359 compatible = "qcom,geni-spi";
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1364 clock-names = "se";
1366 power-domains = <&rpmhpd SC8280XP_CX>;
1370 interconnect-names = "qup-core", "qup-config", "qup-memory";
1375 compatible = "qcom,geni-i2c";
1377 clock-names = "se";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1382 power-domains = <&rpmhpd SC8280XP_CX>;
1386 interconnect-names = "qup-core", "qup-config", "qup-memory";
1391 compatible = "qcom,geni-spi";
1393 #address-cells = <1>;
1394 #size-cells = <0>;
1396 clock-names = "se";
1398 power-domains = <&rpmhpd SC8280XP_CX>;
1402 interconnect-names = "qup-core", "qup-config", "qup-memory";
1407 compatible = "qcom,geni-i2c";
1409 #address-cells = <1>;
1410 #size-cells = <0>;
1411 clock-names = "se";
1414 power-domains = <&rpmhpd SC8280XP_CX>;
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1423 compatible = "qcom,geni-spi";
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1428 clock-names = "se";
1430 power-domains = <&rpmhpd SC8280XP_CX>;
1434 interconnect-names = "qup-core", "qup-config", "qup-memory";
1439 compatible = "qcom,geni-i2c";
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1443 clock-names = "se";
1446 power-domains = <&rpmhpd SC8280XP_CX>;
1450 interconnect-names = "qup-core", "qup-config", "qup-memory";
1455 compatible = "qcom,geni-spi";
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1460 clock-names = "se";
1462 power-domains = <&rpmhpd SC8280XP_CX>;
1466 interconnect-names = "qup-core", "qup-config", "qup-memory";
1471 compatible = "qcom,geni-i2c";
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1475 clock-names = "se";
1478 power-domains = <&rpmhpd SC8280XP_CX>;
1482 interconnect-names = "qup-core", "qup-config", "qup-memory";
1487 compatible = "qcom,geni-spi";
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1492 clock-names = "se";
1494 power-domains = <&rpmhpd SC8280XP_CX>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1504 compatible = "qcom,geni-se-qup";
1508 clock-names = "m-ahb", "s-ahb";
1511 #address-cells = <2>;
1512 #size-cells = <2>;
1518 compatible = "qcom,geni-i2c";
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1523 clock-names = "se";
1525 power-domains = <&rpmhpd SC8280XP_CX>;
1529 interconnect-names = "qup-core", "qup-config", "qup-memory";
1534 compatible = "qcom,geni-spi";
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1539 clock-names = "se";
1541 power-domains = <&rpmhpd SC8280XP_CX>;
1545 interconnect-names = "qup-core", "qup-config", "qup-memory";
1550 compatible = "qcom,geni-i2c";
1552 #address-cells = <1>;
1553 #size-cells = <0>;
1555 clock-names = "se";
1557 power-domains = <&rpmhpd SC8280XP_CX>;
1561 interconnect-names = "qup-core", "qup-config", "qup-memory";
1566 compatible = "qcom,geni-spi";
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1571 clock-names = "se";
1573 power-domains = <&rpmhpd SC8280XP_CX>;
1577 interconnect-names = "qup-core", "qup-config", "qup-memory";
1582 compatible = "qcom,geni-i2c";
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1587 clock-names = "se";
1589 power-domains = <&rpmhpd SC8280XP_CX>;
1593 interconnect-names = "qup-core", "qup-config", "qup-memory";
1598 compatible = "qcom,geni-spi";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1603 clock-names = "se";
1605 power-domains = <&rpmhpd SC8280XP_CX>;
1609 interconnect-names = "qup-core", "qup-config", "qup-memory";
1614 compatible = "qcom,geni-i2c";
1616 #address-cells = <1>;
1617 #size-cells = <0>;
1619 clock-names = "se";
1621 power-domains = <&rpmhpd SC8280XP_CX>;
1625 interconnect-names = "qup-core", "qup-config", "qup-memory";
1630 compatible = "qcom,geni-spi";
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1635 clock-names = "se";
1637 power-domains = <&rpmhpd SC8280XP_CX>;
1641 interconnect-names = "qup-core", "qup-config", "qup-memory";
1646 compatible = "qcom,geni-i2c";
1648 #address-cells = <1>;
1649 #size-cells = <0>;
1651 clock-names = "se";
1653 power-domains = <&rpmhpd SC8280XP_CX>;
1657 interconnect-names = "qup-core", "qup-config", "qup-memory";
1662 compatible = "qcom,geni-spi";
1664 #address-cells = <1>;
1665 #size-cells = <0>;
1667 clock-names = "se";
1669 power-domains = <&rpmhpd SC8280XP_CX>;
1673 interconnect-names = "qup-core", "qup-config", "qup-memory";
1678 compatible = "qcom,geni-i2c";
1680 #address-cells = <1>;
1681 #size-cells = <0>;
1683 clock-names = "se";
1685 power-domains = <&rpmhpd SC8280XP_CX>;
1689 interconnect-names = "qup-core", "qup-config", "qup-memory";
1694 compatible = "qcom,geni-spi";
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1699 clock-names = "se";
1701 power-domains = <&rpmhpd SC8280XP_CX>;
1705 interconnect-names = "qup-core", "qup-config", "qup-memory";
1710 compatible = "qcom,geni-i2c";
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1715 clock-names = "se";
1717 power-domains = <&rpmhpd SC8280XP_CX>;
1721 interconnect-names = "qup-core", "qup-config", "qup-memory";
1726 compatible = "qcom,geni-spi";
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1731 clock-names = "se";
1733 power-domains = <&rpmhpd SC8280XP_CX>;
1737 interconnect-names = "qup-core", "qup-config", "qup-memory";
1742 compatible = "qcom,geni-i2c";
1744 #address-cells = <1>;
1745 #size-cells = <0>;
1747 clock-names = "se";
1749 power-domains = <&rpmhpd SC8280XP_CX>;
1753 interconnect-names = "qup-core", "qup-config", "qup-memory";
1758 compatible = "qcom,geni-spi";
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1763 clock-names = "se";
1765 power-domains = <&rpmhpd SC8280XP_CX>;
1769 interconnect-names = "qup-core", "qup-config", "qup-memory";
1775 compatible = "qcom,prng-ee";
1778 clock-names = "core";
1783 compatible = "qcom,pcie-sc8280xp";
1790 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1791 #address-cells = <3>;
1792 #size-cells = <2>;
1795 bus-range = <0x00 0xff>;
1797 dma-coherent;
1799 linux,pci-domain = <6>;
1800 num-lanes = <1>;
1802 msi-map = <0x0 &its 0xe0000 0x10000>;
1808 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1810 #interrupt-cells = <1>;
1811 interrupt-map-mask = <0 0 0 0x7>;
1812 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1826 clock-names = "aux",
1836 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1837 assigned-clock-rates = <19200000>;
1841 interconnect-names = "pcie-mem", "cpu-pcie";
1844 reset-names = "pci";
1846 power-domains = <&gcc PCIE_4_GDSC>;
1847 required-opps = <&rpmhpd_opp_nom>;
1850 phy-names = "pciephy";
1857 bus-range = <0x01 0xff>;
1859 #address-cells = <3>;
1860 #size-cells = <2>;
1866 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1875 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1878 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1879 assigned-clock-rates = <100000000>;
1881 power-domains = <&gcc PCIE_4_GDSC>;
1884 reset-names = "phy";
1886 #clock-cells = <0>;
1887 clock-output-names = "pcie_4_pipe_clk";
1889 #phy-cells = <0>;
1896 compatible = "qcom,pcie-sc8280xp";
1903 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1904 #address-cells = <3>;
1905 #size-cells = <2>;
1908 bus-range = <0x00 0xff>;
1910 dma-coherent;
1912 linux,pci-domain = <5>;
1913 num-lanes = <2>;
1915 msi-map = <0x0 &its 0xd0000 0x10000>;
1921 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1923 #interrupt-cells = <1>;
1924 interrupt-map-mask = <0 0 0 0x7>;
1925 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1938 clock-names = "aux",
1947 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1948 assigned-clock-rates = <19200000>;
1952 interconnect-names = "pcie-mem", "cpu-pcie";
1955 reset-names = "pci";
1957 power-domains = <&gcc PCIE_3B_GDSC>;
1958 required-opps = <&rpmhpd_opp_nom>;
1961 phy-names = "pciephy";
1968 bus-range = <0x01 0xff>;
1970 #address-cells = <3>;
1971 #size-cells = <2>;
1977 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1986 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1989 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1990 assigned-clock-rates = <100000000>;
1992 power-domains = <&gcc PCIE_3B_GDSC>;
1995 reset-names = "phy";
1997 #clock-cells = <0>;
1998 clock-output-names = "pcie_3b_pipe_clk";
2000 #phy-cells = <0>;
2007 compatible = "qcom,pcie-sc8280xp";
2014 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2015 #address-cells = <3>;
2016 #size-cells = <2>;
2019 bus-range = <0x00 0xff>;
2021 dma-coherent;
2023 linux,pci-domain = <4>;
2024 num-lanes = <4>;
2026 msi-map = <0x0 &its 0xc0000 0x10000>;
2032 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2034 #interrupt-cells = <1>;
2035 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
2049 clock-names = "aux",
2058 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2059 assigned-clock-rates = <19200000>;
2063 interconnect-names = "pcie-mem", "cpu-pcie";
2066 reset-names = "pci";
2068 power-domains = <&gcc PCIE_3A_GDSC>;
2069 required-opps = <&rpmhpd_opp_nom>;
2072 phy-names = "pciephy";
2079 bus-range = <0x01 0xff>;
2081 #address-cells = <3>;
2082 #size-cells = <2>;
2088 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2098 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2101 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2102 assigned-clock-rates = <100000000>;
2104 power-domains = <&gcc PCIE_3A_GDSC>;
2107 reset-names = "phy";
2109 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2111 #clock-cells = <0>;
2112 clock-output-names = "pcie_3a_pipe_clk";
2114 #phy-cells = <0>;
2121 compatible = "qcom,pcie-sc8280xp";
2128 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2129 #address-cells = <3>;
2130 #size-cells = <2>;
2133 bus-range = <0x00 0xff>;
2135 dma-coherent;
2137 linux,pci-domain = <3>;
2138 num-lanes = <2>;
2140 msi-map = <0x0 &its 0xb0000 0x10000>;
2146 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2148 #interrupt-cells = <1>;
2149 interrupt-map-mask = <0 0 0 0x7>;
2150 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2163 clock-names = "aux",
2172 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2173 assigned-clock-rates = <19200000>;
2177 interconnect-names = "pcie-mem", "cpu-pcie";
2180 reset-names = "pci";
2182 power-domains = <&gcc PCIE_2B_GDSC>;
2183 required-opps = <&rpmhpd_opp_nom>;
2186 phy-names = "pciephy";
2193 bus-range = <0x01 0xff>;
2195 #address-cells = <3>;
2196 #size-cells = <2>;
2202 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2211 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2214 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2215 assigned-clock-rates = <100000000>;
2217 power-domains = <&gcc PCIE_2B_GDSC>;
2220 reset-names = "phy";
2222 #clock-cells = <0>;
2223 clock-output-names = "pcie_2b_pipe_clk";
2225 #phy-cells = <0>;
2232 compatible = "qcom,pcie-sc8280xp";
2239 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2240 #address-cells = <3>;
2241 #size-cells = <2>;
2244 bus-range = <0x00 0xff>;
2246 dma-coherent;
2248 linux,pci-domain = <2>;
2249 num-lanes = <4>;
2251 msi-map = <0x0 &its 0xa0000 0x10000>;
2257 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2259 #interrupt-cells = <1>;
2260 interrupt-map-mask = <0 0 0 0x7>;
2261 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2274 clock-names = "aux",
2283 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2284 assigned-clock-rates = <19200000>;
2288 interconnect-names = "pcie-mem", "cpu-pcie";
2291 reset-names = "pci";
2293 power-domains = <&gcc PCIE_2A_GDSC>;
2294 required-opps = <&rpmhpd_opp_nom>;
2297 phy-names = "pciephy";
2304 bus-range = <0x01 0xff>;
2306 #address-cells = <3>;
2307 #size-cells = <2>;
2313 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2323 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2326 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2327 assigned-clock-rates = <100000000>;
2329 power-domains = <&gcc PCIE_2A_GDSC>;
2332 reset-names = "phy";
2334 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2336 #clock-cells = <0>;
2337 clock-output-names = "pcie_2a_pipe_clk";
2339 #phy-cells = <0>;
2345 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2346 "jedec,ufs-2.0";
2350 phy-names = "ufsphy";
2351 lanes-per-direction = <2>;
2352 #reset-cells = <1>;
2354 reset-names = "rst";
2356 power-domains = <&gcc UFS_PHY_GDSC>;
2357 required-opps = <&rpmhpd_opp_nom>;
2360 dma-coherent;
2370 clock-names = "core_clk",
2378 freq-table-hz = <75000000 300000000>,
2390 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2396 clock-names = "ref",
2400 power-domains = <&gcc UFS_PHY_GDSC>;
2403 reset-names = "ufsphy";
2405 #phy-cells = <0>;
2411 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2412 "jedec,ufs-2.0";
2416 phy-names = "ufsphy";
2417 lanes-per-direction = <2>;
2418 #reset-cells = <1>;
2420 reset-names = "rst";
2422 power-domains = <&gcc UFS_CARD_GDSC>;
2425 dma-coherent;
2435 clock-names = "core_clk",
2443 freq-table-hz = <75000000 300000000>,
2455 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2461 clock-names = "ref",
2465 power-domains = <&gcc UFS_CARD_GDSC>;
2468 reset-names = "ufsphy";
2470 #phy-cells = <0>;
2476 compatible = "qcom,tcsr-mutex";
2478 #hwlock-cells = <1>;
2482 compatible = "qcom,sc8280xp-tcsr", "syscon";
2487 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas";
2490 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2495 interrupt-names = "wdog",
2499 "stop-ack";
2502 clock-names = "xo";
2504 power-domains = <&rpmhpd SC8280XP_LCX>,
2506 power-domain-names = "lcx", "lmx";
2508 memory-region = <&pil_slpi_mem>;
2512 qcom,smem-states = <&smp2p_slpi_out 0>;
2513 qcom,smem-state-names = "stop";
2517 glink-edge {
2518 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2525 qcom,remote-pid = <3>;
2529 qcom,glink-channels = "fastrpcglink-apps-dsp";
2531 qcom,non-secure-domain;
2532 #address-cells = <1>;
2533 #size-cells = <0>;
2535 compute-cb@1 {
2536 compatible = "qcom,fastrpc-compute-cb";
2541 compute-cb@2 {
2542 compatible = "qcom,fastrpc-compute-cb";
2547 compute-cb@3 {
2548 compatible = "qcom,fastrpc-compute-cb";
2557 compatible = "qcom,sc8280xp-adsp-pas";
2560 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2566 interrupt-names = "wdog", "fatal", "ready",
2567 "handover", "stop-ack", "shutdown-ack";
2570 clock-names = "xo";
2572 power-domains = <&rpmhpd SC8280XP_LCX>,
2574 power-domain-names = "lcx", "lmx";
2576 memory-region = <&pil_adsp_mem>;
2580 qcom,smem-states = <&smp2p_adsp_out 0>;
2581 qcom,smem-state-names = "stop";
2585 remoteproc_adsp_glink: glink-edge {
2586 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2593 qcom,remote-pid = <2>;
2597 qcom,glink-channels = "adsp_apps";
2600 #address-cells = <1>;
2601 #size-cells = <0>;
2606 #sound-dai-cells = <0>;
2607 qcom,protection-domain = "avs/audio",
2610 compatible = "qcom,q6apm-dais";
2615 compatible = "qcom,q6apm-lpass-dais";
2616 #sound-dai-cells = <1>;
2623 qcom,protection-domain = "avs/audio",
2625 q6prmcc: clock-controller {
2626 compatible = "qcom,q6prm-lpass-clocks";
2627 #clock-cells = <2>;
2635 compatible = "qcom,sc8280xp-lpass-rx-macro";
2642 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2643 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2645 assigned-clock-rates = <19200000>, <19200000>;
2647 clock-output-names = "mclk";
2648 #clock-cells = <0>;
2649 #sound-dai-cells = <1>;
2651 pinctrl-names = "default";
2652 pinctrl-0 = <&rx_swr_default>;
2658 compatible = "qcom,soundwire-v1.6.0";
2662 clock-names = "iface";
2664 reset-names = "swr_audio_cgcr";
2667 qcom,din-ports = <0>;
2668 qcom,dout-ports = <5>;
2670 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2671 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2672 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2673 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2674 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2675 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2676 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2677 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2678 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2680 #sound-dai-cells = <1>;
2681 #address-cells = <2>;
2682 #size-cells = <0>;
2688 compatible = "qcom,sc8280xp-lpass-tx-macro";
2690 pinctrl-names = "default";
2691 pinctrl-0 = <&tx_swr_default>;
2698 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2699 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2701 assigned-clock-rates = <19200000>, <19200000>;
2702 clock-output-names = "mclk";
2704 #clock-cells = <0>;
2705 #sound-dai-cells = <1>;
2711 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2718 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2719 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2721 assigned-clock-rates = <19200000>, <19200000>;
2723 #clock-cells = <0>;
2724 clock-output-names = "mclk";
2725 #sound-dai-cells = <1>;
2727 pinctrl-names = "default";
2728 pinctrl-0 = <&wsa_swr_default>;
2735 compatible = "qcom,soundwire-v1.6.0";
2738 clock-names = "iface";
2740 reset-names = "swr_audio_cgcr";
2743 qcom,din-ports = <2>;
2744 qcom,dout-ports = <6>;
2746 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2747 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2748 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2749 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2750 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2751 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2752 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2753 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2754 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2756 #sound-dai-cells = <1>;
2757 #address-cells = <2>;
2758 #size-cells = <0>;
2763 lpass_audiocc: clock-controller@32a9000 {
2764 compatible = "qcom,sc8280xp-lpassaudiocc";
2766 #clock-cells = <1>;
2767 #reset-cells = <1>;
2771 compatible = "qcom,soundwire-v1.6.0";
2775 interrupt-names = "core", "wakeup";
2778 clock-names = "iface";
2780 reset-names = "swr_audio_cgcr";
2782 #sound-dai-cells = <1>;
2783 #address-cells = <2>;
2784 #size-cells = <0>;
2786 qcom,din-ports = <4>;
2787 qcom,dout-ports = <0>;
2788 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2789 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2790 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2791 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2792 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2793 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2794 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2795 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2796 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2802 compatible = "qcom,sc8280xp-lpass-va-macro";
2808 clock-names = "mclk", "macro", "dcodec", "npl";
2809 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2810 assigned-clock-rates = <19200000>;
2812 #clock-cells = <0>;
2813 clock-output-names = "fsgen";
2814 #sound-dai-cells = <1>;
2820 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2823 gpio-controller;
2824 #gpio-cells = <2>;
2825 gpio-ranges = <&lpass_tlmm 0 0 19>;
2829 clock-names = "core", "audio";
2833 tx_swr_default: tx-swr-default-state {
2834 clk-pins {
2837 drive-strength = <2>;
2838 slew-rate = <1>;
2839 bias-disable;
2842 data-pins {
2845 drive-strength = <2>;
2846 slew-rate = <1>;
2847 bias-bus-hold;
2851 rx_swr_default: rx-swr-default-state {
2852 clk-pins {
2855 drive-strength = <2>;
2856 slew-rate = <1>;
2857 bias-disable;
2860 data-pins {
2863 drive-strength = <2>;
2864 slew-rate = <1>;
2865 bias-bus-hold;
2869 dmic01_default: dmic01-default-state {
2870 clk-pins {
2873 drive-strength = <8>;
2874 output-high;
2877 data-pins {
2880 drive-strength = <8>;
2881 input-enable;
2885 dmic01_sleep: dmic01-sleep-state {
2886 clk-pins {
2889 drive-strength = <2>;
2890 bias-disable;
2891 output-low;
2894 data-pins {
2897 drive-strength = <2>;
2898 bias-pull-down;
2899 input-enable;
2903 dmic23_default: dmic23-default-state {
2904 clk-pins {
2907 drive-strength = <8>;
2908 output-high;
2911 data-pins {
2914 drive-strength = <8>;
2915 input-enable;
2919 dmic23_sleep: dmic23-sleep-state {
2920 clk-pins {
2923 drive-strength = <2>;
2924 bias-disable;
2925 output-low;
2928 data-pins {
2931 drive-strength = <2>;
2932 bias-pull-down;
2933 input-enable;
2937 wsa_swr_default: wsa-swr-default-state {
2938 clk-pins {
2941 drive-strength = <2>;
2942 slew-rate = <1>;
2943 bias-disable;
2946 data-pins {
2949 drive-strength = <2>;
2950 slew-rate = <1>;
2951 bias-bus-hold;
2955 wsa2_swr_default: wsa2-swr-default-state {
2956 clk-pins {
2959 drive-strength = <2>;
2960 slew-rate = <1>;
2961 bias-disable;
2964 data-pins {
2967 drive-strength = <2>;
2968 slew-rate = <1>;
2969 bias-bus-hold;
2974 lpasscc: clock-controller@33e0000 {
2975 compatible = "qcom,sc8280xp-lpasscc";
2977 #clock-cells = <1>;
2978 #reset-cells = <1>;
2982 compatible = "qcom,adreno-690.0", "qcom,adreno";
2987 reg-names = "kgsl_3d0_reg_memory",
2992 operating-points-v2 = <&gpu_opp_table>;
2996 interconnect-names = "gfx-mem";
2997 #cooling-cells = <2>;
3001 gpu_opp_table: opp-table {
3002 compatible = "operating-points-v2";
3004 opp-270000000 {
3005 opp-hz = /bits/ 64 <270000000>;
3006 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3007 opp-peak-kBps = <451000>;
3010 opp-410000000 {
3011 opp-hz = /bits/ 64 <410000000>;
3012 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3013 opp-peak-kBps = <1555000>;
3016 opp-500000000 {
3017 opp-hz = /bits/ 64 <500000000>;
3018 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3019 opp-peak-kBps = <1555000>;
3022 opp-547000000 {
3023 opp-hz = /bits/ 64 <547000000>;
3024 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3025 opp-peak-kBps = <1555000>;
3028 opp-606000000 {
3029 opp-hz = /bits/ 64 <606000000>;
3030 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3031 opp-peak-kBps = <2736000>;
3034 opp-640000000 {
3035 opp-hz = /bits/ 64 <640000000>;
3036 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3037 opp-peak-kBps = <2736000>;
3040 opp-655000000 {
3041 opp-hz = /bits/ 64 <655000000>;
3042 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3043 opp-peak-kBps = <2736000>;
3046 opp-690000000 {
3047 opp-hz = /bits/ 64 <690000000>;
3048 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3049 opp-peak-kBps = <2736000>;
3055 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
3059 reg-names = "gmu", "rscc", "gmu_pdc";
3062 interrupt-names = "hfi", "gmu";
3070 clock-names = "gmu",
3077 power-domains = <&gpucc GPU_CC_CX_GDSC>,
3079 power-domain-names = "cx",
3082 operating-points-v2 = <&gmu_opp_table>;
3084 gmu_opp_table: opp-table {
3085 compatible = "operating-points-v2";
3087 opp-200000000 {
3088 opp-hz = /bits/ 64 <200000000>;
3089 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3092 opp-500000000 {
3093 opp-hz = /bits/ 64 <500000000>;
3094 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3099 gpucc: clock-controller@3d90000 {
3100 compatible = "qcom,sc8280xp-gpucc";
3105 clock-names = "bi_tcxo",
3109 power-domains = <&rpmhpd SC8280XP_GFX>;
3110 #clock-cells = <1>;
3111 #reset-cells = <1>;
3112 #power-domain-cells = <1>;
3116 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
3117 "qcom,smmu-500", "arm,mmu-500";
3119 #iommu-cells = <2>;
3120 #global-interrupts = <2>;
3143 clock-names = "gcc_gpu_memnoc_gfx_clk",
3151 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3152 dma-coherent;
3156 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3161 interrupt-names = "hc_irq", "pwr_irq";
3166 clock-names = "iface", "core", "xo";
3170 interconnect-names = "sdhc-ddr","cpu-sdhc";
3172 power-domains = <&rpmhpd SC8280XP_CX>;
3173 operating-points-v2 = <&sdc2_opp_table>;
3174 bus-width = <4>;
3175 dma-coherent;
3179 sdc2_opp_table: opp-table {
3180 compatible = "operating-points-v2";
3182 opp-100000000 {
3183 opp-hz = /bits/ 64 <100000000>;
3184 required-opps = <&rpmhpd_opp_low_svs>;
3185 opp-peak-kBps = <1800000 400000>;
3186 opp-avg-kBps = <100000 0>;
3189 opp-202000000 {
3190 opp-hz = /bits/ 64 <202000000>;
3191 required-opps = <&rpmhpd_opp_svs_l1>;
3192 opp-peak-kBps = <5400000 1600000>;
3193 opp-avg-kBps = <200000 0>;
3199 compatible = "qcom,sc8280xp-usb-hs-phy",
3200 "qcom,usb-snps-hs-5nm-phy";
3203 clock-names = "ref";
3206 #phy-cells = <0>;
3212 compatible = "qcom,sc8280xp-usb-hs-phy",
3213 "qcom,usb-snps-hs-5nm-phy";
3216 clock-names = "ref";
3219 #phy-cells = <0>;
3225 compatible = "qcom,sc8280xp-usb-hs-phy",
3226 "qcom,usb-snps-hs-5nm-phy";
3229 clock-names = "ref";
3232 #phy-cells = <0>;
3238 compatible = "qcom,sc8280xp-usb-hs-phy",
3239 "qcom,usb-snps-hs-5nm-phy";
3242 clock-names = "ref";
3245 #phy-cells = <0>;
3251 compatible = "qcom,sc8280xp-usb-hs-phy",
3252 "qcom,usb-snps-hs-5nm-phy";
3255 clock-names = "ref";
3258 #phy-cells = <0>;
3264 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3271 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3273 power-domains = <&gcc USB30_PRIM_GDSC>;
3277 reset-names = "phy", "common";
3279 #clock-cells = <1>;
3280 #phy-cells = <1>;
3285 #address-cells = <1>;
3286 #size-cells = <0>;
3298 remote-endpoint = <&usb_0_dwc3_ss>;
3311 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
3318 clock-names = "aux", "ref", "com_aux", "pipe";
3322 reset-names = "phy", "phy_phy";
3324 power-domains = <&gcc USB30_MP_GDSC>;
3326 #clock-cells = <0>;
3327 clock-output-names = "usb2_phy0_pipe_clk";
3329 #phy-cells = <0>;
3335 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
3342 clock-names = "aux", "ref", "com_aux", "pipe";
3346 reset-names = "phy", "phy_phy";
3348 power-domains = <&gcc USB30_MP_GDSC>;
3350 #clock-cells = <0>;
3351 clock-output-names = "usb2_phy1_pipe_clk";
3353 #phy-cells = <0>;
3359 compatible = "qcom,sc8280xp-usb-hs-phy",
3360 "qcom,usb-snps-hs-5nm-phy";
3362 #phy-cells = <0>;
3365 clock-names = "ref";
3373 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3380 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3382 power-domains = <&gcc USB30_SEC_GDSC>;
3386 reset-names = "phy", "common";
3388 #clock-cells = <1>;
3389 #phy-cells = <1>;
3394 #address-cells = <1>;
3395 #size-cells = <0>;
3407 remote-endpoint = <&usb_1_dwc3_ss>;
3420 compatible = "qcom,sc8280xp-dp-phy";
3428 clock-names = "aux", "cfg_ahb";
3429 power-domains = <&rpmhpd SC8280XP_MX>;
3431 #clock-cells = <1>;
3432 #phy-cells = <0>;
3438 compatible = "qcom,sc8280xp-dp-phy";
3446 clock-names = "aux", "cfg_ahb";
3447 power-domains = <&rpmhpd SC8280XP_MX>;
3449 #clock-cells = <1>;
3450 #phy-cells = <0>;
3456 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3463 operating-points-v2 = <&llcc_bwmon_opp_table>;
3465 llcc_bwmon_opp_table: opp-table {
3466 compatible = "operating-points-v2";
3468 opp-0 {
3469 opp-peak-kBps = <762000>;
3471 opp-1 {
3472 opp-peak-kBps = <1720000>;
3474 opp-2 {
3475 opp-peak-kBps = <2086000>;
3477 opp-3 {
3478 opp-peak-kBps = <2597000>;
3480 opp-4 {
3481 opp-peak-kBps = <2929000>;
3483 opp-5 {
3484 opp-peak-kBps = <3879000>;
3486 opp-6 {
3487 opp-peak-kBps = <5161000>;
3489 opp-7 {
3490 opp-peak-kBps = <5931000>;
3492 opp-8 {
3493 opp-peak-kBps = <6515000>;
3495 opp-9 {
3496 opp-peak-kBps = <7980000>;
3498 opp-10 {
3499 opp-peak-kBps = <8136000>;
3501 opp-11 {
3502 opp-peak-kBps = <10437000>;
3504 opp-12 {
3505 opp-peak-kBps = <12191000>;
3511 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3517 operating-points-v2 = <&cpu_bwmon_opp_table>;
3519 cpu_bwmon_opp_table: opp-table {
3520 compatible = "operating-points-v2";
3522 opp-0 {
3523 opp-peak-kBps = <2288000>;
3525 opp-1 {
3526 opp-peak-kBps = <4577000>;
3528 opp-2 {
3529 opp-peak-kBps = <7110000>;
3531 opp-3 {
3532 opp-peak-kBps = <9155000>;
3534 opp-4 {
3535 opp-peak-kBps = <12298000>;
3537 opp-5 {
3538 opp-peak-kBps = <14236000>;
3540 opp-6 {
3541 opp-peak-kBps = <15258001>;
3546 system-cache-controller@9200000 {
3547 compatible = "qcom,sc8280xp-llcc";
3553 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3560 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
3562 #address-cells = <2>;
3563 #size-cells = <2>;
3575 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3578 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3580 assigned-clock-rates = <19200000>, <200000000>;
3582 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3601 interrupt-names = "pwr_event_1", "pwr_event_2",
3611 power-domains = <&gcc USB30_MP_GDSC>;
3612 required-opps = <&rpmhpd_opp_nom>;
3618 interconnect-names = "usb-ddr", "apps-usb";
3620 wakeup-source;
3633 phy-names = "usb2-0", "usb3-0",
3634 "usb2-1", "usb3-1",
3635 "usb2-2",
3636 "usb2-3";
3638 snps,dis-u1-entry-quirk;
3639 snps,dis-u2-entry-quirk;
3644 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3646 #address-cells = <2>;
3647 #size-cells = <2>;
3659 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3662 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3664 assigned-clock-rates = <19200000>, <200000000>;
3666 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3671 interrupt-names = "pwr_event",
3677 power-domains = <&gcc USB30_PRIM_GDSC>;
3678 required-opps = <&rpmhpd_opp_nom>;
3684 interconnect-names = "usb-ddr", "apps-usb";
3686 wakeup-source;
3696 phy-names = "usb2-phy", "usb3-phy";
3697 snps,dis-u1-entry-quirk;
3698 snps,dis-u2-entry-quirk;
3701 #address-cells = <1>;
3702 #size-cells = <0>;
3715 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
3723 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3725 #address-cells = <2>;
3726 #size-cells = <2>;
3738 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3741 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3743 assigned-clock-rates = <19200000>, <200000000>;
3745 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3750 interrupt-names = "pwr_event",
3756 power-domains = <&gcc USB30_SEC_GDSC>;
3757 required-opps = <&rpmhpd_opp_nom>;
3763 interconnect-names = "usb-ddr", "apps-usb";
3765 wakeup-source;
3775 phy-names = "usb2-phy", "usb3-phy";
3776 snps,dis-u1-entry-quirk;
3777 snps,dis-u2-entry-quirk;
3780 #address-cells = <1>;
3781 #size-cells = <0>;
3794 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3802 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3811 clock-names = "camnoc_axi",
3816 power-domains = <&camcc TITAN_TOP_GDSC>;
3818 pinctrl-0 = <&cci0_default>;
3819 pinctrl-1 = <&cci0_sleep>;
3820 pinctrl-names = "default", "sleep";
3822 #address-cells = <1>;
3823 #size-cells = <0>;
3827 cci0_i2c0: i2c-bus@0 {
3829 clock-frequency = <1000000>;
3830 #address-cells = <1>;
3831 #size-cells = <0>;
3834 cci0_i2c1: i2c-bus@1 {
3836 clock-frequency = <1000000>;
3837 #address-cells = <1>;
3838 #size-cells = <0>;
3843 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3852 clock-names = "camnoc_axi",
3857 power-domains = <&camcc TITAN_TOP_GDSC>;
3859 pinctrl-0 = <&cci1_default>;
3860 pinctrl-1 = <&cci1_sleep>;
3861 pinctrl-names = "default", "sleep";
3863 #address-cells = <1>;
3864 #size-cells = <0>;
3868 cci1_i2c0: i2c-bus@0 {
3870 clock-frequency = <1000000>;
3871 #address-cells = <1>;
3872 #size-cells = <0>;
3875 cci1_i2c1: i2c-bus@1 {
3877 clock-frequency = <1000000>;
3878 #address-cells = <1>;
3879 #size-cells = <0>;
3884 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3893 clock-names = "camnoc_axi",
3897 power-domains = <&camcc TITAN_TOP_GDSC>;
3899 pinctrl-0 = <&cci2_default>;
3900 pinctrl-1 = <&cci2_sleep>;
3901 pinctrl-names = "default", "sleep";
3903 #address-cells = <1>;
3904 #size-cells = <0>;
3908 cci2_i2c0: i2c-bus@0 {
3910 clock-frequency = <1000000>;
3911 #address-cells = <1>;
3912 #size-cells = <0>;
3915 cci2_i2c1: i2c-bus@1 {
3917 clock-frequency = <1000000>;
3918 #address-cells = <1>;
3919 #size-cells = <0>;
3924 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3933 clock-names = "camnoc_axi",
3938 power-domains = <&camcc TITAN_TOP_GDSC>;
3940 pinctrl-0 = <&cci3_default>;
3941 pinctrl-1 = <&cci3_sleep>;
3942 pinctrl-names = "default", "sleep";
3944 #address-cells = <1>;
3945 #size-cells = <0>;
3949 cci3_i2c0: i2c-bus@0 {
3951 clock-frequency = <1000000>;
3952 #address-cells = <1>;
3953 #size-cells = <0>;
3956 cci3_i2c1: i2c-bus@1 {
3958 clock-frequency = <1000000>;
3959 #address-cells = <1>;
3960 #size-cells = <0>;
3965 compatible = "qcom,sc8280xp-camss";
3987 reg-names = "csiphy2",
4028 interrupt-names = "csid1_lite",
4049 power-domains = <&camcc IFE_0_GDSC>,
4054 power-domain-names = "ife0",
4100 clock-names = "camnoc_axi",
4162 interconnect-names = "cam_ahb",
4170 #address-cells = <1>;
4171 #size-cells = <0>;
4175 #address-cells = <1>;
4176 #size-cells = <0>;
4181 #address-cells = <1>;
4182 #size-cells = <0>;
4187 #address-cells = <1>;
4188 #size-cells = <0>;
4193 #address-cells = <1>;
4194 #size-cells = <0>;
4199 camcc: clock-controller@ad00000 {
4200 compatible = "qcom,sc8280xp-camcc";
4206 power-domains = <&rpmhpd SC8280XP_MMCX>;
4207 required-opps = <&rpmhpd_opp_low_svs>;
4208 #clock-cells = <1>;
4209 #reset-cells = <1>;
4210 #power-domain-cells = <1>;
4213 mdss0: display-subsystem@ae00000 {
4214 compatible = "qcom,sc8280xp-mdss";
4216 reg-names = "mdss";
4221 clock-names = "iface",
4227 interconnect-names = "mdp0-mem", "mdp1-mem";
4229 power-domains = <&dispcc0 MDSS_GDSC>;
4232 interrupt-controller;
4233 #interrupt-cells = <1>;
4234 #address-cells = <2>;
4235 #size-cells = <2>;
4240 mdss0_mdp: display-controller@ae01000 {
4241 compatible = "qcom,sc8280xp-dpu";
4244 reg-names = "mdp", "vbif";
4252 clock-names = "bus",
4258 interrupt-parent = <&mdss0>;
4260 power-domains = <&rpmhpd SC8280XP_MMCX>;
4262 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4263 assigned-clock-rates = <19200000>;
4264 operating-points-v2 = <&mdss0_mdp_opp_table>;
4267 #address-cells = <1>;
4268 #size-cells = <0>;
4273 remote-endpoint = <&mdss0_dp0_in>;
4280 remote-endpoint = <&mdss0_dp1_in>;
4287 remote-endpoint = <&mdss0_dp3_in>;
4294 remote-endpoint = <&mdss0_dp2_in>;
4299 mdss0_mdp_opp_table: opp-table {
4300 compatible = "operating-points-v2";
4302 opp-200000000 {
4303 opp-hz = /bits/ 64 <200000000>;
4304 required-opps = <&rpmhpd_opp_low_svs>;
4307 opp-300000000 {
4308 opp-hz = /bits/ 64 <300000000>;
4309 required-opps = <&rpmhpd_opp_svs>;
4312 opp-375000000 {
4313 opp-hz = /bits/ 64 <375000000>;
4314 required-opps = <&rpmhpd_opp_svs_l1>;
4317 opp-500000000 {
4318 opp-hz = /bits/ 64 <500000000>;
4319 required-opps = <&rpmhpd_opp_nom>;
4321 opp-600000000 {
4322 opp-hz = /bits/ 64 <600000000>;
4323 required-opps = <&rpmhpd_opp_turbo_l1>;
4328 mdss0_dp0: displayport-controller@ae90000 {
4329 compatible = "qcom,sc8280xp-dp";
4335 interrupt-parent = <&mdss0>;
4342 clock-names = "core_iface", "core_aux",
4347 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4349 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4353 phy-names = "dp";
4355 #sound-dai-cells = <0>;
4357 operating-points-v2 = <&mdss0_dp0_opp_table>;
4358 power-domains = <&rpmhpd SC8280XP_MMCX>;
4363 #address-cells = <1>;
4364 #size-cells = <0>;
4370 remote-endpoint = <&mdss0_intf0_out>;
4382 mdss0_dp0_opp_table: opp-table {
4383 compatible = "operating-points-v2";
4385 opp-160000000 {
4386 opp-hz = /bits/ 64 <160000000>;
4387 required-opps = <&rpmhpd_opp_low_svs>;
4390 opp-270000000 {
4391 opp-hz = /bits/ 64 <270000000>;
4392 required-opps = <&rpmhpd_opp_svs>;
4395 opp-540000000 {
4396 opp-hz = /bits/ 64 <540000000>;
4397 required-opps = <&rpmhpd_opp_svs_l1>;
4400 opp-810000000 {
4401 opp-hz = /bits/ 64 <810000000>;
4402 required-opps = <&rpmhpd_opp_nom>;
4407 mdss0_dp1: displayport-controller@ae98000 {
4408 compatible = "qcom,sc8280xp-dp";
4414 interrupt-parent = <&mdss0>;
4421 clock-names = "core_iface", "core_aux",
4425 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4427 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4431 phy-names = "dp";
4433 #sound-dai-cells = <0>;
4435 operating-points-v2 = <&mdss0_dp1_opp_table>;
4436 power-domains = <&rpmhpd SC8280XP_MMCX>;
4441 #address-cells = <1>;
4442 #size-cells = <0>;
4448 remote-endpoint = <&mdss0_intf4_out>;
4460 mdss0_dp1_opp_table: opp-table {
4461 compatible = "operating-points-v2";
4463 opp-160000000 {
4464 opp-hz = /bits/ 64 <160000000>;
4465 required-opps = <&rpmhpd_opp_low_svs>;
4468 opp-270000000 {
4469 opp-hz = /bits/ 64 <270000000>;
4470 required-opps = <&rpmhpd_opp_svs>;
4473 opp-540000000 {
4474 opp-hz = /bits/ 64 <540000000>;
4475 required-opps = <&rpmhpd_opp_svs_l1>;
4478 opp-810000000 {
4479 opp-hz = /bits/ 64 <810000000>;
4480 required-opps = <&rpmhpd_opp_nom>;
4485 mdss0_dp2: displayport-controller@ae9a000 {
4486 compatible = "qcom,sc8280xp-dp";
4498 clock-names = "core_iface", "core_aux",
4501 interrupt-parent = <&mdss0>;
4504 phy-names = "dp";
4505 power-domains = <&rpmhpd SC8280XP_MMCX>;
4507 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4509 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4510 operating-points-v2 = <&mdss0_dp2_opp_table>;
4512 #sound-dai-cells = <0>;
4517 #address-cells = <1>;
4518 #size-cells = <0>;
4523 remote-endpoint = <&mdss0_intf6_out>;
4532 mdss0_dp2_opp_table: opp-table {
4533 compatible = "operating-points-v2";
4535 opp-160000000 {
4536 opp-hz = /bits/ 64 <160000000>;
4537 required-opps = <&rpmhpd_opp_low_svs>;
4540 opp-270000000 {
4541 opp-hz = /bits/ 64 <270000000>;
4542 required-opps = <&rpmhpd_opp_svs>;
4545 opp-540000000 {
4546 opp-hz = /bits/ 64 <540000000>;
4547 required-opps = <&rpmhpd_opp_svs_l1>;
4550 opp-810000000 {
4551 opp-hz = /bits/ 64 <810000000>;
4552 required-opps = <&rpmhpd_opp_nom>;
4557 mdss0_dp3: displayport-controller@aea0000 {
4558 compatible = "qcom,sc8280xp-dp";
4570 clock-names = "core_iface", "core_aux",
4573 interrupt-parent = <&mdss0>;
4576 phy-names = "dp";
4577 power-domains = <&rpmhpd SC8280XP_MMCX>;
4579 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4581 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4582 operating-points-v2 = <&mdss0_dp3_opp_table>;
4584 #sound-dai-cells = <0>;
4589 #address-cells = <1>;
4590 #size-cells = <0>;
4595 remote-endpoint = <&mdss0_intf5_out>;
4604 mdss0_dp3_opp_table: opp-table {
4605 compatible = "operating-points-v2";
4607 opp-160000000 {
4608 opp-hz = /bits/ 64 <160000000>;
4609 required-opps = <&rpmhpd_opp_low_svs>;
4612 opp-270000000 {
4613 opp-hz = /bits/ 64 <270000000>;
4614 required-opps = <&rpmhpd_opp_svs>;
4617 opp-540000000 {
4618 opp-hz = /bits/ 64 <540000000>;
4619 required-opps = <&rpmhpd_opp_svs_l1>;
4622 opp-810000000 {
4623 opp-hz = /bits/ 64 <810000000>;
4624 required-opps = <&rpmhpd_opp_nom>;
4631 compatible = "qcom,sc8280xp-dp-phy";
4639 clock-names = "aux", "cfg_ahb";
4640 power-domains = <&rpmhpd SC8280XP_MX>;
4642 #clock-cells = <1>;
4643 #phy-cells = <0>;
4649 compatible = "qcom,sc8280xp-dp-phy";
4657 clock-names = "aux", "cfg_ahb";
4658 power-domains = <&rpmhpd SC8280XP_MX>;
4660 #clock-cells = <1>;
4661 #phy-cells = <0>;
4666 dispcc0: clock-controller@af00000 {
4667 compatible = "qcom,sc8280xp-dispcc0";
4685 power-domains = <&rpmhpd SC8280XP_MMCX>;
4687 #clock-cells = <1>;
4688 #power-domain-cells = <1>;
4689 #reset-cells = <1>;
4694 pdc: interrupt-controller@b220000 {
4695 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4697 qcom,pdc-ranges = <0 480 40>,
4754 #interrupt-cells = <2>;
4755 interrupt-parent = <&intc>;
4756 interrupt-controller;
4759 tsens2: thermal-sensor@c251000 {
4760 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4764 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
4766 interrupt-names = "uplow", "critical";
4767 #thermal-sensor-cells = <1>;
4770 tsens3: thermal-sensor@c252000 {
4771 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4775 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
4777 interrupt-names = "uplow", "critical";
4778 #thermal-sensor-cells = <1>;
4781 tsens0: thermal-sensor@c263000 {
4782 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4786 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4788 interrupt-names = "uplow", "critical";
4789 #thermal-sensor-cells = <1>;
4799 tsens1: thermal-sensor@c265000 {
4800 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4804 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4806 interrupt-names = "uplow", "critical";
4807 #thermal-sensor-cells = <1>;
4810 aoss_qmp: power-management@c300000 {
4811 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4813 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4816 #clock-cells = <0>;
4820 compatible = "qcom,rpmh-stats";
4826 compatible = "qcom,spmi-pmic-arb";
4832 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4833 interrupt-names = "periph_irq";
4834 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4837 #address-cells = <2>;
4838 #size-cells = <0>;
4839 interrupt-controller;
4840 #interrupt-cells = <4>;
4844 compatible = "qcom,sc8280xp-tlmm";
4847 gpio-controller;
4848 #gpio-cells = <2>;
4849 interrupt-controller;
4850 #interrupt-cells = <2>;
4851 gpio-ranges = <&tlmm 0 0 230>;
4852 wakeup-parent = <&pdc>;
4854 cci0_default: cci0-default-state {
4855 cci0_i2c0_default: cci0-i2c0-default-pins {
4859 drive-strength = <2>;
4860 bias-pull-up;
4863 cci0_i2c1_default: cci0-i2c1-default-pins {
4867 drive-strength = <2>;
4868 bias-pull-up;
4872 cci0_sleep: cci0-sleep-state {
4873 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4877 drive-strength = <2>;
4878 bias-pull-down;
4881 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4885 drive-strength = <2>;
4886 bias-pull-down;
4890 cci1_default: cci1-default-state {
4891 cci1_i2c0_default: cci1-i2c0-default-pins {
4895 drive-strength = <2>;
4896 bias-pull-up;
4899 cci1_i2c1_default: cci1-i2c1-default-pins {
4903 drive-strength = <2>;
4904 bias-pull-up;
4908 cci1_sleep: cci1-sleep-state {
4909 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4913 drive-strength = <2>;
4914 bias-pull-down;
4917 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4921 drive-strength = <2>;
4922 bias-pull-down;
4926 cci2_default: cci2-default-state {
4927 cci2_i2c0_default: cci2-i2c0-default-pins {
4931 drive-strength = <2>;
4932 bias-pull-up;
4935 cci2_i2c1_default: cci2-i2c1-default-pins {
4939 drive-strength = <2>;
4940 bias-pull-up;
4944 cci2_sleep: cci2-sleep-state {
4945 cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
4949 drive-strength = <2>;
4950 bias-pull-down;
4953 cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
4957 drive-strength = <2>;
4958 bias-pull-down;
4962 cci3_default: cci3-default-state {
4963 cci3_i2c0_default: cci3-i2c0-default-pins {
4967 drive-strength = <2>;
4968 bias-pull-up;
4971 cci3_i2c1_default: cci3-i2c1-default-pins {
4975 drive-strength = <2>;
4976 bias-pull-up;
4980 cci3_sleep: cci3-sleep-state {
4981 cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
4985 drive-strength = <2>;
4986 bias-pull-down;
4989 cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
4993 drive-strength = <2>;
4994 bias-pull-down;
4998 qup_uart18_default: qup-uart18-default-state {
4999 cts-pins {
5002 drive-strength = <2>;
5003 bias-disable;
5006 rts-pins {
5009 drive-strength = <2>;
5010 bias-disable;
5013 tx-pins {
5016 drive-strength = <2>;
5017 bias-disable;
5020 rx-pins {
5023 drive-strength = <2>;
5024 bias-disable;
5030 compatible = "arm,smmu-v3";
5032 #iommu-cells = <1>;
5036 interrupt-names = "eventq",
5038 "cmdq-sync";
5039 dma-coherent;
5044 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
5046 #iommu-cells = <2>;
5047 #global-interrupts = <2>;
5178 dma-coherent;
5181 intc: interrupt-controller@17a00000 {
5182 compatible = "arm,gic-v3";
5183 interrupt-controller;
5184 #interrupt-cells = <3>;
5188 #redistributor-regions = <1>;
5189 redistributor-stride = <0 0x20000>;
5191 #address-cells = <2>;
5192 #size-cells = <2>;
5195 its: msi-controller@17a40000 {
5196 compatible = "arm,gic-v3-its";
5198 msi-controller;
5199 #msi-cells = <1>;
5204 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5211 compatible = "arm,armv7-timer-mem";
5213 #address-cells = <1>;
5214 #size-cells = <1>;
5218 frame-number = <0>;
5226 frame-number = <1>;
5233 frame-number = <2>;
5240 frame-number = <3>;
5247 frame-number = <4>;
5254 frame-number = <5>;
5261 frame-number = <6>;
5269 compatible = "qcom,rpmh-rsc";
5273 reg-names = "drv-0", "drv-1", "drv-2";
5277 qcom,tcs-offset = <0xd00>;
5278 qcom,drv-id = <2>;
5279 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5282 power-domains = <&cluster_pd>;
5284 apps_bcm_voter: bcm-voter {
5285 compatible = "qcom,bcm-voter";
5288 rpmhcc: clock-controller {
5289 compatible = "qcom,sc8280xp-rpmh-clk";
5290 #clock-cells = <1>;
5291 clock-names = "xo";
5295 rpmhpd: power-controller {
5296 compatible = "qcom,sc8280xp-rpmhpd";
5297 #power-domain-cells = <1>;
5298 operating-points-v2 = <&rpmhpd_opp_table>;
5300 rpmhpd_opp_table: opp-table {
5301 compatible = "operating-points-v2";
5304 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5308 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5312 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5316 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5320 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5324 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5328 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5332 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5347 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5351 clock-names = "xo", "alternate";
5353 #interconnect-cells = <1>;
5357 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5360 reg-names = "freq-domain0", "freq-domain1";
5364 interrupt-names = "dcvsh-irq-0",
5365 "dcvsh-irq-1";
5368 clock-names = "xo", "alternate";
5370 #freq-domain-cells = <1>;
5371 #clock-cells = <1>;
5375 compatible = "qcom,sc8280xp-nsp0-pas";
5378 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5383 interrupt-names = "wdog", "fatal", "ready",
5384 "handover", "stop-ack";
5387 clock-names = "xo";
5389 power-domains = <&rpmhpd SC8280XP_NSP>;
5390 power-domain-names = "nsp";
5392 memory-region = <&pil_nsp0_mem>;
5394 qcom,smem-states = <&smp2p_nsp0_out 0>;
5395 qcom,smem-state-names = "stop";
5401 glink-edge {
5402 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5409 qcom,remote-pid = <5>;
5413 qcom,glink-channels = "fastrpcglink-apps-dsp";
5415 #address-cells = <1>;
5416 #size-cells = <0>;
5418 compute-cb@1 {
5419 compatible = "qcom,fastrpc-compute-cb";
5424 compute-cb@2 {
5425 compatible = "qcom,fastrpc-compute-cb";
5430 compute-cb@3 {
5431 compatible = "qcom,fastrpc-compute-cb";
5436 compute-cb@4 {
5437 compatible = "qcom,fastrpc-compute-cb";
5442 compute-cb@5 {
5443 compatible = "qcom,fastrpc-compute-cb";
5448 compute-cb@6 {
5449 compatible = "qcom,fastrpc-compute-cb";
5454 compute-cb@7 {
5455 compatible = "qcom,fastrpc-compute-cb";
5460 compute-cb@8 {
5461 compatible = "qcom,fastrpc-compute-cb";
5466 compute-cb@9 {
5467 compatible = "qcom,fastrpc-compute-cb";
5472 compute-cb@10 {
5473 compatible = "qcom,fastrpc-compute-cb";
5478 compute-cb@11 {
5479 compatible = "qcom,fastrpc-compute-cb";
5484 compute-cb@12 {
5485 compatible = "qcom,fastrpc-compute-cb";
5490 compute-cb@13 {
5491 compatible = "qcom,fastrpc-compute-cb";
5496 compute-cb@14 {
5497 compatible = "qcom,fastrpc-compute-cb";
5506 compatible = "qcom,sc8280xp-nsp1-pas";
5509 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5514 interrupt-names = "wdog", "fatal", "ready",
5515 "handover", "stop-ack";
5518 clock-names = "xo";
5520 power-domains = <&rpmhpd SC8280XP_NSP>;
5521 power-domain-names = "nsp";
5523 memory-region = <&pil_nsp1_mem>;
5525 qcom,smem-states = <&smp2p_nsp1_out 0>;
5526 qcom,smem-state-names = "stop";
5532 glink-edge {
5533 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5540 qcom,remote-pid = <12>;
5544 mdss1: display-subsystem@22000000 {
5545 compatible = "qcom,sc8280xp-mdss";
5547 reg-names = "mdss";
5552 clock-names = "iface",
5557 interconnect-names = "mdp0-mem", "mdp1-mem";
5561 power-domains = <&dispcc1 MDSS_GDSC>;
5564 interrupt-controller;
5565 #interrupt-cells = <1>;
5566 #address-cells = <2>;
5567 #size-cells = <2>;
5572 mdss1_mdp: display-controller@22001000 {
5573 compatible = "qcom,sc8280xp-dpu";
5576 reg-names = "mdp", "vbif";
5584 clock-names = "bus",
5590 interrupt-parent = <&mdss1>;
5592 power-domains = <&rpmhpd SC8280XP_MMCX>;
5594 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5595 assigned-clock-rates = <19200000>;
5596 operating-points-v2 = <&mdss1_mdp_opp_table>;
5599 #address-cells = <1>;
5600 #size-cells = <0>;
5605 remote-endpoint = <&mdss1_dp0_in>;
5612 remote-endpoint = <&mdss1_dp1_in>;
5619 remote-endpoint = <&mdss1_dp3_in>;
5626 remote-endpoint = <&mdss1_dp2_in>;
5631 mdss1_mdp_opp_table: opp-table {
5632 compatible = "operating-points-v2";
5634 opp-200000000 {
5635 opp-hz = /bits/ 64 <200000000>;
5636 required-opps = <&rpmhpd_opp_low_svs>;
5639 opp-300000000 {
5640 opp-hz = /bits/ 64 <300000000>;
5641 required-opps = <&rpmhpd_opp_svs>;
5644 opp-375000000 {
5645 opp-hz = /bits/ 64 <375000000>;
5646 required-opps = <&rpmhpd_opp_svs_l1>;
5649 opp-500000000 {
5650 opp-hz = /bits/ 64 <500000000>;
5651 required-opps = <&rpmhpd_opp_nom>;
5653 opp-600000000 {
5654 opp-hz = /bits/ 64 <600000000>;
5655 required-opps = <&rpmhpd_opp_turbo_l1>;
5660 mdss1_dp0: displayport-controller@22090000 {
5661 compatible = "qcom,sc8280xp-dp";
5673 clock-names = "core_iface", "core_aux",
5676 interrupt-parent = <&mdss1>;
5679 phy-names = "dp";
5680 power-domains = <&rpmhpd SC8280XP_MMCX>;
5682 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5684 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5685 operating-points-v2 = <&mdss1_dp0_opp_table>;
5687 #sound-dai-cells = <0>;
5692 #address-cells = <1>;
5693 #size-cells = <0>;
5698 remote-endpoint = <&mdss1_intf0_out>;
5707 mdss1_dp0_opp_table: opp-table {
5708 compatible = "operating-points-v2";
5710 opp-160000000 {
5711 opp-hz = /bits/ 64 <160000000>;
5712 required-opps = <&rpmhpd_opp_low_svs>;
5715 opp-270000000 {
5716 opp-hz = /bits/ 64 <270000000>;
5717 required-opps = <&rpmhpd_opp_svs>;
5720 opp-540000000 {
5721 opp-hz = /bits/ 64 <540000000>;
5722 required-opps = <&rpmhpd_opp_svs_l1>;
5725 opp-810000000 {
5726 opp-hz = /bits/ 64 <810000000>;
5727 required-opps = <&rpmhpd_opp_nom>;
5732 mdss1_dp1: displayport-controller@22098000 {
5733 compatible = "qcom,sc8280xp-dp";
5745 clock-names = "core_iface", "core_aux",
5748 interrupt-parent = <&mdss1>;
5751 phy-names = "dp";
5752 power-domains = <&rpmhpd SC8280XP_MMCX>;
5754 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5756 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5757 operating-points-v2 = <&mdss1_dp1_opp_table>;
5759 #sound-dai-cells = <0>;
5764 #address-cells = <1>;
5765 #size-cells = <0>;
5770 remote-endpoint = <&mdss1_intf4_out>;
5779 mdss1_dp1_opp_table: opp-table {
5780 compatible = "operating-points-v2";
5782 opp-160000000 {
5783 opp-hz = /bits/ 64 <160000000>;
5784 required-opps = <&rpmhpd_opp_low_svs>;
5787 opp-270000000 {
5788 opp-hz = /bits/ 64 <270000000>;
5789 required-opps = <&rpmhpd_opp_svs>;
5792 opp-540000000 {
5793 opp-hz = /bits/ 64 <540000000>;
5794 required-opps = <&rpmhpd_opp_svs_l1>;
5797 opp-810000000 {
5798 opp-hz = /bits/ 64 <810000000>;
5799 required-opps = <&rpmhpd_opp_nom>;
5804 mdss1_dp2: displayport-controller@2209a000 {
5805 compatible = "qcom,sc8280xp-dp";
5817 clock-names = "core_iface", "core_aux",
5820 interrupt-parent = <&mdss1>;
5823 phy-names = "dp";
5824 power-domains = <&rpmhpd SC8280XP_MMCX>;
5826 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5828 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5829 operating-points-v2 = <&mdss1_dp2_opp_table>;
5831 #sound-dai-cells = <0>;
5836 #address-cells = <1>;
5837 #size-cells = <0>;
5842 remote-endpoint = <&mdss1_intf6_out>;
5851 mdss1_dp2_opp_table: opp-table {
5852 compatible = "operating-points-v2";
5854 opp-160000000 {
5855 opp-hz = /bits/ 64 <160000000>;
5856 required-opps = <&rpmhpd_opp_low_svs>;
5859 opp-270000000 {
5860 opp-hz = /bits/ 64 <270000000>;
5861 required-opps = <&rpmhpd_opp_svs>;
5864 opp-540000000 {
5865 opp-hz = /bits/ 64 <540000000>;
5866 required-opps = <&rpmhpd_opp_svs_l1>;
5869 opp-810000000 {
5870 opp-hz = /bits/ 64 <810000000>;
5871 required-opps = <&rpmhpd_opp_nom>;
5876 mdss1_dp3: displayport-controller@220a0000 {
5877 compatible = "qcom,sc8280xp-dp";
5889 clock-names = "core_iface", "core_aux",
5892 interrupt-parent = <&mdss1>;
5895 phy-names = "dp";
5896 power-domains = <&rpmhpd SC8280XP_MMCX>;
5898 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5900 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5901 operating-points-v2 = <&mdss1_dp3_opp_table>;
5903 #sound-dai-cells = <0>;
5908 #address-cells = <1>;
5909 #size-cells = <0>;
5914 remote-endpoint = <&mdss1_intf5_out>;
5923 mdss1_dp3_opp_table: opp-table {
5924 compatible = "operating-points-v2";
5926 opp-160000000 {
5927 opp-hz = /bits/ 64 <160000000>;
5928 required-opps = <&rpmhpd_opp_low_svs>;
5931 opp-270000000 {
5932 opp-hz = /bits/ 64 <270000000>;
5933 required-opps = <&rpmhpd_opp_svs>;
5936 opp-540000000 {
5937 opp-hz = /bits/ 64 <540000000>;
5938 required-opps = <&rpmhpd_opp_svs_l1>;
5941 opp-810000000 {
5942 opp-hz = /bits/ 64 <810000000>;
5943 required-opps = <&rpmhpd_opp_nom>;
5950 compatible = "qcom,sc8280xp-dp-phy";
5958 clock-names = "aux", "cfg_ahb";
5959 power-domains = <&rpmhpd SC8280XP_MX>;
5961 #clock-cells = <1>;
5962 #phy-cells = <0>;
5968 compatible = "qcom,sc8280xp-dp-phy";
5976 clock-names = "aux", "cfg_ahb";
5977 power-domains = <&rpmhpd SC8280XP_MX>;
5979 #clock-cells = <1>;
5980 #phy-cells = <0>;
5985 dispcc1: clock-controller@22100000 {
5986 compatible = "qcom,sc8280xp-dispcc1";
6004 power-domains = <&rpmhpd SC8280XP_MMCX>;
6006 #clock-cells = <1>;
6007 #power-domain-cells = <1>;
6008 #reset-cells = <1>;
6014 compatible = "qcom,sc8280xp-ethqos";
6017 reg-names = "stmmaceth", "rgmii";
6023 clock-names = "stmmaceth",
6030 interrupt-names = "macirq", "eth_lpi";
6033 power-domains = <&gcc EMAC_1_GDSC>;
6037 rx-fifo-depth = <4096>;
6038 tx-fifo-depth = <4096>;
6047 thermal-zones {
6048 cpu0-thermal {
6049 polling-delay-passive = <250>;
6051 thermal-sensors = <&tsens0 1>;
6054 cpu-crit {
6062 cpu1-thermal {
6063 polling-delay-passive = <250>;
6065 thermal-sensors = <&tsens0 2>;
6068 cpu-crit {
6076 cpu2-thermal {
6077 polling-delay-passive = <250>;
6079 thermal-sensors = <&tsens0 3>;
6082 cpu-crit {
6090 cpu3-thermal {
6091 polling-delay-passive = <250>;
6093 thermal-sensors = <&tsens0 4>;
6096 cpu-crit {
6104 cpu4-thermal {
6105 polling-delay-passive = <250>;
6107 thermal-sensors = <&tsens0 5>;
6110 cpu-crit {
6118 cpu5-thermal {
6119 polling-delay-passive = <250>;
6121 thermal-sensors = <&tsens0 6>;
6124 cpu-crit {
6132 cpu6-thermal {
6133 polling-delay-passive = <250>;
6135 thermal-sensors = <&tsens0 7>;
6138 cpu-crit {
6146 cpu7-thermal {
6147 polling-delay-passive = <250>;
6149 thermal-sensors = <&tsens0 8>;
6152 cpu-crit {
6160 cluster0-thermal {
6161 polling-delay-passive = <250>;
6163 thermal-sensors = <&tsens0 9>;
6166 cpu-crit {
6174 gpu-thermal {
6175 polling-delay-passive = <250>;
6177 thermal-sensors = <&tsens2 2>;
6179 cooling-maps {
6182 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6187 gpu_alert0: trip-point0 {
6193 trip-point1 {
6201 mem-thermal {
6202 polling-delay-passive = <250>;
6204 thermal-sensors = <&tsens1 15>;
6207 trip-point0 {
6217 compatible = "arm,armv8-timer";