Lines Matching +full:gcc +full:- +full:sc8280xp
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6afe.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
32 xo_board_clk: xo-board-clk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <32764>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a78c";
53 enable-method = "psci";
54 capacity-dmips-mhz = <981>;
55 dynamic-power-coefficient = <549>;
56 next-level-cache = <&l2_0>;
57 power-domains = <&cpu_pd0>;
58 power-domain-names = "psci";
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 operating-points-v2 = <&cpu0_opp_table>;
62 #cooling-cells = <2>;
63 l2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&l3_0>;
68 l3_0: l3-cache {
70 cache-level = <3>;
71 cache-unified;
78 compatible = "arm,cortex-a78c";
81 enable-method = "psci";
82 capacity-dmips-mhz = <981>;
83 dynamic-power-coefficient = <549>;
84 next-level-cache = <&l2_100>;
85 power-domains = <&cpu_pd1>;
86 power-domain-names = "psci";
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 operating-points-v2 = <&cpu0_opp_table>;
90 #cooling-cells = <2>;
91 l2_100: l2-cache {
93 cache-level = <2>;
94 cache-unified;
95 next-level-cache = <&l3_0>;
101 compatible = "arm,cortex-a78c";
104 enable-method = "psci";
105 capacity-dmips-mhz = <981>;
106 dynamic-power-coefficient = <549>;
107 next-level-cache = <&l2_200>;
108 power-domains = <&cpu_pd2>;
109 power-domain-names = "psci";
110 qcom,freq-domain = <&cpufreq_hw 0>;
111 operating-points-v2 = <&cpu0_opp_table>;
113 #cooling-cells = <2>;
114 l2_200: l2-cache {
116 cache-level = <2>;
117 cache-unified;
118 next-level-cache = <&l3_0>;
124 compatible = "arm,cortex-a78c";
127 enable-method = "psci";
128 capacity-dmips-mhz = <981>;
129 dynamic-power-coefficient = <549>;
130 next-level-cache = <&l2_300>;
131 power-domains = <&cpu_pd3>;
132 power-domain-names = "psci";
133 qcom,freq-domain = <&cpufreq_hw 0>;
134 operating-points-v2 = <&cpu0_opp_table>;
136 #cooling-cells = <2>;
137 l2_300: l2-cache {
139 cache-level = <2>;
140 cache-unified;
141 next-level-cache = <&l3_0>;
147 compatible = "arm,cortex-x1c";
150 enable-method = "psci";
151 capacity-dmips-mhz = <1024>;
152 dynamic-power-coefficient = <590>;
153 next-level-cache = <&l2_400>;
154 power-domains = <&cpu_pd4>;
155 power-domain-names = "psci";
156 qcom,freq-domain = <&cpufreq_hw 1>;
157 operating-points-v2 = <&cpu4_opp_table>;
159 #cooling-cells = <2>;
160 l2_400: l2-cache {
162 cache-level = <2>;
163 cache-unified;
164 next-level-cache = <&l3_0>;
170 compatible = "arm,cortex-x1c";
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
175 dynamic-power-coefficient = <590>;
176 next-level-cache = <&l2_500>;
177 power-domains = <&cpu_pd5>;
178 power-domain-names = "psci";
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 operating-points-v2 = <&cpu4_opp_table>;
182 #cooling-cells = <2>;
183 l2_500: l2-cache {
185 cache-level = <2>;
186 cache-unified;
187 next-level-cache = <&l3_0>;
193 compatible = "arm,cortex-x1c";
196 enable-method = "psci";
197 capacity-dmips-mhz = <1024>;
198 dynamic-power-coefficient = <590>;
199 next-level-cache = <&l2_600>;
200 power-domains = <&cpu_pd6>;
201 power-domain-names = "psci";
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
205 #cooling-cells = <2>;
206 l2_600: l2-cache {
208 cache-level = <2>;
209 cache-unified;
210 next-level-cache = <&l3_0>;
216 compatible = "arm,cortex-x1c";
219 enable-method = "psci";
220 capacity-dmips-mhz = <1024>;
221 dynamic-power-coefficient = <590>;
222 next-level-cache = <&l2_700>;
223 power-domains = <&cpu_pd7>;
224 power-domain-names = "psci";
225 qcom,freq-domain = <&cpufreq_hw 1>;
226 operating-points-v2 = <&cpu4_opp_table>;
228 #cooling-cells = <2>;
229 l2_700: l2-cache {
231 cache-level = <2>;
232 cache-unified;
233 next-level-cache = <&l3_0>;
237 cpu-map {
273 idle-states {
274 entry-method = "psci";
276 little_cpu_sleep_0: cpu-sleep-0-0 {
277 compatible = "arm,idle-state";
278 idle-state-name = "little-rail-power-collapse";
279 arm,psci-suspend-param = <0x40000004>;
280 entry-latency-us = <355>;
281 exit-latency-us = <909>;
282 min-residency-us = <3934>;
283 local-timer-stop;
286 big_cpu_sleep_0: cpu-sleep-1-0 {
287 compatible = "arm,idle-state";
288 idle-state-name = "big-rail-power-collapse";
289 arm,psci-suspend-param = <0x40000004>;
290 entry-latency-us = <241>;
291 exit-latency-us = <1461>;
292 min-residency-us = <4488>;
293 local-timer-stop;
297 domain-idle-states {
298 cluster_sleep_0: cluster-sleep-0 {
299 compatible = "domain-idle-state";
300 arm,psci-suspend-param = <0x4100c344>;
301 entry-latency-us = <3263>;
302 exit-latency-us = <6562>;
303 min-residency-us = <9987>;
310 compatible = "qcom,scm-sc8280xp", "qcom,scm";
312 qcom,dload-mode = <&tcsr 0x13000>;
316 aggre1_noc: interconnect-aggre1-noc {
317 compatible = "qcom,sc8280xp-aggre1-noc";
318 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_voter>;
322 aggre2_noc: interconnect-aggre2-noc {
323 compatible = "qcom,sc8280xp-aggre2-noc";
324 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_voter>;
328 clk_virt: interconnect-clk-virt {
329 compatible = "qcom,sc8280xp-clk-virt";
330 #interconnect-cells = <2>;
331 qcom,bcm-voters = <&apps_bcm_voter>;
334 config_noc: interconnect-config-noc {
335 compatible = "qcom,sc8280xp-config-noc";
336 #interconnect-cells = <2>;
337 qcom,bcm-voters = <&apps_bcm_voter>;
340 dc_noc: interconnect-dc-noc {
341 compatible = "qcom,sc8280xp-dc-noc";
342 #interconnect-cells = <2>;
343 qcom,bcm-voters = <&apps_bcm_voter>;
346 gem_noc: interconnect-gem-noc {
347 compatible = "qcom,sc8280xp-gem-noc";
348 #interconnect-cells = <2>;
349 qcom,bcm-voters = <&apps_bcm_voter>;
352 lpass_noc: interconnect-lpass-ag-noc {
353 compatible = "qcom,sc8280xp-lpass-ag-noc";
354 #interconnect-cells = <2>;
355 qcom,bcm-voters = <&apps_bcm_voter>;
358 mc_virt: interconnect-mc-virt {
359 compatible = "qcom,sc8280xp-mc-virt";
360 #interconnect-cells = <2>;
361 qcom,bcm-voters = <&apps_bcm_voter>;
364 mmss_noc: interconnect-mmss-noc {
365 compatible = "qcom,sc8280xp-mmss-noc";
366 #interconnect-cells = <2>;
367 qcom,bcm-voters = <&apps_bcm_voter>;
370 nspa_noc: interconnect-nspa-noc {
371 compatible = "qcom,sc8280xp-nspa-noc";
372 #interconnect-cells = <2>;
373 qcom,bcm-voters = <&apps_bcm_voter>;
376 nspb_noc: interconnect-nspb-noc {
377 compatible = "qcom,sc8280xp-nspb-noc";
378 #interconnect-cells = <2>;
379 qcom,bcm-voters = <&apps_bcm_voter>;
382 system_noc: interconnect-system-noc {
383 compatible = "qcom,sc8280xp-system-noc";
384 #interconnect-cells = <2>;
385 qcom,bcm-voters = <&apps_bcm_voter>;
394 cpu0_opp_table: opp-table-cpu0 {
395 compatible = "operating-points-v2";
396 opp-shared;
398 opp-300000000 {
399 opp-hz = /bits/ 64 <300000000>;
400 opp-peak-kBps = <(300000 * 32)>;
402 opp-403200000 {
403 opp-hz = /bits/ 64 <403200000>;
404 opp-peak-kBps = <(384000 * 32)>;
406 opp-499200000 {
407 opp-hz = /bits/ 64 <499200000>;
408 opp-peak-kBps = <(480000 * 32)>;
410 opp-595200000 {
411 opp-hz = /bits/ 64 <595200000>;
412 opp-peak-kBps = <(576000 * 32)>;
414 opp-691200000 {
415 opp-hz = /bits/ 64 <691200000>;
416 opp-peak-kBps = <(672000 * 32)>;
418 opp-806400000 {
419 opp-hz = /bits/ 64 <806400000>;
420 opp-peak-kBps = <(768000 * 32)>;
422 opp-902400000 {
423 opp-hz = /bits/ 64 <902400000>;
424 opp-peak-kBps = <(864000 * 32)>;
426 opp-1017600000 {
427 opp-hz = /bits/ 64 <1017600000>;
428 opp-peak-kBps = <(960000 * 32)>;
430 opp-1113600000 {
431 opp-hz = /bits/ 64 <1113600000>;
432 opp-peak-kBps = <(1075200 * 32)>;
434 opp-1209600000 {
435 opp-hz = /bits/ 64 <1209600000>;
436 opp-peak-kBps = <(1171200 * 32)>;
438 opp-1324800000 {
439 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <(1267200 * 32)>;
442 opp-1440000000 {
443 opp-hz = /bits/ 64 <1440000000>;
444 opp-peak-kBps = <(1363200 * 32)>;
446 opp-1555200000 {
447 opp-hz = /bits/ 64 <1555200000>;
448 opp-peak-kBps = <(1536000 * 32)>;
450 opp-1670400000 {
451 opp-hz = /bits/ 64 <1670400000>;
452 opp-peak-kBps = <(1612800 * 32)>;
454 opp-1785600000 {
455 opp-hz = /bits/ 64 <1785600000>;
456 opp-peak-kBps = <(1689600 * 32)>;
458 opp-1881600000 {
459 opp-hz = /bits/ 64 <1881600000>;
460 opp-peak-kBps = <(1689600 * 32)>;
462 opp-1996800000 {
463 opp-hz = /bits/ 64 <1996800000>;
464 opp-peak-kBps = <(1689600 * 32)>;
466 opp-2112000000 {
467 opp-hz = /bits/ 64 <2112000000>;
468 opp-peak-kBps = <(1689600 * 32)>;
470 opp-2227200000 {
471 opp-hz = /bits/ 64 <2227200000>;
472 opp-peak-kBps = <(1689600 * 32)>;
474 opp-2342400000 {
475 opp-hz = /bits/ 64 <2342400000>;
476 opp-peak-kBps = <(1689600 * 32)>;
478 opp-2438400000 {
479 opp-hz = /bits/ 64 <2438400000>;
480 opp-peak-kBps = <(1689600 * 32)>;
484 cpu4_opp_table: opp-table-cpu4 {
485 compatible = "operating-points-v2";
486 opp-shared;
488 opp-825600000 {
489 opp-hz = /bits/ 64 <825600000>;
490 opp-peak-kBps = <(768000 * 32)>;
492 opp-940800000 {
493 opp-hz = /bits/ 64 <940800000>;
494 opp-peak-kBps = <(864000 * 32)>;
496 opp-1056000000 {
497 opp-hz = /bits/ 64 <1056000000>;
498 opp-peak-kBps = <(960000 * 32)>;
500 opp-1171200000 {
501 opp-hz = /bits/ 64 <1171200000>;
502 opp-peak-kBps = <(1171200 * 32)>;
504 opp-1286400000 {
505 opp-hz = /bits/ 64 <1286400000>;
506 opp-peak-kBps = <(1267200 * 32)>;
508 opp-1401600000 {
509 opp-hz = /bits/ 64 <1401600000>;
510 opp-peak-kBps = <(1363200 * 32)>;
512 opp-1516800000 {
513 opp-hz = /bits/ 64 <1516800000>;
514 opp-peak-kBps = <(1459200 * 32)>;
516 opp-1632000000 {
517 opp-hz = /bits/ 64 <1632000000>;
518 opp-peak-kBps = <(1612800 * 32)>;
520 opp-1747200000 {
521 opp-hz = /bits/ 64 <1747200000>;
522 opp-peak-kBps = <(1689600 * 32)>;
524 opp-1862400000 {
525 opp-hz = /bits/ 64 <1862400000>;
526 opp-peak-kBps = <(1689600 * 32)>;
528 opp-1977600000 {
529 opp-hz = /bits/ 64 <1977600000>;
530 opp-peak-kBps = <(1689600 * 32)>;
532 opp-2073600000 {
533 opp-hz = /bits/ 64 <2073600000>;
534 opp-peak-kBps = <(1689600 * 32)>;
536 opp-2169600000 {
537 opp-hz = /bits/ 64 <2169600000>;
538 opp-peak-kBps = <(1689600 * 32)>;
540 opp-2284800000 {
541 opp-hz = /bits/ 64 <2284800000>;
542 opp-peak-kBps = <(1689600 * 32)>;
544 opp-2400000000 {
545 opp-hz = /bits/ 64 <2400000000>;
546 opp-peak-kBps = <(1689600 * 32)>;
548 opp-2496000000 {
549 opp-hz = /bits/ 64 <2496000000>;
550 opp-peak-kBps = <(1689600 * 32)>;
552 opp-2592000000 {
553 opp-hz = /bits/ 64 <2592000000>;
554 opp-peak-kBps = <(1689600 * 32)>;
556 opp-2688000000 {
557 opp-hz = /bits/ 64 <2688000000>;
558 opp-peak-kBps = <(1689600 * 32)>;
560 opp-2803200000 {
561 opp-hz = /bits/ 64 <2803200000>;
562 opp-peak-kBps = <(1689600 * 32)>;
564 opp-2899200000 {
565 opp-hz = /bits/ 64 <2899200000>;
566 opp-peak-kBps = <(1689600 * 32)>;
568 opp-2995200000 {
569 opp-hz = /bits/ 64 <2995200000>;
570 opp-peak-kBps = <(1689600 * 32)>;
574 qup_opp_table_100mhz: opp-table-qup100mhz {
575 compatible = "operating-points-v2";
577 opp-75000000 {
578 opp-hz = /bits/ 64 <75000000>;
579 required-opps = <&rpmhpd_opp_low_svs>;
582 opp-100000000 {
583 opp-hz = /bits/ 64 <100000000>;
584 required-opps = <&rpmhpd_opp_svs>;
589 compatible = "arm,armv8-pmuv3";
594 compatible = "arm,psci-1.0";
597 cpu_pd0: power-domain-cpu0 {
598 #power-domain-cells = <0>;
599 power-domains = <&cluster_pd>;
600 domain-idle-states = <&little_cpu_sleep_0>;
603 cpu_pd1: power-domain-cpu1 {
604 #power-domain-cells = <0>;
605 power-domains = <&cluster_pd>;
606 domain-idle-states = <&little_cpu_sleep_0>;
609 cpu_pd2: power-domain-cpu2 {
610 #power-domain-cells = <0>;
611 power-domains = <&cluster_pd>;
612 domain-idle-states = <&little_cpu_sleep_0>;
615 cpu_pd3: power-domain-cpu3 {
616 #power-domain-cells = <0>;
617 power-domains = <&cluster_pd>;
618 domain-idle-states = <&little_cpu_sleep_0>;
621 cpu_pd4: power-domain-cpu4 {
622 #power-domain-cells = <0>;
623 power-domains = <&cluster_pd>;
624 domain-idle-states = <&big_cpu_sleep_0>;
627 cpu_pd5: power-domain-cpu5 {
628 #power-domain-cells = <0>;
629 power-domains = <&cluster_pd>;
630 domain-idle-states = <&big_cpu_sleep_0>;
633 cpu_pd6: power-domain-cpu6 {
634 #power-domain-cells = <0>;
635 power-domains = <&cluster_pd>;
636 domain-idle-states = <&big_cpu_sleep_0>;
639 cpu_pd7: power-domain-cpu7 {
640 #power-domain-cells = <0>;
641 power-domains = <&cluster_pd>;
642 domain-idle-states = <&big_cpu_sleep_0>;
645 cluster_pd: power-domain-cpu-cluster0 {
646 #power-domain-cells = <0>;
647 domain-idle-states = <&cluster_sleep_0>;
651 reserved-memory {
652 #address-cells = <2>;
653 #size-cells = <2>;
656 reserved-region@80000000 {
658 no-map;
661 cmd_db: cmd-db-region@80860000 {
662 compatible = "qcom,cmd-db";
664 no-map;
667 reserved-region@80880000 {
669 no-map;
672 smem_mem: smem-region@80900000 {
675 no-map;
679 reserved-region@80b00000 {
681 no-map;
684 reserved-region@83b00000 {
686 no-map;
689 reserved-region@85b00000 {
691 no-map;
694 pil_gpu_mem: gpu-mem@8bf00000 {
696 no-map;
699 pil_adsp_mem: adsp-region@86c00000 {
701 no-map;
704 pil_slpi_mem: slpi-region@88c00000 {
706 no-map;
709 pil_nsp0_mem: cdsp0-region@8a100000 {
711 no-map;
714 pil_nsp1_mem: cdsp1-region@8c600000 {
716 no-map;
719 reserved-region@aeb00000 {
721 no-map;
725 smp2p-adsp {
728 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
734 qcom,local-pid = <0>;
735 qcom,remote-pid = <2>;
737 smp2p_adsp_out: master-kernel {
738 qcom,entry-name = "master-kernel";
739 #qcom,smem-state-cells = <1>;
742 smp2p_adsp_in: slave-kernel {
743 qcom,entry-name = "slave-kernel";
744 interrupt-controller;
745 #interrupt-cells = <2>;
749 smp2p-nsp0 {
752 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
758 qcom,local-pid = <0>;
759 qcom,remote-pid = <5>;
761 smp2p_nsp0_out: master-kernel {
762 qcom,entry-name = "master-kernel";
763 #qcom,smem-state-cells = <1>;
766 smp2p_nsp0_in: slave-kernel {
767 qcom,entry-name = "slave-kernel";
768 interrupt-controller;
769 #interrupt-cells = <2>;
773 smp2p-nsp1 {
776 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
782 qcom,local-pid = <0>;
783 qcom,remote-pid = <12>;
785 smp2p_nsp1_out: master-kernel {
786 qcom,entry-name = "master-kernel";
787 #qcom,smem-state-cells = <1>;
790 smp2p_nsp1_in: slave-kernel {
791 qcom,entry-name = "slave-kernel";
792 interrupt-controller;
793 #interrupt-cells = <2>;
797 smp2p-slpi {
800 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
806 qcom,local-pid = <0>;
807 qcom,remote-pid = <3>;
809 smp2p_slpi_out: master-kernel {
810 qcom,entry-name = "master-kernel";
811 #qcom,smem-state-cells = <1>;
814 smp2p_slpi_in: slave-kernel {
815 qcom,entry-name = "slave-kernel";
816 interrupt-controller;
817 #interrupt-cells = <2>;
822 compatible = "simple-bus";
823 #address-cells = <2>;
824 #size-cells = <2>;
826 dma-ranges = <0 0 0 0 0x10 0>;
829 compatible = "qcom,sc8280xp-ethqos";
832 reg-names = "stmmaceth", "rgmii";
834 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
835 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
836 <&gcc GCC_EMAC0_PTP_CLK>,
837 <&gcc GCC_EMAC0_RGMII_CLK>;
838 clock-names = "stmmaceth",
845 interrupt-names = "macirq", "eth_lpi";
848 power-domains = <&gcc EMAC_0_GDSC>;
852 rx-fifo-depth = <4096>;
853 tx-fifo-depth = <4096>;
858 gcc: clock-controller@100000 { label
859 compatible = "qcom,gcc-sc8280xp";
861 #clock-cells = <1>;
862 #reset-cells = <1>;
863 #power-domain-cells = <1>;
897 power-domains = <&rpmhpd SC8280XP_CX>;
901 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
904 interrupt-controller;
905 #interrupt-cells = <3>;
906 #mbox-cells = <2>;
910 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom";
912 #address-cells = <1>;
913 #size-cells = <1>;
915 gpu_speed_bin: gpu-speed-bin@18b {
921 gpi_dma2: dma-controller@800000 {
922 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma";
938 dma-channels = <12>;
939 dma-channel-mask = <0xfff>;
940 #dma-cells = <3>;
948 compatible = "qcom,geni-se-qup";
950 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
951 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
952 clock-names = "m-ahb", "s-ahb";
955 #address-cells = <2>;
956 #size-cells = <2>;
962 compatible = "qcom,geni-i2c";
964 #address-cells = <1>;
965 #size-cells = <0>;
966 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
967 clock-names = "se";
969 power-domains = <&rpmhpd SC8280XP_CX>;
973 interconnect-names = "qup-core", "qup-config", "qup-memory";
977 dma-names = "tx",
984 compatible = "qcom,geni-spi";
986 #address-cells = <1>;
987 #size-cells = <0>;
988 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
989 clock-names = "se";
991 power-domains = <&rpmhpd SC8280XP_CX>;
995 interconnect-names = "qup-core", "qup-config", "qup-memory";
999 dma-names = "tx",
1006 compatible = "qcom,geni-i2c";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1010 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1011 clock-names = "se";
1013 power-domains = <&rpmhpd SC8280XP_CX>;
1017 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 dma-names = "tx",
1028 compatible = "qcom,geni-spi";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1033 clock-names = "se";
1035 power-domains = <&rpmhpd SC8280XP_CX>;
1039 interconnect-names = "qup-core", "qup-config", "qup-memory";
1043 dma-names = "tx",
1050 compatible = "qcom,geni-uart";
1052 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1053 clock-names = "se";
1055 operating-points-v2 = <&qup_opp_table_100mhz>;
1056 power-domains = <&rpmhpd SC8280XP_CX>;
1059 interconnect-names = "qup-core", "qup-config";
1064 compatible = "qcom,geni-i2c";
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1069 clock-names = "se";
1071 power-domains = <&rpmhpd SC8280XP_CX>;
1075 interconnect-names = "qup-core", "qup-config", "qup-memory";
1079 dma-names = "tx",
1086 compatible = "qcom,geni-spi";
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1091 clock-names = "se";
1093 power-domains = <&rpmhpd SC8280XP_CX>;
1097 interconnect-names = "qup-core", "qup-config", "qup-memory";
1101 dma-names = "tx",
1108 compatible = "qcom,geni-uart";
1110 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1111 clock-names = "se";
1113 operating-points-v2 = <&qup_opp_table_100mhz>;
1114 power-domains = <&rpmhpd SC8280XP_CX>;
1117 interconnect-names = "qup-core", "qup-config";
1119 pinctrl-0 = <&qup_uart18_default>;
1120 pinctrl-names = "default";
1126 compatible = "qcom,geni-i2c";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1131 clock-names = "se";
1133 power-domains = <&rpmhpd SC8280XP_CX>;
1137 interconnect-names = "qup-core", "qup-config", "qup-memory";
1141 dma-names = "tx",
1148 compatible = "qcom,geni-spi";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1153 clock-names = "se";
1155 power-domains = <&rpmhpd SC8280XP_CX>;
1159 interconnect-names = "qup-core", "qup-config", "qup-memory";
1163 dma-names = "tx",
1170 compatible = "qcom,geni-i2c";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1175 clock-names = "se";
1177 power-domains = <&rpmhpd SC8280XP_CX>;
1181 interconnect-names = "qup-core", "qup-config", "qup-memory";
1185 dma-names = "tx",
1192 compatible = "qcom,geni-spi";
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1196 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1197 clock-names = "se";
1199 power-domains = <&rpmhpd SC8280XP_CX>;
1203 interconnect-names = "qup-core", "qup-config", "qup-memory";
1207 dma-names = "tx",
1214 compatible = "qcom,geni-i2c";
1216 clock-names = "se";
1217 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 power-domains = <&rpmhpd SC8280XP_CX>;
1225 interconnect-names = "qup-core", "qup-config", "qup-memory";
1229 dma-names = "tx",
1236 compatible = "qcom,geni-spi";
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1241 clock-names = "se";
1243 power-domains = <&rpmhpd SC8280XP_CX>;
1247 interconnect-names = "qup-core", "qup-config", "qup-memory";
1251 dma-names = "tx",
1258 compatible = "qcom,geni-i2c";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1262 clock-names = "se";
1263 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1265 power-domains = <&rpmhpd SC8280XP_CX>;
1269 interconnect-names = "qup-core", "qup-config", "qup-memory";
1273 dma-names = "tx",
1280 compatible = "qcom,geni-spi";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1285 clock-names = "se";
1287 power-domains = <&rpmhpd SC8280XP_CX>;
1291 interconnect-names = "qup-core", "qup-config", "qup-memory";
1295 dma-names = "tx",
1302 compatible = "qcom,geni-i2c";
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306 clock-names = "se";
1307 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1309 power-domains = <&rpmhpd SC8280XP_CX>;
1313 interconnect-names = "qup-core", "qup-config", "qup-memory";
1317 dma-names = "tx",
1324 compatible = "qcom,geni-spi";
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1329 clock-names = "se";
1331 power-domains = <&rpmhpd SC8280XP_CX>;
1335 interconnect-names = "qup-core", "qup-config", "qup-memory";
1339 dma-names = "tx",
1346 gpi_dma0: dma-controller@900000 {
1347 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma";
1364 dma-channels = <13>;
1365 dma-channel-mask = <0x1fff>;
1366 #dma-cells = <3>;
1374 compatible = "qcom,geni-se-qup";
1376 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1377 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1378 clock-names = "m-ahb", "s-ahb";
1381 #address-cells = <2>;
1382 #size-cells = <2>;
1388 compatible = "qcom,geni-i2c";
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392 clock-names = "se";
1393 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1395 power-domains = <&rpmhpd SC8280XP_CX>;
1399 interconnect-names = "qup-core", "qup-config", "qup-memory";
1403 dma-names = "tx",
1410 compatible = "qcom,geni-spi";
1412 #address-cells = <1>;
1413 #size-cells = <0>;
1414 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1415 clock-names = "se";
1417 power-domains = <&rpmhpd SC8280XP_CX>;
1421 interconnect-names = "qup-core", "qup-config", "qup-memory";
1425 dma-names = "tx",
1432 compatible = "qcom,geni-i2c";
1434 #address-cells = <1>;
1435 #size-cells = <0>;
1436 clock-names = "se";
1437 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1439 power-domains = <&rpmhpd SC8280XP_CX>;
1443 interconnect-names = "qup-core", "qup-config", "qup-memory";
1447 dma-names = "tx",
1454 compatible = "qcom,geni-spi";
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1458 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1459 clock-names = "se";
1461 power-domains = <&rpmhpd SC8280XP_CX>;
1465 interconnect-names = "qup-core", "qup-config", "qup-memory";
1469 dma-names = "tx",
1476 compatible = "qcom,geni-i2c";
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1480 clock-names = "se";
1481 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1483 power-domains = <&rpmhpd SC8280XP_CX>;
1487 interconnect-names = "qup-core", "qup-config", "qup-memory";
1491 dma-names = "tx",
1498 compatible = "qcom,geni-spi";
1500 #address-cells = <1>;
1501 #size-cells = <0>;
1502 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1503 clock-names = "se";
1505 power-domains = <&rpmhpd SC8280XP_CX>;
1509 interconnect-names = "qup-core", "qup-config", "qup-memory";
1513 dma-names = "tx",
1520 compatible = "qcom,geni-uart";
1522 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1523 clock-names = "se";
1525 operating-points-v2 = <&qup_opp_table_100mhz>;
1526 power-domains = <&rpmhpd SC8280XP_CX>;
1529 interconnect-names = "qup-core", "qup-config";
1534 compatible = "qcom,geni-i2c";
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1538 clock-names = "se";
1539 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 power-domains = <&rpmhpd SC8280XP_CX>;
1545 interconnect-names = "qup-core", "qup-config", "qup-memory";
1549 dma-names = "tx",
1556 compatible = "qcom,geni-spi";
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1560 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1561 clock-names = "se";
1563 power-domains = <&rpmhpd SC8280XP_CX>;
1567 interconnect-names = "qup-core", "qup-config", "qup-memory";
1571 dma-names = "tx",
1578 compatible = "qcom,geni-i2c";
1580 clock-names = "se";
1581 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1585 power-domains = <&rpmhpd SC8280XP_CX>;
1589 interconnect-names = "qup-core", "qup-config", "qup-memory";
1593 dma-names = "tx",
1600 compatible = "qcom,geni-spi";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1605 clock-names = "se";
1607 power-domains = <&rpmhpd SC8280XP_CX>;
1611 interconnect-names = "qup-core", "qup-config", "qup-memory";
1615 dma-names = "tx",
1622 compatible = "qcom,geni-i2c";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626 clock-names = "se";
1627 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1629 power-domains = <&rpmhpd SC8280XP_CX>;
1633 interconnect-names = "qup-core", "qup-config", "qup-memory";
1637 dma-names = "tx",
1644 compatible = "qcom,geni-spi";
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1649 clock-names = "se";
1651 power-domains = <&rpmhpd SC8280XP_CX>;
1655 interconnect-names = "qup-core", "qup-config", "qup-memory";
1659 dma-names = "tx",
1666 compatible = "qcom,geni-i2c";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670 clock-names = "se";
1671 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1673 power-domains = <&rpmhpd SC8280XP_CX>;
1677 interconnect-names = "qup-core", "qup-config", "qup-memory";
1681 dma-names = "tx",
1688 compatible = "qcom,geni-spi";
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1692 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1693 clock-names = "se";
1695 power-domains = <&rpmhpd SC8280XP_CX>;
1699 interconnect-names = "qup-core", "qup-config", "qup-memory";
1703 dma-names = "tx",
1710 compatible = "qcom,geni-i2c";
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1714 clock-names = "se";
1715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1717 power-domains = <&rpmhpd SC8280XP_CX>;
1721 interconnect-names = "qup-core", "qup-config", "qup-memory";
1725 dma-names = "tx",
1732 compatible = "qcom,geni-spi";
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1736 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1737 clock-names = "se";
1739 power-domains = <&rpmhpd SC8280XP_CX>;
1743 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dma-names = "tx",
1754 gpi_dma1: dma-controller@a00000 {
1755 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma";
1771 dma-channels = <12>;
1772 dma-channel-mask = <0xfff>;
1773 #dma-cells = <3>;
1781 compatible = "qcom,geni-se-qup";
1783 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1784 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1785 clock-names = "m-ahb", "s-ahb";
1788 #address-cells = <2>;
1789 #size-cells = <2>;
1795 compatible = "qcom,geni-i2c";
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1799 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1800 clock-names = "se";
1802 power-domains = <&rpmhpd SC8280XP_CX>;
1806 interconnect-names = "qup-core", "qup-config", "qup-memory";
1810 dma-names = "tx",
1817 compatible = "qcom,geni-spi";
1819 #address-cells = <1>;
1820 #size-cells = <0>;
1821 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1822 clock-names = "se";
1824 power-domains = <&rpmhpd SC8280XP_CX>;
1828 interconnect-names = "qup-core", "qup-config", "qup-memory";
1832 dma-names = "tx",
1839 compatible = "qcom,geni-i2c";
1841 #address-cells = <1>;
1842 #size-cells = <0>;
1843 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1844 clock-names = "se";
1846 power-domains = <&rpmhpd SC8280XP_CX>;
1850 interconnect-names = "qup-core", "qup-config", "qup-memory";
1854 dma-names = "tx",
1861 compatible = "qcom,geni-spi";
1863 #address-cells = <1>;
1864 #size-cells = <0>;
1865 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 clock-names = "se";
1868 power-domains = <&rpmhpd SC8280XP_CX>;
1872 interconnect-names = "qup-core", "qup-config", "qup-memory";
1876 dma-names = "tx",
1883 compatible = "qcom,geni-i2c";
1885 #address-cells = <1>;
1886 #size-cells = <0>;
1887 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1888 clock-names = "se";
1890 power-domains = <&rpmhpd SC8280XP_CX>;
1894 interconnect-names = "qup-core", "qup-config", "qup-memory";
1898 dma-names = "tx",
1905 compatible = "qcom,geni-spi";
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1909 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1910 clock-names = "se";
1912 power-domains = <&rpmhpd SC8280XP_CX>;
1916 interconnect-names = "qup-core", "qup-config", "qup-memory";
1920 dma-names = "tx",
1927 compatible = "qcom,geni-i2c";
1929 #address-cells = <1>;
1930 #size-cells = <0>;
1931 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1932 clock-names = "se";
1934 power-domains = <&rpmhpd SC8280XP_CX>;
1938 interconnect-names = "qup-core", "qup-config", "qup-memory";
1942 dma-names = "tx",
1949 compatible = "qcom,geni-spi";
1951 #address-cells = <1>;
1952 #size-cells = <0>;
1953 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1954 clock-names = "se";
1956 power-domains = <&rpmhpd SC8280XP_CX>;
1960 interconnect-names = "qup-core", "qup-config", "qup-memory";
1964 dma-names = "tx",
1971 compatible = "qcom,geni-i2c";
1973 #address-cells = <1>;
1974 #size-cells = <0>;
1975 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1976 clock-names = "se";
1978 power-domains = <&rpmhpd SC8280XP_CX>;
1982 interconnect-names = "qup-core", "qup-config", "qup-memory";
1986 dma-names = "tx",
1993 compatible = "qcom,geni-spi";
1995 #address-cells = <1>;
1996 #size-cells = <0>;
1997 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1998 clock-names = "se";
2000 power-domains = <&rpmhpd SC8280XP_CX>;
2004 interconnect-names = "qup-core", "qup-config", "qup-memory";
2008 dma-names = "tx",
2015 compatible = "qcom,geni-i2c";
2017 #address-cells = <1>;
2018 #size-cells = <0>;
2019 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2020 clock-names = "se";
2022 power-domains = <&rpmhpd SC8280XP_CX>;
2026 interconnect-names = "qup-core", "qup-config", "qup-memory";
2030 dma-names = "tx",
2037 compatible = "qcom,geni-spi";
2039 #address-cells = <1>;
2040 #size-cells = <0>;
2041 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2042 clock-names = "se";
2044 power-domains = <&rpmhpd SC8280XP_CX>;
2048 interconnect-names = "qup-core", "qup-config", "qup-memory";
2052 dma-names = "tx",
2059 compatible = "qcom,geni-i2c";
2061 #address-cells = <1>;
2062 #size-cells = <0>;
2063 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2064 clock-names = "se";
2066 power-domains = <&rpmhpd SC8280XP_CX>;
2070 interconnect-names = "qup-core", "qup-config", "qup-memory";
2074 dma-names = "tx",
2081 compatible = "qcom,geni-spi";
2083 #address-cells = <1>;
2084 #size-cells = <0>;
2085 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2086 clock-names = "se";
2088 power-domains = <&rpmhpd SC8280XP_CX>;
2092 interconnect-names = "qup-core", "qup-config", "qup-memory";
2096 dma-names = "tx",
2103 compatible = "qcom,geni-i2c";
2105 #address-cells = <1>;
2106 #size-cells = <0>;
2107 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2108 clock-names = "se";
2110 power-domains = <&rpmhpd SC8280XP_CX>;
2114 interconnect-names = "qup-core", "qup-config", "qup-memory";
2118 dma-names = "tx",
2125 compatible = "qcom,geni-spi";
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2129 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2130 clock-names = "se";
2132 power-domains = <&rpmhpd SC8280XP_CX>;
2136 interconnect-names = "qup-core", "qup-config", "qup-memory";
2140 dma-names = "tx",
2148 compatible = "qcom,prng-ee";
2151 clock-names = "core";
2156 compatible = "qcom,pcie-sc8280xp";
2163 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2164 #address-cells = <3>;
2165 #size-cells = <2>;
2168 bus-range = <0x00 0xff>;
2170 dma-coherent;
2172 linux,pci-domain = <6>;
2173 num-lanes = <1>;
2175 msi-map = <0x0 &its 0xe0000 0x10000>;
2181 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2183 #interrupt-cells = <1>;
2184 interrupt-map-mask = <0 0 0 0x7>;
2185 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2190 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
2191 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
2192 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
2193 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
2194 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
2195 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2196 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2197 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
2198 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
2199 clock-names = "aux",
2209 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
2210 assigned-clock-rates = <19200000>;
2214 interconnect-names = "pcie-mem", "cpu-pcie";
2216 resets = <&gcc GCC_PCIE_4_BCR>;
2217 reset-names = "pci";
2219 power-domains = <&gcc PCIE_4_GDSC>;
2220 required-opps = <&rpmhpd_opp_nom>;
2223 phy-names = "pciephy";
2230 bus-range = <0x01 0xff>;
2232 #address-cells = <3>;
2233 #size-cells = <2>;
2239 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
2242 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
2243 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
2244 <&gcc GCC_PCIE_4_CLKREF_CLK>,
2245 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
2246 <&gcc GCC_PCIE_4_PIPE_CLK>,
2247 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
2248 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2251 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
2252 assigned-clock-rates = <100000000>;
2254 power-domains = <&gcc PCIE_4_GDSC>;
2256 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
2257 reset-names = "phy";
2259 #clock-cells = <0>;
2260 clock-output-names = "pcie_4_pipe_clk";
2262 #phy-cells = <0>;
2269 compatible = "qcom,pcie-sc8280xp";
2276 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2277 #address-cells = <3>;
2278 #size-cells = <2>;
2281 bus-range = <0x00 0xff>;
2283 dma-coherent;
2285 linux,pci-domain = <5>;
2286 num-lanes = <2>;
2288 msi-map = <0x0 &its 0xd0000 0x10000>;
2294 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2296 #interrupt-cells = <1>;
2297 interrupt-map-mask = <0 0 0 0x7>;
2298 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
2303 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
2304 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
2305 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
2306 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
2307 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
2308 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2309 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2310 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2311 clock-names = "aux",
2320 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
2321 assigned-clock-rates = <19200000>;
2325 interconnect-names = "pcie-mem", "cpu-pcie";
2327 resets = <&gcc GCC_PCIE_3B_BCR>;
2328 reset-names = "pci";
2330 power-domains = <&gcc PCIE_3B_GDSC>;
2331 required-opps = <&rpmhpd_opp_nom>;
2334 phy-names = "pciephy";
2341 bus-range = <0x01 0xff>;
2343 #address-cells = <3>;
2344 #size-cells = <2>;
2350 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2353 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
2354 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
2355 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2356 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
2357 <&gcc GCC_PCIE_3B_PIPE_CLK>,
2358 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
2359 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2362 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
2363 assigned-clock-rates = <100000000>;
2365 power-domains = <&gcc PCIE_3B_GDSC>;
2367 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
2368 reset-names = "phy";
2370 #clock-cells = <0>;
2371 clock-output-names = "pcie_3b_pipe_clk";
2373 #phy-cells = <0>;
2380 compatible = "qcom,pcie-sc8280xp";
2387 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2388 #address-cells = <3>;
2389 #size-cells = <2>;
2392 bus-range = <0x00 0xff>;
2394 dma-coherent;
2396 linux,pci-domain = <4>;
2397 num-lanes = <4>;
2399 msi-map = <0x0 &its 0xc0000 0x10000>;
2405 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2407 #interrupt-cells = <1>;
2408 interrupt-map-mask = <0 0 0 0x7>;
2409 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
2414 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2415 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2416 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
2417 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
2418 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2420 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2421 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2422 clock-names = "aux",
2431 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2432 assigned-clock-rates = <19200000>;
2436 interconnect-names = "pcie-mem", "cpu-pcie";
2438 resets = <&gcc GCC_PCIE_3A_BCR>;
2439 reset-names = "pci";
2441 power-domains = <&gcc PCIE_3A_GDSC>;
2442 required-opps = <&rpmhpd_opp_nom>;
2445 phy-names = "pciephy";
2452 bus-range = <0x01 0xff>;
2454 #address-cells = <3>;
2455 #size-cells = <2>;
2461 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2465 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2466 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2467 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2468 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2469 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2470 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2471 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2474 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2475 assigned-clock-rates = <100000000>;
2477 power-domains = <&gcc PCIE_3A_GDSC>;
2479 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2480 reset-names = "phy";
2482 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2484 #clock-cells = <0>;
2485 clock-output-names = "pcie_3a_pipe_clk";
2487 #phy-cells = <0>;
2494 compatible = "qcom,pcie-sc8280xp";
2501 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2502 #address-cells = <3>;
2503 #size-cells = <2>;
2506 bus-range = <0x00 0xff>;
2508 dma-coherent;
2510 linux,pci-domain = <3>;
2511 num-lanes = <2>;
2513 msi-map = <0x0 &its 0xb0000 0x10000>;
2519 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2521 #interrupt-cells = <1>;
2522 interrupt-map-mask = <0 0 0 0x7>;
2523 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2528 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2529 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2530 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2531 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2532 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2533 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2534 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2535 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2536 clock-names = "aux",
2545 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2546 assigned-clock-rates = <19200000>;
2550 interconnect-names = "pcie-mem", "cpu-pcie";
2552 resets = <&gcc GCC_PCIE_2B_BCR>;
2553 reset-names = "pci";
2555 power-domains = <&gcc PCIE_2B_GDSC>;
2556 required-opps = <&rpmhpd_opp_nom>;
2559 phy-names = "pciephy";
2566 bus-range = <0x01 0xff>;
2568 #address-cells = <3>;
2569 #size-cells = <2>;
2575 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2578 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2579 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2580 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2581 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2582 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2583 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2584 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2587 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2588 assigned-clock-rates = <100000000>;
2590 power-domains = <&gcc PCIE_2B_GDSC>;
2592 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2593 reset-names = "phy";
2595 #clock-cells = <0>;
2596 clock-output-names = "pcie_2b_pipe_clk";
2598 #phy-cells = <0>;
2605 compatible = "qcom,pcie-sc8280xp";
2612 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2613 #address-cells = <3>;
2614 #size-cells = <2>;
2617 bus-range = <0x00 0xff>;
2619 dma-coherent;
2621 linux,pci-domain = <2>;
2622 num-lanes = <4>;
2624 msi-map = <0x0 &its 0xa0000 0x10000>;
2630 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2632 #interrupt-cells = <1>;
2633 interrupt-map-mask = <0 0 0 0x7>;
2634 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2639 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2640 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2641 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2642 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2643 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2644 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2645 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2646 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2647 clock-names = "aux",
2656 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2657 assigned-clock-rates = <19200000>;
2661 interconnect-names = "pcie-mem", "cpu-pcie";
2663 resets = <&gcc GCC_PCIE_2A_BCR>;
2664 reset-names = "pci";
2666 power-domains = <&gcc PCIE_2A_GDSC>;
2667 required-opps = <&rpmhpd_opp_nom>;
2670 phy-names = "pciephy";
2677 bus-range = <0x01 0xff>;
2679 #address-cells = <3>;
2680 #size-cells = <2>;
2686 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2690 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2691 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2692 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2693 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2694 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2695 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2696 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2699 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2700 assigned-clock-rates = <100000000>;
2702 power-domains = <&gcc PCIE_2A_GDSC>;
2704 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2705 reset-names = "phy";
2707 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2709 #clock-cells = <0>;
2710 clock-output-names = "pcie_2a_pipe_clk";
2712 #phy-cells = <0>;
2718 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2719 "jedec,ufs-2.0";
2723 phy-names = "ufsphy";
2724 lanes-per-direction = <2>;
2725 #reset-cells = <1>;
2726 resets = <&gcc GCC_UFS_PHY_BCR>;
2727 reset-names = "rst";
2729 power-domains = <&gcc UFS_PHY_GDSC>;
2730 required-opps = <&rpmhpd_opp_nom>;
2733 dma-coherent;
2735 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2736 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2737 <&gcc GCC_UFS_PHY_AHB_CLK>,
2738 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2739 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2740 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2741 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2742 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2743 clock-names = "core_clk",
2751 freq-table-hz = <75000000 300000000>,
2763 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2767 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2768 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
2769 clock-names = "ref",
2773 power-domains = <&gcc UFS_PHY_GDSC>;
2776 reset-names = "ufsphy";
2778 #phy-cells = <0>;
2784 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2785 "jedec,ufs-2.0";
2789 phy-names = "ufsphy";
2790 lanes-per-direction = <2>;
2791 #reset-cells = <1>;
2792 resets = <&gcc GCC_UFS_CARD_BCR>;
2793 reset-names = "rst";
2795 power-domains = <&gcc UFS_CARD_GDSC>;
2798 dma-coherent;
2800 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2801 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2802 <&gcc GCC_UFS_CARD_AHB_CLK>,
2803 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2804 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2805 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2806 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2807 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2808 clock-names = "core_clk",
2816 freq-table-hz = <75000000 300000000>,
2828 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2832 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
2833 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
2834 clock-names = "ref",
2838 power-domains = <&gcc UFS_CARD_GDSC>;
2841 reset-names = "ufsphy";
2843 #phy-cells = <0>;
2849 compatible = "qcom,tcsr-mutex";
2851 #hwlock-cells = <1>;
2855 compatible = "qcom,sc8280xp-tcsr", "syscon";
2860 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas";
2863 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2868 interrupt-names = "wdog",
2872 "stop-ack";
2875 clock-names = "xo";
2877 power-domains = <&rpmhpd SC8280XP_LCX>,
2879 power-domain-names = "lcx", "lmx";
2881 memory-region = <&pil_slpi_mem>;
2885 qcom,smem-states = <&smp2p_slpi_out 0>;
2886 qcom,smem-state-names = "stop";
2890 glink-edge {
2891 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2898 qcom,remote-pid = <3>;
2902 qcom,glink-channels = "fastrpcglink-apps-dsp";
2904 qcom,non-secure-domain;
2905 #address-cells = <1>;
2906 #size-cells = <0>;
2908 compute-cb@1 {
2909 compatible = "qcom,fastrpc-compute-cb";
2914 compute-cb@2 {
2915 compatible = "qcom,fastrpc-compute-cb";
2920 compute-cb@3 {
2921 compatible = "qcom,fastrpc-compute-cb";
2930 compatible = "qcom,sc8280xp-adsp-pas";
2933 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2939 interrupt-names = "wdog", "fatal", "ready",
2940 "handover", "stop-ack", "shutdown-ack";
2943 clock-names = "xo";
2945 power-domains = <&rpmhpd SC8280XP_LCX>,
2947 power-domain-names = "lcx", "lmx";
2949 memory-region = <&pil_adsp_mem>;
2953 qcom,smem-states = <&smp2p_adsp_out 0>;
2954 qcom,smem-state-names = "stop";
2958 remoteproc_adsp_glink: glink-edge {
2959 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2966 qcom,remote-pid = <2>;
2970 qcom,glink-channels = "adsp_apps";
2973 #address-cells = <1>;
2974 #size-cells = <0>;
2979 #sound-dai-cells = <0>;
2980 qcom,protection-domain = "avs/audio",
2983 compatible = "qcom,q6apm-dais";
2988 compatible = "qcom,q6apm-lpass-dais";
2989 #sound-dai-cells = <1>;
2996 qcom,protection-domain = "avs/audio",
2998 q6prmcc: clock-controller {
2999 compatible = "qcom,q6prm-lpass-clocks";
3000 #clock-cells = <2>;
3008 compatible = "qcom,sc8280xp-lpass-rx-macro";
3015 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
3016 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3018 assigned-clock-rates = <19200000>, <19200000>;
3020 clock-output-names = "mclk";
3021 #clock-cells = <0>;
3022 #sound-dai-cells = <1>;
3024 pinctrl-names = "default";
3025 pinctrl-0 = <&rx_swr_default>;
3031 compatible = "qcom,soundwire-v1.6.0";
3035 clock-names = "iface";
3037 reset-names = "swr_audio_cgcr";
3040 qcom,din-ports = <0>;
3041 qcom,dout-ports = <5>;
3043 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
3044 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
3045 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
3046 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
3047 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
3048 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
3049 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
3050 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
3051 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3053 #sound-dai-cells = <1>;
3054 #address-cells = <2>;
3055 #size-cells = <0>;
3061 compatible = "qcom,sc8280xp-lpass-tx-macro";
3063 pinctrl-names = "default";
3064 pinctrl-0 = <&tx_swr_default>;
3071 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
3072 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3074 assigned-clock-rates = <19200000>, <19200000>;
3075 clock-output-names = "mclk";
3077 #clock-cells = <0>;
3078 #sound-dai-cells = <1>;
3084 compatible = "qcom,sc8280xp-lpass-wsa-macro";
3091 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
3092 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3094 assigned-clock-rates = <19200000>, <19200000>;
3096 #clock-cells = <0>;
3097 clock-output-names = "mclk";
3098 #sound-dai-cells = <1>;
3100 pinctrl-names = "default";
3101 pinctrl-0 = <&wsa_swr_default>;
3108 compatible = "qcom,soundwire-v1.6.0";
3111 clock-names = "iface";
3113 reset-names = "swr_audio_cgcr";
3116 qcom,din-ports = <2>;
3117 qcom,dout-ports = <6>;
3119 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
3120 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
3121 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
3122 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3123 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3124 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3125 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
3126 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3127 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3129 #sound-dai-cells = <1>;
3130 #address-cells = <2>;
3131 #size-cells = <0>;
3136 lpass_audiocc: clock-controller@32a9000 {
3137 compatible = "qcom,sc8280xp-lpassaudiocc";
3139 #clock-cells = <1>;
3140 #reset-cells = <1>;
3144 compatible = "qcom,soundwire-v1.6.0";
3148 interrupt-names = "core", "wakeup";
3151 clock-names = "iface";
3153 reset-names = "swr_audio_cgcr";
3155 #sound-dai-cells = <1>;
3156 #address-cells = <2>;
3157 #size-cells = <0>;
3159 qcom,din-ports = <4>;
3160 qcom,dout-ports = <0>;
3161 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3162 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
3163 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3164 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3165 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3166 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3167 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3168 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3169 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
3175 compatible = "qcom,sc8280xp-lpass-va-macro";
3181 clock-names = "mclk", "macro", "dcodec", "npl";
3182 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3183 assigned-clock-rates = <19200000>;
3185 #clock-cells = <0>;
3186 clock-output-names = "fsgen";
3187 #sound-dai-cells = <1>;
3193 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
3196 gpio-controller;
3197 #gpio-cells = <2>;
3198 gpio-ranges = <&lpass_tlmm 0 0 19>;
3202 clock-names = "core", "audio";
3206 tx_swr_default: tx-swr-default-state {
3207 clk-pins {
3210 drive-strength = <2>;
3211 slew-rate = <1>;
3212 bias-disable;
3215 data-pins {
3218 drive-strength = <2>;
3219 slew-rate = <1>;
3220 bias-bus-hold;
3224 rx_swr_default: rx-swr-default-state {
3225 clk-pins {
3228 drive-strength = <2>;
3229 slew-rate = <1>;
3230 bias-disable;
3233 data-pins {
3236 drive-strength = <2>;
3237 slew-rate = <1>;
3238 bias-bus-hold;
3242 dmic01_default: dmic01-default-state {
3243 clk-pins {
3246 drive-strength = <8>;
3247 output-high;
3250 data-pins {
3253 drive-strength = <8>;
3254 input-enable;
3258 dmic01_sleep: dmic01-sleep-state {
3259 clk-pins {
3262 drive-strength = <2>;
3263 bias-disable;
3264 output-low;
3267 data-pins {
3270 drive-strength = <2>;
3271 bias-pull-down;
3272 input-enable;
3276 dmic23_default: dmic23-default-state {
3277 clk-pins {
3280 drive-strength = <8>;
3281 output-high;
3284 data-pins {
3287 drive-strength = <8>;
3288 input-enable;
3292 dmic23_sleep: dmic23-sleep-state {
3293 clk-pins {
3296 drive-strength = <2>;
3297 bias-disable;
3298 output-low;
3301 data-pins {
3304 drive-strength = <2>;
3305 bias-pull-down;
3306 input-enable;
3310 wsa_swr_default: wsa-swr-default-state {
3311 clk-pins {
3314 drive-strength = <2>;
3315 slew-rate = <1>;
3316 bias-disable;
3319 data-pins {
3322 drive-strength = <2>;
3323 slew-rate = <1>;
3324 bias-bus-hold;
3328 wsa2_swr_default: wsa2-swr-default-state {
3329 clk-pins {
3332 drive-strength = <2>;
3333 slew-rate = <1>;
3334 bias-disable;
3337 data-pins {
3340 drive-strength = <2>;
3341 slew-rate = <1>;
3342 bias-bus-hold;
3347 lpasscc: clock-controller@33e0000 {
3348 compatible = "qcom,sc8280xp-lpasscc";
3350 #clock-cells = <1>;
3351 #reset-cells = <1>;
3355 compatible = "qcom,adreno-690.0", "qcom,adreno";
3360 reg-names = "kgsl_3d0_reg_memory",
3365 operating-points-v2 = <&gpu_opp_table>;
3369 interconnect-names = "gfx-mem";
3370 #cooling-cells = <2>;
3374 gpu_zap_shader: zap-shader {
3375 memory-region = <&pil_gpu_mem>;
3378 gpu_opp_table: opp-table {
3379 compatible = "operating-points-v2";
3381 opp-270000000 {
3382 opp-hz = /bits/ 64 <270000000>;
3383 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3384 opp-peak-kBps = <451000>;
3387 opp-410000000 {
3388 opp-hz = /bits/ 64 <410000000>;
3389 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3390 opp-peak-kBps = <1555000>;
3393 opp-500000000 {
3394 opp-hz = /bits/ 64 <500000000>;
3395 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3396 opp-peak-kBps = <1555000>;
3399 opp-547000000 {
3400 opp-hz = /bits/ 64 <547000000>;
3401 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3402 opp-peak-kBps = <1555000>;
3405 opp-606000000 {
3406 opp-hz = /bits/ 64 <606000000>;
3407 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3408 opp-peak-kBps = <2736000>;
3411 opp-640000000 {
3412 opp-hz = /bits/ 64 <640000000>;
3413 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3414 opp-peak-kBps = <2736000>;
3417 opp-655000000 {
3418 opp-hz = /bits/ 64 <655000000>;
3419 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3420 opp-peak-kBps = <2736000>;
3423 opp-690000000 {
3424 opp-hz = /bits/ 64 <690000000>;
3425 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3426 opp-peak-kBps = <2736000>;
3432 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
3436 reg-names = "gmu", "rscc", "gmu_pdc";
3439 interrupt-names = "hfi", "gmu";
3442 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3443 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3447 clock-names = "gmu",
3454 power-domains = <&gpucc GPU_CC_CX_GDSC>,
3456 power-domain-names = "cx",
3459 operating-points-v2 = <&gmu_opp_table>;
3461 gmu_opp_table: opp-table {
3462 compatible = "operating-points-v2";
3464 opp-200000000 {
3465 opp-hz = /bits/ 64 <200000000>;
3466 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3469 opp-500000000 {
3470 opp-hz = /bits/ 64 <500000000>;
3471 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3476 gpucc: clock-controller@3d90000 {
3477 compatible = "qcom,sc8280xp-gpucc";
3480 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3481 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3482 clock-names = "bi_tcxo",
3486 power-domains = <&rpmhpd SC8280XP_GFX>;
3487 #clock-cells = <1>;
3488 #reset-cells = <1>;
3489 #power-domain-cells = <1>;
3493 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
3494 "qcom,smmu-500", "arm,mmu-500";
3496 #iommu-cells = <2>;
3497 #global-interrupts = <2>;
3513 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3514 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3520 clock-names = "gcc_gpu_memnoc_gfx_clk",
3528 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3529 dma-coherent;
3533 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3538 interrupt-names = "hc_irq", "pwr_irq";
3540 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3541 <&gcc GCC_SDCC2_APPS_CLK>,
3543 clock-names = "iface", "core", "xo";
3544 resets = <&gcc GCC_SDCC2_BCR>;
3547 interconnect-names = "sdhc-ddr","cpu-sdhc";
3549 power-domains = <&rpmhpd SC8280XP_CX>;
3550 operating-points-v2 = <&sdc2_opp_table>;
3551 bus-width = <4>;
3552 dma-coherent;
3556 sdc2_opp_table: opp-table {
3557 compatible = "operating-points-v2";
3559 opp-100000000 {
3560 opp-hz = /bits/ 64 <100000000>;
3561 required-opps = <&rpmhpd_opp_low_svs>;
3562 opp-peak-kBps = <1800000 400000>;
3563 opp-avg-kBps = <100000 0>;
3566 opp-202000000 {
3567 opp-hz = /bits/ 64 <202000000>;
3568 required-opps = <&rpmhpd_opp_svs_l1>;
3569 opp-peak-kBps = <5400000 1600000>;
3570 opp-avg-kBps = <200000 0>;
3576 compatible = "qcom,sc8280xp-usb-hs-phy",
3577 "qcom,usb-snps-hs-5nm-phy";
3580 clock-names = "ref";
3581 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3583 #phy-cells = <0>;
3589 compatible = "qcom,sc8280xp-usb-hs-phy",
3590 "qcom,usb-snps-hs-5nm-phy";
3592 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
3593 clock-names = "ref";
3594 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
3596 #phy-cells = <0>;
3602 compatible = "qcom,sc8280xp-usb-hs-phy",
3603 "qcom,usb-snps-hs-5nm-phy";
3605 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
3606 clock-names = "ref";
3607 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
3609 #phy-cells = <0>;
3615 compatible = "qcom,sc8280xp-usb-hs-phy",
3616 "qcom,usb-snps-hs-5nm-phy";
3618 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
3619 clock-names = "ref";
3620 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
3622 #phy-cells = <0>;
3628 compatible = "qcom,sc8280xp-usb-hs-phy",
3629 "qcom,usb-snps-hs-5nm-phy";
3631 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
3632 clock-names = "ref";
3633 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
3635 #phy-cells = <0>;
3641 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3644 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3645 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3646 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3647 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3648 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3650 power-domains = <&gcc USB30_PRIM_GDSC>;
3652 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3653 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3654 reset-names = "phy", "common";
3656 #clock-cells = <1>;
3657 #phy-cells = <1>;
3662 #address-cells = <1>;
3663 #size-cells = <0>;
3675 remote-endpoint = <&usb_0_dwc3_ss>;
3688 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
3691 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3692 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
3693 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3694 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
3695 clock-names = "aux", "ref", "com_aux", "pipe";
3697 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
3698 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
3699 reset-names = "phy", "phy_phy";
3701 power-domains = <&gcc USB30_MP_GDSC>;
3703 #clock-cells = <0>;
3704 clock-output-names = "usb2_phy0_pipe_clk";
3706 #phy-cells = <0>;
3712 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
3715 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3716 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
3717 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3718 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
3719 clock-names = "aux", "ref", "com_aux", "pipe";
3721 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
3722 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
3723 reset-names = "phy", "phy_phy";
3725 power-domains = <&gcc USB30_MP_GDSC>;
3727 #clock-cells = <0>;
3728 clock-output-names = "usb2_phy1_pipe_clk";
3730 #phy-cells = <0>;
3736 compatible = "qcom,sc8280xp-refgen-regulator",
3737 "qcom,sm8250-refgen-regulator";
3742 compatible = "qcom,sc8280xp-usb-hs-phy",
3743 "qcom,usb-snps-hs-5nm-phy";
3745 #phy-cells = <0>;
3748 clock-names = "ref";
3750 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3756 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3759 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3760 <&gcc GCC_USB4_CLKREF_CLK>,
3761 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3762 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3763 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3765 power-domains = <&gcc USB30_SEC_GDSC>;
3767 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3768 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3769 reset-names = "phy", "common";
3771 #clock-cells = <1>;
3772 #phy-cells = <1>;
3777 #address-cells = <1>;
3778 #size-cells = <0>;
3790 remote-endpoint = <&usb_1_dwc3_ss>;
3803 compatible = "qcom,sc8280xp-dp-phy";
3811 clock-names = "aux", "cfg_ahb";
3812 power-domains = <&rpmhpd SC8280XP_MX>;
3814 #clock-cells = <1>;
3815 #phy-cells = <0>;
3821 compatible = "qcom,sc8280xp-dp-phy";
3829 clock-names = "aux", "cfg_ahb";
3830 power-domains = <&rpmhpd SC8280XP_MX>;
3832 #clock-cells = <1>;
3833 #phy-cells = <0>;
3839 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3846 operating-points-v2 = <&llcc_bwmon_opp_table>;
3848 llcc_bwmon_opp_table: opp-table {
3849 compatible = "operating-points-v2";
3851 opp-0 {
3852 opp-peak-kBps = <762000>;
3854 opp-1 {
3855 opp-peak-kBps = <1720000>;
3857 opp-2 {
3858 opp-peak-kBps = <2086000>;
3860 opp-3 {
3861 opp-peak-kBps = <2597000>;
3863 opp-4 {
3864 opp-peak-kBps = <2929000>;
3866 opp-5 {
3867 opp-peak-kBps = <3879000>;
3869 opp-6 {
3870 opp-peak-kBps = <5161000>;
3872 opp-7 {
3873 opp-peak-kBps = <5931000>;
3875 opp-8 {
3876 opp-peak-kBps = <6515000>;
3878 opp-9 {
3879 opp-peak-kBps = <7980000>;
3881 opp-10 {
3882 opp-peak-kBps = <8136000>;
3884 opp-11 {
3885 opp-peak-kBps = <10437000>;
3887 opp-12 {
3888 opp-peak-kBps = <12191000>;
3894 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3900 operating-points-v2 = <&cpu_bwmon_opp_table>;
3902 cpu_bwmon_opp_table: opp-table {
3903 compatible = "operating-points-v2";
3905 opp-0 {
3906 opp-peak-kBps = <2288000>;
3908 opp-1 {
3909 opp-peak-kBps = <4577000>;
3911 opp-2 {
3912 opp-peak-kBps = <7110000>;
3914 opp-3 {
3915 opp-peak-kBps = <9155000>;
3917 opp-4 {
3918 opp-peak-kBps = <12298000>;
3920 opp-5 {
3921 opp-peak-kBps = <14236000>;
3923 opp-6 {
3924 opp-peak-kBps = <15258001>;
3929 system-cache-controller@9200000 {
3930 compatible = "qcom,sc8280xp-llcc";
3936 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3943 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
3945 #address-cells = <2>;
3946 #size-cells = <2>;
3949 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
3950 <&gcc GCC_USB30_MP_MASTER_CLK>,
3951 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
3952 <&gcc GCC_USB30_MP_SLEEP_CLK>,
3953 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3954 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3955 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3956 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3957 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3958 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3961 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3962 <&gcc GCC_USB30_MP_MASTER_CLK>;
3963 assigned-clock-rates = <19200000>, <200000000>;
3965 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3984 interrupt-names = "pwr_event_1", "pwr_event_2",
3994 power-domains = <&gcc USB30_MP_GDSC>;
3995 required-opps = <&rpmhpd_opp_nom>;
3997 resets = <&gcc GCC_USB30_MP_BCR>;
4001 interconnect-names = "usb-ddr", "apps-usb";
4003 wakeup-source;
4016 phy-names = "usb2-0", "usb3-0",
4017 "usb2-1", "usb3-1",
4018 "usb2-2",
4019 "usb2-3";
4021 snps,dis-u1-entry-quirk;
4022 snps,dis-u2-entry-quirk;
4027 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
4029 #address-cells = <2>;
4030 #size-cells = <2>;
4033 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4034 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4035 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4036 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4037 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4038 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4039 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
4040 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
4041 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4042 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
4045 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4046 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4047 assigned-clock-rates = <19200000>, <200000000>;
4049 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
4054 interrupt-names = "pwr_event",
4060 power-domains = <&gcc USB30_PRIM_GDSC>;
4061 required-opps = <&rpmhpd_opp_nom>;
4063 resets = <&gcc GCC_USB30_PRIM_BCR>;
4067 interconnect-names = "usb-ddr", "apps-usb";
4069 wakeup-source;
4079 phy-names = "usb2-phy", "usb3-phy";
4080 snps,dis-u1-entry-quirk;
4081 snps,dis-u2-entry-quirk;
4084 #address-cells = <1>;
4085 #size-cells = <0>;
4098 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
4106 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
4108 #address-cells = <2>;
4109 #size-cells = <2>;
4112 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4113 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4114 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4115 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4116 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4117 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4118 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
4119 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
4120 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4121 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
4124 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4125 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4126 assigned-clock-rates = <19200000>, <200000000>;
4128 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
4133 interrupt-names = "pwr_event",
4139 power-domains = <&gcc USB30_SEC_GDSC>;
4140 required-opps = <&rpmhpd_opp_nom>;
4142 resets = <&gcc GCC_USB30_SEC_BCR>;
4146 interconnect-names = "usb-ddr", "apps-usb";
4148 wakeup-source;
4158 phy-names = "usb2-phy", "usb3-phy";
4159 snps,dis-u1-entry-quirk;
4160 snps,dis-u2-entry-quirk;
4163 #address-cells = <1>;
4164 #size-cells = <0>;
4177 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4185 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
4194 clock-names = "camnoc_axi",
4199 power-domains = <&camcc TITAN_TOP_GDSC>;
4201 pinctrl-0 = <&cci0_default>;
4202 pinctrl-1 = <&cci0_sleep>;
4203 pinctrl-names = "default", "sleep";
4205 #address-cells = <1>;
4206 #size-cells = <0>;
4210 cci0_i2c0: i2c-bus@0 {
4212 clock-frequency = <1000000>;
4213 #address-cells = <1>;
4214 #size-cells = <0>;
4217 cci0_i2c1: i2c-bus@1 {
4219 clock-frequency = <1000000>;
4220 #address-cells = <1>;
4221 #size-cells = <0>;
4226 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
4235 clock-names = "camnoc_axi",
4240 power-domains = <&camcc TITAN_TOP_GDSC>;
4242 pinctrl-0 = <&cci1_default>;
4243 pinctrl-1 = <&cci1_sleep>;
4244 pinctrl-names = "default", "sleep";
4246 #address-cells = <1>;
4247 #size-cells = <0>;
4251 cci1_i2c0: i2c-bus@0 {
4253 clock-frequency = <1000000>;
4254 #address-cells = <1>;
4255 #size-cells = <0>;
4258 cci1_i2c1: i2c-bus@1 {
4260 clock-frequency = <1000000>;
4261 #address-cells = <1>;
4262 #size-cells = <0>;
4267 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
4276 clock-names = "camnoc_axi",
4280 power-domains = <&camcc TITAN_TOP_GDSC>;
4282 pinctrl-0 = <&cci2_default>;
4283 pinctrl-1 = <&cci2_sleep>;
4284 pinctrl-names = "default", "sleep";
4286 #address-cells = <1>;
4287 #size-cells = <0>;
4291 cci2_i2c0: i2c-bus@0 {
4293 clock-frequency = <1000000>;
4294 #address-cells = <1>;
4295 #size-cells = <0>;
4298 cci2_i2c1: i2c-bus@1 {
4300 clock-frequency = <1000000>;
4301 #address-cells = <1>;
4302 #size-cells = <0>;
4307 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
4316 clock-names = "camnoc_axi",
4321 power-domains = <&camcc TITAN_TOP_GDSC>;
4323 pinctrl-0 = <&cci3_default>;
4324 pinctrl-1 = <&cci3_sleep>;
4325 pinctrl-names = "default", "sleep";
4327 #address-cells = <1>;
4328 #size-cells = <0>;
4332 cci3_i2c0: i2c-bus@0 {
4334 clock-frequency = <1000000>;
4335 #address-cells = <1>;
4336 #size-cells = <0>;
4339 cci3_i2c1: i2c-bus@1 {
4341 clock-frequency = <1000000>;
4342 #address-cells = <1>;
4343 #size-cells = <0>;
4348 compatible = "qcom,sc8280xp-camss";
4370 reg-names = "csiphy2",
4411 interrupt-names = "csid1_lite",
4432 power-domains = <&camcc IFE_0_GDSC>,
4437 power-domain-names = "ife0",
4481 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4482 <&gcc GCC_CAMERA_SF_AXI_CLK>;
4483 clock-names = "camnoc_axi",
4545 interconnect-names = "cam_ahb",
4553 #address-cells = <1>;
4554 #size-cells = <0>;
4558 #address-cells = <1>;
4559 #size-cells = <0>;
4564 #address-cells = <1>;
4565 #size-cells = <0>;
4570 #address-cells = <1>;
4571 #size-cells = <0>;
4576 #address-cells = <1>;
4577 #size-cells = <0>;
4582 camcc: clock-controller@ad00000 {
4583 compatible = "qcom,sc8280xp-camcc";
4585 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4589 power-domains = <&rpmhpd SC8280XP_MMCX>;
4590 required-opps = <&rpmhpd_opp_low_svs>;
4591 #clock-cells = <1>;
4592 #reset-cells = <1>;
4593 #power-domain-cells = <1>;
4596 mdss0: display-subsystem@ae00000 {
4597 compatible = "qcom,sc8280xp-mdss";
4599 reg-names = "mdss";
4601 clocks = <&gcc GCC_DISP_AHB_CLK>,
4604 clock-names = "iface",
4610 interconnect-names = "mdp0-mem", "mdp1-mem";
4612 power-domains = <&dispcc0 MDSS_GDSC>;
4615 interrupt-controller;
4616 #interrupt-cells = <1>;
4617 #address-cells = <2>;
4618 #size-cells = <2>;
4623 mdss0_mdp: display-controller@ae01000 {
4624 compatible = "qcom,sc8280xp-dpu";
4627 reg-names = "mdp", "vbif";
4629 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4630 <&gcc GCC_DISP_SF_AXI_CLK>,
4635 clock-names = "bus",
4641 interrupt-parent = <&mdss0>;
4643 power-domains = <&rpmhpd SC8280XP_MMCX>;
4645 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4646 assigned-clock-rates = <19200000>;
4647 operating-points-v2 = <&mdss0_mdp_opp_table>;
4650 #address-cells = <1>;
4651 #size-cells = <0>;
4656 remote-endpoint = <&mdss0_dp0_in>;
4663 remote-endpoint = <&mdss0_dp1_in>;
4670 remote-endpoint = <&mdss0_dp3_in>;
4677 remote-endpoint = <&mdss0_dp2_in>;
4682 mdss0_mdp_opp_table: opp-table {
4683 compatible = "operating-points-v2";
4685 opp-200000000 {
4686 opp-hz = /bits/ 64 <200000000>;
4687 required-opps = <&rpmhpd_opp_low_svs>;
4690 opp-300000000 {
4691 opp-hz = /bits/ 64 <300000000>;
4692 required-opps = <&rpmhpd_opp_svs>;
4695 opp-375000000 {
4696 opp-hz = /bits/ 64 <375000000>;
4697 required-opps = <&rpmhpd_opp_svs_l1>;
4700 opp-500000000 {
4701 opp-hz = /bits/ 64 <500000000>;
4702 required-opps = <&rpmhpd_opp_nom>;
4704 opp-600000000 {
4705 opp-hz = /bits/ 64 <600000000>;
4706 required-opps = <&rpmhpd_opp_turbo_l1>;
4711 mdss0_dp0: displayport-controller@ae90000 {
4712 compatible = "qcom,sc8280xp-dp";
4718 interrupt-parent = <&mdss0>;
4726 clock-names = "core_iface", "core_aux",
4732 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4735 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4740 phy-names = "dp";
4742 #sound-dai-cells = <0>;
4744 operating-points-v2 = <&mdss0_dp0_opp_table>;
4745 power-domains = <&rpmhpd SC8280XP_MMCX>;
4750 #address-cells = <1>;
4751 #size-cells = <0>;
4757 remote-endpoint = <&mdss0_intf0_out>;
4769 mdss0_dp0_opp_table: opp-table {
4770 compatible = "operating-points-v2";
4772 opp-160000000 {
4773 opp-hz = /bits/ 64 <160000000>;
4774 required-opps = <&rpmhpd_opp_low_svs>;
4777 opp-270000000 {
4778 opp-hz = /bits/ 64 <270000000>;
4779 required-opps = <&rpmhpd_opp_svs>;
4782 opp-540000000 {
4783 opp-hz = /bits/ 64 <540000000>;
4784 required-opps = <&rpmhpd_opp_svs_l1>;
4787 opp-810000000 {
4788 opp-hz = /bits/ 64 <810000000>;
4789 required-opps = <&rpmhpd_opp_nom>;
4794 mdss0_dp1: displayport-controller@ae98000 {
4795 compatible = "qcom,sc8280xp-dp";
4801 interrupt-parent = <&mdss0>;
4809 clock-names = "core_iface", "core_aux",
4814 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4817 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4822 phy-names = "dp";
4824 #sound-dai-cells = <0>;
4826 operating-points-v2 = <&mdss0_dp1_opp_table>;
4827 power-domains = <&rpmhpd SC8280XP_MMCX>;
4832 #address-cells = <1>;
4833 #size-cells = <0>;
4839 remote-endpoint = <&mdss0_intf4_out>;
4851 mdss0_dp1_opp_table: opp-table {
4852 compatible = "operating-points-v2";
4854 opp-160000000 {
4855 opp-hz = /bits/ 64 <160000000>;
4856 required-opps = <&rpmhpd_opp_low_svs>;
4859 opp-270000000 {
4860 opp-hz = /bits/ 64 <270000000>;
4861 required-opps = <&rpmhpd_opp_svs>;
4864 opp-540000000 {
4865 opp-hz = /bits/ 64 <540000000>;
4866 required-opps = <&rpmhpd_opp_svs_l1>;
4869 opp-810000000 {
4870 opp-hz = /bits/ 64 <810000000>;
4871 required-opps = <&rpmhpd_opp_nom>;
4876 mdss0_dp2: displayport-controller@ae9a000 {
4877 compatible = "qcom,sc8280xp-dp";
4890 clock-names = "core_iface", "core_aux",
4894 interrupt-parent = <&mdss0>;
4897 phy-names = "dp";
4898 power-domains = <&rpmhpd SC8280XP_MMCX>;
4900 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4903 assigned-clock-parents = <&mdss0_dp2_phy 0>,
4906 operating-points-v2 = <&mdss0_dp2_opp_table>;
4908 #sound-dai-cells = <0>;
4913 #address-cells = <1>;
4914 #size-cells = <0>;
4919 remote-endpoint = <&mdss0_intf6_out>;
4931 mdss0_dp2_opp_table: opp-table {
4932 compatible = "operating-points-v2";
4934 opp-160000000 {
4935 opp-hz = /bits/ 64 <160000000>;
4936 required-opps = <&rpmhpd_opp_low_svs>;
4939 opp-270000000 {
4940 opp-hz = /bits/ 64 <270000000>;
4941 required-opps = <&rpmhpd_opp_svs>;
4944 opp-540000000 {
4945 opp-hz = /bits/ 64 <540000000>;
4946 required-opps = <&rpmhpd_opp_svs_l1>;
4949 opp-810000000 {
4950 opp-hz = /bits/ 64 <810000000>;
4951 required-opps = <&rpmhpd_opp_nom>;
4956 mdss0_dp3: displayport-controller@aea0000 {
4957 compatible = "qcom,sc8280xp-dp";
4969 clock-names = "core_iface", "core_aux",
4972 interrupt-parent = <&mdss0>;
4975 phy-names = "dp";
4976 power-domains = <&rpmhpd SC8280XP_MMCX>;
4978 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4980 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4981 operating-points-v2 = <&mdss0_dp3_opp_table>;
4983 #sound-dai-cells = <0>;
4988 #address-cells = <1>;
4989 #size-cells = <0>;
4994 remote-endpoint = <&mdss0_intf5_out>;
5006 mdss0_dp3_opp_table: opp-table {
5007 compatible = "operating-points-v2";
5009 opp-160000000 {
5010 opp-hz = /bits/ 64 <160000000>;
5011 required-opps = <&rpmhpd_opp_low_svs>;
5014 opp-270000000 {
5015 opp-hz = /bits/ 64 <270000000>;
5016 required-opps = <&rpmhpd_opp_svs>;
5019 opp-540000000 {
5020 opp-hz = /bits/ 64 <540000000>;
5021 required-opps = <&rpmhpd_opp_svs_l1>;
5024 opp-810000000 {
5025 opp-hz = /bits/ 64 <810000000>;
5026 required-opps = <&rpmhpd_opp_nom>;
5033 compatible = "qcom,sc8280xp-dp-phy";
5041 clock-names = "aux", "cfg_ahb";
5042 power-domains = <&rpmhpd SC8280XP_MX>;
5044 #clock-cells = <1>;
5045 #phy-cells = <0>;
5051 compatible = "qcom,sc8280xp-dp-phy";
5059 clock-names = "aux", "cfg_ahb";
5060 power-domains = <&rpmhpd SC8280XP_MX>;
5062 #clock-cells = <1>;
5063 #phy-cells = <0>;
5068 dispcc0: clock-controller@af00000 {
5069 compatible = "qcom,sc8280xp-dispcc0";
5072 clocks = <&gcc GCC_DISP_AHB_CLK>,
5087 power-domains = <&rpmhpd SC8280XP_MMCX>;
5089 #clock-cells = <1>;
5090 #power-domain-cells = <1>;
5091 #reset-cells = <1>;
5096 pdc: interrupt-controller@b220000 {
5097 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
5099 qcom,pdc-ranges = <0 480 40>,
5156 #interrupt-cells = <2>;
5157 interrupt-parent = <&intc>;
5158 interrupt-controller;
5161 tsens2: thermal-sensor@c251000 {
5162 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
5166 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
5168 interrupt-names = "uplow", "critical";
5169 #thermal-sensor-cells = <1>;
5172 tsens3: thermal-sensor@c252000 {
5173 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
5177 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
5179 interrupt-names = "uplow", "critical";
5180 #thermal-sensor-cells = <1>;
5183 tsens0: thermal-sensor@c263000 {
5184 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
5188 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
5190 interrupt-names = "uplow", "critical";
5191 #thermal-sensor-cells = <1>;
5201 tsens1: thermal-sensor@c265000 {
5202 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
5206 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
5208 interrupt-names = "uplow", "critical";
5209 #thermal-sensor-cells = <1>;
5212 aoss_qmp: power-management@c300000 {
5213 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
5215 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
5218 #clock-cells = <0>;
5222 compatible = "qcom,rpmh-stats";
5228 compatible = "qcom,spmi-pmic-arb";
5234 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5235 interrupt-names = "periph_irq";
5236 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5239 #address-cells = <2>;
5240 #size-cells = <0>;
5241 interrupt-controller;
5242 #interrupt-cells = <4>;
5246 compatible = "qcom,sc8280xp-tlmm";
5249 gpio-controller;
5250 #gpio-cells = <2>;
5251 interrupt-controller;
5252 #interrupt-cells = <2>;
5253 gpio-ranges = <&tlmm 0 0 230>;
5254 wakeup-parent = <&pdc>;
5256 cci0_default: cci0-default-state {
5257 cci0_i2c0_default: cci0-i2c0-default-pins {
5261 drive-strength = <2>;
5262 bias-pull-up;
5265 cci0_i2c1_default: cci0-i2c1-default-pins {
5269 drive-strength = <2>;
5270 bias-pull-up;
5274 cci0_sleep: cci0-sleep-state {
5275 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5279 drive-strength = <2>;
5280 bias-pull-down;
5283 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5287 drive-strength = <2>;
5288 bias-pull-down;
5292 cci1_default: cci1-default-state {
5293 cci1_i2c0_default: cci1-i2c0-default-pins {
5297 drive-strength = <2>;
5298 bias-pull-up;
5301 cci1_i2c1_default: cci1-i2c1-default-pins {
5305 drive-strength = <2>;
5306 bias-pull-up;
5310 cci1_sleep: cci1-sleep-state {
5311 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5315 drive-strength = <2>;
5316 bias-pull-down;
5319 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5323 drive-strength = <2>;
5324 bias-pull-down;
5328 cci2_default: cci2-default-state {
5329 cci2_i2c0_default: cci2-i2c0-default-pins {
5333 drive-strength = <2>;
5334 bias-pull-up;
5337 cci2_i2c1_default: cci2-i2c1-default-pins {
5341 drive-strength = <2>;
5342 bias-pull-up;
5346 cci2_sleep: cci2-sleep-state {
5347 cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
5351 drive-strength = <2>;
5352 bias-pull-down;
5355 cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
5359 drive-strength = <2>;
5360 bias-pull-down;
5364 cci3_default: cci3-default-state {
5365 cci3_i2c0_default: cci3-i2c0-default-pins {
5369 drive-strength = <2>;
5370 bias-pull-up;
5373 cci3_i2c1_default: cci3-i2c1-default-pins {
5377 drive-strength = <2>;
5378 bias-pull-up;
5382 cci3_sleep: cci3-sleep-state {
5383 cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
5387 drive-strength = <2>;
5388 bias-pull-down;
5391 cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
5395 drive-strength = <2>;
5396 bias-pull-down;
5400 qup_uart18_default: qup-uart18-default-state {
5401 cts-pins {
5404 drive-strength = <2>;
5405 bias-disable;
5408 rts-pins {
5411 drive-strength = <2>;
5412 bias-disable;
5415 tx-pins {
5418 drive-strength = <2>;
5419 bias-disable;
5422 rx-pins {
5425 drive-strength = <2>;
5426 bias-disable;
5432 compatible = "arm,smmu-v3";
5434 #iommu-cells = <1>;
5438 interrupt-names = "eventq",
5440 "cmdq-sync";
5441 dma-coherent;
5446 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
5448 #iommu-cells = <2>;
5449 #global-interrupts = <2>;
5580 dma-coherent;
5583 intc: interrupt-controller@17a00000 {
5584 compatible = "arm,gic-v3";
5585 interrupt-controller;
5586 #interrupt-cells = <3>;
5590 #redistributor-regions = <1>;
5591 redistributor-stride = <0 0x20000>;
5593 #address-cells = <2>;
5594 #size-cells = <2>;
5597 its: msi-controller@17a40000 {
5598 compatible = "arm,gic-v3-its";
5600 msi-controller;
5601 #msi-cells = <1>;
5606 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5613 compatible = "arm,armv7-timer-mem";
5615 #address-cells = <1>;
5616 #size-cells = <1>;
5620 frame-number = <0>;
5628 frame-number = <1>;
5635 frame-number = <2>;
5642 frame-number = <3>;
5649 frame-number = <4>;
5656 frame-number = <5>;
5663 frame-number = <6>;
5671 compatible = "qcom,rpmh-rsc";
5675 reg-names = "drv-0", "drv-1", "drv-2";
5679 qcom,tcs-offset = <0xd00>;
5680 qcom,drv-id = <2>;
5681 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5684 power-domains = <&cluster_pd>;
5686 apps_bcm_voter: bcm-voter {
5687 compatible = "qcom,bcm-voter";
5690 rpmhcc: clock-controller {
5691 compatible = "qcom,sc8280xp-rpmh-clk";
5692 #clock-cells = <1>;
5693 clock-names = "xo";
5697 rpmhpd: power-controller {
5698 compatible = "qcom,sc8280xp-rpmhpd";
5699 #power-domain-cells = <1>;
5700 operating-points-v2 = <&rpmhpd_opp_table>;
5702 rpmhpd_opp_table: opp-table {
5703 compatible = "operating-points-v2";
5706 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5710 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5714 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5718 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5722 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5726 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5730 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5734 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5738 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5742 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5749 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5752 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5753 clock-names = "xo", "alternate";
5755 #interconnect-cells = <1>;
5759 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5762 reg-names = "freq-domain0", "freq-domain1";
5766 interrupt-names = "dcvsh-irq-0",
5767 "dcvsh-irq-1";
5769 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5770 clock-names = "xo", "alternate";
5772 #freq-domain-cells = <1>;
5773 #clock-cells = <1>;
5777 compatible = "qcom,sc8280xp-nsp0-pas";
5780 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5785 interrupt-names = "wdog", "fatal", "ready",
5786 "handover", "stop-ack";
5789 clock-names = "xo";
5791 power-domains = <&rpmhpd SC8280XP_NSP>;
5792 power-domain-names = "nsp";
5794 memory-region = <&pil_nsp0_mem>;
5796 qcom,smem-states = <&smp2p_nsp0_out 0>;
5797 qcom,smem-state-names = "stop";
5803 glink-edge {
5804 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5811 qcom,remote-pid = <5>;
5815 qcom,glink-channels = "fastrpcglink-apps-dsp";
5817 #address-cells = <1>;
5818 #size-cells = <0>;
5820 compute-cb@1 {
5821 compatible = "qcom,fastrpc-compute-cb";
5826 compute-cb@2 {
5827 compatible = "qcom,fastrpc-compute-cb";
5832 compute-cb@3 {
5833 compatible = "qcom,fastrpc-compute-cb";
5838 compute-cb@4 {
5839 compatible = "qcom,fastrpc-compute-cb";
5844 compute-cb@5 {
5845 compatible = "qcom,fastrpc-compute-cb";
5850 compute-cb@6 {
5851 compatible = "qcom,fastrpc-compute-cb";
5856 compute-cb@7 {
5857 compatible = "qcom,fastrpc-compute-cb";
5862 compute-cb@8 {
5863 compatible = "qcom,fastrpc-compute-cb";
5868 compute-cb@9 {
5869 compatible = "qcom,fastrpc-compute-cb";
5874 compute-cb@10 {
5875 compatible = "qcom,fastrpc-compute-cb";
5880 compute-cb@11 {
5881 compatible = "qcom,fastrpc-compute-cb";
5886 compute-cb@12 {
5887 compatible = "qcom,fastrpc-compute-cb";
5892 compute-cb@13 {
5893 compatible = "qcom,fastrpc-compute-cb";
5898 compute-cb@14 {
5899 compatible = "qcom,fastrpc-compute-cb";
5908 compatible = "qcom,sc8280xp-nsp1-pas";
5911 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5916 interrupt-names = "wdog", "fatal", "ready",
5917 "handover", "stop-ack";
5920 clock-names = "xo";
5922 power-domains = <&rpmhpd SC8280XP_NSP>;
5923 power-domain-names = "nsp";
5925 memory-region = <&pil_nsp1_mem>;
5927 qcom,smem-states = <&smp2p_nsp1_out 0>;
5928 qcom,smem-state-names = "stop";
5934 glink-edge {
5935 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5942 qcom,remote-pid = <12>;
5946 mdss1: display-subsystem@22000000 {
5947 compatible = "qcom,sc8280xp-mdss";
5949 reg-names = "mdss";
5951 clocks = <&gcc GCC_DISP_AHB_CLK>,
5954 clock-names = "iface",
5959 interconnect-names = "mdp0-mem", "mdp1-mem";
5963 power-domains = <&dispcc1 MDSS_GDSC>;
5966 interrupt-controller;
5967 #interrupt-cells = <1>;
5968 #address-cells = <2>;
5969 #size-cells = <2>;
5974 mdss1_mdp: display-controller@22001000 {
5975 compatible = "qcom,sc8280xp-dpu";
5978 reg-names = "mdp", "vbif";
5980 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5981 <&gcc GCC_DISP_SF_AXI_CLK>,
5986 clock-names = "bus",
5992 interrupt-parent = <&mdss1>;
5994 power-domains = <&rpmhpd SC8280XP_MMCX>;
5996 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5997 assigned-clock-rates = <19200000>;
5998 operating-points-v2 = <&mdss1_mdp_opp_table>;
6001 #address-cells = <1>;
6002 #size-cells = <0>;
6007 remote-endpoint = <&mdss1_dp0_in>;
6014 remote-endpoint = <&mdss1_dp1_in>;
6021 remote-endpoint = <&mdss1_dp3_in>;
6028 remote-endpoint = <&mdss1_dp2_in>;
6033 mdss1_mdp_opp_table: opp-table {
6034 compatible = "operating-points-v2";
6036 opp-200000000 {
6037 opp-hz = /bits/ 64 <200000000>;
6038 required-opps = <&rpmhpd_opp_low_svs>;
6041 opp-300000000 {
6042 opp-hz = /bits/ 64 <300000000>;
6043 required-opps = <&rpmhpd_opp_svs>;
6046 opp-375000000 {
6047 opp-hz = /bits/ 64 <375000000>;
6048 required-opps = <&rpmhpd_opp_svs_l1>;
6051 opp-500000000 {
6052 opp-hz = /bits/ 64 <500000000>;
6053 required-opps = <&rpmhpd_opp_nom>;
6055 opp-600000000 {
6056 opp-hz = /bits/ 64 <600000000>;
6057 required-opps = <&rpmhpd_opp_turbo_l1>;
6062 mdss1_dp0: displayport-controller@22090000 {
6063 compatible = "qcom,sc8280xp-dp";
6076 clock-names = "core_iface", "core_aux",
6080 interrupt-parent = <&mdss1>;
6083 phy-names = "dp";
6084 power-domains = <&rpmhpd SC8280XP_MMCX>;
6086 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
6089 assigned-clock-parents = <&mdss1_dp0_phy 0>,
6092 operating-points-v2 = <&mdss1_dp0_opp_table>;
6094 #sound-dai-cells = <0>;
6099 #address-cells = <1>;
6100 #size-cells = <0>;
6105 remote-endpoint = <&mdss1_intf0_out>;
6117 mdss1_dp0_opp_table: opp-table {
6118 compatible = "operating-points-v2";
6120 opp-160000000 {
6121 opp-hz = /bits/ 64 <160000000>;
6122 required-opps = <&rpmhpd_opp_low_svs>;
6125 opp-270000000 {
6126 opp-hz = /bits/ 64 <270000000>;
6127 required-opps = <&rpmhpd_opp_svs>;
6130 opp-540000000 {
6131 opp-hz = /bits/ 64 <540000000>;
6132 required-opps = <&rpmhpd_opp_svs_l1>;
6135 opp-810000000 {
6136 opp-hz = /bits/ 64 <810000000>;
6137 required-opps = <&rpmhpd_opp_nom>;
6142 mdss1_dp1: displayport-controller@22098000 {
6143 compatible = "qcom,sc8280xp-dp";
6156 clock-names = "core_iface", "core_aux",
6160 interrupt-parent = <&mdss1>;
6163 phy-names = "dp";
6164 power-domains = <&rpmhpd SC8280XP_MMCX>;
6166 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
6169 assigned-clock-parents = <&mdss1_dp1_phy 0>,
6172 operating-points-v2 = <&mdss1_dp1_opp_table>;
6174 #sound-dai-cells = <0>;
6179 #address-cells = <1>;
6180 #size-cells = <0>;
6185 remote-endpoint = <&mdss1_intf4_out>;
6197 mdss1_dp1_opp_table: opp-table {
6198 compatible = "operating-points-v2";
6200 opp-160000000 {
6201 opp-hz = /bits/ 64 <160000000>;
6202 required-opps = <&rpmhpd_opp_low_svs>;
6205 opp-270000000 {
6206 opp-hz = /bits/ 64 <270000000>;
6207 required-opps = <&rpmhpd_opp_svs>;
6210 opp-540000000 {
6211 opp-hz = /bits/ 64 <540000000>;
6212 required-opps = <&rpmhpd_opp_svs_l1>;
6215 opp-810000000 {
6216 opp-hz = /bits/ 64 <810000000>;
6217 required-opps = <&rpmhpd_opp_nom>;
6222 mdss1_dp2: displayport-controller@2209a000 {
6223 compatible = "qcom,sc8280xp-dp";
6236 clock-names = "core_iface", "core_aux",
6240 interrupt-parent = <&mdss1>;
6243 phy-names = "dp";
6244 power-domains = <&rpmhpd SC8280XP_MMCX>;
6246 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
6249 assigned-clock-parents = <&mdss1_dp2_phy 0>,
6252 operating-points-v2 = <&mdss1_dp2_opp_table>;
6254 #sound-dai-cells = <0>;
6259 #address-cells = <1>;
6260 #size-cells = <0>;
6265 remote-endpoint = <&mdss1_intf6_out>;
6277 mdss1_dp2_opp_table: opp-table {
6278 compatible = "operating-points-v2";
6280 opp-160000000 {
6281 opp-hz = /bits/ 64 <160000000>;
6282 required-opps = <&rpmhpd_opp_low_svs>;
6285 opp-270000000 {
6286 opp-hz = /bits/ 64 <270000000>;
6287 required-opps = <&rpmhpd_opp_svs>;
6290 opp-540000000 {
6291 opp-hz = /bits/ 64 <540000000>;
6292 required-opps = <&rpmhpd_opp_svs_l1>;
6295 opp-810000000 {
6296 opp-hz = /bits/ 64 <810000000>;
6297 required-opps = <&rpmhpd_opp_nom>;
6302 mdss1_dp3: displayport-controller@220a0000 {
6303 compatible = "qcom,sc8280xp-dp";
6315 clock-names = "core_iface", "core_aux",
6318 interrupt-parent = <&mdss1>;
6321 phy-names = "dp";
6322 power-domains = <&rpmhpd SC8280XP_MMCX>;
6324 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
6326 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
6327 operating-points-v2 = <&mdss1_dp3_opp_table>;
6329 #sound-dai-cells = <0>;
6334 #address-cells = <1>;
6335 #size-cells = <0>;
6340 remote-endpoint = <&mdss1_intf5_out>;
6352 mdss1_dp3_opp_table: opp-table {
6353 compatible = "operating-points-v2";
6355 opp-160000000 {
6356 opp-hz = /bits/ 64 <160000000>;
6357 required-opps = <&rpmhpd_opp_low_svs>;
6360 opp-270000000 {
6361 opp-hz = /bits/ 64 <270000000>;
6362 required-opps = <&rpmhpd_opp_svs>;
6365 opp-540000000 {
6366 opp-hz = /bits/ 64 <540000000>;
6367 required-opps = <&rpmhpd_opp_svs_l1>;
6370 opp-810000000 {
6371 opp-hz = /bits/ 64 <810000000>;
6372 required-opps = <&rpmhpd_opp_nom>;
6379 compatible = "qcom,sc8280xp-dp-phy";
6387 clock-names = "aux", "cfg_ahb";
6388 power-domains = <&rpmhpd SC8280XP_MX>;
6390 #clock-cells = <1>;
6391 #phy-cells = <0>;
6397 compatible = "qcom,sc8280xp-dp-phy";
6405 clock-names = "aux", "cfg_ahb";
6406 power-domains = <&rpmhpd SC8280XP_MX>;
6408 #clock-cells = <1>;
6409 #phy-cells = <0>;
6414 dispcc1: clock-controller@22100000 {
6415 compatible = "qcom,sc8280xp-dispcc1";
6418 clocks = <&gcc GCC_DISP_AHB_CLK>,
6433 power-domains = <&rpmhpd SC8280XP_MMCX>;
6435 #clock-cells = <1>;
6436 #power-domain-cells = <1>;
6437 #reset-cells = <1>;
6443 compatible = "qcom,sc8280xp-ethqos";
6446 reg-names = "stmmaceth", "rgmii";
6448 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
6449 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
6450 <&gcc GCC_EMAC1_PTP_CLK>,
6451 <&gcc GCC_EMAC1_RGMII_CLK>;
6452 clock-names = "stmmaceth",
6459 interrupt-names = "macirq", "eth_lpi";
6462 power-domains = <&gcc EMAC_1_GDSC>;
6466 rx-fifo-depth = <4096>;
6467 tx-fifo-depth = <4096>;
6476 thermal-zones {
6477 cpu0-thermal {
6478 polling-delay-passive = <250>;
6480 thermal-sensors = <&tsens0 1>;
6483 cpu-crit {
6491 cpu1-thermal {
6492 polling-delay-passive = <250>;
6494 thermal-sensors = <&tsens0 2>;
6497 cpu-crit {
6505 cpu2-thermal {
6506 polling-delay-passive = <250>;
6508 thermal-sensors = <&tsens0 3>;
6511 cpu-crit {
6519 cpu3-thermal {
6520 polling-delay-passive = <250>;
6522 thermal-sensors = <&tsens0 4>;
6525 cpu-crit {
6533 cpu4-thermal {
6534 polling-delay-passive = <250>;
6536 thermal-sensors = <&tsens0 5>;
6539 cpu-crit {
6547 cpu5-thermal {
6548 polling-delay-passive = <250>;
6550 thermal-sensors = <&tsens0 6>;
6553 cpu-crit {
6561 cpu6-thermal {
6562 polling-delay-passive = <250>;
6564 thermal-sensors = <&tsens0 7>;
6567 cpu-crit {
6575 cpu7-thermal {
6576 polling-delay-passive = <250>;
6578 thermal-sensors = <&tsens0 8>;
6581 cpu-crit {
6589 cluster0-thermal {
6590 polling-delay-passive = <250>;
6592 thermal-sensors = <&tsens0 9>;
6595 cpu-crit {
6603 gpu-thermal {
6604 polling-delay-passive = <250>;
6606 thermal-sensors = <&tsens2 2>;
6608 cooling-maps {
6611 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6616 gpu_alert0: trip-point0 {
6622 trip-point1 {
6630 mem-thermal {
6631 polling-delay-passive = <250>;
6633 thermal-sensors = <&tsens1 15>;
6636 trip-point0 {
6646 compatible = "arm,armv8-timer";