Lines Matching +full:0 +full:xae91000
33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
101 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
124 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
147 reg = <0x0 0x400>;
170 reg = <0x0 0x500>;
193 reg = <0x0 0x600>;
216 reg = <0x0 0x700>;
275 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
278 arm,psci-suspend-param = <0x40000004>;
285 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
288 arm,psci-suspend-param = <0x40000004>;
297 CLUSTER_SLEEP_0: cluster-sleep-0 {
299 arm,psci-suspend-param = <0x4100c344>;
310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311 qcom,dload-mode = <&tcsr 0x13000>;
390 reg = <0x0 0x80000000 0x0 0x0>;
597 #power-domain-cells = <0>;
603 #power-domain-cells = <0>;
609 #power-domain-cells = <0>;
615 #power-domain-cells = <0>;
621 #power-domain-cells = <0>;
627 #power-domain-cells = <0>;
633 #power-domain-cells = <0>;
639 #power-domain-cells = <0>;
645 #power-domain-cells = <0>;
656 reg = <0 0x80000000 0 0x860000>;
662 reg = <0 0x80860000 0 0x20000>;
667 reg = <0 0x80880000 0 0x80000>;
673 reg = <0 0x80900000 0 0x200000>;
679 reg = <0 0x80b00000 0 0x100000>;
684 reg = <0 0x83b00000 0 0x1700000>;
689 reg = <0 0x85b00000 0 0xc00000>;
694 reg = <0 0x86c00000 0 0x2000000>;
699 reg = <0 0x8a100000 0 0x1e00000>;
704 reg = <0 0x8c600000 0 0x1e00000>;
709 reg = <0 0xaeb00000 0 0x16600000>;
723 qcom,local-pid = <0>;
747 qcom,local-pid = <0>;
771 qcom,local-pid = <0>;
786 soc: soc@0 {
790 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>;
795 reg = <0x0 0x00020000 0x0 0x10000>,
796 <0x0 0x00036000 0x0 0x100>;
812 iommus = <&apps_smmu 0x4c0 0xf>;
825 reg = <0x0 0x00100000 0x0 0x1f0000>;
831 <0>,
832 <0>,
833 <0>,
834 <0>,
835 <0>,
836 <0>,
838 <0>,
839 <0>,
840 <0>,
841 <0>,
842 <0>,
843 <0>,
844 <0>,
846 <0>,
847 <0>,
848 <0>,
849 <0>,
850 <0>,
851 <0>,
852 <0>,
853 <0>,
854 <0>,
860 <0>,
861 <0>;
867 reg = <0 0x00408000 0 0x1000>;
876 reg = <0 0x00784000 0 0x3000>;
881 reg = <0x18b 0x1>;
888 reg = <0 0x008c0000 0 0x2000>;
892 iommus = <&apps_smmu 0xa3 0>;
902 reg = <0 0x00880000 0 0x4000>;
904 #size-cells = <0>;
909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
911 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
918 reg = <0 0x00880000 0 0x4000>;
920 #size-cells = <0>;
925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
934 reg = <0 0x00884000 0 0x4000>;
936 #size-cells = <0>;
941 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
942 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
943 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
950 reg = <0 0x00884000 0 0x4000>;
952 #size-cells = <0>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
966 reg = <0 0x00884000 0 0x4000>;
972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
980 reg = <0 0x00888000 0 0x4000>;
982 #size-cells = <0>;
987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
996 reg = <0 0x00888000 0 0x4000>;
998 #size-cells = <0>;
1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1012 reg = <0 0x0088c000 0 0x4000>;
1014 #size-cells = <0>;
1019 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1020 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1021 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1028 reg = <0 0x0088c000 0 0x4000>;
1030 #size-cells = <0>;
1035 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1036 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1044 reg = <0 0x00890000 0 0x4000>;
1046 #size-cells = <0>;
1051 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1053 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1060 reg = <0 0x00890000 0 0x4000>;
1062 #size-cells = <0>;
1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1069 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1076 reg = <0 0x00894000 0 0x4000>;
1081 #size-cells = <0>;
1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1092 reg = <0 0x00894000 0 0x4000>;
1094 #size-cells = <0>;
1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1100 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1101 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1108 reg = <0 0x00898000 0 0x4000>;
1110 #size-cells = <0>;
1115 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1117 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1124 reg = <0 0x00898000 0 0x4000>;
1126 #size-cells = <0>;
1131 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1133 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1140 reg = <0 0x0089c000 0 0x4000>;
1142 #size-cells = <0>;
1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1148 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1156 reg = <0 0x0089c000 0 0x4000>;
1158 #size-cells = <0>;
1163 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1165 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1173 reg = <0 0x009c0000 0 0x6000>;
1177 iommus = <&apps_smmu 0x563 0>;
1187 reg = <0 0x00980000 0 0x4000>;
1189 #size-cells = <0>;
1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1196 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1203 reg = <0 0x00980000 0 0x4000>;
1205 #size-cells = <0>;
1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1212 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1219 reg = <0 0x00984000 0 0x4000>;
1221 #size-cells = <0>;
1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1228 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1235 reg = <0 0x00984000 0 0x4000>;
1237 #size-cells = <0>;
1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1244 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1251 reg = <0 0x00988000 0 0x4000>;
1253 #size-cells = <0>;
1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1260 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1267 reg = <0 0x00988000 0 0x4000>;
1269 #size-cells = <0>;
1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1275 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1276 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1283 reg = <0 0x00988000 0 0x4000>;
1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1297 reg = <0 0x0098c000 0 0x4000>;
1299 #size-cells = <0>;
1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1305 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1313 reg = <0 0x0098c000 0 0x4000>;
1315 #size-cells = <0>;
1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1322 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1329 reg = <0 0x00990000 0 0x4000>;
1334 #size-cells = <0>;
1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1345 reg = <0 0x00990000 0 0x4000>;
1347 #size-cells = <0>;
1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1354 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1361 reg = <0 0x00994000 0 0x4000>;
1363 #size-cells = <0>;
1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1370 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1377 reg = <0 0x00994000 0 0x4000>;
1379 #size-cells = <0>;
1384 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1386 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1393 reg = <0 0x00998000 0 0x4000>;
1395 #size-cells = <0>;
1400 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1402 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1409 reg = <0 0x00998000 0 0x4000>;
1411 #size-cells = <0>;
1416 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1418 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1425 reg = <0 0x0099c000 0 0x4000>;
1427 #size-cells = <0>;
1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1434 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1441 reg = <0 0x0099c000 0 0x4000>;
1443 #size-cells = <0>;
1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1449 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1450 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1458 reg = <0 0x00ac0000 0 0x6000>;
1462 iommus = <&apps_smmu 0x83 0>;
1472 reg = <0 0x00a80000 0 0x4000>;
1474 #size-cells = <0>;
1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1481 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 reg = <0 0x00a80000 0 0x4000>;
1490 #size-cells = <0>;
1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1504 reg = <0 0x00a84000 0 0x4000>;
1506 #size-cells = <0>;
1511 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1512 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1513 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1520 reg = <0 0x00a84000 0 0x4000>;
1522 #size-cells = <0>;
1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1536 reg = <0 0x00a88000 0 0x4000>;
1538 #size-cells = <0>;
1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1545 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1552 reg = <0 0x00a88000 0 0x4000>;
1554 #size-cells = <0>;
1559 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1560 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1561 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 reg = <0 0x00a8c000 0 0x4000>;
1570 #size-cells = <0>;
1575 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1576 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1577 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1584 reg = <0 0x00a8c000 0 0x4000>;
1586 #size-cells = <0>;
1591 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1593 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1600 reg = <0 0x00a90000 0 0x4000>;
1602 #size-cells = <0>;
1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1609 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1616 reg = <0 0x00a90000 0 0x4000>;
1618 #size-cells = <0>;
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1625 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1632 reg = <0 0x00a94000 0 0x4000>;
1634 #size-cells = <0>;
1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1641 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 reg = <0 0x00a94000 0 0x4000>;
1650 #size-cells = <0>;
1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1657 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1664 reg = <0 0x00a98000 0 0x4000>;
1666 #size-cells = <0>;
1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1673 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1680 reg = <0 0x00a98000 0 0x4000>;
1682 #size-cells = <0>;
1687 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1688 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1689 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1696 reg = <0 0x00a9c000 0 0x4000>;
1698 #size-cells = <0>;
1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1705 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1712 reg = <0 0x00a9c000 0 0x4000>;
1714 #size-cells = <0>;
1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1720 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1721 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1729 reg = <0 0x010d3000 0 0x1000>;
1737 reg = <0x0 0x01c00000 0x0 0x3000>,
1738 <0x0 0x30000000 0x0 0xf1d>,
1739 <0x0 0x30000f20 0x0 0xa8>,
1740 <0x0 0x30001000 0x0 0x1000>,
1741 <0x0 0x30100000 0x0 0x100000>,
1742 <0x0 0x01c03000 0x0 0x1000>;
1746 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1747 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1748 bus-range = <0x00 0xff>;
1755 msi-map = <0x0 &its 0xe0000 0x10000>;
1764 interrupt-map-mask = <0 0 0 0x7>;
1765 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1766 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1767 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1768 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1792 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1793 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1807 pcie4_port0: pcie@0 {
1809 reg = <0x0 0x0 0x0 0x0 0x0>;
1810 bus-range = <0x01 0xff>;
1820 reg = <0x0 0x01c06000 0x0 0x2000>;
1839 #clock-cells = <0>;
1842 #phy-cells = <0>;
1850 reg = <0x0 0x01c08000 0x0 0x3000>,
1851 <0x0 0x32000000 0x0 0xf1d>,
1852 <0x0 0x32000f20 0x0 0xa8>,
1853 <0x0 0x32001000 0x0 0x1000>,
1854 <0x0 0x32100000 0x0 0x100000>,
1855 <0x0 0x01c0b000 0x0 0x1000>;
1859 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1860 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1861 bus-range = <0x00 0xff>;
1868 msi-map = <0x0 &its 0xd0000 0x10000>;
1877 interrupt-map-mask = <0 0 0 0x7>;
1878 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1879 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1880 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1881 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1903 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1918 pcie3b_port0: pcie@0 {
1920 reg = <0x0 0x0 0x0 0x0 0x0>;
1921 bus-range = <0x01 0xff>;
1931 reg = <0x0 0x01c0e000 0x0 0x2000>;
1950 #clock-cells = <0>;
1953 #phy-cells = <0>;
1961 reg = <0x0 0x01c10000 0x0 0x3000>,
1962 <0x0 0x34000000 0x0 0xf1d>,
1963 <0x0 0x34000f20 0x0 0xa8>,
1964 <0x0 0x34001000 0x0 0x1000>,
1965 <0x0 0x34100000 0x0 0x100000>,
1966 <0x0 0x01c13000 0x0 0x1000>;
1970 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1971 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1972 bus-range = <0x00 0xff>;
1979 msi-map = <0x0 &its 0xc0000 0x10000>;
1988 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1990 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1991 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1992 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
2014 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2015 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2029 pcie3a_port0: pcie@0 {
2031 reg = <0x0 0x0 0x0 0x0 0x0>;
2032 bus-range = <0x01 0xff>;
2042 reg = <0x0 0x01c14000 0x0 0x2000>,
2043 <0x0 0x01c16000 0x0 0x2000>;
2062 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2064 #clock-cells = <0>;
2067 #phy-cells = <0>;
2075 reg = <0x0 0x01c18000 0x0 0x3000>,
2076 <0x0 0x38000000 0x0 0xf1d>,
2077 <0x0 0x38000f20 0x0 0xa8>,
2078 <0x0 0x38001000 0x0 0x1000>,
2079 <0x0 0x38100000 0x0 0x100000>,
2080 <0x0 0x01c1b000 0x0 0x1000>;
2084 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2085 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2086 bus-range = <0x00 0xff>;
2093 msi-map = <0x0 &its 0xb0000 0x10000>;
2102 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2104 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2105 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2106 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2128 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2143 pcie2b_port0: pcie@0 {
2145 reg = <0x0 0x0 0x0 0x0 0x0>;
2146 bus-range = <0x01 0xff>;
2156 reg = <0x0 0x01c1e000 0x0 0x2000>;
2175 #clock-cells = <0>;
2178 #phy-cells = <0>;
2186 reg = <0x0 0x01c20000 0x0 0x3000>,
2187 <0x0 0x3c000000 0x0 0xf1d>,
2188 <0x0 0x3c000f20 0x0 0xa8>,
2189 <0x0 0x3c001000 0x0 0x1000>,
2190 <0x0 0x3c100000 0x0 0x100000>,
2191 <0x0 0x01c23000 0x0 0x1000>;
2195 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2196 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2197 bus-range = <0x00 0xff>;
2204 msi-map = <0x0 &its 0xa0000 0x10000>;
2213 interrupt-map-mask = <0 0 0 0x7>;
2214 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2215 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2216 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2217 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2239 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2240 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2254 pcie2a_port0: pcie@0 {
2256 reg = <0x0 0x0 0x0 0x0 0x0>;
2257 bus-range = <0x01 0xff>;
2267 reg = <0x0 0x01c24000 0x0 0x2000>,
2268 <0x0 0x01c26000 0x0 0x2000>;
2287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2289 #clock-cells = <0>;
2292 #phy-cells = <0>;
2300 reg = <0 0x01d84000 0 0x3000>;
2312 iommus = <&apps_smmu 0xe0 0x0>;
2332 <0 0>,
2333 <0 0>,
2335 <0 0>,
2336 <0 0>,
2337 <0 0>,
2338 <0 0>;
2344 reg = <0 0x01d87000 0 0x1000>;
2355 resets = <&ufs_mem_hc 0>;
2358 #phy-cells = <0>;
2366 reg = <0 0x01da4000 0 0x3000>;
2377 iommus = <&apps_smmu 0x4a0 0x0>;
2397 <0 0>,
2398 <0 0>,
2400 <0 0>,
2401 <0 0>,
2402 <0 0>,
2403 <0 0>;
2409 reg = <0 0x01da7000 0 0x1000>;
2420 resets = <&ufs_card_hc 0>;
2423 #phy-cells = <0>;
2430 reg = <0x0 0x01f40000 0x0 0x20000>;
2436 reg = <0x0 0x01fc0000 0x0 0x30000>;
2442 reg = <0 0x03d00000 0 0x40000>,
2443 <0 0x03d9e000 0 0x1000>,
2444 <0 0x03d61000 0 0x800>;
2449 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2453 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2514 reg = <0 0x03d6a000 0 0x34000>,
2515 <0 0x03de0000 0 0x10000>,
2516 <0 0x0b290000 0 0x10000>;
2539 iommus = <&gpu_smmu 5 0xc00>;
2559 reg = <0 0x03d90000 0 0x9000>;
2576 reg = <0 0x03da0000 0 0x20000>;
2616 reg = <0 0x088e5000 0 0x400>;
2621 #phy-cells = <0>;
2629 reg = <0 0x088e7000 0 0x400>;
2634 #phy-cells = <0>;
2642 reg = <0 0x088e8000 0 0x400>;
2647 #phy-cells = <0>;
2655 reg = <0 0x088e9000 0 0x400>;
2660 #phy-cells = <0>;
2668 reg = <0 0x088ea000 0 0x400>;
2673 #phy-cells = <0>;
2680 reg = <0 0x088ef000 0 0x2000>;
2694 #clock-cells = <0>;
2697 #phy-cells = <0>;
2704 reg = <0 0x088f1000 0 0x2000>;
2718 #clock-cells = <0>;
2721 #phy-cells = <0>;
2728 reg = <0 0x03000000 0 0x100>;
2731 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2750 qcom,smem-states = <&smp2p_adsp_out 0>;
2771 #size-cells = <0>;
2776 #sound-dai-cells = <0>;
2781 iommus = <&apps_smmu 0x0c01 0x0>;
2806 reg = <0 0x03200000 0 0x1000>;
2818 #clock-cells = <0>;
2822 pinctrl-0 = <&rx_swr_default>;
2829 reg = <0 0x03210000 0 0x2000>;
2837 qcom,din-ports = <0>;
2840 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2841 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2842 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2843 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2844 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2845 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2846 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2847 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2848 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2852 #size-cells = <0>;
2859 reg = <0 0x03220000 0 0x1000>;
2861 pinctrl-0 = <&tx_swr_default>;
2874 #clock-cells = <0>;
2882 reg = <0 0x03240000 0 0x1000>;
2893 #clock-cells = <0>;
2898 pinctrl-0 = <&wsa_swr_default>;
2904 reg = <0 0x03250000 0 0x2000>;
2916 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2917 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2918 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2919 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2920 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2921 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2922 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2923 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2924 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2928 #size-cells = <0>;
2935 reg = <0 0x032a9000 0 0x1000>;
2942 reg = <0 0x03330000 0 0x2000>;
2954 #size-cells = <0>;
2957 qcom,dout-ports = <0>;
2958 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2959 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2960 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2961 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2965 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2966 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2973 reg = <0 0x03370000 0 0x1000>;
2982 #clock-cells = <0>;
2991 reg = <0 0x33c0000 0x0 0x20000>,
2992 <0 0x3550000 0x0 0x10000>;
2995 gpio-ranges = <&lpass_tlmm 0 0 19>;
3146 reg = <0 0x033e0000 0 0x12000>;
3153 reg = <0 0x08804000 0 0x1000>;
3164 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3167 iommus = <&apps_smmu 0x4e0 0x0>;
3182 opp-avg-kBps = <100000 0>;
3189 opp-avg-kBps = <200000 0>;
3196 reg = <0 0x088eb000 0 0x4000>;
3217 #size-cells = <0>;
3219 port@0 {
3220 reg = <0>;
3244 reg = <0 0x08902000 0 0x400>;
3245 #phy-cells = <0>;
3257 reg = <0 0x08903000 0 0x4000>;
3278 #size-cells = <0>;
3280 port@0 {
3281 reg = <0>;
3304 reg = <0 0x08909a00 0 0x19c>,
3305 <0 0x08909200 0 0xec>,
3306 <0 0x08909600 0 0xec>,
3307 <0 0x08909000 0 0x1c8>;
3315 #phy-cells = <0>;
3322 reg = <0 0x0890ca00 0 0x19c>,
3323 <0 0x0890c200 0 0xec>,
3324 <0 0x0890c600 0 0xec>,
3325 <0 0x0890c000 0 0x1c8>;
3333 #phy-cells = <0>;
3340 reg = <0 0x09091000 0 0x1000>;
3351 opp-0 {
3395 reg = <0 0x090b6400 0 0x600>;
3405 opp-0 {
3431 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3432 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3433 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3434 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3435 <0 0x09600000 0 0x58000>;
3444 reg = <0 0x0a4f8800 0 0x400>;
3499 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
3500 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
3509 reg = <0 0x0a400000 0 0xcd00>;
3511 iommus = <&apps_smmu 0x800 0x0>;
3516 phy-names = "usb2-0", "usb3-0",
3526 reg = <0 0x0a6f8800 0 0x400>;
3563 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3564 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3573 reg = <0 0x0a600000 0 0xcd00>;
3575 iommus = <&apps_smmu 0x820 0x0>;
3581 #size-cells = <0>;
3583 port@0 {
3584 reg = <0>;
3603 reg = <0 0x0a8f8800 0 0x400>;
3640 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3641 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3650 reg = <0 0x0a800000 0 0xcd00>;
3652 iommus = <&apps_smmu 0x860 0x0>;
3658 #size-cells = <0>;
3660 port@0 {
3661 reg = <0>;
3680 reg = <0 0x0ac4a000 0 0x1000>;
3695 pinctrl-0 = <&cci0_default>;
3700 #size-cells = <0>;
3704 cci0_i2c0: i2c-bus@0 {
3705 reg = <0>;
3708 #size-cells = <0>;
3715 #size-cells = <0>;
3721 reg = <0 0x0ac4b000 0 0x1000>;
3736 pinctrl-0 = <&cci1_default>;
3741 #size-cells = <0>;
3745 cci1_i2c0: i2c-bus@0 {
3746 reg = <0>;
3749 #size-cells = <0>;
3756 #size-cells = <0>;
3762 reg = <0 0x0ac4c000 0 0x1000>;
3776 pinctrl-0 = <&cci2_default>;
3781 #size-cells = <0>;
3785 cci2_i2c0: i2c-bus@0 {
3786 reg = <0>;
3789 #size-cells = <0>;
3796 #size-cells = <0>;
3802 reg = <0 0x0ac4d000 0 0x1000>;
3817 pinctrl-0 = <&cci3_default>;
3822 #size-cells = <0>;
3826 cci3_i2c0: i2c-bus@0 {
3827 reg = <0>;
3830 #size-cells = <0>;
3837 #size-cells = <0>;
3844 reg = <0 0x0ac5a000 0 0x2000>,
3845 <0 0x0ac5c000 0 0x2000>,
3846 <0 0x0ac65000 0 0x2000>,
3847 <0 0x0ac67000 0 0x2000>,
3848 <0 0x0acaf000 0 0x4000>,
3849 <0 0x0acb3000 0 0x1000>,
3850 <0 0x0acb6000 0 0x4000>,
3851 <0 0x0acba000 0 0x1000>,
3852 <0 0x0acbd000 0 0x4000>,
3853 <0 0x0acc1000 0 0x1000>,
3854 <0 0x0acc4000 0 0x4000>,
3855 <0 0x0acc8000 0 0x1000>,
3856 <0 0x0accb000 0 0x4000>,
3857 <0 0x0accf000 0 0x1000>,
3858 <0 0x0acd2000 0 0x4000>,
3859 <0 0x0acd6000 0 0x1000>,
3860 <0 0x0acd9000 0 0x4000>,
3861 <0 0x0acdd000 0 0x1000>,
3862 <0 0x0ace0000 0 0x4000>,
3863 <0 0x0ace4000 0 0x1000>;
4018 iommus = <&apps_smmu 0x2000 0x4e0>,
4019 <&apps_smmu 0x2020 0x4e0>,
4020 <&apps_smmu 0x2040 0x4e0>,
4021 <&apps_smmu 0x2060 0x4e0>,
4022 <&apps_smmu 0x2080 0x4e0>,
4023 <&apps_smmu 0x20e0 0x4e0>,
4024 <&apps_smmu 0x20c0 0x4e0>,
4025 <&apps_smmu 0x20a0 0x4e0>,
4026 <&apps_smmu 0x2400 0x4e0>,
4027 <&apps_smmu 0x2420 0x4e0>,
4028 <&apps_smmu 0x2440 0x4e0>,
4029 <&apps_smmu 0x2460 0x4e0>,
4030 <&apps_smmu 0x2480 0x4e0>,
4031 <&apps_smmu 0x24e0 0x4e0>,
4032 <&apps_smmu 0x24c0 0x4e0>,
4033 <&apps_smmu 0x24a0 0x4e0>;
4035 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
4036 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
4037 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
4038 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
4048 #size-cells = <0>;
4050 port@0 {
4051 reg = <0>;
4053 #size-cells = <0>;
4059 #size-cells = <0>;
4065 #size-cells = <0>;
4071 #size-cells = <0>;
4078 reg = <0 0x0ad00000 0 0x20000>;
4092 reg = <0 0x0ae00000 0 0x1000>;
4102 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4103 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4105 iommus = <&apps_smmu 0x1000 0x402>;
4119 reg = <0 0x0ae01000 0 0x8f000>,
4120 <0 0x0aeb0000 0 0x2008>;
4136 interrupts = <0>;
4145 #size-cells = <0>;
4147 port@0 {
4148 reg = <0>;
4207 reg = <0 0xae90000 0 0x200>,
4208 <0 0xae90200 0 0x200>,
4209 <0 0xae90400 0 0x600>,
4210 <0 0xae91000 0 0x400>,
4211 <0 0xae91400 0 0x400>;
4232 #sound-dai-cells = <0>;
4241 #size-cells = <0>;
4243 port@0 {
4244 reg = <0>;
4286 reg = <0 0xae98000 0 0x200>,
4287 <0 0xae98200 0 0x200>,
4288 <0 0xae98400 0 0x600>,
4289 <0 0xae99000 0 0x400>,
4290 <0 0xae99400 0 0x400>;
4310 #sound-dai-cells = <0>;
4319 #size-cells = <0>;
4321 port@0 {
4322 reg = <0>;
4364 reg = <0 0xae9a000 0 0x200>,
4365 <0 0xae9a200 0 0x200>,
4366 <0 0xae9a400 0 0x600>,
4367 <0 0xae9b000 0 0x400>,
4368 <0 0xae9b400 0 0x400>;
4386 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4389 #sound-dai-cells = <0>;
4395 #size-cells = <0>;
4397 port@0 {
4398 reg = <0>;
4436 reg = <0 0xaea0000 0 0x200>,
4437 <0 0xaea0200 0 0x200>,
4438 <0 0xaea0400 0 0x600>,
4439 <0 0xaea1000 0 0x400>,
4440 <0 0xaea1400 0 0x400>;
4458 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4461 #sound-dai-cells = <0>;
4467 #size-cells = <0>;
4469 port@0 {
4470 reg = <0>;
4509 reg = <0 0x0aec2a00 0 0x19c>,
4510 <0 0x0aec2200 0 0xec>,
4511 <0 0x0aec2600 0 0xec>,
4512 <0 0x0aec2000 0 0x1c8>;
4520 #phy-cells = <0>;
4527 reg = <0 0x0aec5a00 0 0x19c>,
4528 <0 0x0aec5200 0 0xec>,
4529 <0 0x0aec5600 0 0xec>,
4530 <0 0x0aec5000 0 0x1c8>;
4538 #phy-cells = <0>;
4545 reg = <0 0x0af00000 0 0x20000>;
4554 <&mdss0_dp2_phy 0>,
4556 <&mdss0_dp3_phy 0>,
4558 <0>,
4559 <0>,
4560 <0>,
4561 <0>;
4573 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4574 qcom,pdc-ranges = <0 480 40>,
4638 reg = <0 0x0c251000 0 0x1ff>,
4639 <0 0x0c224000 0 0x8>;
4649 reg = <0 0x0c252000 0 0x1ff>,
4650 <0 0x0c225000 0 0x8>;
4660 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4661 <0 0x0c222000 0 0x8>; /* SROT */
4671 reg = <0 0x0c264000 0 0x4>;
4678 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4679 <0 0x0c223000 0 0x8>; /* SROT */
4689 reg = <0 0x0c300000 0 0x400>;
4693 #clock-cells = <0>;
4698 reg = <0 0x0c3f0000 0 0x400>;
4704 reg = <0 0x0c440000 0 0x1100>,
4705 <0 0x0c600000 0 0x2000000>,
4706 <0 0x0e600000 0 0x100000>,
4707 <0 0x0e700000 0 0xa0000>,
4708 <0 0x0c40a000 0 0x26000>;
4712 qcom,ee = <0>;
4713 qcom,channel = <0>;
4715 #size-cells = <0>;
4722 reg = <0 0x0f100000 0 0x300000>;
4728 gpio-ranges = <&tlmm 0 0 230>;
4878 reg = <0 0x15000000 0 0x100000>;
5017 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5018 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5021 redistributor-stride = <0 0x20000>;
5029 reg = <0 0x17a40000 0 0x20000>;
5037 reg = <0 0x17c10000 0 0x1000>;
5039 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5044 reg = <0x0 0x17c20000 0x0 0x1000>;
5047 ranges = <0x0 0x0 0x0 0x20000000>;
5050 frame-number = <0>;
5053 reg = <0x17c21000 0x1000>,
5054 <0x17c22000 0x1000>;
5060 reg = <0x17c23000 0x1000>;
5067 reg = <0x17c25000 0x1000>;
5074 reg = <0x17c26000 0x1000>;
5081 reg = <0x17c29000 0x1000>;
5088 reg = <0x17c2b000 0x1000>;
5095 reg = <0x17c2d000 0x1000>;
5102 reg = <0x0 0x18200000 0x0 0x10000>,
5103 <0x0 0x18210000 0x0 0x10000>,
5104 <0x0 0x18220000 0x0 0x10000>;
5105 reg-names = "drv-0", "drv-1", "drv-2";
5109 qcom,tcs-offset = <0xd00>;
5180 reg = <0 0x18590000 0 0x1000>;
5190 reg = <0 0x18591000 0 0x1000>,
5191 <0 0x18592000 0 0x1000>;
5196 interrupt-names = "dcvsh-irq-0",
5208 reg = <0 0x1b300000 0 0x100>;
5211 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5226 qcom,smem-states = <&smp2p_nsp0_out 0>;
5229 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5248 #size-cells = <0>;
5253 iommus = <&apps_smmu 0x3181 0x0420>;
5259 iommus = <&apps_smmu 0x3182 0x0420>;
5265 iommus = <&apps_smmu 0x3183 0x0420>;
5271 iommus = <&apps_smmu 0x3184 0x0420>;
5277 iommus = <&apps_smmu 0x3185 0x0420>;
5283 iommus = <&apps_smmu 0x3186 0x0420>;
5289 iommus = <&apps_smmu 0x3187 0x0420>;
5295 iommus = <&apps_smmu 0x3188 0x0420>;
5301 iommus = <&apps_smmu 0x318b 0x0420>;
5307 iommus = <&apps_smmu 0x318b 0x0420>;
5313 iommus = <&apps_smmu 0x318c 0x0420>;
5319 iommus = <&apps_smmu 0x318d 0x0420>;
5325 iommus = <&apps_smmu 0x318e 0x0420>;
5331 iommus = <&apps_smmu 0x318f 0x0420>;
5339 reg = <0 0x21300000 0 0x100>;
5342 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5357 qcom,smem-states = <&smp2p_nsp1_out 0>;
5360 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5378 reg = <0 0x22000000 0 0x1000>;
5387 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5388 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5392 iommus = <&apps_smmu 0x1800 0x402>;
5406 reg = <0 0x22001000 0 0x8f000>,
5407 <0 0x220b0000 0 0x2008>;
5423 interrupts = <0>;
5432 #size-cells = <0>;
5434 port@0 {
5435 reg = <0>;
5494 reg = <0 0x22090000 0 0x200>,
5495 <0 0x22090200 0 0x200>,
5496 <0 0x22090400 0 0x600>,
5497 <0 0x22091000 0 0x400>,
5498 <0 0x22091400 0 0x400>;
5516 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5519 #sound-dai-cells = <0>;
5525 #size-cells = <0>;
5527 port@0 {
5528 reg = <0>;
5566 reg = <0 0x22098000 0 0x200>,
5567 <0 0x22098200 0 0x200>,
5568 <0 0x22098400 0 0x600>,
5569 <0 0x22099000 0 0x400>,
5570 <0 0x22099400 0 0x400>;
5588 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5591 #sound-dai-cells = <0>;
5597 #size-cells = <0>;
5599 port@0 {
5600 reg = <0>;
5638 reg = <0 0x2209a000 0 0x200>,
5639 <0 0x2209a200 0 0x200>,
5640 <0 0x2209a400 0 0x600>,
5641 <0 0x2209b000 0 0x400>,
5642 <0 0x2209b400 0 0x400>;
5660 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5663 #sound-dai-cells = <0>;
5669 #size-cells = <0>;
5671 port@0 {
5672 reg = <0>;
5710 reg = <0 0x220a0000 0 0x200>,
5711 <0 0x220a0200 0 0x200>,
5712 <0 0x220a0400 0 0x600>,
5713 <0 0x220a1000 0 0x400>,
5714 <0 0x220a1400 0 0x400>;
5732 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5735 #sound-dai-cells = <0>;
5741 #size-cells = <0>;
5743 port@0 {
5744 reg = <0>;
5783 reg = <0 0x220c2a00 0 0x19c>,
5784 <0 0x220c2200 0 0xec>,
5785 <0 0x220c2600 0 0xec>,
5786 <0 0x220c2000 0 0x1c8>;
5794 #phy-cells = <0>;
5801 reg = <0 0x220c5a00 0 0x19c>,
5802 <0 0x220c5200 0 0xec>,
5803 <0 0x220c5600 0 0xec>,
5804 <0 0x220c5000 0 0x1c8>;
5812 #phy-cells = <0>;
5819 reg = <0 0x22100000 0 0x20000>;
5823 <0>,
5824 <&mdss1_dp0_phy 0>,
5826 <&mdss1_dp1_phy 0>,
5828 <&mdss1_dp2_phy 0>,
5830 <&mdss1_dp3_phy 0>,
5832 <0>,
5833 <0>,
5834 <0>,
5835 <0>;
5847 reg = <0x0 0x23000000 0x0 0x10000>,
5848 <0x0 0x23016000 0x0 0x100>;
5864 iommus = <&apps_smmu 0x40 0xf>;