Lines Matching +full:0 +full:x0aec2a00
33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
101 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
124 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
147 reg = <0x0 0x400>;
170 reg = <0x0 0x500>;
193 reg = <0x0 0x600>;
216 reg = <0x0 0x700>;
275 little_cpu_sleep_0: cpu-sleep-0-0 {
278 arm,psci-suspend-param = <0x40000004>;
285 big_cpu_sleep_0: cpu-sleep-1-0 {
288 arm,psci-suspend-param = <0x40000004>;
297 cluster_sleep_0: cluster-sleep-0 {
299 arm,psci-suspend-param = <0x4100c344>;
310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311 qcom,dload-mode = <&tcsr 0x13000>;
390 reg = <0x0 0x80000000 0x0 0x0>;
597 #power-domain-cells = <0>;
603 #power-domain-cells = <0>;
609 #power-domain-cells = <0>;
615 #power-domain-cells = <0>;
621 #power-domain-cells = <0>;
627 #power-domain-cells = <0>;
633 #power-domain-cells = <0>;
639 #power-domain-cells = <0>;
645 #power-domain-cells = <0>;
656 reg = <0 0x80000000 0 0x860000>;
662 reg = <0 0x80860000 0 0x20000>;
667 reg = <0 0x80880000 0 0x80000>;
673 reg = <0 0x80900000 0 0x200000>;
679 reg = <0 0x80b00000 0 0x100000>;
684 reg = <0 0x83b00000 0 0x1700000>;
689 reg = <0 0x85b00000 0 0xc00000>;
694 reg = <0 0x86c00000 0 0x2000000>;
699 reg = <0 0x88c00000 0 0x1500000>;
704 reg = <0 0x8a100000 0 0x1e00000>;
709 reg = <0 0x8c600000 0 0x1e00000>;
714 reg = <0 0xaeb00000 0 0x16600000>;
728 qcom,local-pid = <0>;
752 qcom,local-pid = <0>;
776 qcom,local-pid = <0>;
800 qcom,local-pid = <0>;
815 soc: soc@0 {
819 ranges = <0 0 0 0 0x10 0>;
820 dma-ranges = <0 0 0 0 0x10 0>;
824 reg = <0x0 0x00020000 0x0 0x10000>,
825 <0x0 0x00036000 0x0 0x100>;
841 iommus = <&apps_smmu 0x4c0 0xf>;
854 reg = <0x0 0x00100000 0x0 0x1f0000>;
860 <0>,
861 <0>,
862 <0>,
863 <0>,
864 <0>,
865 <0>,
867 <0>,
868 <0>,
869 <0>,
870 <0>,
871 <0>,
872 <0>,
873 <0>,
875 <0>,
876 <0>,
877 <0>,
878 <0>,
879 <0>,
880 <0>,
881 <0>,
882 <0>,
883 <0>,
889 <0>,
890 <0>;
896 reg = <0 0x00408000 0 0x1000>;
905 reg = <0 0x00784000 0 0x3000>;
910 reg = <0x18b 0x1>;
917 reg = <0 0x008c0000 0 0x2000>;
921 iommus = <&apps_smmu 0xa3 0>;
931 reg = <0 0x00880000 0 0x4000>;
933 #size-cells = <0>;
938 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
940 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
947 reg = <0 0x00880000 0 0x4000>;
949 #size-cells = <0>;
954 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
956 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
963 reg = <0 0x00884000 0 0x4000>;
965 #size-cells = <0>;
970 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
972 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
979 reg = <0 0x00884000 0 0x4000>;
981 #size-cells = <0>;
986 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
988 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
995 reg = <0 0x00884000 0 0x4000>;
1001 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1002 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1009 reg = <0 0x00888000 0 0x4000>;
1011 #size-cells = <0>;
1016 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1018 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1025 reg = <0 0x00888000 0 0x4000>;
1027 #size-cells = <0>;
1032 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1033 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1034 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1041 reg = <0 0x00888000 0 0x4000>;
1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1048 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1051 pinctrl-0 = <&qup_uart18_default>;
1059 reg = <0 0x0088c000 0 0x4000>;
1061 #size-cells = <0>;
1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1068 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1075 reg = <0 0x0088c000 0 0x4000>;
1077 #size-cells = <0>;
1082 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1083 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1084 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1091 reg = <0 0x00890000 0 0x4000>;
1093 #size-cells = <0>;
1098 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1099 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1100 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1107 reg = <0 0x00890000 0 0x4000>;
1109 #size-cells = <0>;
1114 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1116 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1123 reg = <0 0x00894000 0 0x4000>;
1128 #size-cells = <0>;
1130 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1132 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1139 reg = <0 0x00894000 0 0x4000>;
1141 #size-cells = <0>;
1146 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1148 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1155 reg = <0 0x00898000 0 0x4000>;
1157 #size-cells = <0>;
1162 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1163 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1164 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1171 reg = <0 0x00898000 0 0x4000>;
1173 #size-cells = <0>;
1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1179 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1180 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1187 reg = <0 0x0089c000 0 0x4000>;
1189 #size-cells = <0>;
1194 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1196 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1203 reg = <0 0x0089c000 0 0x4000>;
1205 #size-cells = <0>;
1210 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1212 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1220 reg = <0 0x009c0000 0 0x6000>;
1224 iommus = <&apps_smmu 0x563 0>;
1234 reg = <0 0x00980000 0 0x4000>;
1236 #size-cells = <0>;
1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1242 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1243 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1250 reg = <0 0x00980000 0 0x4000>;
1252 #size-cells = <0>;
1257 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1259 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1266 reg = <0 0x00984000 0 0x4000>;
1268 #size-cells = <0>;
1273 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1274 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1275 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1282 reg = <0 0x00984000 0 0x4000>;
1284 #size-cells = <0>;
1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1291 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1298 reg = <0 0x00988000 0 0x4000>;
1300 #size-cells = <0>;
1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1306 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1307 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1314 reg = <0 0x00988000 0 0x4000>;
1316 #size-cells = <0>;
1321 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1322 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1323 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1330 reg = <0 0x00988000 0 0x4000>;
1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1344 reg = <0 0x0098c000 0 0x4000>;
1346 #size-cells = <0>;
1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1352 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1353 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1360 reg = <0 0x0098c000 0 0x4000>;
1362 #size-cells = <0>;
1367 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1368 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1369 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1376 reg = <0 0x00990000 0 0x4000>;
1381 #size-cells = <0>;
1383 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1384 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1385 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1392 reg = <0 0x00990000 0 0x4000>;
1394 #size-cells = <0>;
1399 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1401 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1408 reg = <0 0x00994000 0 0x4000>;
1410 #size-cells = <0>;
1415 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1417 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1424 reg = <0 0x00994000 0 0x4000>;
1426 #size-cells = <0>;
1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1433 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1440 reg = <0 0x00998000 0 0x4000>;
1442 #size-cells = <0>;
1447 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1449 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1456 reg = <0 0x00998000 0 0x4000>;
1458 #size-cells = <0>;
1463 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1464 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1465 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1472 reg = <0 0x0099c000 0 0x4000>;
1474 #size-cells = <0>;
1479 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1481 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1488 reg = <0 0x0099c000 0 0x4000>;
1490 #size-cells = <0>;
1495 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1497 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1505 reg = <0 0x00ac0000 0 0x6000>;
1509 iommus = <&apps_smmu 0x83 0>;
1519 reg = <0 0x00a80000 0 0x4000>;
1521 #size-cells = <0>;
1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1527 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1528 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1535 reg = <0 0x00a80000 0 0x4000>;
1537 #size-cells = <0>;
1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1543 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1544 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1551 reg = <0 0x00a84000 0 0x4000>;
1553 #size-cells = <0>;
1558 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1559 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1560 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1567 reg = <0 0x00a84000 0 0x4000>;
1569 #size-cells = <0>;
1574 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1575 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1576 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1583 reg = <0 0x00a88000 0 0x4000>;
1585 #size-cells = <0>;
1590 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1591 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1592 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1599 reg = <0 0x00a88000 0 0x4000>;
1601 #size-cells = <0>;
1606 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1607 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1608 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1615 reg = <0 0x00a8c000 0 0x4000>;
1617 #size-cells = <0>;
1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1623 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1624 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1631 reg = <0 0x00a8c000 0 0x4000>;
1633 #size-cells = <0>;
1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1639 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1640 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1647 reg = <0 0x00a90000 0 0x4000>;
1649 #size-cells = <0>;
1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1655 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1656 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1663 reg = <0 0x00a90000 0 0x4000>;
1665 #size-cells = <0>;
1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1671 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1672 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1679 reg = <0 0x00a94000 0 0x4000>;
1681 #size-cells = <0>;
1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1687 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1688 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1695 reg = <0 0x00a94000 0 0x4000>;
1697 #size-cells = <0>;
1702 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1703 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1704 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1711 reg = <0 0x00a98000 0 0x4000>;
1713 #size-cells = <0>;
1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1719 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1720 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1727 reg = <0 0x00a98000 0 0x4000>;
1729 #size-cells = <0>;
1734 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1735 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1736 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1743 reg = <0 0x00a9c000 0 0x4000>;
1745 #size-cells = <0>;
1750 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1751 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1752 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1759 reg = <0 0x00a9c000 0 0x4000>;
1761 #size-cells = <0>;
1766 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1767 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1768 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1776 reg = <0 0x010d3000 0 0x1000>;
1784 reg = <0x0 0x01c00000 0x0 0x3000>,
1785 <0x0 0x30000000 0x0 0xf1d>,
1786 <0x0 0x30000f20 0x0 0xa8>,
1787 <0x0 0x30001000 0x0 0x1000>,
1788 <0x0 0x30100000 0x0 0x100000>,
1789 <0x0 0x01c03000 0x0 0x1000>;
1793 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1794 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1795 bus-range = <0x00 0xff>;
1802 msi-map = <0x0 &its 0xe0000 0x10000>;
1811 interrupt-map-mask = <0 0 0 0x7>;
1812 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1813 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1814 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1815 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1839 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1854 pcie4_port0: pcie@0 {
1856 reg = <0x0 0x0 0x0 0x0 0x0>;
1857 bus-range = <0x01 0xff>;
1867 reg = <0x0 0x01c06000 0x0 0x2000>;
1886 #clock-cells = <0>;
1889 #phy-cells = <0>;
1897 reg = <0x0 0x01c08000 0x0 0x3000>,
1898 <0x0 0x32000000 0x0 0xf1d>,
1899 <0x0 0x32000f20 0x0 0xa8>,
1900 <0x0 0x32001000 0x0 0x1000>,
1901 <0x0 0x32100000 0x0 0x100000>,
1902 <0x0 0x01c0b000 0x0 0x1000>;
1906 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1907 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1908 bus-range = <0x00 0xff>;
1915 msi-map = <0x0 &its 0xd0000 0x10000>;
1924 interrupt-map-mask = <0 0 0 0x7>;
1925 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1926 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1927 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1928 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1950 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1965 pcie3b_port0: pcie@0 {
1967 reg = <0x0 0x0 0x0 0x0 0x0>;
1968 bus-range = <0x01 0xff>;
1978 reg = <0x0 0x01c0e000 0x0 0x2000>;
1997 #clock-cells = <0>;
2000 #phy-cells = <0>;
2008 reg = <0x0 0x01c10000 0x0 0x3000>,
2009 <0x0 0x34000000 0x0 0xf1d>,
2010 <0x0 0x34000f20 0x0 0xa8>,
2011 <0x0 0x34001000 0x0 0x1000>,
2012 <0x0 0x34100000 0x0 0x100000>,
2013 <0x0 0x01c13000 0x0 0x1000>;
2017 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
2018 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
2019 bus-range = <0x00 0xff>;
2026 msi-map = <0x0 &its 0xc0000 0x10000>;
2035 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
2037 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
2038 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
2039 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
2061 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2076 pcie3a_port0: pcie@0 {
2078 reg = <0x0 0x0 0x0 0x0 0x0>;
2079 bus-range = <0x01 0xff>;
2089 reg = <0x0 0x01c14000 0x0 0x2000>,
2090 <0x0 0x01c16000 0x0 0x2000>;
2109 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2111 #clock-cells = <0>;
2114 #phy-cells = <0>;
2122 reg = <0x0 0x01c18000 0x0 0x3000>,
2123 <0x0 0x38000000 0x0 0xf1d>,
2124 <0x0 0x38000f20 0x0 0xa8>,
2125 <0x0 0x38001000 0x0 0x1000>,
2126 <0x0 0x38100000 0x0 0x100000>,
2127 <0x0 0x01c1b000 0x0 0x1000>;
2131 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2132 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2133 bus-range = <0x00 0xff>;
2140 msi-map = <0x0 &its 0xb0000 0x10000>;
2149 interrupt-map-mask = <0 0 0 0x7>;
2150 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2151 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2152 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2153 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2175 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2176 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2190 pcie2b_port0: pcie@0 {
2192 reg = <0x0 0x0 0x0 0x0 0x0>;
2193 bus-range = <0x01 0xff>;
2203 reg = <0x0 0x01c1e000 0x0 0x2000>;
2222 #clock-cells = <0>;
2225 #phy-cells = <0>;
2233 reg = <0x0 0x01c20000 0x0 0x3000>,
2234 <0x0 0x3c000000 0x0 0xf1d>,
2235 <0x0 0x3c000f20 0x0 0xa8>,
2236 <0x0 0x3c001000 0x0 0x1000>,
2237 <0x0 0x3c100000 0x0 0x100000>,
2238 <0x0 0x01c23000 0x0 0x1000>;
2242 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2243 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2244 bus-range = <0x00 0xff>;
2251 msi-map = <0x0 &its 0xa0000 0x10000>;
2260 interrupt-map-mask = <0 0 0 0x7>;
2261 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2262 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2263 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2264 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2286 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2287 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2301 pcie2a_port0: pcie@0 {
2303 reg = <0x0 0x0 0x0 0x0 0x0>;
2304 bus-range = <0x01 0xff>;
2314 reg = <0x0 0x01c24000 0x0 0x2000>,
2315 <0x0 0x01c26000 0x0 0x2000>;
2334 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2336 #clock-cells = <0>;
2339 #phy-cells = <0>;
2347 reg = <0 0x01d84000 0 0x3000>;
2359 iommus = <&apps_smmu 0xe0 0x0>;
2379 <0 0>,
2380 <0 0>,
2382 <0 0>,
2383 <0 0>,
2384 <0 0>,
2385 <0 0>;
2391 reg = <0 0x01d87000 0 0x1000>;
2402 resets = <&ufs_mem_hc 0>;
2405 #phy-cells = <0>;
2413 reg = <0 0x01da4000 0 0x3000>;
2424 iommus = <&apps_smmu 0x4a0 0x0>;
2444 <0 0>,
2445 <0 0>,
2447 <0 0>,
2448 <0 0>,
2449 <0 0>,
2450 <0 0>;
2456 reg = <0 0x01da7000 0 0x1000>;
2467 resets = <&ufs_card_hc 0>;
2470 #phy-cells = <0>;
2477 reg = <0x0 0x01f40000 0x0 0x20000>;
2483 reg = <0x0 0x01fc0000 0x0 0x30000>;
2488 reg = <0 0x02400000 0 0x10000>;
2491 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2512 qcom,smem-states = <&smp2p_slpi_out 0>;
2533 #size-cells = <0>;
2538 iommus = <&apps_smmu 0x0521 0x0>;
2544 iommus = <&apps_smmu 0x0522 0x0>;
2550 iommus = <&apps_smmu 0x0523 0x0>;
2558 reg = <0 0x03000000 0 0x10000>;
2561 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2580 qcom,smem-states = <&smp2p_adsp_out 0>;
2601 #size-cells = <0>;
2606 #sound-dai-cells = <0>;
2611 iommus = <&apps_smmu 0x0c01 0x0>;
2636 reg = <0 0x03200000 0 0x1000>;
2648 #clock-cells = <0>;
2652 pinctrl-0 = <&rx_swr_default>;
2659 reg = <0 0x03210000 0 0x2000>;
2667 qcom,din-ports = <0>;
2670 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2671 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2672 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2673 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2674 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2675 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2676 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2677 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2678 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2682 #size-cells = <0>;
2689 reg = <0 0x03220000 0 0x1000>;
2691 pinctrl-0 = <&tx_swr_default>;
2704 #clock-cells = <0>;
2712 reg = <0 0x03240000 0 0x1000>;
2723 #clock-cells = <0>;
2728 pinctrl-0 = <&wsa_swr_default>;
2734 reg = <0 0x03250000 0 0x2000>;
2746 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2747 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2748 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2749 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2750 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2751 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2752 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2753 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2754 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2758 #size-cells = <0>;
2765 reg = <0 0x032a9000 0 0x1000>;
2772 reg = <0 0x03330000 0 0x2000>;
2784 #size-cells = <0>;
2787 qcom,dout-ports = <0>;
2788 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2789 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2790 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2791 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2792 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2793 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2794 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2795 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2796 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2803 reg = <0 0x03370000 0 0x1000>;
2812 #clock-cells = <0>;
2821 reg = <0 0x33c0000 0x0 0x20000>,
2822 <0 0x3550000 0x0 0x10000>;
2825 gpio-ranges = <&lpass_tlmm 0 0 19>;
2976 reg = <0 0x033e0000 0 0x12000>;
2984 reg = <0 0x03d00000 0 0x40000>,
2985 <0 0x03d9e000 0 0x1000>,
2986 <0 0x03d61000 0 0x800>;
2991 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2995 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3056 reg = <0 0x03d6a000 0 0x34000>,
3057 <0 0x03de0000 0 0x10000>,
3058 <0 0x0b290000 0 0x10000>;
3081 iommus = <&gpu_smmu 5 0xc00>;
3101 reg = <0 0x03d90000 0 0x9000>;
3118 reg = <0 0x03da0000 0 0x20000>;
3157 reg = <0 0x08804000 0 0x1000>;
3168 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3171 iommus = <&apps_smmu 0x4e0 0x0>;
3186 opp-avg-kBps = <100000 0>;
3193 opp-avg-kBps = <200000 0>;
3201 reg = <0 0x088e5000 0 0x400>;
3206 #phy-cells = <0>;
3214 reg = <0 0x088e7000 0 0x400>;
3219 #phy-cells = <0>;
3227 reg = <0 0x088e8000 0 0x400>;
3232 #phy-cells = <0>;
3240 reg = <0 0x088e9000 0 0x400>;
3245 #phy-cells = <0>;
3253 reg = <0 0x088ea000 0 0x400>;
3258 #phy-cells = <0>;
3265 reg = <0 0x088eb000 0 0x4000>;
3286 #size-cells = <0>;
3288 port@0 {
3289 reg = <0>;
3312 reg = <0 0x088ef000 0 0x2000>;
3326 #clock-cells = <0>;
3329 #phy-cells = <0>;
3336 reg = <0 0x088f1000 0 0x2000>;
3350 #clock-cells = <0>;
3353 #phy-cells = <0>;
3361 reg = <0 0x08902000 0 0x400>;
3362 #phy-cells = <0>;
3374 reg = <0 0x08903000 0 0x4000>;
3395 #size-cells = <0>;
3397 port@0 {
3398 reg = <0>;
3421 reg = <0 0x08909a00 0 0x19c>,
3422 <0 0x08909200 0 0xec>,
3423 <0 0x08909600 0 0xec>,
3424 <0 0x08909000 0 0x1c8>;
3432 #phy-cells = <0>;
3439 reg = <0 0x0890ca00 0 0x19c>,
3440 <0 0x0890c200 0 0xec>,
3441 <0 0x0890c600 0 0xec>,
3442 <0 0x0890c000 0 0x1c8>;
3450 #phy-cells = <0>;
3457 reg = <0 0x09091000 0 0x1000>;
3468 opp-0 {
3512 reg = <0 0x090b6400 0 0x600>;
3522 opp-0 {
3548 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3549 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3550 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3551 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3552 <0 0x09600000 0 0x58000>;
3561 reg = <0 0x0a4f8800 0 0x400>;
3616 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
3617 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
3626 reg = <0 0x0a400000 0 0xcd00>;
3628 iommus = <&apps_smmu 0x800 0x0>;
3633 phy-names = "usb2-0", "usb3-0",
3645 reg = <0 0x0a6f8800 0 0x400>;
3682 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3683 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3692 reg = <0 0x0a600000 0 0xcd00>;
3694 iommus = <&apps_smmu 0x820 0x0>;
3702 #size-cells = <0>;
3704 port@0 {
3705 reg = <0>;
3724 reg = <0 0x0a8f8800 0 0x400>;
3761 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3762 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3771 reg = <0 0x0a800000 0 0xcd00>;
3773 iommus = <&apps_smmu 0x860 0x0>;
3781 #size-cells = <0>;
3783 port@0 {
3784 reg = <0>;
3803 reg = <0 0x0ac4a000 0 0x1000>;
3818 pinctrl-0 = <&cci0_default>;
3823 #size-cells = <0>;
3827 cci0_i2c0: i2c-bus@0 {
3828 reg = <0>;
3831 #size-cells = <0>;
3838 #size-cells = <0>;
3844 reg = <0 0x0ac4b000 0 0x1000>;
3859 pinctrl-0 = <&cci1_default>;
3864 #size-cells = <0>;
3868 cci1_i2c0: i2c-bus@0 {
3869 reg = <0>;
3872 #size-cells = <0>;
3879 #size-cells = <0>;
3885 reg = <0 0x0ac4c000 0 0x1000>;
3899 pinctrl-0 = <&cci2_default>;
3904 #size-cells = <0>;
3908 cci2_i2c0: i2c-bus@0 {
3909 reg = <0>;
3912 #size-cells = <0>;
3919 #size-cells = <0>;
3925 reg = <0 0x0ac4d000 0 0x1000>;
3940 pinctrl-0 = <&cci3_default>;
3945 #size-cells = <0>;
3949 cci3_i2c0: i2c-bus@0 {
3950 reg = <0>;
3953 #size-cells = <0>;
3960 #size-cells = <0>;
3967 reg = <0 0x0ac5a000 0 0x2000>,
3968 <0 0x0ac5c000 0 0x2000>,
3969 <0 0x0ac65000 0 0x2000>,
3970 <0 0x0ac67000 0 0x2000>,
3971 <0 0x0acaf000 0 0x4000>,
3972 <0 0x0acb3000 0 0x1000>,
3973 <0 0x0acb6000 0 0x4000>,
3974 <0 0x0acba000 0 0x1000>,
3975 <0 0x0acbd000 0 0x4000>,
3976 <0 0x0acc1000 0 0x1000>,
3977 <0 0x0acc4000 0 0x4000>,
3978 <0 0x0acc8000 0 0x1000>,
3979 <0 0x0accb000 0 0x4000>,
3980 <0 0x0accf000 0 0x1000>,
3981 <0 0x0acd2000 0 0x4000>,
3982 <0 0x0acd6000 0 0x1000>,
3983 <0 0x0acd9000 0 0x4000>,
3984 <0 0x0acdd000 0 0x1000>,
3985 <0 0x0ace0000 0 0x4000>,
3986 <0 0x0ace4000 0 0x1000>;
4141 iommus = <&apps_smmu 0x2000 0x4e0>,
4142 <&apps_smmu 0x2020 0x4e0>,
4143 <&apps_smmu 0x2040 0x4e0>,
4144 <&apps_smmu 0x2060 0x4e0>,
4145 <&apps_smmu 0x2080 0x4e0>,
4146 <&apps_smmu 0x20e0 0x4e0>,
4147 <&apps_smmu 0x20c0 0x4e0>,
4148 <&apps_smmu 0x20a0 0x4e0>,
4149 <&apps_smmu 0x2400 0x4e0>,
4150 <&apps_smmu 0x2420 0x4e0>,
4151 <&apps_smmu 0x2440 0x4e0>,
4152 <&apps_smmu 0x2460 0x4e0>,
4153 <&apps_smmu 0x2480 0x4e0>,
4154 <&apps_smmu 0x24e0 0x4e0>,
4155 <&apps_smmu 0x24c0 0x4e0>,
4156 <&apps_smmu 0x24a0 0x4e0>;
4158 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
4159 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
4160 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
4161 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
4171 #size-cells = <0>;
4173 port@0 {
4174 reg = <0>;
4176 #size-cells = <0>;
4182 #size-cells = <0>;
4188 #size-cells = <0>;
4194 #size-cells = <0>;
4201 reg = <0 0x0ad00000 0 0x20000>;
4215 reg = <0 0x0ae00000 0 0x1000>;
4225 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4226 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4228 iommus = <&apps_smmu 0x1000 0x402>;
4242 reg = <0 0x0ae01000 0 0x8f000>,
4243 <0 0x0aeb0000 0 0x3000>;
4259 interrupts = <0>;
4268 #size-cells = <0>;
4270 port@0 {
4271 reg = <0>;
4330 reg = <0 0xae90000 0 0x200>,
4331 <0 0xae90200 0 0x200>,
4332 <0 0xae90400 0 0x600>,
4333 <0 0xae91000 0 0x400>,
4334 <0 0xae91400 0 0x400>;
4355 #sound-dai-cells = <0>;
4364 #size-cells = <0>;
4366 port@0 {
4367 reg = <0>;
4409 reg = <0 0xae98000 0 0x200>,
4410 <0 0xae98200 0 0x200>,
4411 <0 0xae98400 0 0x600>,
4412 <0 0xae99000 0 0x400>,
4413 <0 0xae99400 0 0x400>;
4433 #sound-dai-cells = <0>;
4442 #size-cells = <0>;
4444 port@0 {
4445 reg = <0>;
4487 reg = <0 0xae9a000 0 0x200>,
4488 <0 0xae9a200 0 0x200>,
4489 <0 0xae9a400 0 0x600>,
4490 <0 0xae9b000 0 0x400>,
4491 <0 0xae9b400 0 0x400>;
4509 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4512 #sound-dai-cells = <0>;
4518 #size-cells = <0>;
4520 port@0 {
4521 reg = <0>;
4559 reg = <0 0xaea0000 0 0x200>,
4560 <0 0xaea0200 0 0x200>,
4561 <0 0xaea0400 0 0x600>,
4562 <0 0xaea1000 0 0x400>,
4563 <0 0xaea1400 0 0x400>;
4581 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4584 #sound-dai-cells = <0>;
4590 #size-cells = <0>;
4592 port@0 {
4593 reg = <0>;
4632 reg = <0 0x0aec2a00 0 0x19c>,
4633 <0 0x0aec2200 0 0xec>,
4634 <0 0x0aec2600 0 0xec>,
4635 <0 0x0aec2000 0 0x1c8>;
4643 #phy-cells = <0>;
4650 reg = <0 0x0aec5a00 0 0x19c>,
4651 <0 0x0aec5200 0 0xec>,
4652 <0 0x0aec5600 0 0xec>,
4653 <0 0x0aec5000 0 0x1c8>;
4661 #phy-cells = <0>;
4668 reg = <0 0x0af00000 0 0x20000>;
4677 <&mdss0_dp2_phy 0>,
4679 <&mdss0_dp3_phy 0>,
4681 <0>,
4682 <0>,
4683 <0>,
4684 <0>;
4696 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4697 qcom,pdc-ranges = <0 480 40>,
4761 reg = <0 0x0c251000 0 0x1ff>,
4762 <0 0x0c224000 0 0x8>;
4772 reg = <0 0x0c252000 0 0x1ff>,
4773 <0 0x0c225000 0 0x8>;
4783 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4784 <0 0x0c222000 0 0x8>; /* SROT */
4794 reg = <0 0x0c264000 0 0x4>;
4801 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4802 <0 0x0c223000 0 0x8>; /* SROT */
4812 reg = <0 0x0c300000 0 0x400>;
4816 #clock-cells = <0>;
4821 reg = <0 0x0c3f0000 0 0x400>;
4827 reg = <0 0x0c440000 0 0x1100>,
4828 <0 0x0c600000 0 0x2000000>,
4829 <0 0x0e600000 0 0x100000>,
4830 <0 0x0e700000 0 0xa0000>,
4831 <0 0x0c40a000 0 0x26000>;
4835 qcom,ee = <0>;
4836 qcom,channel = <0>;
4838 #size-cells = <0>;
4845 reg = <0 0x0f100000 0 0x300000>;
4851 gpio-ranges = <&tlmm 0 0 230>;
5031 reg = <0 0x14f80000 0 0x80000>;
5045 reg = <0 0x15000000 0 0x100000>;
5185 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5186 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5189 redistributor-stride = <0 0x20000>;
5197 reg = <0 0x17a40000 0 0x20000>;
5205 reg = <0 0x17c10000 0 0x1000>;
5207 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5212 reg = <0x0 0x17c20000 0x0 0x1000>;
5215 ranges = <0x0 0x0 0x0 0x20000000>;
5218 frame-number = <0>;
5221 reg = <0x17c21000 0x1000>,
5222 <0x17c22000 0x1000>;
5228 reg = <0x17c23000 0x1000>;
5235 reg = <0x17c25000 0x1000>;
5242 reg = <0x17c26000 0x1000>;
5249 reg = <0x17c29000 0x1000>;
5256 reg = <0x17c2b000 0x1000>;
5263 reg = <0x17c2d000 0x1000>;
5270 reg = <0x0 0x18200000 0x0 0x10000>,
5271 <0x0 0x18210000 0x0 0x10000>,
5272 <0x0 0x18220000 0x0 0x10000>;
5273 reg-names = "drv-0", "drv-1", "drv-2";
5277 qcom,tcs-offset = <0xd00>;
5348 reg = <0 0x18590000 0 0x1000>;
5358 reg = <0 0x18591000 0 0x1000>,
5359 <0 0x18592000 0 0x1000>;
5364 interrupt-names = "dcvsh-irq-0",
5376 reg = <0 0x1b300000 0 0x10000>;
5379 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5394 qcom,smem-states = <&smp2p_nsp0_out 0>;
5397 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5416 #size-cells = <0>;
5421 iommus = <&apps_smmu 0x3181 0x0420>;
5427 iommus = <&apps_smmu 0x3182 0x0420>;
5433 iommus = <&apps_smmu 0x3183 0x0420>;
5439 iommus = <&apps_smmu 0x3184 0x0420>;
5445 iommus = <&apps_smmu 0x3185 0x0420>;
5451 iommus = <&apps_smmu 0x3186 0x0420>;
5457 iommus = <&apps_smmu 0x3187 0x0420>;
5463 iommus = <&apps_smmu 0x3188 0x0420>;
5469 iommus = <&apps_smmu 0x318b 0x0420>;
5475 iommus = <&apps_smmu 0x318b 0x0420>;
5481 iommus = <&apps_smmu 0x318c 0x0420>;
5487 iommus = <&apps_smmu 0x318d 0x0420>;
5493 iommus = <&apps_smmu 0x318e 0x0420>;
5499 iommus = <&apps_smmu 0x318f 0x0420>;
5507 reg = <0 0x21300000 0 0x10000>;
5510 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5525 qcom,smem-states = <&smp2p_nsp1_out 0>;
5528 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5546 reg = <0 0x22000000 0 0x1000>;
5555 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5556 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5560 iommus = <&apps_smmu 0x1800 0x402>;
5574 reg = <0 0x22001000 0 0x8f000>,
5575 <0 0x220b0000 0 0x3000>;
5591 interrupts = <0>;
5600 #size-cells = <0>;
5602 port@0 {
5603 reg = <0>;
5662 reg = <0 0x22090000 0 0x200>,
5663 <0 0x22090200 0 0x200>,
5664 <0 0x22090400 0 0x600>,
5665 <0 0x22091000 0 0x400>,
5666 <0 0x22091400 0 0x400>;
5684 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5687 #sound-dai-cells = <0>;
5693 #size-cells = <0>;
5695 port@0 {
5696 reg = <0>;
5734 reg = <0 0x22098000 0 0x200>,
5735 <0 0x22098200 0 0x200>,
5736 <0 0x22098400 0 0x600>,
5737 <0 0x22099000 0 0x400>,
5738 <0 0x22099400 0 0x400>;
5756 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5759 #sound-dai-cells = <0>;
5765 #size-cells = <0>;
5767 port@0 {
5768 reg = <0>;
5806 reg = <0 0x2209a000 0 0x200>,
5807 <0 0x2209a200 0 0x200>,
5808 <0 0x2209a400 0 0x600>,
5809 <0 0x2209b000 0 0x400>,
5810 <0 0x2209b400 0 0x400>;
5828 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5831 #sound-dai-cells = <0>;
5837 #size-cells = <0>;
5839 port@0 {
5840 reg = <0>;
5878 reg = <0 0x220a0000 0 0x200>,
5879 <0 0x220a0200 0 0x200>,
5880 <0 0x220a0400 0 0x600>,
5881 <0 0x220a1000 0 0x400>,
5882 <0 0x220a1400 0 0x400>;
5900 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5903 #sound-dai-cells = <0>;
5909 #size-cells = <0>;
5911 port@0 {
5912 reg = <0>;
5951 reg = <0 0x220c2a00 0 0x19c>,
5952 <0 0x220c2200 0 0xec>,
5953 <0 0x220c2600 0 0xec>,
5954 <0 0x220c2000 0 0x1c8>;
5962 #phy-cells = <0>;
5969 reg = <0 0x220c5a00 0 0x19c>,
5970 <0 0x220c5200 0 0xec>,
5971 <0 0x220c5600 0 0xec>,
5972 <0 0x220c5000 0 0x1c8>;
5980 #phy-cells = <0>;
5987 reg = <0 0x22100000 0 0x20000>;
5991 <0>,
5992 <&mdss1_dp0_phy 0>,
5994 <&mdss1_dp1_phy 0>,
5996 <&mdss1_dp2_phy 0>,
5998 <&mdss1_dp3_phy 0>,
6000 <0>,
6001 <0>,
6002 <0>,
6003 <0>;
6015 reg = <0x0 0x23000000 0x0 0x10000>,
6016 <0x0 0x23016000 0x0 0x100>;
6032 iommus = <&apps_smmu 0x40 0xf>;