Lines Matching refs:gcc
9 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
790 gcc: clock-controller@100000 { label
791 compatible = "qcom,gcc-sc8180x";
808 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
809 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
835 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
849 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
861 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
876 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
890 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
902 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
917 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
931 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
943 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
958 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
972 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
984 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
999 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1013 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1025 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1040 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1054 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1066 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1081 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1095 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1107 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1122 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1136 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1149 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1150 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1161 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1176 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1190 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1202 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1217 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1231 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1243 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1258 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1272 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1284 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1299 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1313 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1325 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1340 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1354 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1366 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1381 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1395 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1408 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1409 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1420 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1435 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1449 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1461 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1476 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1490 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1502 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1517 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1531 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1543 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1558 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1572 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1584 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1599 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1613 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1625 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1640 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1654 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1754 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1755 <&gcc GCC_PCIE_0_AUX_CLK>,
1756 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1757 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1758 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1759 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
1767 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1773 resets = <&gcc GCC_PCIE_0_BCR>;
1776 power-domains = <&gcc PCIE_0_GDSC>;
1802 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1803 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1804 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1805 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1806 <&gcc GCC_PCIE_0_PIPE_CLK>;
1816 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1819 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1873 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1874 <&gcc GCC_PCIE_3_AUX_CLK>,
1875 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1876 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1877 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1878 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>;
1886 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1892 resets = <&gcc GCC_PCIE_3_BCR>;
1895 power-domains = <&gcc PCIE_3_GDSC>;
1921 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1923 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1924 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
1925 <&gcc GCC_PCIE_3_PIPE_CLK>;
1936 resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1939 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1993 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1994 <&gcc GCC_PCIE_1_AUX_CLK>,
1995 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1996 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1997 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1998 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
2006 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2012 resets = <&gcc GCC_PCIE_1_BCR>;
2015 power-domains = <&gcc PCIE_1_GDSC>;
2041 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2044 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2045 <&gcc GCC_PCIE_1_PIPE_CLK>;
2056 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2059 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2113 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2114 <&gcc GCC_PCIE_2_AUX_CLK>,
2115 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2116 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2117 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2118 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>;
2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2132 resets = <&gcc GCC_PCIE_2_BCR>;
2135 power-domains = <&gcc PCIE_2_GDSC>;
2161 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2162 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2163 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2164 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2165 <&gcc GCC_PCIE_2_PIPE_CLK>;
2176 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2194 resets = <&gcc GCC_UFS_PHY_BCR>;
2199 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2200 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2201 <&gcc GCC_UFS_PHY_AHB_CLK>,
2202 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2204 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2205 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2206 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2224 power-domains = <&gcc UFS_PHY_GDSC>;
2240 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2241 <&gcc GCC_UFS_MEM_CLKREF_EN>;
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2343 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2344 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2374 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2375 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2400 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2401 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2494 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2507 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2523 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;
2537 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;
2552 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2553 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2554 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2555 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2561 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
2562 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
2600 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2601 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2602 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2603 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2609 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2610 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2613 power-domains = <&gcc USB30_MP_GDSC>;
2627 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2628 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2629 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2630 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2636 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2637 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2640 power-domains = <&gcc USB30_MP_GDSC>;
2654 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2655 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2656 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2657 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2662 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
2663 <&gcc GCC_USB3_PHY_SEC_BCR>;
2725 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
2726 <&gcc GCC_USB30_MP_MASTER_CLK>,
2727 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
2728 <&gcc GCC_USB30_MP_SLEEP_CLK>,
2729 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2730 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2742 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2743 <&gcc GCC_USB30_MP_MASTER_CLK>;
2762 power-domains = <&gcc USB30_MP_GDSC>;
2764 resets = <&gcc GCC_USB30_MP_BCR>;
2803 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2804 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2805 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2806 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2807 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2808 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2815 resets = <&gcc GCC_USB30_PRIM_BCR>;
2816 power-domains = <&gcc USB30_PRIM_GDSC>;
2822 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2823 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2871 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2872 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2873 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2874 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2875 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2876 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2883 resets = <&gcc GCC_USB30_SEC_BCR>;
2884 power-domains = <&gcc USB30_SEC_GDSC>;
2897 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2898 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2950 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
2963 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2981 <&gcc GCC_DISP_HF_AXI_CLK>,
2982 <&gcc GCC_DISP_SF_AXI_CLK>,
3020 <&gcc GCC_DISP_HF_AXI_CLK>,
3120 <&gcc GCC_DISP_HF_AXI_CLK>;
3209 <&gcc GCC_DISP_HF_AXI_CLK>;
3927 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3962 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;