Lines Matching +full:smp2p +full:- +full:mpss
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sc8180x-camcc.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc8180x.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/thermal/thermal.h>
23 interrupt-parent = <&intc>;
25 #address-cells = <2>;
26 #size-cells = <2>;
29 xo_board_clk: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <38400000>;
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
44 #address-cells = <2>;
45 #size-cells = <0>;
51 enable-method = "psci";
52 capacity-dmips-mhz = <602>;
53 next-level-cache = <&l2_0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
55 operating-points-v2 = <&cpu0_opp_table>;
58 power-domains = <&cpu_pd0>;
59 power-domain-names = "psci";
60 #cooling-cells = <2>;
63 l2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&l3_0>;
68 l3_0: l3-cache {
70 cache-level = <3>;
71 cache-unified;
80 enable-method = "psci";
81 capacity-dmips-mhz = <602>;
82 next-level-cache = <&l2_100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 operating-points-v2 = <&cpu0_opp_table>;
87 power-domains = <&cpu_pd1>;
88 power-domain-names = "psci";
89 #cooling-cells = <2>;
92 l2_100: l2-cache {
94 cache-level = <2>;
95 cache-unified;
96 next-level-cache = <&l3_0>;
105 enable-method = "psci";
106 capacity-dmips-mhz = <602>;
107 next-level-cache = <&l2_200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
109 operating-points-v2 = <&cpu0_opp_table>;
112 power-domains = <&cpu_pd2>;
113 power-domain-names = "psci";
114 #cooling-cells = <2>;
117 l2_200: l2-cache {
119 cache-level = <2>;
120 cache-unified;
121 next-level-cache = <&l3_0>;
129 enable-method = "psci";
130 capacity-dmips-mhz = <602>;
131 next-level-cache = <&l2_300>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = <&cpu0_opp_table>;
136 power-domains = <&cpu_pd3>;
137 power-domain-names = "psci";
138 #cooling-cells = <2>;
141 l2_300: l2-cache {
143 cache-unified;
144 cache-level = <2>;
145 next-level-cache = <&l3_0>;
153 enable-method = "psci";
154 capacity-dmips-mhz = <1024>;
155 next-level-cache = <&l2_400>;
156 qcom,freq-domain = <&cpufreq_hw 1>;
157 operating-points-v2 = <&cpu4_opp_table>;
160 power-domains = <&cpu_pd4>;
161 power-domain-names = "psci";
162 #cooling-cells = <2>;
165 l2_400: l2-cache {
167 cache-unified;
168 cache-level = <2>;
169 next-level-cache = <&l3_0>;
177 enable-method = "psci";
178 capacity-dmips-mhz = <1024>;
179 next-level-cache = <&l2_500>;
180 qcom,freq-domain = <&cpufreq_hw 1>;
181 operating-points-v2 = <&cpu4_opp_table>;
184 power-domains = <&cpu_pd5>;
185 power-domain-names = "psci";
186 #cooling-cells = <2>;
189 l2_500: l2-cache {
191 cache-unified;
192 cache-level = <2>;
193 next-level-cache = <&l3_0>;
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
203 next-level-cache = <&l2_600>;
204 qcom,freq-domain = <&cpufreq_hw 1>;
205 operating-points-v2 = <&cpu4_opp_table>;
208 power-domains = <&cpu_pd6>;
209 power-domain-names = "psci";
210 #cooling-cells = <2>;
213 l2_600: l2-cache {
215 cache-unified;
216 cache-level = <2>;
217 next-level-cache = <&l3_0>;
225 enable-method = "psci";
226 capacity-dmips-mhz = <1024>;
227 next-level-cache = <&l2_700>;
228 qcom,freq-domain = <&cpufreq_hw 1>;
229 operating-points-v2 = <&cpu4_opp_table>;
232 power-domains = <&cpu_pd7>;
233 power-domain-names = "psci";
234 #cooling-cells = <2>;
237 l2_700: l2-cache {
239 cache-unified;
240 cache-level = <2>;
241 next-level-cache = <&l3_0>;
245 cpu-map {
281 idle-states {
282 entry-method = "psci";
284 little_cpu_sleep_0: cpu-sleep-0-0 {
285 compatible = "arm,idle-state";
286 arm,psci-suspend-param = <0x40000004>;
287 entry-latency-us = <355>;
288 exit-latency-us = <909>;
289 min-residency-us = <3934>;
290 local-timer-stop;
293 big_cpu_sleep_0: cpu-sleep-1-0 {
294 compatible = "arm,idle-state";
295 arm,psci-suspend-param = <0x40000004>;
296 entry-latency-us = <2411>;
297 exit-latency-us = <1461>;
298 min-residency-us = <4488>;
299 local-timer-stop;
303 domain-idle-states {
304 cluster_sleep_apss_off: cluster-sleep-0 {
305 compatible = "domain-idle-state";
306 arm,psci-suspend-param = <0x41000044>;
307 entry-latency-us = <3300>;
308 exit-latency-us = <3300>;
309 min-residency-us = <6000>;
312 cluster_sleep_aoss_sleep: cluster-sleep-1 {
313 compatible = "domain-idle-state";
314 arm,psci-suspend-param = <0x4100a344>;
315 entry-latency-us = <3263>;
316 exit-latency-us = <6562>;
317 min-residency-us = <9987>;
322 cpu0_opp_table: opp-table-cpu0 {
323 compatible = "operating-points-v2";
324 opp-shared;
326 opp-300000000 {
327 opp-hz = /bits/ 64 <300000000>;
328 opp-peak-kBps = <800000 9600000>;
331 opp-422400000 {
332 opp-hz = /bits/ 64 <422400000>;
333 opp-peak-kBps = <800000 9600000>;
336 opp-537600000 {
337 opp-hz = /bits/ 64 <537600000>;
338 opp-peak-kBps = <800000 12902400>;
341 opp-652800000 {
342 opp-hz = /bits/ 64 <652800000>;
343 opp-peak-kBps = <800000 12902400>;
346 opp-768000000 {
347 opp-hz = /bits/ 64 <768000000>;
348 opp-peak-kBps = <800000 15974400>;
351 opp-883200000 {
352 opp-hz = /bits/ 64 <883200000>;
353 opp-peak-kBps = <1804000 19660800>;
356 opp-998400000 {
357 opp-hz = /bits/ 64 <998400000>;
358 opp-peak-kBps = <1804000 19660800>;
361 opp-1113600000 {
362 opp-hz = /bits/ 64 <1113600000>;
363 opp-peak-kBps = <1804000 22732800>;
366 opp-1228800000 {
367 opp-hz = /bits/ 64 <1228800000>;
368 opp-peak-kBps = <1804000 22732800>;
371 opp-1363200000 {
372 opp-hz = /bits/ 64 <1363200000>;
373 opp-peak-kBps = <2188000 25804800>;
376 opp-1478400000 {
377 opp-hz = /bits/ 64 <1478400000>;
378 opp-peak-kBps = <2188000 31948800>;
381 opp-1574400000 {
382 opp-hz = /bits/ 64 <1574400000>;
383 opp-peak-kBps = <3072000 31948800>;
386 opp-1670400000 {
387 opp-hz = /bits/ 64 <1670400000>;
388 opp-peak-kBps = <3072000 31948800>;
391 opp-1766400000 {
392 opp-hz = /bits/ 64 <1766400000>;
393 opp-peak-kBps = <3072000 31948800>;
397 cpu4_opp_table: opp-table-cpu4 {
398 compatible = "operating-points-v2";
399 opp-shared;
401 opp-825600000 {
402 opp-hz = /bits/ 64 <825600000>;
403 opp-peak-kBps = <1804000 15974400>;
406 opp-940800000 {
407 opp-hz = /bits/ 64 <940800000>;
408 opp-peak-kBps = <2188000 19660800>;
411 opp-1056000000 {
412 opp-hz = /bits/ 64 <1056000000>;
413 opp-peak-kBps = <2188000 22732800>;
416 opp-1171200000 {
417 opp-hz = /bits/ 64 <1171200000>;
418 opp-peak-kBps = <3072000 25804800>;
421 opp-1286400000 {
422 opp-hz = /bits/ 64 <1286400000>;
423 opp-peak-kBps = <3072000 31948800>;
426 opp-1420800000 {
427 opp-hz = /bits/ 64 <1420800000>;
428 opp-peak-kBps = <4068000 31948800>;
431 opp-1536000000 {
432 opp-hz = /bits/ 64 <1536000000>;
433 opp-peak-kBps = <4068000 31948800>;
436 opp-1651200000 {
437 opp-hz = /bits/ 64 <1651200000>;
438 opp-peak-kBps = <4068000 40550400>;
441 opp-1766400000 {
442 opp-hz = /bits/ 64 <1766400000>;
443 opp-peak-kBps = <4068000 40550400>;
446 opp-1881600000 {
447 opp-hz = /bits/ 64 <1881600000>;
448 opp-peak-kBps = <4068000 43008000>;
451 opp-1996800000 {
452 opp-hz = /bits/ 64 <1996800000>;
453 opp-peak-kBps = <6220000 43008000>;
456 opp-2131200000 {
457 opp-hz = /bits/ 64 <2131200000>;
458 opp-peak-kBps = <6220000 49152000>;
461 opp-2246400000 {
462 opp-hz = /bits/ 64 <2246400000>;
463 opp-peak-kBps = <7216000 49152000>;
466 opp-2361600000 {
467 opp-hz = /bits/ 64 <2361600000>;
468 opp-peak-kBps = <8368000 49152000>;
471 opp-2457600000 {
472 opp-hz = /bits/ 64 <2457600000>;
473 opp-peak-kBps = <8368000 51609600>;
476 opp-2553600000 {
477 opp-hz = /bits/ 64 <2553600000>;
478 opp-peak-kBps = <8368000 51609600>;
481 opp-2649600000 {
482 opp-hz = /bits/ 64 <2649600000>;
483 opp-peak-kBps = <8368000 51609600>;
486 opp-2745600000 {
487 opp-hz = /bits/ 64 <2745600000>;
488 opp-peak-kBps = <8368000 51609600>;
491 opp-2841600000 {
492 opp-hz = /bits/ 64 <2841600000>;
493 opp-peak-kBps = <8368000 51609600>;
496 opp-2918400000 {
497 opp-hz = /bits/ 64 <2918400000>;
498 opp-peak-kBps = <8368000 51609600>;
501 opp-2995200000 {
502 opp-hz = /bits/ 64 <2995200000>;
503 opp-peak-kBps = <8368000 51609600>;
509 compatible = "qcom,scm-sc8180x", "qcom,scm";
513 camnoc_virt: interconnect-camnoc-virt {
514 compatible = "qcom,sc8180x-camnoc-virt";
515 #interconnect-cells = <2>;
516 qcom,bcm-voters = <&apps_bcm_voter>;
519 mc_virt: interconnect-mc-virt {
520 compatible = "qcom,sc8180x-mc-virt";
521 #interconnect-cells = <2>;
522 qcom,bcm-voters = <&apps_bcm_voter>;
525 qup_virt: interconnect-qup-virt {
526 compatible = "qcom,sc8180x-qup-virt";
527 #interconnect-cells = <2>;
528 qcom,bcm-voters = <&apps_bcm_voter>;
538 compatible = "arm,armv8-pmuv3";
543 compatible = "arm,psci-1.0";
546 cpu_pd0: power-domain-cpu0 {
547 #power-domain-cells = <0>;
548 power-domains = <&cluster_pd>;
549 domain-idle-states = <&little_cpu_sleep_0>;
552 cpu_pd1: power-domain-cpu1 {
553 #power-domain-cells = <0>;
554 power-domains = <&cluster_pd>;
555 domain-idle-states = <&little_cpu_sleep_0>;
558 cpu_pd2: power-domain-cpu2 {
559 #power-domain-cells = <0>;
560 power-domains = <&cluster_pd>;
561 domain-idle-states = <&little_cpu_sleep_0>;
564 cpu_pd3: power-domain-cpu3 {
565 #power-domain-cells = <0>;
566 power-domains = <&cluster_pd>;
567 domain-idle-states = <&little_cpu_sleep_0>;
570 cpu_pd4: power-domain-cpu4 {
571 #power-domain-cells = <0>;
572 power-domains = <&cluster_pd>;
573 domain-idle-states = <&big_cpu_sleep_0>;
576 cpu_pd5: power-domain-cpu5 {
577 #power-domain-cells = <0>;
578 power-domains = <&cluster_pd>;
579 domain-idle-states = <&big_cpu_sleep_0>;
582 cpu_pd6: power-domain-cpu6 {
583 #power-domain-cells = <0>;
584 power-domains = <&cluster_pd>;
585 domain-idle-states = <&big_cpu_sleep_0>;
588 cpu_pd7: power-domain-cpu7 {
589 #power-domain-cells = <0>;
590 power-domains = <&cluster_pd>;
591 domain-idle-states = <&big_cpu_sleep_0>;
594 cluster_pd: power-domain-cpu-cluster0 {
595 #power-domain-cells = <0>;
596 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
600 reserved-memory {
601 #address-cells = <2>;
602 #size-cells = <2>;
607 no-map;
612 no-map;
617 no-map;
620 aop_cmd_db: cmd-db@85f20000 {
621 compatible = "qcom,cmd-db";
623 no-map;
628 no-map;
634 no-map;
640 no-map;
645 no-map;
650 no-map;
655 no-map;
660 no-map;
664 smp2p-cdsp {
665 compatible = "qcom,smp2p";
672 qcom,local-pid = <0>;
673 qcom,remote-pid = <5>;
675 cdsp_smp2p_out: master-kernel {
676 qcom,entry-name = "master-kernel";
677 #qcom,smem-state-cells = <1>;
680 cdsp_smp2p_in: slave-kernel {
681 qcom,entry-name = "slave-kernel";
683 interrupt-controller;
684 #interrupt-cells = <2>;
688 smp2p-lpass {
689 compatible = "qcom,smp2p";
696 qcom,local-pid = <0>;
697 qcom,remote-pid = <2>;
699 adsp_smp2p_out: master-kernel {
700 qcom,entry-name = "master-kernel";
701 #qcom,smem-state-cells = <1>;
704 adsp_smp2p_in: slave-kernel {
705 qcom,entry-name = "slave-kernel";
707 interrupt-controller;
708 #interrupt-cells = <2>;
712 smp2p-mpss {
713 compatible = "qcom,smp2p";
720 qcom,local-pid = <0>;
721 qcom,remote-pid = <1>;
723 modem_smp2p_out: master-kernel {
724 qcom,entry-name = "master-kernel";
725 #qcom,smem-state-cells = <1>;
728 modem_smp2p_in: slave-kernel {
729 qcom,entry-name = "slave-kernel";
731 interrupt-controller;
732 #interrupt-cells = <2>;
735 modem_smp2p_ipa_out: ipa-ap-to-modem {
736 qcom,entry-name = "ipa";
737 #qcom,smem-state-cells = <1>;
740 modem_smp2p_ipa_in: ipa-modem-to-ap {
741 qcom,entry-name = "ipa";
742 interrupt-controller;
743 #interrupt-cells = <2>;
746 modem_smp2p_wlan_in: wlan-wpss-to-ap {
747 qcom,entry-name = "wlan";
748 interrupt-controller;
749 #interrupt-cells = <2>;
753 smp2p-slpi {
754 compatible = "qcom,smp2p";
761 qcom,local-pid = <0>;
762 qcom,remote-pid = <3>;
764 slpi_smp2p_out: master-kernel {
765 qcom,entry-name = "master-kernel";
766 #qcom,smem-state-cells = <1>;
769 slpi_smp2p_in: slave-kernel {
770 qcom,entry-name = "slave-kernel";
772 interrupt-controller;
773 #interrupt-cells = <2>;
778 compatible = "simple-bus";
779 #address-cells = <2>;
780 #size-cells = <2>;
782 dma-ranges = <0 0 0 0 0x10 0>;
784 gcc: clock-controller@100000 {
785 compatible = "qcom,gcc-sc8180x";
787 #clock-cells = <1>;
788 #reset-cells = <1>;
789 #power-domain-cells = <1>;
793 clock-names = "bi_tcxo",
796 power-domains = <&rpmhpd SC8180X_CX>;
800 compatible = "qcom,geni-se-qup";
804 clock-names = "m-ahb", "s-ahb";
805 #address-cells = <2>;
806 #size-cells = <2>;
812 compatible = "qcom,geni-i2c";
815 clock-names = "se";
820 interconnect-names = "qup-core", "qup-config", "qup-memory";
821 #address-cells = <1>;
822 #size-cells = <0>;
827 compatible = "qcom,geni-spi";
830 clock-names = "se";
834 interconnect-names = "qup-core", "qup-config";
835 #address-cells = <1>;
836 #size-cells = <0>;
841 compatible = "qcom,geni-uart";
844 clock-names = "se";
848 interconnect-names = "qup-core", "qup-config";
853 compatible = "qcom,geni-i2c";
856 clock-names = "se";
861 interconnect-names = "qup-core", "qup-config", "qup-memory";
862 #address-cells = <1>;
863 #size-cells = <0>;
868 compatible = "qcom,geni-spi";
871 clock-names = "se";
875 interconnect-names = "qup-core", "qup-config";
876 #address-cells = <1>;
877 #size-cells = <0>;
882 compatible = "qcom,geni-uart";
885 clock-names = "se";
889 interconnect-names = "qup-core", "qup-config";
894 compatible = "qcom,geni-i2c";
897 clock-names = "se";
902 interconnect-names = "qup-core", "qup-config", "qup-memory";
903 #address-cells = <1>;
904 #size-cells = <0>;
909 compatible = "qcom,geni-spi";
912 clock-names = "se";
916 interconnect-names = "qup-core", "qup-config";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,geni-uart";
926 clock-names = "se";
930 interconnect-names = "qup-core", "qup-config";
935 compatible = "qcom,geni-i2c";
938 clock-names = "se";
943 interconnect-names = "qup-core", "qup-config", "qup-memory";
944 #address-cells = <1>;
945 #size-cells = <0>;
950 compatible = "qcom,geni-spi";
953 clock-names = "se";
957 interconnect-names = "qup-core", "qup-config";
958 #address-cells = <1>;
959 #size-cells = <0>;
964 compatible = "qcom,geni-uart";
967 clock-names = "se";
971 interconnect-names = "qup-core", "qup-config";
976 compatible = "qcom,geni-i2c";
979 clock-names = "se";
984 interconnect-names = "qup-core", "qup-config", "qup-memory";
985 #address-cells = <1>;
986 #size-cells = <0>;
991 compatible = "qcom,geni-spi";
994 clock-names = "se";
998 interconnect-names = "qup-core", "qup-config";
999 #address-cells = <1>;
1000 #size-cells = <0>;
1005 compatible = "qcom,geni-uart";
1008 clock-names = "se";
1012 interconnect-names = "qup-core", "qup-config";
1017 compatible = "qcom,geni-i2c";
1020 clock-names = "se";
1025 interconnect-names = "qup-core", "qup-config", "qup-memory";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1032 compatible = "qcom,geni-spi";
1035 clock-names = "se";
1039 interconnect-names = "qup-core", "qup-config";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1046 compatible = "qcom,geni-uart";
1049 clock-names = "se";
1053 interconnect-names = "qup-core", "qup-config";
1058 compatible = "qcom,geni-i2c";
1061 clock-names = "se";
1066 interconnect-names = "qup-core", "qup-config", "qup-memory";
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1073 compatible = "qcom,geni-spi";
1076 clock-names = "se";
1080 interconnect-names = "qup-core", "qup-config";
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1087 compatible = "qcom,geni-uart";
1090 clock-names = "se";
1094 interconnect-names = "qup-core", "qup-config";
1099 compatible = "qcom,geni-i2c";
1102 clock-names = "se";
1107 interconnect-names = "qup-core", "qup-config", "qup-memory";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1114 compatible = "qcom,geni-spi";
1117 clock-names = "se";
1121 interconnect-names = "qup-core", "qup-config";
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,geni-uart";
1131 clock-names = "se";
1135 interconnect-names = "qup-core", "qup-config";
1141 compatible = "qcom,geni-se-qup";
1145 clock-names = "m-ahb", "s-ahb";
1146 #address-cells = <2>;
1147 #size-cells = <2>;
1153 compatible = "qcom,geni-i2c";
1156 clock-names = "se";
1161 interconnect-names = "qup-core", "qup-config", "qup-memory";
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1168 compatible = "qcom,geni-spi";
1171 clock-names = "se";
1175 interconnect-names = "qup-core", "qup-config";
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1182 compatible = "qcom,geni-uart";
1185 clock-names = "se";
1189 interconnect-names = "qup-core", "qup-config";
1194 compatible = "qcom,geni-i2c";
1197 clock-names = "se";
1202 interconnect-names = "qup-core", "qup-config", "qup-memory";
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1209 compatible = "qcom,geni-spi";
1212 clock-names = "se";
1216 interconnect-names = "qup-core", "qup-config";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1223 compatible = "qcom,geni-debug-uart";
1226 clock-names = "se";
1230 interconnect-names = "qup-core", "qup-config";
1235 compatible = "qcom,geni-i2c";
1238 clock-names = "se";
1243 interconnect-names = "qup-core", "qup-config", "qup-memory";
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1250 compatible = "qcom,geni-spi";
1253 clock-names = "se";
1257 interconnect-names = "qup-core", "qup-config";
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1264 compatible = "qcom,geni-uart";
1267 clock-names = "se";
1271 interconnect-names = "qup-core", "qup-config";
1276 compatible = "qcom,geni-i2c";
1279 clock-names = "se";
1284 interconnect-names = "qup-core", "qup-config", "qup-memory";
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1291 compatible = "qcom,geni-spi";
1294 clock-names = "se";
1298 interconnect-names = "qup-core", "qup-config";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1305 compatible = "qcom,geni-uart";
1308 clock-names = "se";
1312 interconnect-names = "qup-core", "qup-config";
1317 compatible = "qcom,geni-i2c";
1320 clock-names = "se";
1325 interconnect-names = "qup-core", "qup-config", "qup-memory";
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1332 compatible = "qcom,geni-spi";
1335 clock-names = "se";
1339 interconnect-names = "qup-core", "qup-config";
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1346 compatible = "qcom,geni-uart";
1349 clock-names = "se";
1353 interconnect-names = "qup-core", "qup-config";
1358 compatible = "qcom,geni-i2c";
1361 clock-names = "se";
1366 interconnect-names = "qup-core", "qup-config", "qup-memory";
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1373 compatible = "qcom,geni-spi";
1376 clock-names = "se";
1380 interconnect-names = "qup-core", "qup-config";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1387 compatible = "qcom,geni-uart";
1390 clock-names = "se";
1394 interconnect-names = "qup-core", "qup-config";
1400 compatible = "qcom,geni-se-qup";
1404 clock-names = "m-ahb", "s-ahb";
1405 #address-cells = <2>;
1406 #size-cells = <2>;
1412 compatible = "qcom,geni-i2c";
1415 clock-names = "se";
1420 interconnect-names = "qup-core", "qup-config", "qup-memory";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1427 compatible = "qcom,geni-spi";
1430 clock-names = "se";
1434 interconnect-names = "qup-core", "qup-config";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1441 compatible = "qcom,geni-uart";
1444 clock-names = "se";
1448 interconnect-names = "qup-core", "qup-config";
1453 compatible = "qcom,geni-i2c";
1456 clock-names = "se";
1461 interconnect-names = "qup-core", "qup-config", "qup-memory";
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1468 compatible = "qcom,geni-spi";
1471 clock-names = "se";
1475 interconnect-names = "qup-core", "qup-config";
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1482 compatible = "qcom,geni-uart";
1485 clock-names = "se";
1489 interconnect-names = "qup-core", "qup-config";
1494 compatible = "qcom,geni-i2c";
1497 clock-names = "se";
1502 interconnect-names = "qup-core", "qup-config", "qup-memory";
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1509 compatible = "qcom,geni-spi";
1512 clock-names = "se";
1516 interconnect-names = "qup-core", "qup-config";
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1523 compatible = "qcom,geni-uart";
1526 clock-names = "se";
1530 interconnect-names = "qup-core", "qup-config";
1535 compatible = "qcom,geni-i2c";
1538 clock-names = "se";
1543 interconnect-names = "qup-core", "qup-config", "qup-memory";
1544 #address-cells = <1>;
1545 #size-cells = <0>;
1550 compatible = "qcom,geni-spi";
1553 clock-names = "se";
1557 interconnect-names = "qup-core", "qup-config";
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1564 compatible = "qcom,geni-uart";
1567 clock-names = "se";
1571 interconnect-names = "qup-core", "qup-config";
1576 compatible = "qcom,geni-i2c";
1579 clock-names = "se";
1584 interconnect-names = "qup-core", "qup-config", "qup-memory";
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1591 compatible = "qcom,geni-spi";
1594 clock-names = "se";
1598 interconnect-names = "qup-core", "qup-config";
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1605 compatible = "qcom,geni-uart";
1608 clock-names = "se";
1612 interconnect-names = "qup-core", "qup-config";
1617 compatible = "qcom,geni-i2c";
1620 clock-names = "se";
1625 interconnect-names = "qup-core", "qup-config", "qup-memory";
1626 #address-cells = <1>;
1627 #size-cells = <0>;
1632 compatible = "qcom,geni-spi";
1635 clock-names = "se";
1639 interconnect-names = "qup-core", "qup-config";
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1646 compatible = "qcom,geni-uart";
1649 clock-names = "se";
1653 interconnect-names = "qup-core", "qup-config";
1659 compatible = "qcom,sc8180x-config-noc";
1661 #interconnect-cells = <2>;
1662 qcom,bcm-voters = <&apps_bcm_voter>;
1666 compatible = "qcom,sc8180x-system-noc";
1668 #interconnect-cells = <2>;
1669 qcom,bcm-voters = <&apps_bcm_voter>;
1673 compatible = "qcom,sc8180x-aggre1-noc";
1675 #interconnect-cells = <2>;
1676 qcom,bcm-voters = <&apps_bcm_voter>;
1680 compatible = "qcom,sc8180x-aggre2-noc";
1682 #interconnect-cells = <2>;
1683 qcom,bcm-voters = <&apps_bcm_voter>;
1687 compatible = "qcom,sc8180x-compute-noc";
1689 #interconnect-cells = <2>;
1690 qcom,bcm-voters = <&apps_bcm_voter>;
1694 compatible = "qcom,sc8180x-mmss-noc";
1696 #interconnect-cells = <2>;
1697 qcom,bcm-voters = <&apps_bcm_voter>;
1701 compatible = "qcom,pcie-sc8180x";
1707 reg-names = "parf",
1713 linux,pci-domain = <0>;
1714 bus-range = <0x00 0xff>;
1715 num-lanes = <2>;
1717 #address-cells = <3>;
1718 #size-cells = <2>;
1732 interrupt-names = "msi0",
1741 #interrupt-cells = <1>;
1742 interrupt-map-mask = <0 0 0 0x7>;
1743 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1754 clock-names = "pipe",
1761 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1762 assigned-clock-rates = <19200000>;
1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1768 reset-names = "pci";
1770 power-domains = <&gcc PCIE_0_GDSC>;
1774 interconnect-names = "pcie-mem", "cpu-pcie";
1777 phy-names = "pciephy";
1778 dma-coherent;
1785 bus-range = <0x01 0xff>;
1787 #address-cells = <3>;
1788 #size-cells = <2>;
1794 compatible = "qcom,sc8180x-qmp-pcie-phy";
1801 clock-names = "aux",
1806 #clock-cells = <0>;
1807 clock-output-names = "pcie_0_pipe_clk";
1808 #phy-cells = <0>;
1811 reset-names = "phy";
1813 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1814 assigned-clock-rates = <100000000>;
1820 compatible = "qcom,pcie-sc8180x";
1826 reg-names = "parf",
1832 linux,pci-domain = <3>;
1833 bus-range = <0x00 0xff>;
1834 num-lanes = <2>;
1836 #address-cells = <3>;
1837 #size-cells = <2>;
1851 interrupt-names = "msi0",
1860 #interrupt-cells = <1>;
1861 interrupt-map-mask = <0 0 0 0x7>;
1862 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1873 clock-names = "pipe",
1880 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1881 assigned-clock-rates = <19200000>;
1883 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1887 reset-names = "pci";
1889 power-domains = <&gcc PCIE_3_GDSC>;
1893 interconnect-names = "pcie-mem", "cpu-pcie";
1896 phy-names = "pciephy";
1897 dma-coherent;
1904 bus-range = <0x01 0xff>;
1906 #address-cells = <3>;
1907 #size-cells = <2>;
1913 compatible = "qcom,sc8180x-qmp-pcie-phy";
1920 clock-names = "aux",
1925 #clock-cells = <0>;
1926 clock-output-names = "pcie_3_pipe_clk";
1928 #phy-cells = <0>;
1931 reset-names = "phy";
1933 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1934 assigned-clock-rates = <100000000>;
1940 compatible = "qcom,pcie-sc8180x";
1946 reg-names = "parf",
1952 linux,pci-domain = <1>;
1953 bus-range = <0x00 0xff>;
1954 num-lanes = <2>;
1956 #address-cells = <3>;
1957 #size-cells = <2>;
1971 interrupt-names = "msi0",
1980 #interrupt-cells = <1>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1993 clock-names = "pipe",
2000 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2001 assigned-clock-rates = <19200000>;
2003 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2007 reset-names = "pci";
2009 power-domains = <&gcc PCIE_1_GDSC>;
2013 interconnect-names = "pcie-mem", "cpu-pcie";
2016 phy-names = "pciephy";
2017 dma-coherent;
2024 bus-range = <0x01 0xff>;
2026 #address-cells = <3>;
2027 #size-cells = <2>;
2033 compatible = "qcom,sc8180x-qmp-pcie-phy";
2040 clock-names = "aux",
2045 #clock-cells = <0>;
2046 clock-output-names = "pcie_1_pipe_clk";
2048 #phy-cells = <0>;
2051 reset-names = "phy";
2053 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2054 assigned-clock-rates = <100000000>;
2060 compatible = "qcom,pcie-sc8180x";
2066 reg-names = "parf",
2072 linux,pci-domain = <2>;
2073 bus-range = <0x00 0xff>;
2074 num-lanes = <4>;
2076 #address-cells = <3>;
2077 #size-cells = <2>;
2091 interrupt-names = "msi0",
2100 #interrupt-cells = <1>;
2101 interrupt-map-mask = <0 0 0 0x7>;
2102 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2113 clock-names = "pipe",
2120 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2121 assigned-clock-rates = <19200000>;
2123 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2127 reset-names = "pci";
2129 power-domains = <&gcc PCIE_2_GDSC>;
2133 interconnect-names = "pcie-mem", "cpu-pcie";
2136 phy-names = "pciephy";
2137 dma-coherent;
2144 bus-range = <0x01 0xff>;
2146 #address-cells = <3>;
2147 #size-cells = <2>;
2153 compatible = "qcom,sc8180x-qmp-pcie-phy";
2160 clock-names = "aux",
2165 #clock-cells = <0>;
2166 clock-output-names = "pcie_2_pipe_clk";
2168 #phy-cells = <0>;
2171 reset-names = "phy";
2173 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2174 assigned-clock-rates = <100000000>;
2180 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2181 "jedec,ufs-2.0";
2185 phy-names = "ufsphy";
2186 lanes-per-direction = <2>;
2187 #reset-cells = <1>;
2189 reset-names = "rst";
2201 clock-names = "core_clk",
2209 freq-table-hz = <37500000 300000000>,
2218 power-domains = <&gcc UFS_PHY_GDSC>;
2224 interconnect-names = "ufs-ddr", "cpu-ufs";
2229 ufs_mem_phy: phy-wrapper@1d87000 {
2230 compatible = "qcom,sc8180x-qmp-ufs-phy";
2236 clock-names = "ref",
2241 reset-names = "ufsphy";
2243 power-domains = <&gcc UFS_PHY_GDSC>;
2245 #phy-cells = <0>;
2251 compatible = "qcom,tcsr-mutex";
2253 #hwlock-cells = <1>;
2257 compatible = "qcom,adreno-680.1", "qcom,adreno";
2260 reg-names = "kgsl_3d0_reg_memory";
2266 operating-points-v2 = <&gpu_opp_table>;
2269 interconnect-names = "gfx-mem";
2272 #cooling-cells = <2>;
2276 gpu_opp_table: opp-table {
2277 compatible = "operating-points-v2";
2279 opp-514000000 {
2280 opp-hz = /bits/ 64 <514000000>;
2281 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2284 opp-500000000 {
2285 opp-hz = /bits/ 64 <500000000>;
2286 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2289 opp-461000000 {
2290 opp-hz = /bits/ 64 <461000000>;
2291 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2294 opp-405000000 {
2295 opp-hz = /bits/ 64 <405000000>;
2296 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2299 opp-315000000 {
2300 opp-hz = /bits/ 64 <315000000>;
2301 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2304 opp-256000000 {
2305 opp-hz = /bits/ 64 <256000000>;
2306 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2309 opp-177000000 {
2310 opp-hz = /bits/ 64 <177000000>;
2311 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2317 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2322 reg-names = "gmu",
2328 interrupt-names = "hfi", "gmu";
2335 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2337 power-domains = <&gpucc GPU_CX_GDSC>,
2339 power-domain-names = "cx", "gx";
2343 operating-points-v2 = <&gmu_opp_table>;
2345 gmu_opp_table: opp-table {
2346 compatible = "operating-points-v2";
2348 opp-200000000 {
2349 opp-hz = /bits/ 64 <200000000>;
2350 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2353 opp-500000000 {
2354 opp-hz = /bits/ 64 <500000000>;
2355 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2360 gpucc: clock-controller@2c90000 {
2361 compatible = "qcom,sc8180x-gpucc";
2366 clock-names = "bi_tcxo",
2369 #clock-cells = <1>;
2370 #reset-cells = <1>;
2371 #power-domain-cells = <1>;
2375 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2376 "qcom,smmu-500", "arm,mmu-500";
2378 #iommu-cells = <2>;
2379 #global-interrupts = <1>;
2392 clock-names = "ahb", "bus", "iface";
2394 power-domains = <&gpucc GPU_CX_GDSC>;
2398 compatible = "qcom,sc8180x-tlmm";
2402 reg-names = "west", "east", "south";
2404 gpio-controller;
2405 #gpio-cells = <2>;
2406 interrupt-controller;
2407 #interrupt-cells = <2>;
2408 gpio-ranges = <&tlmm 0 0 191>;
2409 wakeup-parent = <&pdc>;
2413 compatible = "qcom,sc8180x-mpss-pas";
2416 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2422 interrupt-names = "wdog", "fatal", "ready", "handover",
2423 "stop-ack", "shutdown-ack";
2426 clock-names = "xo";
2428 power-domains = <&rpmhpd SC8180X_CX>,
2430 power-domain-names = "cx", "mss";
2434 qcom,smem-states = <&modem_smp2p_out 0>;
2435 qcom,smem-state-names = "stop";
2437 glink-edge {
2440 qcom,remote-pid = <1>;
2446 compatible = "qcom,sc8180x-cdsp-pas";
2449 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2454 interrupt-names = "wdog", "fatal", "ready",
2455 "handover", "stop-ack";
2458 clock-names = "xo";
2460 power-domains = <&rpmhpd SC8180X_CX>;
2461 power-domain-names = "cx";
2465 qcom,smem-states = <&cdsp_smp2p_out 0>;
2466 qcom,smem-state-names = "stop";
2470 glink-edge {
2473 qcom,remote-pid = <5>;
2479 compatible = "qcom,sc8180x-usb-hs-phy",
2480 "qcom,usb-snps-hs-7nm-phy";
2483 clock-names = "ref";
2486 #phy-cells = <0>;
2492 compatible = "qcom,sc8180x-usb-hs-phy",
2493 "qcom,usb-snps-hs-7nm-phy";
2496 clock-names = "ref";
2499 #phy-cells = <0>;
2505 compatible = "qcom,sc8180x-usb-hs-phy",
2506 "qcom,usb-snps-hs-7nm-phy";
2508 #phy-cells = <0>;
2511 clock-names = "ref";
2519 compatible = "qcom,sc8180x-usb-hs-phy",
2520 "qcom,usb-snps-hs-7nm-phy";
2522 #phy-cells = <0>;
2525 clock-names = "ref";
2533 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2540 clock-names = "aux",
2547 reset-names = "phy", "common";
2549 #clock-cells = <1>;
2550 #phy-cells = <1>;
2555 #address-cells = <1>;
2556 #size-cells = <0>;
2568 remote-endpoint = <&usb_prim_dwc3_ss>;
2581 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2588 clock-names = "aux",
2595 reset-names = "phy", "phy_phy";
2597 power-domains = <&gcc USB30_MP_GDSC>;
2599 #clock-cells = <0>;
2600 clock-output-names = "usb2_phy0_pipe_clk";
2602 #phy-cells = <0>;
2608 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2615 clock-names = "aux",
2622 reset-names = "phy", "phy_phy";
2624 power-domains = <&gcc USB30_MP_GDSC>;
2626 #clock-cells = <0>;
2627 clock-output-names = "usb2_phy1_pipe_clk";
2629 #phy-cells = <0>;
2635 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2642 clock-names = "aux",
2648 reset-names = "phy", "common";
2650 #clock-cells = <1>;
2651 #phy-cells = <1>;
2656 #address-cells = <1>;
2657 #size-cells = <0>;
2669 remote-endpoint = <&usb_sec_dwc3_ss>;
2681 system-cache-controller@9200000 {
2682 compatible = "qcom,sc8180x-llcc";
2688 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2695 compatible = "qcom,sc8180x-gem-noc";
2697 #interconnect-cells = <2>;
2698 qcom,bcm-voters = <&apps_bcm_voter>;
2702 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
2704 #address-cells = <2>;
2705 #size-cells = <2>;
2707 dma-ranges;
2715 clock-names = "cfg_noc",
2724 interconnect-names = "usb-ddr", "apps-usb";
2726 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2728 assigned-clock-rates = <19200000>, <200000000>;
2730 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
2740 interrupt-names = "pwr_event_1", "pwr_event_2",
2746 power-domains = <&gcc USB30_MP_GDSC>;
2759 snps,dis-u1-entry-quirk;
2760 snps,dis-u2-entry-quirk;
2765 phy-names = "usb2-0",
2766 "usb3-0",
2767 "usb2-1",
2768 "usb3-1";
2774 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2776 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2781 interrupt-names = "pwr_event",
2793 clock-names = "cfg_noc",
2800 power-domains = <&gcc USB30_PRIM_GDSC>;
2804 interconnect-names = "usb-ddr", "apps-usb";
2806 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2808 assigned-clock-rates = <19200000>, <200000000>;
2810 #address-cells = <2>;
2811 #size-cells = <2>;
2813 dma-ranges;
2824 snps,dis-u1-entry-quirk;
2825 snps,dis-u2-entry-quirk;
2827 phy-names = "usb2-phy", "usb3-phy";
2830 #address-cells = <1>;
2831 #size-cells = <0>;
2844 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
2852 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2861 clock-names = "cfg_noc",
2868 power-domains = <&gcc USB30_SEC_GDSC>;
2870 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2875 interrupt-names = "pwr_event",
2881 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2883 assigned-clock-rates = <19200000>, <200000000>;
2887 interconnect-names = "usb-ddr", "apps-usb";
2889 #address-cells = <2>;
2890 #size-cells = <2>;
2892 dma-ranges;
2903 snps,dis-u1-entry-quirk;
2904 snps,dis-u2-entry-quirk;
2906 phy-names = "usb2-phy", "usb3-phy";
2909 #address-cells = <1>;
2910 #size-cells = <0>;
2923 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
2930 camcc: clock-controller@ad00000 {
2931 compatible = "qcom,sc8180x-camcc";
2936 power-domains = <&rpmhpd SC8180X_MMCX>;
2937 required-opps = <&rpmhpd_opp_low_svs>;
2938 #clock-cells = <1>;
2939 #reset-cells = <1>;
2940 #power-domain-cells = <1>;
2944 compatible = "qcom,sc8180x-mdss";
2946 reg-names = "mdss";
2948 power-domains = <&dispcc MDSS_GDSC>;
2954 clock-names = "iface",
2962 interrupt-controller;
2963 #interrupt-cells = <1>;
2971 interconnect-names = "mdp0-mem",
2972 "mdp1-mem",
2973 "cpu-cfg";
2977 #address-cells = <2>;
2978 #size-cells = <2>;
2984 compatible = "qcom,sc8180x-dpu";
2987 reg-names = "mdp", "vbif";
2995 clock-names = "iface",
3002 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3003 assigned-clock-rates = <19200000>;
3005 operating-points-v2 = <&mdp_opp_table>;
3006 power-domains = <&rpmhpd SC8180X_MMCX>;
3008 interrupt-parent = <&mdss>;
3012 #address-cells = <1>;
3013 #size-cells = <0>;
3018 remote-endpoint = <&dp0_in>;
3025 remote-endpoint = <&mdss_dsi0_in>;
3032 remote-endpoint = <&mdss_dsi1_in>;
3039 remote-endpoint = <&dp1_in>;
3046 remote-endpoint = <&edp_in>;
3051 mdp_opp_table: opp-table {
3052 compatible = "operating-points-v2";
3054 opp-200000000 {
3055 opp-hz = /bits/ 64 <200000000>;
3056 required-opps = <&rpmhpd_opp_low_svs>;
3059 opp-300000000 {
3060 opp-hz = /bits/ 64 <300000000>;
3061 required-opps = <&rpmhpd_opp_svs>;
3064 opp-345000000 {
3065 opp-hz = /bits/ 64 <345000000>;
3066 required-opps = <&rpmhpd_opp_svs_l1>;
3069 opp-460000000 {
3070 opp-hz = /bits/ 64 <460000000>;
3071 required-opps = <&rpmhpd_opp_nom>;
3077 compatible = "qcom,mdss-dsi-ctrl";
3079 reg-names = "dsi_ctrl";
3081 interrupt-parent = <&mdss>;
3090 clock-names = "byte",
3097 operating-points-v2 = <&dsi_opp_table>;
3098 power-domains = <&rpmhpd SC8180X_MMCX>;
3101 phy-names = "dsi";
3106 #address-cells = <1>;
3107 #size-cells = <0>;
3112 remote-endpoint = <&dpu_intf1_out>;
3123 dsi_opp_table: opp-table {
3124 compatible = "operating-points-v2";
3126 opp-187500000 {
3127 opp-hz = /bits/ 64 <187500000>;
3128 required-opps = <&rpmhpd_opp_low_svs>;
3131 opp-300000000 {
3132 opp-hz = /bits/ 64 <300000000>;
3133 required-opps = <&rpmhpd_opp_svs>;
3136 opp-358000000 {
3137 opp-hz = /bits/ 64 <358000000>;
3138 required-opps = <&rpmhpd_opp_svs_l1>;
3143 mdss_dsi0_phy: dsi-phy@ae94400 {
3144 compatible = "qcom,dsi-phy-7nm";
3148 reg-names = "dsi_phy",
3152 #clock-cells = <1>;
3153 #phy-cells = <0>;
3157 clock-names = "iface", "ref";
3163 compatible = "qcom,mdss-dsi-ctrl";
3165 reg-names = "dsi_ctrl";
3167 interrupt-parent = <&mdss>;
3176 clock-names = "byte",
3183 operating-points-v2 = <&dsi_opp_table>;
3184 power-domains = <&rpmhpd SC8180X_MMCX>;
3187 phy-names = "dsi";
3192 #address-cells = <1>;
3193 #size-cells = <0>;
3198 remote-endpoint = <&dpu_intf2_out>;
3210 mdss_dsi1_phy: dsi-phy@ae96400 {
3211 compatible = "qcom,dsi-phy-7nm";
3215 reg-names = "dsi_phy",
3219 #clock-cells = <1>;
3220 #phy-cells = <0>;
3224 clock-names = "iface", "ref";
3229 mdss_dp0: displayport-controller@ae90000 {
3230 compatible = "qcom,sc8180x-dp";
3236 interrupt-parent = <&mdss>;
3243 clock-names = "core_iface",
3249 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3251 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3255 phy-names = "dp";
3257 #sound-dai-cells = <0>;
3259 operating-points-v2 = <&dp0_opp_table>;
3260 power-domains = <&rpmhpd SC8180X_MMCX>;
3265 #address-cells = <1>;
3266 #size-cells = <0>;
3271 remote-endpoint = <&dpu_intf0_out>;
3282 dp0_opp_table: opp-table {
3283 compatible = "operating-points-v2";
3285 opp-160000000 {
3286 opp-hz = /bits/ 64 <160000000>;
3287 required-opps = <&rpmhpd_opp_low_svs>;
3290 opp-270000000 {
3291 opp-hz = /bits/ 64 <270000000>;
3292 required-opps = <&rpmhpd_opp_svs>;
3295 opp-540000000 {
3296 opp-hz = /bits/ 64 <540000000>;
3297 required-opps = <&rpmhpd_opp_svs_l1>;
3300 opp-810000000 {
3301 opp-hz = /bits/ 64 <810000000>;
3302 required-opps = <&rpmhpd_opp_nom>;
3307 mdss_dp1: displayport-controller@ae98000 {
3308 compatible = "qcom,sc8180x-dp";
3314 interrupt-parent = <&mdss>;
3321 clock-names = "core_iface",
3327 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3329 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3333 phy-names = "dp";
3335 #sound-dai-cells = <0>;
3337 operating-points-v2 = <&dp0_opp_table>;
3338 power-domains = <&rpmhpd SC8180X_MMCX>;
3343 #address-cells = <1>;
3344 #size-cells = <0>;
3349 remote-endpoint = <&dpu_intf4_out>;
3360 dp1_opp_table: opp-table {
3361 compatible = "operating-points-v2";
3363 opp-160000000 {
3364 opp-hz = /bits/ 64 <160000000>;
3365 required-opps = <&rpmhpd_opp_low_svs>;
3368 opp-270000000 {
3369 opp-hz = /bits/ 64 <270000000>;
3370 required-opps = <&rpmhpd_opp_svs>;
3373 opp-540000000 {
3374 opp-hz = /bits/ 64 <540000000>;
3375 required-opps = <&rpmhpd_opp_svs_l1>;
3378 opp-810000000 {
3379 opp-hz = /bits/ 64 <810000000>;
3380 required-opps = <&rpmhpd_opp_nom>;
3385 mdss_edp: displayport-controller@ae9a000 {
3386 compatible = "qcom,sc8180x-edp";
3391 interrupt-parent = <&mdss>;
3398 clock-names = "core_iface",
3404 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3406 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3409 phy-names = "dp";
3411 operating-points-v2 = <&edp_opp_table>;
3412 power-domains = <&rpmhpd SC8180X_MMCX>;
3417 #address-cells = <1>;
3418 #size-cells = <0>;
3423 remote-endpoint = <&dpu_intf5_out>;
3428 edp_opp_table: opp-table {
3429 compatible = "operating-points-v2";
3431 opp-160000000 {
3432 opp-hz = /bits/ 64 <160000000>;
3433 required-opps = <&rpmhpd_opp_low_svs>;
3436 opp-270000000 {
3437 opp-hz = /bits/ 64 <270000000>;
3438 required-opps = <&rpmhpd_opp_svs>;
3441 opp-540000000 {
3442 opp-hz = /bits/ 64 <540000000>;
3443 required-opps = <&rpmhpd_opp_svs_l1>;
3446 opp-810000000 {
3447 opp-hz = /bits/ 64 <810000000>;
3448 required-opps = <&rpmhpd_opp_nom>;
3455 compatible = "qcom,sc8180x-edp-phy";
3463 clock-names = "aux", "cfg_ahb";
3465 power-domains = <&rpmhpd SC8180X_MX>;
3467 #clock-cells = <1>;
3468 #phy-cells = <0>;
3471 dispcc: clock-controller@af00000 {
3472 compatible = "qcom,sc8180x-dispcc";
3485 clock-names = "bi_tcxo",
3496 power-domains = <&rpmhpd SC8180X_MMCX>;
3497 required-opps = <&rpmhpd_opp_low_svs>;
3498 #clock-cells = <1>;
3499 #reset-cells = <1>;
3500 #power-domain-cells = <1>;
3503 pdc: interrupt-controller@b220000 {
3504 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3506 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3507 #interrupt-cells = <2>;
3508 interrupt-parent = <&intc>;
3509 interrupt-controller;
3512 tsens0: thermal-sensor@c263000 {
3513 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3519 interrupt-names = "uplow", "critical";
3520 #thermal-sensor-cells = <1>;
3523 tsens1: thermal-sensor@c265000 {
3524 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3530 interrupt-names = "uplow", "critical";
3531 #thermal-sensor-cells = <1>;
3534 aoss_qmp: power-management@c300000 {
3535 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3540 #clock-cells = <0>;
3544 compatible = "qcom,rpmh-stats";
3549 compatible = "qcom,spmi-pmic-arb";
3555 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3556 interrupt-names = "periph_irq";
3560 #address-cells = <2>;
3561 #size-cells = <0>;
3562 interrupt-controller;
3563 #interrupt-cells = <4>;
3567 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3569 #iommu-cells = <2>;
3570 #global-interrupts = <1>;
3678 dma-coherent;
3682 compatible = "qcom,sc8180x-adsp-pas";
3685 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3690 interrupt-names = "wdog", "fatal", "ready",
3691 "handover", "stop-ack";
3694 clock-names = "xo";
3696 power-domains = <&rpmhpd SC8180X_CX>;
3697 power-domain-names = "cx";
3701 qcom,smem-states = <&adsp_smp2p_out 0>;
3702 qcom,smem-state-names = "stop";
3706 remoteproc_adsp_glink: glink-edge {
3709 qcom,remote-pid = <2>;
3714 intc: interrupt-controller@17a00000 {
3715 compatible = "arm,gic-v3";
3716 interrupt-controller;
3717 #interrupt-cells = <3>;
3721 #redistributor-regions = <1>;
3722 redistributor-stride = <0 0x20000>;
3726 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3728 #mbox-cells = <1>;
3732 compatible = "arm,armv7-timer-mem";
3735 #address-cells = <1>;
3736 #size-cells = <1>;
3742 frame-number = <0>;
3749 frame-number = <1>;
3756 frame-number = <2>;
3763 frame-number = <3>;
3770 frame-number = <4>;
3777 frame-number = <5>;
3784 frame-number = <6>;
3791 compatible = "qcom,rpmh-rsc";
3795 reg-names = "drv-0", "drv-1", "drv-2";
3799 qcom,tcs-offset = <0xd00>;
3800 qcom,drv-id = <2>;
3801 qcom,tcs-config = <ACTIVE_TCS 2>,
3806 power-domains = <&cluster_pd>;
3808 apps_bcm_voter: bcm-voter {
3809 compatible = "qcom,bcm-voter";
3812 rpmhcc: clock-controller {
3813 compatible = "qcom,sc8180x-rpmh-clk";
3814 #clock-cells = <1>;
3815 clock-names = "xo";
3819 rpmhpd: power-controller {
3820 compatible = "qcom,sc8180x-rpmhpd";
3821 #power-domain-cells = <1>;
3822 operating-points-v2 = <&rpmhpd_opp_table>;
3824 rpmhpd_opp_table: opp-table {
3825 compatible = "operating-points-v2";
3828 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3832 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3836 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3840 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3844 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3848 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3852 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3856 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3860 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3864 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3871 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3875 clock-names = "xo", "alternate";
3877 #interconnect-cells = <1>;
3881 compatible = "qcom,sc8180x-lmh";
3885 qcom,lmh-temp-arm-millicelsius = <65000>;
3886 qcom,lmh-temp-low-millicelsius = <94500>;
3887 qcom,lmh-temp-high-millicelsius = <95000>;
3888 interrupt-controller;
3889 #interrupt-cells = <1>;
3893 compatible = "qcom,sc8180x-lmh";
3897 qcom,lmh-temp-arm-millicelsius = <65000>;
3898 qcom,lmh-temp-low-millicelsius = <94500>;
3899 qcom,lmh-temp-high-millicelsius = <95000>;
3900 interrupt-controller;
3901 #interrupt-cells = <1>;
3905 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw";
3907 reg-names = "freq-domain0", "freq-domain1";
3910 clock-names = "xo", "alternate";
3912 #freq-domain-cells = <1>;
3913 #clock-cells = <1>;
3917 compatible = "qcom,wcn3990-wifi";
3919 reg-names = "membase";
3920 clock-names = "cxo_ref_clk_pin";
3935 qcom,msa-fixed-perm;
3940 thermal-zones {
3941 cpu0-thermal {
3942 polling-delay-passive = <250>;
3944 thermal-sensors = <&tsens0 1>;
3947 cpu-crit {
3955 cpu1-thermal {
3956 polling-delay-passive = <250>;
3958 thermal-sensors = <&tsens0 2>;
3961 cpu-crit {
3969 cpu2-thermal {
3970 polling-delay-passive = <250>;
3972 thermal-sensors = <&tsens0 3>;
3975 cpu-crit {
3983 cpu3-thermal {
3984 polling-delay-passive = <250>;
3986 thermal-sensors = <&tsens0 4>;
3989 cpu-crit {
3997 cpu4-top-thermal {
3998 polling-delay-passive = <250>;
4000 thermal-sensors = <&tsens0 7>;
4003 cpu-crit {
4011 cpu5-top-thermal {
4012 polling-delay-passive = <250>;
4014 thermal-sensors = <&tsens0 8>;
4017 cpu-crit {
4025 cpu6-top-thermal {
4026 polling-delay-passive = <250>;
4028 thermal-sensors = <&tsens0 9>;
4031 cpu-crit {
4039 cpu7-top-thermal {
4040 polling-delay-passive = <250>;
4042 thermal-sensors = <&tsens0 10>;
4045 cpu-crit {
4053 cpu4-bottom-thermal {
4054 polling-delay-passive = <250>;
4056 thermal-sensors = <&tsens0 11>;
4059 cpu-crit {
4067 cpu5-bottom-thermal {
4068 polling-delay-passive = <250>;
4070 thermal-sensors = <&tsens0 12>;
4073 cpu-crit {
4081 cpu6-bottom-thermal {
4082 polling-delay-passive = <250>;
4084 thermal-sensors = <&tsens0 13>;
4087 cpu-crit {
4095 cpu7-bottom-thermal {
4096 polling-delay-passive = <250>;
4098 thermal-sensors = <&tsens0 14>;
4101 cpu-crit {
4109 aoss0-thermal {
4110 polling-delay-passive = <250>;
4112 thermal-sensors = <&tsens0 0>;
4115 trip-point0 {
4123 cluster0-thermal {
4124 polling-delay-passive = <250>;
4126 thermal-sensors = <&tsens0 5>;
4129 cluster-crit {
4137 cluster1-thermal {
4138 polling-delay-passive = <250>;
4140 thermal-sensors = <&tsens0 6>;
4143 cluster-crit {
4151 gpu-top-thermal {
4152 polling-delay-passive = <250>;
4154 thermal-sensors = <&tsens0 15>;
4156 cooling-maps {
4159 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4164 gpu_top_alert0: trip-point0 {
4170 trip-point1 {
4176 trip-point2 {
4184 aoss1-thermal {
4185 polling-delay-passive = <250>;
4187 thermal-sensors = <&tsens1 0>;
4190 trip-point0 {
4198 wlan-thermal {
4199 polling-delay-passive = <250>;
4201 thermal-sensors = <&tsens1 1>;
4204 trip-point0 {
4212 video-thermal {
4213 polling-delay-passive = <250>;
4215 thermal-sensors = <&tsens1 2>;
4218 trip-point0 {
4226 mem-thermal {
4227 polling-delay-passive = <250>;
4229 thermal-sensors = <&tsens1 3>;
4232 trip-point0 {
4240 q6-hvx-thermal {
4241 polling-delay-passive = <250>;
4243 thermal-sensors = <&tsens1 4>;
4246 trip-point0 {
4254 camera-thermal {
4255 polling-delay-passive = <250>;
4257 thermal-sensors = <&tsens1 5>;
4260 trip-point0 {
4268 compute-thermal {
4269 polling-delay-passive = <250>;
4271 thermal-sensors = <&tsens1 6>;
4274 trip-point0 {
4282 mdm-dsp-thermal {
4283 polling-delay-passive = <250>;
4285 thermal-sensors = <&tsens1 7>;
4288 trip-point0 {
4296 npu-thermal {
4297 polling-delay-passive = <250>;
4299 thermal-sensors = <&tsens1 8>;
4302 trip-point0 {
4310 gpu-bottom-thermal {
4311 polling-delay-passive = <250>;
4313 thermal-sensors = <&tsens1 11>;
4315 cooling-maps {
4318 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4323 gpu_bottom_alert0: trip-point0 {
4329 trip-point1 {
4335 trip-point2 {
4345 compatible = "arm,armv8-timer";