Lines Matching +full:pdc +full:- +full:intc
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sc8180x-camcc.h>
13 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sc8180x.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/thermal/thermal.h>
24 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
30 xo_board_clk: xo-board {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <38400000>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32764>;
40 clock-output-names = "sleep_clk";
45 #address-cells = <2>;
46 #size-cells = <0>;
52 enable-method = "psci";
53 capacity-dmips-mhz = <602>;
54 next-level-cache = <&l2_0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
56 operating-points-v2 = <&cpu0_opp_table>;
59 power-domains = <&cpu_pd0>;
60 power-domain-names = "psci";
61 #cooling-cells = <2>;
64 l2_0: l2-cache {
66 cache-level = <2>;
67 cache-unified;
68 next-level-cache = <&l3_0>;
69 l3_0: l3-cache {
71 cache-level = <3>;
72 cache-unified;
81 enable-method = "psci";
82 capacity-dmips-mhz = <602>;
83 next-level-cache = <&l2_100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 operating-points-v2 = <&cpu0_opp_table>;
88 power-domains = <&cpu_pd1>;
89 power-domain-names = "psci";
90 #cooling-cells = <2>;
93 l2_100: l2-cache {
95 cache-level = <2>;
96 cache-unified;
97 next-level-cache = <&l3_0>;
106 enable-method = "psci";
107 capacity-dmips-mhz = <602>;
108 next-level-cache = <&l2_200>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
113 power-domains = <&cpu_pd2>;
114 power-domain-names = "psci";
115 #cooling-cells = <2>;
118 l2_200: l2-cache {
120 cache-level = <2>;
121 cache-unified;
122 next-level-cache = <&l3_0>;
130 enable-method = "psci";
131 capacity-dmips-mhz = <602>;
132 next-level-cache = <&l2_300>;
133 qcom,freq-domain = <&cpufreq_hw 0>;
134 operating-points-v2 = <&cpu0_opp_table>;
137 power-domains = <&cpu_pd3>;
138 power-domain-names = "psci";
139 #cooling-cells = <2>;
142 l2_300: l2-cache {
144 cache-unified;
145 cache-level = <2>;
146 next-level-cache = <&l3_0>;
154 enable-method = "psci";
155 capacity-dmips-mhz = <1024>;
156 next-level-cache = <&l2_400>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
158 operating-points-v2 = <&cpu4_opp_table>;
161 power-domains = <&cpu_pd4>;
162 power-domain-names = "psci";
163 #cooling-cells = <2>;
166 l2_400: l2-cache {
168 cache-unified;
169 cache-level = <2>;
170 next-level-cache = <&l3_0>;
178 enable-method = "psci";
179 capacity-dmips-mhz = <1024>;
180 next-level-cache = <&l2_500>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 operating-points-v2 = <&cpu4_opp_table>;
185 power-domains = <&cpu_pd5>;
186 power-domain-names = "psci";
187 #cooling-cells = <2>;
190 l2_500: l2-cache {
192 cache-unified;
193 cache-level = <2>;
194 next-level-cache = <&l3_0>;
202 enable-method = "psci";
203 capacity-dmips-mhz = <1024>;
204 next-level-cache = <&l2_600>;
205 qcom,freq-domain = <&cpufreq_hw 1>;
206 operating-points-v2 = <&cpu4_opp_table>;
209 power-domains = <&cpu_pd6>;
210 power-domain-names = "psci";
211 #cooling-cells = <2>;
214 l2_600: l2-cache {
216 cache-unified;
217 cache-level = <2>;
218 next-level-cache = <&l3_0>;
226 enable-method = "psci";
227 capacity-dmips-mhz = <1024>;
228 next-level-cache = <&l2_700>;
229 qcom,freq-domain = <&cpufreq_hw 1>;
230 operating-points-v2 = <&cpu4_opp_table>;
233 power-domains = <&cpu_pd7>;
234 power-domain-names = "psci";
235 #cooling-cells = <2>;
238 l2_700: l2-cache {
240 cache-unified;
241 cache-level = <2>;
242 next-level-cache = <&l3_0>;
246 cpu-map {
282 idle-states {
283 entry-method = "psci";
285 little_cpu_sleep_0: cpu-sleep-0-0 {
286 compatible = "arm,idle-state";
287 arm,psci-suspend-param = <0x40000004>;
288 entry-latency-us = <355>;
289 exit-latency-us = <909>;
290 min-residency-us = <3934>;
291 local-timer-stop;
294 big_cpu_sleep_0: cpu-sleep-1-0 {
295 compatible = "arm,idle-state";
296 arm,psci-suspend-param = <0x40000004>;
297 entry-latency-us = <2411>;
298 exit-latency-us = <1461>;
299 min-residency-us = <4488>;
300 local-timer-stop;
304 domain-idle-states {
305 cluster_sleep_apss_off: cluster-sleep-0 {
306 compatible = "domain-idle-state";
307 arm,psci-suspend-param = <0x41000044>;
308 entry-latency-us = <3300>;
309 exit-latency-us = <3300>;
310 min-residency-us = <6000>;
313 cluster_sleep_aoss_sleep: cluster-sleep-1 {
314 compatible = "domain-idle-state";
315 arm,psci-suspend-param = <0x4100a344>;
316 entry-latency-us = <3263>;
317 exit-latency-us = <6562>;
318 min-residency-us = <9987>;
323 cpu0_opp_table: opp-table-cpu0 {
324 compatible = "operating-points-v2";
325 opp-shared;
327 opp-300000000 {
328 opp-hz = /bits/ 64 <300000000>;
329 opp-peak-kBps = <800000 9600000>;
332 opp-422400000 {
333 opp-hz = /bits/ 64 <422400000>;
334 opp-peak-kBps = <800000 9600000>;
337 opp-537600000 {
338 opp-hz = /bits/ 64 <537600000>;
339 opp-peak-kBps = <800000 12902400>;
342 opp-652800000 {
343 opp-hz = /bits/ 64 <652800000>;
344 opp-peak-kBps = <800000 12902400>;
347 opp-768000000 {
348 opp-hz = /bits/ 64 <768000000>;
349 opp-peak-kBps = <800000 15974400>;
352 opp-883200000 {
353 opp-hz = /bits/ 64 <883200000>;
354 opp-peak-kBps = <1804000 19660800>;
357 opp-998400000 {
358 opp-hz = /bits/ 64 <998400000>;
359 opp-peak-kBps = <1804000 19660800>;
362 opp-1113600000 {
363 opp-hz = /bits/ 64 <1113600000>;
364 opp-peak-kBps = <1804000 22732800>;
367 opp-1228800000 {
368 opp-hz = /bits/ 64 <1228800000>;
369 opp-peak-kBps = <1804000 22732800>;
372 opp-1363200000 {
373 opp-hz = /bits/ 64 <1363200000>;
374 opp-peak-kBps = <2188000 25804800>;
377 opp-1478400000 {
378 opp-hz = /bits/ 64 <1478400000>;
379 opp-peak-kBps = <2188000 31948800>;
382 opp-1574400000 {
383 opp-hz = /bits/ 64 <1574400000>;
384 opp-peak-kBps = <3072000 31948800>;
387 opp-1670400000 {
388 opp-hz = /bits/ 64 <1670400000>;
389 opp-peak-kBps = <3072000 31948800>;
392 opp-1766400000 {
393 opp-hz = /bits/ 64 <1766400000>;
394 opp-peak-kBps = <3072000 31948800>;
398 cpu4_opp_table: opp-table-cpu4 {
399 compatible = "operating-points-v2";
400 opp-shared;
402 opp-825600000 {
403 opp-hz = /bits/ 64 <825600000>;
404 opp-peak-kBps = <1804000 15974400>;
407 opp-940800000 {
408 opp-hz = /bits/ 64 <940800000>;
409 opp-peak-kBps = <2188000 19660800>;
412 opp-1056000000 {
413 opp-hz = /bits/ 64 <1056000000>;
414 opp-peak-kBps = <2188000 22732800>;
417 opp-1171200000 {
418 opp-hz = /bits/ 64 <1171200000>;
419 opp-peak-kBps = <3072000 25804800>;
422 opp-1286400000 {
423 opp-hz = /bits/ 64 <1286400000>;
424 opp-peak-kBps = <3072000 31948800>;
427 opp-1420800000 {
428 opp-hz = /bits/ 64 <1420800000>;
429 opp-peak-kBps = <4068000 31948800>;
432 opp-1536000000 {
433 opp-hz = /bits/ 64 <1536000000>;
434 opp-peak-kBps = <4068000 31948800>;
437 opp-1651200000 {
438 opp-hz = /bits/ 64 <1651200000>;
439 opp-peak-kBps = <4068000 40550400>;
442 opp-1766400000 {
443 opp-hz = /bits/ 64 <1766400000>;
444 opp-peak-kBps = <4068000 40550400>;
447 opp-1881600000 {
448 opp-hz = /bits/ 64 <1881600000>;
449 opp-peak-kBps = <4068000 43008000>;
452 opp-1996800000 {
453 opp-hz = /bits/ 64 <1996800000>;
454 opp-peak-kBps = <6220000 43008000>;
457 opp-2131200000 {
458 opp-hz = /bits/ 64 <2131200000>;
459 opp-peak-kBps = <6220000 49152000>;
462 opp-2246400000 {
463 opp-hz = /bits/ 64 <2246400000>;
464 opp-peak-kBps = <7216000 49152000>;
467 opp-2361600000 {
468 opp-hz = /bits/ 64 <2361600000>;
469 opp-peak-kBps = <8368000 49152000>;
472 opp-2457600000 {
473 opp-hz = /bits/ 64 <2457600000>;
474 opp-peak-kBps = <8368000 51609600>;
477 opp-2553600000 {
478 opp-hz = /bits/ 64 <2553600000>;
479 opp-peak-kBps = <8368000 51609600>;
482 opp-2649600000 {
483 opp-hz = /bits/ 64 <2649600000>;
484 opp-peak-kBps = <8368000 51609600>;
487 opp-2745600000 {
488 opp-hz = /bits/ 64 <2745600000>;
489 opp-peak-kBps = <8368000 51609600>;
492 opp-2841600000 {
493 opp-hz = /bits/ 64 <2841600000>;
494 opp-peak-kBps = <8368000 51609600>;
497 opp-2918400000 {
498 opp-hz = /bits/ 64 <2918400000>;
499 opp-peak-kBps = <8368000 51609600>;
502 opp-2995200000 {
503 opp-hz = /bits/ 64 <2995200000>;
504 opp-peak-kBps = <8368000 51609600>;
510 compatible = "qcom,scm-sc8180x", "qcom,scm";
514 camnoc_virt: interconnect-camnoc-virt {
515 compatible = "qcom,sc8180x-camnoc-virt";
516 #interconnect-cells = <2>;
517 qcom,bcm-voters = <&apps_bcm_voter>;
520 mc_virt: interconnect-mc-virt {
521 compatible = "qcom,sc8180x-mc-virt";
522 #interconnect-cells = <2>;
523 qcom,bcm-voters = <&apps_bcm_voter>;
526 qup_virt: interconnect-qup-virt {
527 compatible = "qcom,sc8180x-qup-virt";
528 #interconnect-cells = <2>;
529 qcom,bcm-voters = <&apps_bcm_voter>;
539 compatible = "arm,armv8-pmuv3";
544 compatible = "arm,psci-1.0";
547 cpu_pd0: power-domain-cpu0 {
548 #power-domain-cells = <0>;
549 power-domains = <&cluster_pd>;
550 domain-idle-states = <&little_cpu_sleep_0>;
553 cpu_pd1: power-domain-cpu1 {
554 #power-domain-cells = <0>;
555 power-domains = <&cluster_pd>;
556 domain-idle-states = <&little_cpu_sleep_0>;
559 cpu_pd2: power-domain-cpu2 {
560 #power-domain-cells = <0>;
561 power-domains = <&cluster_pd>;
562 domain-idle-states = <&little_cpu_sleep_0>;
565 cpu_pd3: power-domain-cpu3 {
566 #power-domain-cells = <0>;
567 power-domains = <&cluster_pd>;
568 domain-idle-states = <&little_cpu_sleep_0>;
571 cpu_pd4: power-domain-cpu4 {
572 #power-domain-cells = <0>;
573 power-domains = <&cluster_pd>;
574 domain-idle-states = <&big_cpu_sleep_0>;
577 cpu_pd5: power-domain-cpu5 {
578 #power-domain-cells = <0>;
579 power-domains = <&cluster_pd>;
580 domain-idle-states = <&big_cpu_sleep_0>;
583 cpu_pd6: power-domain-cpu6 {
584 #power-domain-cells = <0>;
585 power-domains = <&cluster_pd>;
586 domain-idle-states = <&big_cpu_sleep_0>;
589 cpu_pd7: power-domain-cpu7 {
590 #power-domain-cells = <0>;
591 power-domains = <&cluster_pd>;
592 domain-idle-states = <&big_cpu_sleep_0>;
595 cluster_pd: power-domain-cpu-cluster0 {
596 #power-domain-cells = <0>;
597 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
601 reserved-memory {
602 #address-cells = <2>;
603 #size-cells = <2>;
608 no-map;
613 no-map;
618 no-map;
621 aop_cmd_db: cmd-db@85f20000 {
622 compatible = "qcom,cmd-db";
624 no-map;
629 no-map;
635 no-map;
641 no-map;
646 no-map;
651 no-map;
656 no-map;
661 no-map;
666 no-map;
670 smp2p-cdsp {
678 qcom,local-pid = <0>;
679 qcom,remote-pid = <5>;
681 cdsp_smp2p_out: master-kernel {
682 qcom,entry-name = "master-kernel";
683 #qcom,smem-state-cells = <1>;
686 cdsp_smp2p_in: slave-kernel {
687 qcom,entry-name = "slave-kernel";
689 interrupt-controller;
690 #interrupt-cells = <2>;
694 smp2p-lpass {
702 qcom,local-pid = <0>;
703 qcom,remote-pid = <2>;
705 adsp_smp2p_out: master-kernel {
706 qcom,entry-name = "master-kernel";
707 #qcom,smem-state-cells = <1>;
710 adsp_smp2p_in: slave-kernel {
711 qcom,entry-name = "slave-kernel";
713 interrupt-controller;
714 #interrupt-cells = <2>;
718 smp2p-mpss {
726 qcom,local-pid = <0>;
727 qcom,remote-pid = <1>;
729 modem_smp2p_out: master-kernel {
730 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells = <1>;
734 modem_smp2p_in: slave-kernel {
735 qcom,entry-name = "slave-kernel";
737 interrupt-controller;
738 #interrupt-cells = <2>;
741 modem_smp2p_ipa_out: ipa-ap-to-modem {
742 qcom,entry-name = "ipa";
743 #qcom,smem-state-cells = <1>;
746 modem_smp2p_ipa_in: ipa-modem-to-ap {
747 qcom,entry-name = "ipa";
748 interrupt-controller;
749 #interrupt-cells = <2>;
752 modem_smp2p_wlan_in: wlan-wpss-to-ap {
753 qcom,entry-name = "wlan";
754 interrupt-controller;
755 #interrupt-cells = <2>;
759 smp2p-slpi {
767 qcom,local-pid = <0>;
768 qcom,remote-pid = <3>;
770 slpi_smp2p_out: master-kernel {
771 qcom,entry-name = "master-kernel";
772 #qcom,smem-state-cells = <1>;
775 slpi_smp2p_in: slave-kernel {
776 qcom,entry-name = "slave-kernel";
778 interrupt-controller;
779 #interrupt-cells = <2>;
784 compatible = "simple-bus";
785 #address-cells = <2>;
786 #size-cells = <2>;
788 dma-ranges = <0 0 0 0 0x10 0>;
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc-sc8180x";
793 #clock-cells = <1>;
794 #reset-cells = <1>;
795 #power-domain-cells = <1>;
799 clock-names = "bi_tcxo",
802 power-domains = <&rpmhpd SC8180X_CX>;
806 compatible = "qcom,geni-se-qup";
810 clock-names = "m-ahb", "s-ahb";
811 #address-cells = <2>;
812 #size-cells = <2>;
818 compatible = "qcom,geni-i2c";
821 clock-names = "se";
826 interconnect-names = "qup-core", "qup-config", "qup-memory";
827 #address-cells = <1>;
828 #size-cells = <0>;
833 compatible = "qcom,geni-spi";
836 clock-names = "se";
840 interconnect-names = "qup-core", "qup-config";
841 #address-cells = <1>;
842 #size-cells = <0>;
847 compatible = "qcom,geni-uart";
850 clock-names = "se";
854 interconnect-names = "qup-core", "qup-config";
859 compatible = "qcom,geni-i2c";
862 clock-names = "se";
867 interconnect-names = "qup-core", "qup-config", "qup-memory";
868 #address-cells = <1>;
869 #size-cells = <0>;
874 compatible = "qcom,geni-spi";
877 clock-names = "se";
881 interconnect-names = "qup-core", "qup-config";
882 #address-cells = <1>;
883 #size-cells = <0>;
888 compatible = "qcom,geni-uart";
891 clock-names = "se";
895 interconnect-names = "qup-core", "qup-config";
900 compatible = "qcom,geni-i2c";
903 clock-names = "se";
908 interconnect-names = "qup-core", "qup-config", "qup-memory";
909 #address-cells = <1>;
910 #size-cells = <0>;
915 compatible = "qcom,geni-spi";
918 clock-names = "se";
922 interconnect-names = "qup-core", "qup-config";
923 #address-cells = <1>;
924 #size-cells = <0>;
929 compatible = "qcom,geni-uart";
932 clock-names = "se";
936 interconnect-names = "qup-core", "qup-config";
941 compatible = "qcom,geni-i2c";
944 clock-names = "se";
949 interconnect-names = "qup-core", "qup-config", "qup-memory";
950 #address-cells = <1>;
951 #size-cells = <0>;
956 compatible = "qcom,geni-spi";
959 clock-names = "se";
963 interconnect-names = "qup-core", "qup-config";
964 #address-cells = <1>;
965 #size-cells = <0>;
970 compatible = "qcom,geni-uart";
973 clock-names = "se";
977 interconnect-names = "qup-core", "qup-config";
982 compatible = "qcom,geni-i2c";
985 clock-names = "se";
990 interconnect-names = "qup-core", "qup-config", "qup-memory";
991 #address-cells = <1>;
992 #size-cells = <0>;
997 compatible = "qcom,geni-spi";
1000 clock-names = "se";
1004 interconnect-names = "qup-core", "qup-config";
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1011 compatible = "qcom,geni-uart";
1014 clock-names = "se";
1018 interconnect-names = "qup-core", "qup-config";
1023 compatible = "qcom,geni-i2c";
1026 clock-names = "se";
1031 interconnect-names = "qup-core", "qup-config", "qup-memory";
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1038 compatible = "qcom,geni-spi";
1041 clock-names = "se";
1045 interconnect-names = "qup-core", "qup-config";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1052 compatible = "qcom,geni-uart";
1055 clock-names = "se";
1059 interconnect-names = "qup-core", "qup-config";
1064 compatible = "qcom,geni-i2c";
1067 clock-names = "se";
1072 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1079 compatible = "qcom,geni-spi";
1082 clock-names = "se";
1086 interconnect-names = "qup-core", "qup-config";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 compatible = "qcom,geni-uart";
1096 clock-names = "se";
1100 interconnect-names = "qup-core", "qup-config";
1105 compatible = "qcom,geni-i2c";
1108 clock-names = "se";
1113 interconnect-names = "qup-core", "qup-config", "qup-memory";
1114 #address-cells = <1>;
1115 #size-cells = <0>;
1120 compatible = "qcom,geni-spi";
1123 clock-names = "se";
1127 interconnect-names = "qup-core", "qup-config";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1134 compatible = "qcom,geni-uart";
1137 clock-names = "se";
1141 interconnect-names = "qup-core", "qup-config";
1147 compatible = "qcom,geni-se-qup";
1151 clock-names = "m-ahb", "s-ahb";
1152 #address-cells = <2>;
1153 #size-cells = <2>;
1159 compatible = "qcom,geni-i2c";
1162 clock-names = "se";
1167 interconnect-names = "qup-core", "qup-config", "qup-memory";
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1174 compatible = "qcom,geni-spi";
1177 clock-names = "se";
1181 interconnect-names = "qup-core", "qup-config";
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1188 compatible = "qcom,geni-uart";
1191 clock-names = "se";
1195 interconnect-names = "qup-core", "qup-config";
1200 compatible = "qcom,geni-i2c";
1203 clock-names = "se";
1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1215 compatible = "qcom,geni-spi";
1218 clock-names = "se";
1222 interconnect-names = "qup-core", "qup-config";
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1229 compatible = "qcom,geni-debug-uart";
1232 clock-names = "se";
1236 interconnect-names = "qup-core", "qup-config";
1241 compatible = "qcom,geni-i2c";
1244 clock-names = "se";
1249 interconnect-names = "qup-core", "qup-config", "qup-memory";
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1256 compatible = "qcom,geni-spi";
1259 clock-names = "se";
1263 interconnect-names = "qup-core", "qup-config";
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1270 compatible = "qcom,geni-uart";
1273 clock-names = "se";
1277 interconnect-names = "qup-core", "qup-config";
1282 compatible = "qcom,geni-i2c";
1285 clock-names = "se";
1290 interconnect-names = "qup-core", "qup-config", "qup-memory";
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1297 compatible = "qcom,geni-spi";
1300 clock-names = "se";
1304 interconnect-names = "qup-core", "qup-config";
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1311 compatible = "qcom,geni-uart";
1314 clock-names = "se";
1318 interconnect-names = "qup-core", "qup-config";
1323 compatible = "qcom,geni-i2c";
1326 clock-names = "se";
1331 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1338 compatible = "qcom,geni-spi";
1341 clock-names = "se";
1345 interconnect-names = "qup-core", "qup-config";
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1352 compatible = "qcom,geni-uart";
1355 clock-names = "se";
1359 interconnect-names = "qup-core", "qup-config";
1364 compatible = "qcom,geni-i2c";
1367 clock-names = "se";
1372 interconnect-names = "qup-core", "qup-config", "qup-memory";
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1379 compatible = "qcom,geni-spi";
1382 clock-names = "se";
1386 interconnect-names = "qup-core", "qup-config";
1387 #address-cells = <1>;
1388 #size-cells = <0>;
1393 compatible = "qcom,geni-uart";
1396 clock-names = "se";
1400 interconnect-names = "qup-core", "qup-config";
1406 compatible = "qcom,geni-se-qup";
1410 clock-names = "m-ahb", "s-ahb";
1411 #address-cells = <2>;
1412 #size-cells = <2>;
1418 compatible = "qcom,geni-i2c";
1421 clock-names = "se";
1426 interconnect-names = "qup-core", "qup-config", "qup-memory";
1427 #address-cells = <1>;
1428 #size-cells = <0>;
1433 compatible = "qcom,geni-spi";
1436 clock-names = "se";
1440 interconnect-names = "qup-core", "qup-config";
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1447 compatible = "qcom,geni-uart";
1450 clock-names = "se";
1454 interconnect-names = "qup-core", "qup-config";
1459 compatible = "qcom,geni-i2c";
1462 clock-names = "se";
1467 interconnect-names = "qup-core", "qup-config", "qup-memory";
1468 #address-cells = <1>;
1469 #size-cells = <0>;
1474 compatible = "qcom,geni-spi";
1477 clock-names = "se";
1481 interconnect-names = "qup-core", "qup-config";
1482 #address-cells = <1>;
1483 #size-cells = <0>;
1488 compatible = "qcom,geni-uart";
1491 clock-names = "se";
1495 interconnect-names = "qup-core", "qup-config";
1500 compatible = "qcom,geni-i2c";
1503 clock-names = "se";
1508 interconnect-names = "qup-core", "qup-config", "qup-memory";
1509 #address-cells = <1>;
1510 #size-cells = <0>;
1515 compatible = "qcom,geni-spi";
1518 clock-names = "se";
1522 interconnect-names = "qup-core", "qup-config";
1523 #address-cells = <1>;
1524 #size-cells = <0>;
1529 compatible = "qcom,geni-uart";
1532 clock-names = "se";
1536 interconnect-names = "qup-core", "qup-config";
1541 compatible = "qcom,geni-i2c";
1544 clock-names = "se";
1549 interconnect-names = "qup-core", "qup-config", "qup-memory";
1550 #address-cells = <1>;
1551 #size-cells = <0>;
1556 compatible = "qcom,geni-spi";
1559 clock-names = "se";
1563 interconnect-names = "qup-core", "qup-config";
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1570 compatible = "qcom,geni-uart";
1573 clock-names = "se";
1577 interconnect-names = "qup-core", "qup-config";
1582 compatible = "qcom,geni-i2c";
1585 clock-names = "se";
1590 interconnect-names = "qup-core", "qup-config", "qup-memory";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1597 compatible = "qcom,geni-spi";
1600 clock-names = "se";
1604 interconnect-names = "qup-core", "qup-config";
1605 #address-cells = <1>;
1606 #size-cells = <0>;
1611 compatible = "qcom,geni-uart";
1614 clock-names = "se";
1618 interconnect-names = "qup-core", "qup-config";
1623 compatible = "qcom,geni-i2c";
1626 clock-names = "se";
1631 interconnect-names = "qup-core", "qup-config", "qup-memory";
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1638 compatible = "qcom,geni-spi";
1641 clock-names = "se";
1645 interconnect-names = "qup-core", "qup-config";
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1652 compatible = "qcom,geni-uart";
1655 clock-names = "se";
1659 interconnect-names = "qup-core", "qup-config";
1665 compatible = "qcom,sc8180x-config-noc";
1667 #interconnect-cells = <2>;
1668 qcom,bcm-voters = <&apps_bcm_voter>;
1672 compatible = "qcom,sc8180x-system-noc";
1674 #interconnect-cells = <2>;
1675 qcom,bcm-voters = <&apps_bcm_voter>;
1679 compatible = "qcom,sc8180x-aggre1-noc";
1681 #interconnect-cells = <2>;
1682 qcom,bcm-voters = <&apps_bcm_voter>;
1686 compatible = "qcom,sc8180x-aggre2-noc";
1688 #interconnect-cells = <2>;
1689 qcom,bcm-voters = <&apps_bcm_voter>;
1693 compatible = "qcom,sc8180x-compute-noc";
1695 #interconnect-cells = <2>;
1696 qcom,bcm-voters = <&apps_bcm_voter>;
1700 compatible = "qcom,sc8180x-mmss-noc";
1702 #interconnect-cells = <2>;
1703 qcom,bcm-voters = <&apps_bcm_voter>;
1707 compatible = "qcom,pcie-sc8180x";
1713 reg-names = "parf",
1719 linux,pci-domain = <0>;
1720 bus-range = <0x00 0xff>;
1721 num-lanes = <2>;
1723 #address-cells = <3>;
1724 #size-cells = <2>;
1738 interrupt-names = "msi0",
1747 #interrupt-cells = <1>;
1748 interrupt-map-mask = <0 0 0 0x7>;
1749 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1750 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1751 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1752 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1760 clock-names = "pipe",
1767 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1768 assigned-clock-rates = <19200000>;
1770 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1774 reset-names = "pci";
1776 power-domains = <&gcc PCIE_0_GDSC>;
1780 interconnect-names = "pcie-mem", "cpu-pcie";
1783 phy-names = "pciephy";
1784 dma-coherent;
1791 bus-range = <0x01 0xff>;
1793 #address-cells = <3>;
1794 #size-cells = <2>;
1800 compatible = "qcom,sc8180x-qmp-pcie-phy";
1807 clock-names = "aux",
1812 #clock-cells = <0>;
1813 clock-output-names = "pcie_0_pipe_clk";
1814 #phy-cells = <0>;
1817 reset-names = "phy";
1819 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1820 assigned-clock-rates = <100000000>;
1826 compatible = "qcom,pcie-sc8180x";
1832 reg-names = "parf",
1838 linux,pci-domain = <3>;
1839 bus-range = <0x00 0xff>;
1840 num-lanes = <2>;
1842 #address-cells = <3>;
1843 #size-cells = <2>;
1857 interrupt-names = "msi0",
1866 #interrupt-cells = <1>;
1867 interrupt-map-mask = <0 0 0 0x7>;
1868 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1869 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1870 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1871 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1879 clock-names = "pipe",
1886 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1887 assigned-clock-rates = <19200000>;
1889 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1893 reset-names = "pci";
1895 power-domains = <&gcc PCIE_3_GDSC>;
1899 interconnect-names = "pcie-mem", "cpu-pcie";
1902 phy-names = "pciephy";
1903 dma-coherent;
1910 bus-range = <0x01 0xff>;
1912 #address-cells = <3>;
1913 #size-cells = <2>;
1919 compatible = "qcom,sc8180x-qmp-pcie-phy";
1926 clock-names = "aux",
1931 #clock-cells = <0>;
1932 clock-output-names = "pcie_3_pipe_clk";
1934 #phy-cells = <0>;
1937 reset-names = "phy";
1939 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1940 assigned-clock-rates = <100000000>;
1946 compatible = "qcom,pcie-sc8180x";
1952 reg-names = "parf",
1958 linux,pci-domain = <1>;
1959 bus-range = <0x00 0xff>;
1960 num-lanes = <2>;
1962 #address-cells = <3>;
1963 #size-cells = <2>;
1977 interrupt-names = "msi0",
1986 #interrupt-cells = <1>;
1987 interrupt-map-mask = <0 0 0 0x7>;
1988 interrupt-map = <0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1989 <0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1990 <0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1991 <0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1999 clock-names = "pipe",
2006 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2007 assigned-clock-rates = <19200000>;
2009 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2013 reset-names = "pci";
2015 power-domains = <&gcc PCIE_1_GDSC>;
2019 interconnect-names = "pcie-mem", "cpu-pcie";
2022 phy-names = "pciephy";
2023 dma-coherent;
2030 bus-range = <0x01 0xff>;
2032 #address-cells = <3>;
2033 #size-cells = <2>;
2039 compatible = "qcom,sc8180x-qmp-pcie-phy";
2046 clock-names = "aux",
2051 #clock-cells = <0>;
2052 clock-output-names = "pcie_1_pipe_clk";
2054 #phy-cells = <0>;
2057 reset-names = "phy";
2059 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2060 assigned-clock-rates = <100000000>;
2066 compatible = "qcom,pcie-sc8180x";
2072 reg-names = "parf",
2078 linux,pci-domain = <2>;
2079 bus-range = <0x00 0xff>;
2080 num-lanes = <4>;
2082 #address-cells = <3>;
2083 #size-cells = <2>;
2097 interrupt-names = "msi0",
2106 #interrupt-cells = <1>;
2107 interrupt-map-mask = <0 0 0 0x7>;
2108 interrupt-map = <0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2109 <0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2110 <0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2111 <0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2119 clock-names = "pipe",
2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2127 assigned-clock-rates = <19200000>;
2129 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2133 reset-names = "pci";
2135 power-domains = <&gcc PCIE_2_GDSC>;
2139 interconnect-names = "pcie-mem", "cpu-pcie";
2142 phy-names = "pciephy";
2143 dma-coherent;
2150 bus-range = <0x01 0xff>;
2152 #address-cells = <3>;
2153 #size-cells = <2>;
2159 compatible = "qcom,sc8180x-qmp-pcie-phy";
2166 clock-names = "aux",
2171 #clock-cells = <0>;
2172 clock-output-names = "pcie_2_pipe_clk";
2174 #phy-cells = <0>;
2177 reset-names = "phy";
2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2180 assigned-clock-rates = <100000000>;
2186 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2187 "jedec,ufs-2.0";
2191 phy-names = "ufsphy";
2192 lanes-per-direction = <2>;
2193 #reset-cells = <1>;
2195 reset-names = "rst";
2207 clock-names = "core_clk",
2215 freq-table-hz = <37500000 300000000>,
2224 power-domains = <&gcc UFS_PHY_GDSC>;
2230 interconnect-names = "ufs-ddr", "cpu-ufs";
2235 ufs_mem_phy: phy-wrapper@1d87000 {
2236 compatible = "qcom,sc8180x-qmp-ufs-phy";
2242 clock-names = "ref",
2247 reset-names = "ufsphy";
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2251 #phy-cells = <0>;
2257 compatible = "qcom,tcsr-mutex";
2259 #hwlock-cells = <1>;
2263 compatible = "qcom,adreno-680.1", "qcom,adreno";
2266 reg-names = "kgsl_3d0_reg_memory";
2272 operating-points-v2 = <&gpu_opp_table>;
2275 interconnect-names = "gfx-mem";
2278 #cooling-cells = <2>;
2282 gpu_zap_shader: zap-shader {
2283 memory-region = <&gpu_mem>;
2286 gpu_opp_table: opp-table {
2287 compatible = "operating-points-v2";
2289 opp-514000000 {
2290 opp-hz = /bits/ 64 <514000000>;
2291 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2294 opp-500000000 {
2295 opp-hz = /bits/ 64 <500000000>;
2296 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2299 opp-461000000 {
2300 opp-hz = /bits/ 64 <461000000>;
2301 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2304 opp-405000000 {
2305 opp-hz = /bits/ 64 <405000000>;
2306 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2309 opp-315000000 {
2310 opp-hz = /bits/ 64 <315000000>;
2311 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2314 opp-256000000 {
2315 opp-hz = /bits/ 64 <256000000>;
2316 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2319 opp-177000000 {
2320 opp-hz = /bits/ 64 <177000000>;
2321 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2327 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2332 reg-names = "gmu",
2338 interrupt-names = "hfi", "gmu";
2345 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2347 power-domains = <&gpucc GPU_CX_GDSC>,
2349 power-domain-names = "cx", "gx";
2353 operating-points-v2 = <&gmu_opp_table>;
2355 gmu_opp_table: opp-table {
2356 compatible = "operating-points-v2";
2358 opp-200000000 {
2359 opp-hz = /bits/ 64 <200000000>;
2360 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2363 opp-500000000 {
2364 opp-hz = /bits/ 64 <500000000>;
2365 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2370 gpucc: clock-controller@2c90000 {
2371 compatible = "qcom,sc8180x-gpucc";
2376 clock-names = "bi_tcxo",
2379 #clock-cells = <1>;
2380 #reset-cells = <1>;
2381 #power-domain-cells = <1>;
2385 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2386 "qcom,smmu-500", "arm,mmu-500";
2388 #iommu-cells = <2>;
2389 #global-interrupts = <1>;
2402 clock-names = "ahb", "bus", "iface";
2404 power-domains = <&gpucc GPU_CX_GDSC>;
2408 compatible = "qcom,sc8180x-tlmm";
2412 reg-names = "west", "east", "south";
2414 gpio-controller;
2415 #gpio-cells = <2>;
2416 interrupt-controller;
2417 #interrupt-cells = <2>;
2418 gpio-ranges = <&tlmm 0 0 191>;
2419 wakeup-parent = <&pdc>;
2423 compatible = "qcom,sc8180x-mpss-pas";
2426 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2432 interrupt-names = "wdog", "fatal", "ready", "handover",
2433 "stop-ack", "shutdown-ack";
2436 clock-names = "xo";
2438 power-domains = <&rpmhpd SC8180X_CX>,
2440 power-domain-names = "cx", "mss";
2444 qcom,smem-states = <&modem_smp2p_out 0>;
2445 qcom,smem-state-names = "stop";
2447 glink-edge {
2450 qcom,remote-pid = <1>;
2456 compatible = "qcom,sc8180x-cdsp-pas";
2459 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2464 interrupt-names = "wdog", "fatal", "ready",
2465 "handover", "stop-ack";
2468 clock-names = "xo";
2470 power-domains = <&rpmhpd SC8180X_CX>;
2471 power-domain-names = "cx";
2475 qcom,smem-states = <&cdsp_smp2p_out 0>;
2476 qcom,smem-state-names = "stop";
2480 glink-edge {
2483 qcom,remote-pid = <5>;
2489 compatible = "qcom,sc8180x-usb-hs-phy",
2490 "qcom,usb-snps-hs-7nm-phy";
2493 clock-names = "ref";
2496 #phy-cells = <0>;
2502 compatible = "qcom,sc8180x-usb-hs-phy",
2503 "qcom,usb-snps-hs-7nm-phy";
2506 clock-names = "ref";
2509 #phy-cells = <0>;
2515 compatible = "qcom,sc8180x-usb-hs-phy",
2516 "qcom,usb-snps-hs-7nm-phy";
2518 #phy-cells = <0>;
2521 clock-names = "ref";
2529 compatible = "qcom,sc8180x-usb-hs-phy",
2530 "qcom,usb-snps-hs-7nm-phy";
2532 #phy-cells = <0>;
2535 clock-names = "ref";
2543 compatible = "qcom,sc8180x-refgen-regulator",
2544 "qcom,sdm845-refgen-regulator";
2549 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2556 clock-names = "aux",
2563 reset-names = "phy", "common";
2565 #clock-cells = <1>;
2566 #phy-cells = <1>;
2571 #address-cells = <1>;
2572 #size-cells = <0>;
2584 remote-endpoint = <&usb_prim_dwc3_ss>;
2597 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2604 clock-names = "aux",
2611 reset-names = "phy", "phy_phy";
2613 power-domains = <&gcc USB30_MP_GDSC>;
2615 #clock-cells = <0>;
2616 clock-output-names = "usb2_phy0_pipe_clk";
2618 #phy-cells = <0>;
2624 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2631 clock-names = "aux",
2638 reset-names = "phy", "phy_phy";
2640 power-domains = <&gcc USB30_MP_GDSC>;
2642 #clock-cells = <0>;
2643 clock-output-names = "usb2_phy1_pipe_clk";
2645 #phy-cells = <0>;
2651 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2658 clock-names = "aux",
2664 reset-names = "phy", "common";
2666 #clock-cells = <1>;
2667 #phy-cells = <1>;
2672 #address-cells = <1>;
2673 #size-cells = <0>;
2685 remote-endpoint = <&usb_sec_dwc3_ss>;
2697 system-cache-controller@9200000 {
2698 compatible = "qcom,sc8180x-llcc";
2704 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2711 compatible = "qcom,sc8180x-gem-noc";
2713 #interconnect-cells = <2>;
2714 qcom,bcm-voters = <&apps_bcm_voter>;
2718 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
2720 #address-cells = <2>;
2721 #size-cells = <2>;
2723 dma-ranges;
2731 clock-names = "cfg_noc",
2740 interconnect-names = "usb-ddr", "apps-usb";
2742 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2744 assigned-clock-rates = <19200000>, <200000000>;
2746 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
2747 <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
2748 <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
2749 <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
2750 <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
2751 <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
2752 <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
2753 <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
2754 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
2755 <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
2756 interrupt-names = "pwr_event_1", "pwr_event_2",
2762 power-domains = <&gcc USB30_MP_GDSC>;
2775 snps,dis-u1-entry-quirk;
2776 snps,dis-u2-entry-quirk;
2781 phy-names = "usb2-0",
2782 "usb3-0",
2783 "usb2-1",
2784 "usb3-1";
2790 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2792 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2793 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2794 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
2795 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2796 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
2797 interrupt-names = "pwr_event",
2809 clock-names = "cfg_noc",
2816 power-domains = <&gcc USB30_PRIM_GDSC>;
2820 interconnect-names = "usb-ddr", "apps-usb";
2822 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2824 assigned-clock-rates = <19200000>, <200000000>;
2826 #address-cells = <2>;
2827 #size-cells = <2>;
2829 dma-ranges;
2840 snps,dis-u1-entry-quirk;
2841 snps,dis-u2-entry-quirk;
2843 phy-names = "usb2-phy", "usb3-phy";
2846 #address-cells = <1>;
2847 #size-cells = <0>;
2860 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
2868 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2877 clock-names = "cfg_noc",
2884 power-domains = <&gcc USB30_SEC_GDSC>;
2886 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2887 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2888 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
2889 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
2890 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
2891 interrupt-names = "pwr_event",
2897 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2899 assigned-clock-rates = <19200000>, <200000000>;
2903 interconnect-names = "usb-ddr", "apps-usb";
2905 #address-cells = <2>;
2906 #size-cells = <2>;
2908 dma-ranges;
2919 snps,dis-u1-entry-quirk;
2920 snps,dis-u2-entry-quirk;
2922 phy-names = "usb2-phy", "usb3-phy";
2925 #address-cells = <1>;
2926 #size-cells = <0>;
2939 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
2946 videocc: clock-controller@ab00000 {
2947 compatible = "qcom,sc8180x-videocc",
2948 "qcom,sm8150-videocc";
2952 clock-names = "iface", "bi_tcxo";
2953 power-domains = <&rpmhpd SC8180X_MMCX>;
2954 required-opps = <&rpmhpd_opp_low_svs>;
2955 #clock-cells = <1>;
2956 #reset-cells = <1>;
2957 #power-domain-cells = <1>;
2960 camcc: clock-controller@ad00000 {
2961 compatible = "qcom,sc8180x-camcc";
2966 power-domains = <&rpmhpd SC8180X_MMCX>;
2967 required-opps = <&rpmhpd_opp_low_svs>;
2968 #clock-cells = <1>;
2969 #reset-cells = <1>;
2970 #power-domain-cells = <1>;
2973 mdss: display-subsystem@ae00000 {
2974 compatible = "qcom,sc8180x-mdss";
2976 reg-names = "mdss";
2978 power-domains = <&dispcc MDSS_GDSC>;
2984 clock-names = "iface",
2992 interrupt-controller;
2993 #interrupt-cells = <1>;
3001 interconnect-names = "mdp0-mem",
3002 "mdp1-mem",
3003 "cpu-cfg";
3007 #address-cells = <2>;
3008 #size-cells = <2>;
3013 mdss_mdp: display-controller@ae01000 {
3014 compatible = "qcom,sc8180x-dpu";
3017 reg-names = "mdp", "vbif";
3025 clock-names = "iface",
3032 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3033 assigned-clock-rates = <19200000>;
3035 operating-points-v2 = <&mdp_opp_table>;
3036 power-domains = <&rpmhpd SC8180X_MMCX>;
3038 interrupt-parent = <&mdss>;
3042 #address-cells = <1>;
3043 #size-cells = <0>;
3048 remote-endpoint = <&dp0_in>;
3055 remote-endpoint = <&mdss_dsi0_in>;
3062 remote-endpoint = <&mdss_dsi1_in>;
3069 remote-endpoint = <&dp1_in>;
3076 remote-endpoint = <&edp_in>;
3081 mdp_opp_table: opp-table {
3082 compatible = "operating-points-v2";
3084 opp-200000000 {
3085 opp-hz = /bits/ 64 <200000000>;
3086 required-opps = <&rpmhpd_opp_low_svs>;
3089 opp-300000000 {
3090 opp-hz = /bits/ 64 <300000000>;
3091 required-opps = <&rpmhpd_opp_svs>;
3094 opp-345000000 {
3095 opp-hz = /bits/ 64 <345000000>;
3096 required-opps = <&rpmhpd_opp_svs_l1>;
3099 opp-460000000 {
3100 opp-hz = /bits/ 64 <460000000>;
3101 required-opps = <&rpmhpd_opp_nom>;
3107 compatible = "qcom,sc8180x-dsi-ctrl",
3108 "qcom,mdss-dsi-ctrl";
3110 reg-names = "dsi_ctrl";
3112 interrupt-parent = <&mdss>;
3121 clock-names = "byte",
3128 operating-points-v2 = <&dsi_opp_table>;
3129 power-domains = <&rpmhpd SC8180X_MMCX>;
3132 phy-names = "dsi";
3134 refgen-supply = <&refgen>;
3139 #address-cells = <1>;
3140 #size-cells = <0>;
3145 remote-endpoint = <&dpu_intf1_out>;
3156 dsi_opp_table: opp-table {
3157 compatible = "operating-points-v2";
3159 opp-187500000 {
3160 opp-hz = /bits/ 64 <187500000>;
3161 required-opps = <&rpmhpd_opp_low_svs>;
3164 opp-300000000 {
3165 opp-hz = /bits/ 64 <300000000>;
3166 required-opps = <&rpmhpd_opp_svs>;
3169 opp-358000000 {
3170 opp-hz = /bits/ 64 <358000000>;
3171 required-opps = <&rpmhpd_opp_svs_l1>;
3177 compatible = "qcom,dsi-phy-7nm";
3181 reg-names = "dsi_phy",
3185 #clock-cells = <1>;
3186 #phy-cells = <0>;
3190 clock-names = "iface", "ref";
3196 compatible = "qcom,sc8180x-dsi-ctrl",
3197 "qcom,mdss-dsi-ctrl";
3199 reg-names = "dsi_ctrl";
3201 interrupt-parent = <&mdss>;
3210 clock-names = "byte",
3217 operating-points-v2 = <&dsi_opp_table>;
3218 power-domains = <&rpmhpd SC8180X_MMCX>;
3221 phy-names = "dsi";
3223 refgen-supply = <&refgen>;
3228 #address-cells = <1>;
3229 #size-cells = <0>;
3234 remote-endpoint = <&dpu_intf2_out>;
3247 compatible = "qcom,dsi-phy-7nm";
3251 reg-names = "dsi_phy",
3255 #clock-cells = <1>;
3256 #phy-cells = <0>;
3260 clock-names = "iface", "ref";
3265 mdss_dp0: displayport-controller@ae90000 {
3266 compatible = "qcom,sc8180x-dp";
3272 interrupt-parent = <&mdss>;
3280 clock-names = "core_iface",
3287 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3290 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3295 phy-names = "dp";
3297 #sound-dai-cells = <0>;
3299 operating-points-v2 = <&dp0_opp_table>;
3300 power-domains = <&rpmhpd SC8180X_MMCX>;
3305 #address-cells = <1>;
3306 #size-cells = <0>;
3311 remote-endpoint = <&dpu_intf0_out>;
3322 dp0_opp_table: opp-table {
3323 compatible = "operating-points-v2";
3325 opp-160000000 {
3326 opp-hz = /bits/ 64 <160000000>;
3327 required-opps = <&rpmhpd_opp_low_svs>;
3330 opp-270000000 {
3331 opp-hz = /bits/ 64 <270000000>;
3332 required-opps = <&rpmhpd_opp_svs>;
3335 opp-540000000 {
3336 opp-hz = /bits/ 64 <540000000>;
3337 required-opps = <&rpmhpd_opp_svs_l1>;
3340 opp-810000000 {
3341 opp-hz = /bits/ 64 <810000000>;
3342 required-opps = <&rpmhpd_opp_nom>;
3347 mdss_dp1: displayport-controller@ae98000 {
3348 compatible = "qcom,sc8180x-dp";
3354 interrupt-parent = <&mdss>;
3362 clock-names = "core_iface",
3369 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3372 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3377 phy-names = "dp";
3379 #sound-dai-cells = <0>;
3381 operating-points-v2 = <&dp0_opp_table>;
3382 power-domains = <&rpmhpd SC8180X_MMCX>;
3387 #address-cells = <1>;
3388 #size-cells = <0>;
3393 remote-endpoint = <&dpu_intf4_out>;
3404 dp1_opp_table: opp-table {
3405 compatible = "operating-points-v2";
3407 opp-160000000 {
3408 opp-hz = /bits/ 64 <160000000>;
3409 required-opps = <&rpmhpd_opp_low_svs>;
3412 opp-270000000 {
3413 opp-hz = /bits/ 64 <270000000>;
3414 required-opps = <&rpmhpd_opp_svs>;
3417 opp-540000000 {
3418 opp-hz = /bits/ 64 <540000000>;
3419 required-opps = <&rpmhpd_opp_svs_l1>;
3422 opp-810000000 {
3423 opp-hz = /bits/ 64 <810000000>;
3424 required-opps = <&rpmhpd_opp_nom>;
3429 mdss_edp: displayport-controller@ae9a000 {
3430 compatible = "qcom,sc8180x-edp";
3436 interrupt-parent = <&mdss>;
3443 clock-names = "core_iface",
3449 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3451 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3454 phy-names = "dp";
3456 operating-points-v2 = <&edp_opp_table>;
3457 power-domains = <&rpmhpd SC8180X_MMCX>;
3462 #address-cells = <1>;
3463 #size-cells = <0>;
3468 remote-endpoint = <&dpu_intf5_out>;
3480 edp_opp_table: opp-table {
3481 compatible = "operating-points-v2";
3483 opp-160000000 {
3484 opp-hz = /bits/ 64 <160000000>;
3485 required-opps = <&rpmhpd_opp_low_svs>;
3488 opp-270000000 {
3489 opp-hz = /bits/ 64 <270000000>;
3490 required-opps = <&rpmhpd_opp_svs>;
3493 opp-540000000 {
3494 opp-hz = /bits/ 64 <540000000>;
3495 required-opps = <&rpmhpd_opp_svs_l1>;
3498 opp-810000000 {
3499 opp-hz = /bits/ 64 <810000000>;
3500 required-opps = <&rpmhpd_opp_nom>;
3507 compatible = "qcom,sc8180x-edp-phy";
3515 clock-names = "aux", "cfg_ahb";
3517 power-domains = <&rpmhpd SC8180X_MX>;
3519 #clock-cells = <1>;
3520 #phy-cells = <0>;
3523 dispcc: clock-controller@af00000 {
3524 compatible = "qcom,sc8180x-dispcc";
3537 clock-names = "bi_tcxo",
3548 power-domains = <&rpmhpd SC8180X_MMCX>;
3549 required-opps = <&rpmhpd_opp_low_svs>;
3550 #clock-cells = <1>;
3551 #reset-cells = <1>;
3552 #power-domain-cells = <1>;
3555 pdc: interrupt-controller@b220000 { label
3556 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3558 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3559 #interrupt-cells = <2>;
3560 interrupt-parent = <&intc>;
3561 interrupt-controller;
3564 tsens0: thermal-sensor@c263000 {
3565 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3571 interrupt-names = "uplow", "critical";
3572 #thermal-sensor-cells = <1>;
3575 tsens1: thermal-sensor@c265000 {
3576 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3582 interrupt-names = "uplow", "critical";
3583 #thermal-sensor-cells = <1>;
3586 aoss_qmp: power-management@c300000 {
3587 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3592 #clock-cells = <0>;
3596 compatible = "qcom,rpmh-stats";
3601 compatible = "qcom,spmi-pmic-arb";
3607 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3608 interrupt-names = "periph_irq";
3612 #address-cells = <2>;
3613 #size-cells = <0>;
3614 interrupt-controller;
3615 #interrupt-cells = <4>;
3619 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3621 #iommu-cells = <2>;
3622 #global-interrupts = <1>;
3730 dma-coherent;
3734 compatible = "qcom,sc8180x-adsp-pas";
3737 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3742 interrupt-names = "wdog", "fatal", "ready",
3743 "handover", "stop-ack";
3746 clock-names = "xo";
3748 power-domains = <&rpmhpd SC8180X_CX>;
3749 power-domain-names = "cx";
3753 qcom,smem-states = <&adsp_smp2p_out 0>;
3754 qcom,smem-state-names = "stop";
3758 remoteproc_adsp_glink: glink-edge {
3761 qcom,remote-pid = <2>;
3766 intc: interrupt-controller@17a00000 { label
3767 compatible = "arm,gic-v3";
3768 interrupt-controller;
3769 #address-cells = <0>;
3770 #interrupt-cells = <3>;
3774 #redistributor-regions = <1>;
3775 redistributor-stride = <0 0x20000>;
3779 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3781 #mbox-cells = <1>;
3785 compatible = "arm,armv7-timer-mem";
3788 #address-cells = <1>;
3789 #size-cells = <1>;
3795 frame-number = <0>;
3802 frame-number = <1>;
3809 frame-number = <2>;
3816 frame-number = <3>;
3823 frame-number = <4>;
3830 frame-number = <5>;
3837 frame-number = <6>;
3844 compatible = "qcom,rpmh-rsc";
3848 reg-names = "drv-0", "drv-1", "drv-2";
3852 qcom,tcs-offset = <0xd00>;
3853 qcom,drv-id = <2>;
3854 qcom,tcs-config = <ACTIVE_TCS 2>,
3859 power-domains = <&cluster_pd>;
3861 apps_bcm_voter: bcm-voter {
3862 compatible = "qcom,bcm-voter";
3865 rpmhcc: clock-controller {
3866 compatible = "qcom,sc8180x-rpmh-clk";
3867 #clock-cells = <1>;
3868 clock-names = "xo";
3872 rpmhpd: power-controller {
3873 compatible = "qcom,sc8180x-rpmhpd";
3874 #power-domain-cells = <1>;
3875 operating-points-v2 = <&rpmhpd_opp_table>;
3877 rpmhpd_opp_table: opp-table {
3878 compatible = "operating-points-v2";
3881 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3885 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3889 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3893 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3897 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3901 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3905 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3909 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3913 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3917 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3924 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3928 clock-names = "xo", "alternate";
3930 #interconnect-cells = <1>;
3934 compatible = "qcom,sc8180x-lmh";
3938 qcom,lmh-temp-arm-millicelsius = <65000>;
3939 qcom,lmh-temp-low-millicelsius = <94500>;
3940 qcom,lmh-temp-high-millicelsius = <95000>;
3941 interrupt-controller;
3942 #interrupt-cells = <1>;
3946 compatible = "qcom,sc8180x-lmh";
3950 qcom,lmh-temp-arm-millicelsius = <65000>;
3951 qcom,lmh-temp-low-millicelsius = <94500>;
3952 qcom,lmh-temp-high-millicelsius = <95000>;
3953 interrupt-controller;
3954 #interrupt-cells = <1>;
3958 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw";
3960 reg-names = "freq-domain0", "freq-domain1";
3963 clock-names = "xo", "alternate";
3965 #freq-domain-cells = <1>;
3966 #clock-cells = <1>;
3970 compatible = "qcom,wcn3990-wifi";
3972 reg-names = "membase";
3973 clock-names = "cxo_ref_clk_pin";
3988 qcom,msa-fixed-perm;
3993 thermal-zones {
3994 cpu0-thermal {
3995 polling-delay-passive = <250>;
3997 thermal-sensors = <&tsens0 1>;
4000 cpu-crit {
4008 cpu1-thermal {
4009 polling-delay-passive = <250>;
4011 thermal-sensors = <&tsens0 2>;
4014 cpu-crit {
4022 cpu2-thermal {
4023 polling-delay-passive = <250>;
4025 thermal-sensors = <&tsens0 3>;
4028 cpu-crit {
4036 cpu3-thermal {
4037 polling-delay-passive = <250>;
4039 thermal-sensors = <&tsens0 4>;
4042 cpu-crit {
4050 cpu4-top-thermal {
4051 polling-delay-passive = <250>;
4053 thermal-sensors = <&tsens0 7>;
4056 cpu-crit {
4064 cpu5-top-thermal {
4065 polling-delay-passive = <250>;
4067 thermal-sensors = <&tsens0 8>;
4070 cpu-crit {
4078 cpu6-top-thermal {
4079 polling-delay-passive = <250>;
4081 thermal-sensors = <&tsens0 9>;
4084 cpu-crit {
4092 cpu7-top-thermal {
4093 polling-delay-passive = <250>;
4095 thermal-sensors = <&tsens0 10>;
4098 cpu-crit {
4106 cpu4-bottom-thermal {
4107 polling-delay-passive = <250>;
4109 thermal-sensors = <&tsens0 11>;
4112 cpu-crit {
4120 cpu5-bottom-thermal {
4121 polling-delay-passive = <250>;
4123 thermal-sensors = <&tsens0 12>;
4126 cpu-crit {
4134 cpu6-bottom-thermal {
4135 polling-delay-passive = <250>;
4137 thermal-sensors = <&tsens0 13>;
4140 cpu-crit {
4148 cpu7-bottom-thermal {
4149 polling-delay-passive = <250>;
4151 thermal-sensors = <&tsens0 14>;
4154 cpu-crit {
4162 aoss0-thermal {
4163 polling-delay-passive = <250>;
4165 thermal-sensors = <&tsens0 0>;
4168 trip-point0 {
4176 cluster0-thermal {
4177 polling-delay-passive = <250>;
4179 thermal-sensors = <&tsens0 5>;
4182 cluster-crit {
4190 cluster1-thermal {
4191 polling-delay-passive = <250>;
4193 thermal-sensors = <&tsens0 6>;
4196 cluster-crit {
4204 gpu-top-thermal {
4205 polling-delay-passive = <250>;
4207 thermal-sensors = <&tsens0 15>;
4209 cooling-maps {
4212 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4217 gpu_top_alert0: trip-point0 {
4223 trip-point1 {
4229 trip-point2 {
4237 aoss1-thermal {
4238 polling-delay-passive = <250>;
4240 thermal-sensors = <&tsens1 0>;
4243 trip-point0 {
4251 wlan-thermal {
4252 polling-delay-passive = <250>;
4254 thermal-sensors = <&tsens1 1>;
4257 trip-point0 {
4265 video-thermal {
4266 polling-delay-passive = <250>;
4268 thermal-sensors = <&tsens1 2>;
4271 trip-point0 {
4279 mem-thermal {
4280 polling-delay-passive = <250>;
4282 thermal-sensors = <&tsens1 3>;
4285 trip-point0 {
4293 q6-hvx-thermal {
4294 polling-delay-passive = <250>;
4296 thermal-sensors = <&tsens1 4>;
4299 trip-point0 {
4307 camera-thermal {
4308 polling-delay-passive = <250>;
4310 thermal-sensors = <&tsens1 5>;
4313 trip-point0 {
4321 compute-thermal {
4322 polling-delay-passive = <250>;
4324 thermal-sensors = <&tsens1 6>;
4327 trip-point0 {
4335 mdm-dsp-thermal {
4336 polling-delay-passive = <250>;
4338 thermal-sensors = <&tsens1 7>;
4341 trip-point0 {
4349 npu-thermal {
4350 polling-delay-passive = <250>;
4352 thermal-sensors = <&tsens1 8>;
4355 trip-point0 {
4363 gpu-bottom-thermal {
4364 polling-delay-passive = <250>;
4366 thermal-sensors = <&tsens1 11>;
4368 cooling-maps {
4371 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4376 gpu_bottom_alert0: trip-point0 {
4382 trip-point1 {
4388 trip-point2 {
4398 compatible = "arm,armv8-timer";