Lines Matching +full:bcm +full:- +full:voter
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8180x.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #include <dt-bindings/thermal/thermal.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 xo_board_clk: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <38400000>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32764>;
37 clock-output-names = "sleep_clk";
42 #address-cells = <2>;
43 #size-cells = <0>;
49 enable-method = "psci";
50 capacity-dmips-mhz = <602>;
51 next-level-cache = <&L2_0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
53 operating-points-v2 = <&cpu0_opp_table>;
56 power-domains = <&CPU_PD0>;
57 power-domain-names = "psci";
58 #cooling-cells = <2>;
61 L2_0: l2-cache {
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&L3_0>;
66 L3_0: l3-cache {
68 cache-level = <3>;
69 cache-unified;
78 enable-method = "psci";
79 capacity-dmips-mhz = <602>;
80 next-level-cache = <&L2_100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
82 operating-points-v2 = <&cpu0_opp_table>;
85 power-domains = <&CPU_PD1>;
86 power-domain-names = "psci";
87 #cooling-cells = <2>;
90 L2_100: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&L3_0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <602>;
105 next-level-cache = <&L2_200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 operating-points-v2 = <&cpu0_opp_table>;
110 power-domains = <&CPU_PD2>;
111 power-domain-names = "psci";
112 #cooling-cells = <2>;
115 L2_200: l2-cache {
117 cache-level = <2>;
118 cache-unified;
119 next-level-cache = <&L3_0>;
127 enable-method = "psci";
128 capacity-dmips-mhz = <602>;
129 next-level-cache = <&L2_300>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
134 power-domains = <&CPU_PD3>;
135 power-domain-names = "psci";
136 #cooling-cells = <2>;
139 L2_300: l2-cache {
141 cache-unified;
142 cache-level = <2>;
143 next-level-cache = <&L3_0>;
151 enable-method = "psci";
152 capacity-dmips-mhz = <1024>;
153 next-level-cache = <&L2_400>;
154 qcom,freq-domain = <&cpufreq_hw 1>;
155 operating-points-v2 = <&cpu4_opp_table>;
158 power-domains = <&CPU_PD4>;
159 power-domain-names = "psci";
160 #cooling-cells = <2>;
163 L2_400: l2-cache {
165 cache-unified;
166 cache-level = <2>;
167 next-level-cache = <&L3_0>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <1024>;
177 next-level-cache = <&L2_500>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
182 power-domains = <&CPU_PD5>;
183 power-domain-names = "psci";
184 #cooling-cells = <2>;
187 L2_500: l2-cache {
189 cache-unified;
190 cache-level = <2>;
191 next-level-cache = <&L3_0>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 next-level-cache = <&L2_600>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
206 power-domains = <&CPU_PD6>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
211 L2_600: l2-cache {
213 cache-unified;
214 cache-level = <2>;
215 next-level-cache = <&L3_0>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1024>;
225 next-level-cache = <&L2_700>;
226 qcom,freq-domain = <&cpufreq_hw 1>;
227 operating-points-v2 = <&cpu4_opp_table>;
230 power-domains = <&CPU_PD7>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
235 L2_700: l2-cache {
237 cache-unified;
238 cache-level = <2>;
239 next-level-cache = <&L3_0>;
243 cpu-map {
279 idle-states {
280 entry-method = "psci";
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 arm,psci-suspend-param = <0x40000004>;
285 entry-latency-us = <355>;
286 exit-latency-us = <909>;
287 min-residency-us = <3934>;
288 local-timer-stop;
291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 arm,psci-suspend-param = <0x40000004>;
294 entry-latency-us = <2411>;
295 exit-latency-us = <1461>;
296 min-residency-us = <4488>;
297 local-timer-stop;
301 domain-idle-states {
302 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
303 compatible = "domain-idle-state";
304 arm,psci-suspend-param = <0x41000044>;
305 entry-latency-us = <3300>;
306 exit-latency-us = <3300>;
307 min-residency-us = <6000>;
310 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
311 compatible = "domain-idle-state";
312 arm,psci-suspend-param = <0x4100a344>;
313 entry-latency-us = <3263>;
314 exit-latency-us = <6562>;
315 min-residency-us = <9987>;
320 cpu0_opp_table: opp-table-cpu0 {
321 compatible = "operating-points-v2";
322 opp-shared;
324 opp-300000000 {
325 opp-hz = /bits/ 64 <300000000>;
326 opp-peak-kBps = <800000 9600000>;
329 opp-422400000 {
330 opp-hz = /bits/ 64 <422400000>;
331 opp-peak-kBps = <800000 9600000>;
334 opp-537600000 {
335 opp-hz = /bits/ 64 <537600000>;
336 opp-peak-kBps = <800000 12902400>;
339 opp-652800000 {
340 opp-hz = /bits/ 64 <652800000>;
341 opp-peak-kBps = <800000 12902400>;
344 opp-768000000 {
345 opp-hz = /bits/ 64 <768000000>;
346 opp-peak-kBps = <800000 15974400>;
349 opp-883200000 {
350 opp-hz = /bits/ 64 <883200000>;
351 opp-peak-kBps = <1804000 19660800>;
354 opp-998400000 {
355 opp-hz = /bits/ 64 <998400000>;
356 opp-peak-kBps = <1804000 19660800>;
359 opp-1113600000 {
360 opp-hz = /bits/ 64 <1113600000>;
361 opp-peak-kBps = <1804000 22732800>;
364 opp-1228800000 {
365 opp-hz = /bits/ 64 <1228800000>;
366 opp-peak-kBps = <1804000 22732800>;
369 opp-1363200000 {
370 opp-hz = /bits/ 64 <1363200000>;
371 opp-peak-kBps = <2188000 25804800>;
374 opp-1478400000 {
375 opp-hz = /bits/ 64 <1478400000>;
376 opp-peak-kBps = <2188000 31948800>;
379 opp-1574400000 {
380 opp-hz = /bits/ 64 <1574400000>;
381 opp-peak-kBps = <3072000 31948800>;
384 opp-1670400000 {
385 opp-hz = /bits/ 64 <1670400000>;
386 opp-peak-kBps = <3072000 31948800>;
389 opp-1766400000 {
390 opp-hz = /bits/ 64 <1766400000>;
391 opp-peak-kBps = <3072000 31948800>;
395 cpu4_opp_table: opp-table-cpu4 {
396 compatible = "operating-points-v2";
397 opp-shared;
399 opp-825600000 {
400 opp-hz = /bits/ 64 <825600000>;
401 opp-peak-kBps = <1804000 15974400>;
404 opp-940800000 {
405 opp-hz = /bits/ 64 <940800000>;
406 opp-peak-kBps = <2188000 19660800>;
409 opp-1056000000 {
410 opp-hz = /bits/ 64 <1056000000>;
411 opp-peak-kBps = <2188000 22732800>;
414 opp-1171200000 {
415 opp-hz = /bits/ 64 <1171200000>;
416 opp-peak-kBps = <3072000 25804800>;
419 opp-1286400000 {
420 opp-hz = /bits/ 64 <1286400000>;
421 opp-peak-kBps = <3072000 31948800>;
424 opp-1420800000 {
425 opp-hz = /bits/ 64 <1420800000>;
426 opp-peak-kBps = <4068000 31948800>;
429 opp-1536000000 {
430 opp-hz = /bits/ 64 <1536000000>;
431 opp-peak-kBps = <4068000 31948800>;
434 opp-1651200000 {
435 opp-hz = /bits/ 64 <1651200000>;
436 opp-peak-kBps = <4068000 40550400>;
439 opp-1766400000 {
440 opp-hz = /bits/ 64 <1766400000>;
441 opp-peak-kBps = <4068000 40550400>;
444 opp-1881600000 {
445 opp-hz = /bits/ 64 <1881600000>;
446 opp-peak-kBps = <4068000 43008000>;
449 opp-1996800000 {
450 opp-hz = /bits/ 64 <1996800000>;
451 opp-peak-kBps = <6220000 43008000>;
454 opp-2131200000 {
455 opp-hz = /bits/ 64 <2131200000>;
456 opp-peak-kBps = <6220000 49152000>;
459 opp-2246400000 {
460 opp-hz = /bits/ 64 <2246400000>;
461 opp-peak-kBps = <7216000 49152000>;
464 opp-2361600000 {
465 opp-hz = /bits/ 64 <2361600000>;
466 opp-peak-kBps = <8368000 49152000>;
469 opp-2457600000 {
470 opp-hz = /bits/ 64 <2457600000>;
471 opp-peak-kBps = <8368000 51609600>;
474 opp-2553600000 {
475 opp-hz = /bits/ 64 <2553600000>;
476 opp-peak-kBps = <8368000 51609600>;
479 opp-2649600000 {
480 opp-hz = /bits/ 64 <2649600000>;
481 opp-peak-kBps = <8368000 51609600>;
484 opp-2745600000 {
485 opp-hz = /bits/ 64 <2745600000>;
486 opp-peak-kBps = <8368000 51609600>;
489 opp-2841600000 {
490 opp-hz = /bits/ 64 <2841600000>;
491 opp-peak-kBps = <8368000 51609600>;
494 opp-2918400000 {
495 opp-hz = /bits/ 64 <2918400000>;
496 opp-peak-kBps = <8368000 51609600>;
499 opp-2995200000 {
500 opp-hz = /bits/ 64 <2995200000>;
501 opp-peak-kBps = <8368000 51609600>;
507 compatible = "qcom,scm-sc8180x", "qcom,scm";
511 camnoc_virt: interconnect-camnoc-virt {
512 compatible = "qcom,sc8180x-camnoc-virt";
513 #interconnect-cells = <2>;
514 qcom,bcm-voters = <&apps_bcm_voter>;
517 mc_virt: interconnect-mc-virt {
518 compatible = "qcom,sc8180x-mc-virt";
519 #interconnect-cells = <2>;
520 qcom,bcm-voters = <&apps_bcm_voter>;
523 qup_virt: interconnect-qup-virt {
524 compatible = "qcom,sc8180x-qup-virt";
525 #interconnect-cells = <2>;
526 qcom,bcm-voters = <&apps_bcm_voter>;
536 compatible = "arm,armv8-pmuv3";
541 compatible = "arm,psci-1.0";
544 CPU_PD0: power-domain-cpu0 {
545 #power-domain-cells = <0>;
546 power-domains = <&CLUSTER_PD>;
547 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
550 CPU_PD1: power-domain-cpu1 {
551 #power-domain-cells = <0>;
552 power-domains = <&CLUSTER_PD>;
553 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
556 CPU_PD2: power-domain-cpu2 {
557 #power-domain-cells = <0>;
558 power-domains = <&CLUSTER_PD>;
559 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
562 CPU_PD3: power-domain-cpu3 {
563 #power-domain-cells = <0>;
564 power-domains = <&CLUSTER_PD>;
565 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
568 CPU_PD4: power-domain-cpu4 {
569 #power-domain-cells = <0>;
570 power-domains = <&CLUSTER_PD>;
571 domain-idle-states = <&BIG_CPU_SLEEP_0>;
574 CPU_PD5: power-domain-cpu5 {
575 #power-domain-cells = <0>;
576 power-domains = <&CLUSTER_PD>;
577 domain-idle-states = <&BIG_CPU_SLEEP_0>;
580 CPU_PD6: power-domain-cpu6 {
581 #power-domain-cells = <0>;
582 power-domains = <&CLUSTER_PD>;
583 domain-idle-states = <&BIG_CPU_SLEEP_0>;
586 CPU_PD7: power-domain-cpu7 {
587 #power-domain-cells = <0>;
588 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = <&BIG_CPU_SLEEP_0>;
592 CLUSTER_PD: power-domain-cpu-cluster0 {
593 #power-domain-cells = <0>;
594 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
598 reserved-memory {
599 #address-cells = <2>;
600 #size-cells = <2>;
605 no-map;
610 no-map;
615 no-map;
618 aop_cmd_db: cmd-db@85f20000 {
619 compatible = "qcom,cmd-db";
621 no-map;
626 no-map;
632 no-map;
638 no-map;
643 no-map;
648 no-map;
653 no-map;
658 no-map;
662 smp2p-cdsp {
670 qcom,local-pid = <0>;
671 qcom,remote-pid = <5>;
673 cdsp_smp2p_out: master-kernel {
674 qcom,entry-name = "master-kernel";
675 #qcom,smem-state-cells = <1>;
678 cdsp_smp2p_in: slave-kernel {
679 qcom,entry-name = "slave-kernel";
681 interrupt-controller;
682 #interrupt-cells = <2>;
686 smp2p-lpass {
694 qcom,local-pid = <0>;
695 qcom,remote-pid = <2>;
697 adsp_smp2p_out: master-kernel {
698 qcom,entry-name = "master-kernel";
699 #qcom,smem-state-cells = <1>;
702 adsp_smp2p_in: slave-kernel {
703 qcom,entry-name = "slave-kernel";
705 interrupt-controller;
706 #interrupt-cells = <2>;
710 smp2p-mpss {
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <1>;
721 modem_smp2p_out: master-kernel {
722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells = <1>;
726 modem_smp2p_in: slave-kernel {
727 qcom,entry-name = "slave-kernel";
729 interrupt-controller;
730 #interrupt-cells = <2>;
733 modem_smp2p_ipa_out: ipa-ap-to-modem {
734 qcom,entry-name = "ipa";
735 #qcom,smem-state-cells = <1>;
738 modem_smp2p_ipa_in: ipa-modem-to-ap {
739 qcom,entry-name = "ipa";
740 interrupt-controller;
741 #interrupt-cells = <2>;
744 modem_smp2p_wlan_in: wlan-wpss-to-ap {
745 qcom,entry-name = "wlan";
746 interrupt-controller;
747 #interrupt-cells = <2>;
751 smp2p-slpi {
759 qcom,local-pid = <0>;
760 qcom,remote-pid = <3>;
762 slpi_smp2p_out: master-kernel {
763 qcom,entry-name = "master-kernel";
764 #qcom,smem-state-cells = <1>;
767 slpi_smp2p_in: slave-kernel {
768 qcom,entry-name = "slave-kernel";
770 interrupt-controller;
771 #interrupt-cells = <2>;
776 compatible = "simple-bus";
777 #address-cells = <2>;
778 #size-cells = <2>;
780 dma-ranges = <0 0 0 0 0x10 0>;
782 gcc: clock-controller@100000 {
783 compatible = "qcom,gcc-sc8180x";
785 #clock-cells = <1>;
786 #reset-cells = <1>;
787 #power-domain-cells = <1>;
791 clock-names = "bi_tcxo",
794 power-domains = <&rpmhpd SC8180X_CX>;
798 compatible = "qcom,geni-se-qup";
802 clock-names = "m-ahb", "s-ahb";
803 #address-cells = <2>;
804 #size-cells = <2>;
810 compatible = "qcom,geni-i2c";
813 clock-names = "se";
818 interconnect-names = "qup-core", "qup-config", "qup-memory";
819 #address-cells = <1>;
820 #size-cells = <0>;
825 compatible = "qcom,geni-spi";
828 clock-names = "se";
832 interconnect-names = "qup-core", "qup-config";
833 #address-cells = <1>;
834 #size-cells = <0>;
839 compatible = "qcom,geni-uart";
842 clock-names = "se";
846 interconnect-names = "qup-core", "qup-config";
851 compatible = "qcom,geni-i2c";
854 clock-names = "se";
859 interconnect-names = "qup-core", "qup-config", "qup-memory";
860 #address-cells = <1>;
861 #size-cells = <0>;
866 compatible = "qcom,geni-spi";
869 clock-names = "se";
873 interconnect-names = "qup-core", "qup-config";
874 #address-cells = <1>;
875 #size-cells = <0>;
880 compatible = "qcom,geni-uart";
883 clock-names = "se";
887 interconnect-names = "qup-core", "qup-config";
892 compatible = "qcom,geni-i2c";
895 clock-names = "se";
900 interconnect-names = "qup-core", "qup-config", "qup-memory";
901 #address-cells = <1>;
902 #size-cells = <0>;
907 compatible = "qcom,geni-spi";
910 clock-names = "se";
914 interconnect-names = "qup-core", "qup-config";
915 #address-cells = <1>;
916 #size-cells = <0>;
921 compatible = "qcom,geni-uart";
924 clock-names = "se";
928 interconnect-names = "qup-core", "qup-config";
933 compatible = "qcom,geni-i2c";
936 clock-names = "se";
941 interconnect-names = "qup-core", "qup-config", "qup-memory";
942 #address-cells = <1>;
943 #size-cells = <0>;
948 compatible = "qcom,geni-spi";
951 clock-names = "se";
955 interconnect-names = "qup-core", "qup-config";
956 #address-cells = <1>;
957 #size-cells = <0>;
962 compatible = "qcom,geni-uart";
965 clock-names = "se";
969 interconnect-names = "qup-core", "qup-config";
974 compatible = "qcom,geni-i2c";
977 clock-names = "se";
982 interconnect-names = "qup-core", "qup-config", "qup-memory";
983 #address-cells = <1>;
984 #size-cells = <0>;
989 compatible = "qcom,geni-spi";
992 clock-names = "se";
996 interconnect-names = "qup-core", "qup-config";
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-uart";
1006 clock-names = "se";
1010 interconnect-names = "qup-core", "qup-config";
1015 compatible = "qcom,geni-i2c";
1018 clock-names = "se";
1023 interconnect-names = "qup-core", "qup-config", "qup-memory";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1030 compatible = "qcom,geni-spi";
1033 clock-names = "se";
1037 interconnect-names = "qup-core", "qup-config";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1044 compatible = "qcom,geni-uart";
1047 clock-names = "se";
1051 interconnect-names = "qup-core", "qup-config";
1056 compatible = "qcom,geni-i2c";
1059 clock-names = "se";
1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1071 compatible = "qcom,geni-spi";
1074 clock-names = "se";
1078 interconnect-names = "qup-core", "qup-config";
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1085 compatible = "qcom,geni-uart";
1088 clock-names = "se";
1092 interconnect-names = "qup-core", "qup-config";
1097 compatible = "qcom,geni-i2c";
1100 clock-names = "se";
1105 interconnect-names = "qup-core", "qup-config", "qup-memory";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1112 compatible = "qcom,geni-spi";
1115 clock-names = "se";
1119 interconnect-names = "qup-core", "qup-config";
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1126 compatible = "qcom,geni-uart";
1129 clock-names = "se";
1133 interconnect-names = "qup-core", "qup-config";
1139 compatible = "qcom,geni-se-qup";
1143 clock-names = "m-ahb", "s-ahb";
1144 #address-cells = <2>;
1145 #size-cells = <2>;
1151 compatible = "qcom,geni-i2c";
1154 clock-names = "se";
1159 interconnect-names = "qup-core", "qup-config", "qup-memory";
1160 #address-cells = <1>;
1161 #size-cells = <0>;
1166 compatible = "qcom,geni-spi";
1169 clock-names = "se";
1173 interconnect-names = "qup-core", "qup-config";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1180 compatible = "qcom,geni-uart";
1183 clock-names = "se";
1187 interconnect-names = "qup-core", "qup-config";
1192 compatible = "qcom,geni-i2c";
1195 clock-names = "se";
1200 interconnect-names = "qup-core", "qup-config", "qup-memory";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1207 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1214 interconnect-names = "qup-core", "qup-config";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "qcom,geni-debug-uart";
1224 clock-names = "se";
1228 interconnect-names = "qup-core", "qup-config";
1233 compatible = "qcom,geni-i2c";
1236 clock-names = "se";
1241 interconnect-names = "qup-core", "qup-config", "qup-memory";
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1248 compatible = "qcom,geni-spi";
1251 clock-names = "se";
1255 interconnect-names = "qup-core", "qup-config";
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1262 compatible = "qcom,geni-uart";
1265 clock-names = "se";
1269 interconnect-names = "qup-core", "qup-config";
1274 compatible = "qcom,geni-i2c";
1277 clock-names = "se";
1282 interconnect-names = "qup-core", "qup-config", "qup-memory";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1289 compatible = "qcom,geni-spi";
1292 clock-names = "se";
1296 interconnect-names = "qup-core", "qup-config";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1303 compatible = "qcom,geni-uart";
1306 clock-names = "se";
1310 interconnect-names = "qup-core", "qup-config";
1315 compatible = "qcom,geni-i2c";
1318 clock-names = "se";
1323 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1330 compatible = "qcom,geni-spi";
1333 clock-names = "se";
1337 interconnect-names = "qup-core", "qup-config";
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1344 compatible = "qcom,geni-uart";
1347 clock-names = "se";
1351 interconnect-names = "qup-core", "qup-config";
1356 compatible = "qcom,geni-i2c";
1359 clock-names = "se";
1364 interconnect-names = "qup-core", "qup-config", "qup-memory";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1371 compatible = "qcom,geni-spi";
1374 clock-names = "se";
1378 interconnect-names = "qup-core", "qup-config";
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1385 compatible = "qcom,geni-uart";
1388 clock-names = "se";
1392 interconnect-names = "qup-core", "qup-config";
1398 compatible = "qcom,geni-se-qup";
1402 clock-names = "m-ahb", "s-ahb";
1403 #address-cells = <2>;
1404 #size-cells = <2>;
1410 compatible = "qcom,geni-i2c";
1413 clock-names = "se";
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1419 #address-cells = <1>;
1420 #size-cells = <0>;
1425 compatible = "qcom,geni-spi";
1428 clock-names = "se";
1432 interconnect-names = "qup-core", "qup-config";
1433 #address-cells = <1>;
1434 #size-cells = <0>;
1439 compatible = "qcom,geni-uart";
1442 clock-names = "se";
1446 interconnect-names = "qup-core", "qup-config";
1451 compatible = "qcom,geni-i2c";
1454 clock-names = "se";
1459 interconnect-names = "qup-core", "qup-config", "qup-memory";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1466 compatible = "qcom,geni-spi";
1469 clock-names = "se";
1473 interconnect-names = "qup-core", "qup-config";
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1480 compatible = "qcom,geni-uart";
1483 clock-names = "se";
1487 interconnect-names = "qup-core", "qup-config";
1492 compatible = "qcom,geni-i2c";
1495 clock-names = "se";
1500 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1507 compatible = "qcom,geni-spi";
1510 clock-names = "se";
1514 interconnect-names = "qup-core", "qup-config";
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1521 compatible = "qcom,geni-uart";
1524 clock-names = "se";
1528 interconnect-names = "qup-core", "qup-config";
1533 compatible = "qcom,geni-i2c";
1536 clock-names = "se";
1541 interconnect-names = "qup-core", "qup-config", "qup-memory";
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1548 compatible = "qcom,geni-spi";
1551 clock-names = "se";
1555 interconnect-names = "qup-core", "qup-config";
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1562 compatible = "qcom,geni-uart";
1565 clock-names = "se";
1569 interconnect-names = "qup-core", "qup-config";
1574 compatible = "qcom,geni-i2c";
1577 clock-names = "se";
1582 interconnect-names = "qup-core", "qup-config", "qup-memory";
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1589 compatible = "qcom,geni-spi";
1592 clock-names = "se";
1596 interconnect-names = "qup-core", "qup-config";
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1603 compatible = "qcom,geni-uart";
1606 clock-names = "se";
1610 interconnect-names = "qup-core", "qup-config";
1615 compatible = "qcom,geni-i2c";
1618 clock-names = "se";
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1630 compatible = "qcom,geni-spi";
1633 clock-names = "se";
1637 interconnect-names = "qup-core", "qup-config";
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1644 compatible = "qcom,geni-uart";
1647 clock-names = "se";
1651 interconnect-names = "qup-core", "qup-config";
1657 compatible = "qcom,sc8180x-config-noc";
1659 #interconnect-cells = <2>;
1660 qcom,bcm-voters = <&apps_bcm_voter>;
1664 compatible = "qcom,sc8180x-system-noc";
1666 #interconnect-cells = <2>;
1667 qcom,bcm-voters = <&apps_bcm_voter>;
1671 compatible = "qcom,sc8180x-aggre1-noc";
1673 #interconnect-cells = <2>;
1674 qcom,bcm-voters = <&apps_bcm_voter>;
1678 compatible = "qcom,sc8180x-aggre2-noc";
1680 #interconnect-cells = <2>;
1681 qcom,bcm-voters = <&apps_bcm_voter>;
1685 compatible = "qcom,sc8180x-compute-noc";
1687 #interconnect-cells = <2>;
1688 qcom,bcm-voters = <&apps_bcm_voter>;
1692 compatible = "qcom,sc8180x-mmss-noc";
1694 #interconnect-cells = <2>;
1695 qcom,bcm-voters = <&apps_bcm_voter>;
1699 compatible = "qcom,pcie-sc8180x";
1705 reg-names = "parf",
1711 linux,pci-domain = <0>;
1712 bus-range = <0x00 0xff>;
1713 num-lanes = <2>;
1715 #address-cells = <3>;
1716 #size-cells = <2>;
1729 interrupt-names = "msi0",
1737 #interrupt-cells = <1>;
1738 interrupt-map-mask = <0 0 0 0x7>;
1739 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1752 clock-names = "pipe",
1761 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1762 assigned-clock-rates = <19200000>;
1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1768 reset-names = "pci";
1770 power-domains = <&gcc PCIE_0_GDSC>;
1774 interconnect-names = "pcie-mem", "cpu-pcie";
1777 phy-names = "pciephy";
1778 dma-coherent;
1785 bus-range = <0x01 0xff>;
1787 #address-cells = <3>;
1788 #size-cells = <2>;
1794 compatible = "qcom,sc8180x-qmp-pcie-phy";
1801 clock-names = "aux",
1806 #clock-cells = <0>;
1807 clock-output-names = "pcie_0_pipe_clk";
1808 #phy-cells = <0>;
1811 reset-names = "phy";
1813 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1814 assigned-clock-rates = <100000000>;
1820 compatible = "qcom,pcie-sc8180x";
1826 reg-names = "parf",
1832 linux,pci-domain = <3>;
1833 bus-range = <0x00 0xff>;
1834 num-lanes = <2>;
1836 #address-cells = <3>;
1837 #size-cells = <2>;
1850 interrupt-names = "msi0",
1858 #interrupt-cells = <1>;
1859 interrupt-map-mask = <0 0 0 0x7>;
1860 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1873 clock-names = "pipe",
1882 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1883 assigned-clock-rates = <19200000>;
1885 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1889 reset-names = "pci";
1891 power-domains = <&gcc PCIE_3_GDSC>;
1895 interconnect-names = "pcie-mem", "cpu-pcie";
1898 phy-names = "pciephy";
1899 dma-coherent;
1906 bus-range = <0x01 0xff>;
1908 #address-cells = <3>;
1909 #size-cells = <2>;
1915 compatible = "qcom,sc8180x-qmp-pcie-phy";
1922 clock-names = "aux",
1927 #clock-cells = <0>;
1928 clock-output-names = "pcie_3_pipe_clk";
1930 #phy-cells = <0>;
1933 reset-names = "phy";
1935 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1936 assigned-clock-rates = <100000000>;
1942 compatible = "qcom,pcie-sc8180x";
1948 reg-names = "parf",
1954 linux,pci-domain = <1>;
1955 bus-range = <0x00 0xff>;
1956 num-lanes = <2>;
1958 #address-cells = <3>;
1959 #size-cells = <2>;
1972 interrupt-names = "msi0",
1980 #interrupt-cells = <1>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1995 clock-names = "pipe",
2004 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2005 assigned-clock-rates = <19200000>;
2007 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2011 reset-names = "pci";
2013 power-domains = <&gcc PCIE_1_GDSC>;
2017 interconnect-names = "pcie-mem", "cpu-pcie";
2020 phy-names = "pciephy";
2021 dma-coherent;
2028 bus-range = <0x01 0xff>;
2030 #address-cells = <3>;
2031 #size-cells = <2>;
2037 compatible = "qcom,sc8180x-qmp-pcie-phy";
2044 clock-names = "aux",
2049 #clock-cells = <0>;
2050 clock-output-names = "pcie_1_pipe_clk";
2052 #phy-cells = <0>;
2055 reset-names = "phy";
2057 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2058 assigned-clock-rates = <100000000>;
2064 compatible = "qcom,pcie-sc8180x";
2070 reg-names = "parf",
2076 linux,pci-domain = <2>;
2077 bus-range = <0x00 0xff>;
2078 num-lanes = <4>;
2080 #address-cells = <3>;
2081 #size-cells = <2>;
2094 interrupt-names = "msi0",
2102 #interrupt-cells = <1>;
2103 interrupt-map-mask = <0 0 0 0x7>;
2104 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2117 clock-names = "pipe",
2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2127 assigned-clock-rates = <19200000>;
2129 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2133 reset-names = "pci";
2135 power-domains = <&gcc PCIE_2_GDSC>;
2139 interconnect-names = "pcie-mem", "cpu-pcie";
2142 phy-names = "pciephy";
2143 dma-coherent;
2150 bus-range = <0x01 0xff>;
2152 #address-cells = <3>;
2153 #size-cells = <2>;
2159 compatible = "qcom,sc8180x-qmp-pcie-phy";
2166 clock-names = "aux",
2171 #clock-cells = <0>;
2172 clock-output-names = "pcie_2_pipe_clk";
2174 #phy-cells = <0>;
2177 reset-names = "phy";
2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2180 assigned-clock-rates = <100000000>;
2186 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2187 "jedec,ufs-2.0";
2191 phy-names = "ufsphy";
2192 lanes-per-direction = <2>;
2193 #reset-cells = <1>;
2195 reset-names = "rst";
2207 clock-names = "core_clk",
2215 freq-table-hz = <37500000 300000000>,
2224 power-domains = <&gcc UFS_PHY_GDSC>;
2230 interconnect-names = "ufs-ddr", "cpu-ufs";
2235 ufs_mem_phy: phy-wrapper@1d87000 {
2236 compatible = "qcom,sc8180x-qmp-ufs-phy";
2242 clock-names = "ref",
2247 reset-names = "ufsphy";
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2251 #phy-cells = <0>;
2257 compatible = "qcom,tcsr-mutex";
2259 #hwlock-cells = <1>;
2263 compatible = "qcom,adreno-680.1", "qcom,adreno";
2266 reg-names = "kgsl_3d0_reg_memory";
2272 operating-points-v2 = <&gpu_opp_table>;
2275 interconnect-names = "gfx-mem";
2278 #cooling-cells = <2>;
2282 gpu_opp_table: opp-table {
2283 compatible = "operating-points-v2";
2285 opp-514000000 {
2286 opp-hz = /bits/ 64 <514000000>;
2287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2290 opp-500000000 {
2291 opp-hz = /bits/ 64 <500000000>;
2292 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2295 opp-461000000 {
2296 opp-hz = /bits/ 64 <461000000>;
2297 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2300 opp-405000000 {
2301 opp-hz = /bits/ 64 <405000000>;
2302 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2305 opp-315000000 {
2306 opp-hz = /bits/ 64 <315000000>;
2307 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2310 opp-256000000 {
2311 opp-hz = /bits/ 64 <256000000>;
2312 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2315 opp-177000000 {
2316 opp-hz = /bits/ 64 <177000000>;
2317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2323 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2328 reg-names = "gmu",
2334 interrupt-names = "hfi", "gmu";
2341 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2343 power-domains = <&gpucc GPU_CX_GDSC>,
2345 power-domain-names = "cx", "gx";
2349 operating-points-v2 = <&gmu_opp_table>;
2351 gmu_opp_table: opp-table {
2352 compatible = "operating-points-v2";
2354 opp-200000000 {
2355 opp-hz = /bits/ 64 <200000000>;
2356 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2359 opp-500000000 {
2360 opp-hz = /bits/ 64 <500000000>;
2361 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2366 gpucc: clock-controller@2c90000 {
2367 compatible = "qcom,sc8180x-gpucc";
2372 clock-names = "bi_tcxo",
2375 #clock-cells = <1>;
2376 #reset-cells = <1>;
2377 #power-domain-cells = <1>;
2381 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2382 "qcom,smmu-500", "arm,mmu-500";
2384 #iommu-cells = <2>;
2385 #global-interrupts = <1>;
2398 clock-names = "ahb", "bus", "iface";
2400 power-domains = <&gpucc GPU_CX_GDSC>;
2404 compatible = "qcom,sc8180x-tlmm";
2408 reg-names = "west", "east", "south";
2410 gpio-controller;
2411 #gpio-cells = <2>;
2412 interrupt-controller;
2413 #interrupt-cells = <2>;
2414 gpio-ranges = <&tlmm 0 0 191>;
2415 wakeup-parent = <&pdc>;
2419 compatible = "qcom,sc8180x-mpss-pas";
2422 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2428 interrupt-names = "wdog", "fatal", "ready", "handover",
2429 "stop-ack", "shutdown-ack";
2432 clock-names = "xo";
2434 power-domains = <&rpmhpd SC8180X_CX>,
2436 power-domain-names = "cx", "mss";
2440 qcom,smem-states = <&modem_smp2p_out 0>;
2441 qcom,smem-state-names = "stop";
2443 glink-edge {
2446 qcom,remote-pid = <1>;
2452 compatible = "qcom,sc8180x-cdsp-pas";
2455 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2460 interrupt-names = "wdog", "fatal", "ready",
2461 "handover", "stop-ack";
2464 clock-names = "xo";
2466 power-domains = <&rpmhpd SC8180X_CX>;
2467 power-domain-names = "cx";
2471 qcom,smem-states = <&cdsp_smp2p_out 0>;
2472 qcom,smem-state-names = "stop";
2476 glink-edge {
2479 qcom,remote-pid = <5>;
2485 compatible = "qcom,sc8180x-usb-hs-phy",
2486 "qcom,usb-snps-hs-7nm-phy";
2489 clock-names = "ref";
2492 #phy-cells = <0>;
2498 compatible = "qcom,sc8180x-usb-hs-phy",
2499 "qcom,usb-snps-hs-7nm-phy";
2502 clock-names = "ref";
2505 #phy-cells = <0>;
2511 compatible = "qcom,sc8180x-usb-hs-phy",
2512 "qcom,usb-snps-hs-7nm-phy";
2514 #phy-cells = <0>;
2517 clock-names = "ref";
2525 compatible = "qcom,sc8180x-usb-hs-phy",
2526 "qcom,usb-snps-hs-7nm-phy";
2528 #phy-cells = <0>;
2531 clock-names = "ref";
2539 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2546 clock-names = "aux",
2553 reset-names = "phy", "common";
2555 #clock-cells = <1>;
2556 #phy-cells = <1>;
2561 #address-cells = <1>;
2562 #size-cells = <0>;
2574 remote-endpoint = <&usb_prim_dwc3_ss>;
2587 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2594 clock-names = "aux",
2601 reset-names = "phy", "phy_phy";
2603 power-domains = <&gcc USB30_MP_GDSC>;
2605 #clock-cells = <0>;
2606 clock-output-names = "usb2_phy0_pipe_clk";
2608 #phy-cells = <0>;
2614 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2621 clock-names = "aux",
2628 reset-names = "phy", "phy_phy";
2630 power-domains = <&gcc USB30_MP_GDSC>;
2632 #clock-cells = <0>;
2633 clock-output-names = "usb2_phy1_pipe_clk";
2635 #phy-cells = <0>;
2641 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2648 clock-names = "aux",
2654 reset-names = "phy", "common";
2656 #clock-cells = <1>;
2657 #phy-cells = <1>;
2662 #address-cells = <1>;
2663 #size-cells = <0>;
2675 remote-endpoint = <&usb_sec_dwc3_ss>;
2687 system-cache-controller@9200000 {
2688 compatible = "qcom,sc8180x-llcc";
2694 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2701 compatible = "qcom,sc8180x-gem-noc";
2703 #interconnect-cells = <2>;
2704 qcom,bcm-voters = <&apps_bcm_voter>;
2708 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
2710 #address-cells = <2>;
2711 #size-cells = <2>;
2713 dma-ranges;
2721 clock-names = "cfg_noc",
2730 interconnect-names = "usb-ddr", "apps-usb";
2732 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2734 assigned-clock-rates = <19200000>, <200000000>;
2736 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
2746 interrupt-names = "pwr_event_1", "pwr_event_2",
2752 power-domains = <&gcc USB30_MP_GDSC>;
2769 phy-names = "usb2-0",
2770 "usb3-0",
2771 "usb2-1",
2772 "usb3-1";
2778 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2780 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2785 interrupt-names = "pwr_event",
2797 clock-names = "cfg_noc",
2804 power-domains = <&gcc USB30_PRIM_GDSC>;
2808 interconnect-names = "usb-ddr", "apps-usb";
2810 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2812 assigned-clock-rates = <19200000>, <200000000>;
2814 #address-cells = <2>;
2815 #size-cells = <2>;
2817 dma-ranges;
2829 phy-names = "usb2-phy", "usb3-phy";
2832 #address-cells = <1>;
2833 #size-cells = <0>;
2846 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
2854 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2863 clock-names = "cfg_noc",
2870 power-domains = <&gcc USB30_SEC_GDSC>;
2872 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2877 interrupt-names = "pwr_event",
2883 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2885 assigned-clock-rates = <19200000>, <200000000>;
2889 interconnect-names = "usb-ddr", "apps-usb";
2891 #address-cells = <2>;
2892 #size-cells = <2>;
2894 dma-ranges;
2906 phy-names = "usb2-phy", "usb3-phy";
2909 #address-cells = <1>;
2910 #size-cells = <0>;
2923 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
2931 compatible = "qcom,sc8180x-mdss";
2933 reg-names = "mdss";
2935 power-domains = <&dispcc MDSS_GDSC>;
2941 clock-names = "iface",
2949 interrupt-controller;
2950 #interrupt-cells = <1>;
2958 interconnect-names = "mdp0-mem",
2959 "mdp1-mem",
2960 "cpu-cfg";
2964 #address-cells = <2>;
2965 #size-cells = <2>;
2971 compatible = "qcom,sc8180x-dpu";
2974 reg-names = "mdp", "vbif";
2982 clock-names = "iface",
2989 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2990 assigned-clock-rates = <19200000>;
2992 operating-points-v2 = <&mdp_opp_table>;
2993 power-domains = <&rpmhpd SC8180X_MMCX>;
2995 interrupt-parent = <&mdss>;
2999 #address-cells = <1>;
3000 #size-cells = <0>;
3005 remote-endpoint = <&dp0_in>;
3012 remote-endpoint = <&mdss_dsi0_in>;
3019 remote-endpoint = <&mdss_dsi1_in>;
3026 remote-endpoint = <&dp1_in>;
3033 remote-endpoint = <&edp_in>;
3038 mdp_opp_table: opp-table {
3039 compatible = "operating-points-v2";
3041 opp-200000000 {
3042 opp-hz = /bits/ 64 <200000000>;
3043 required-opps = <&rpmhpd_opp_low_svs>;
3046 opp-300000000 {
3047 opp-hz = /bits/ 64 <300000000>;
3048 required-opps = <&rpmhpd_opp_svs>;
3051 opp-345000000 {
3052 opp-hz = /bits/ 64 <345000000>;
3053 required-opps = <&rpmhpd_opp_svs_l1>;
3056 opp-460000000 {
3057 opp-hz = /bits/ 64 <460000000>;
3058 required-opps = <&rpmhpd_opp_nom>;
3064 compatible = "qcom,mdss-dsi-ctrl";
3066 reg-names = "dsi_ctrl";
3068 interrupt-parent = <&mdss>;
3077 clock-names = "byte",
3084 operating-points-v2 = <&dsi_opp_table>;
3085 power-domains = <&rpmhpd SC8180X_MMCX>;
3088 phy-names = "dsi";
3093 #address-cells = <1>;
3094 #size-cells = <0>;
3099 remote-endpoint = <&dpu_intf1_out>;
3110 dsi_opp_table: opp-table {
3111 compatible = "operating-points-v2";
3113 opp-187500000 {
3114 opp-hz = /bits/ 64 <187500000>;
3115 required-opps = <&rpmhpd_opp_low_svs>;
3118 opp-300000000 {
3119 opp-hz = /bits/ 64 <300000000>;
3120 required-opps = <&rpmhpd_opp_svs>;
3123 opp-358000000 {
3124 opp-hz = /bits/ 64 <358000000>;
3125 required-opps = <&rpmhpd_opp_svs_l1>;
3130 mdss_dsi0_phy: dsi-phy@ae94400 {
3131 compatible = "qcom,dsi-phy-7nm";
3135 reg-names = "dsi_phy",
3139 #clock-cells = <1>;
3140 #phy-cells = <0>;
3144 clock-names = "iface", "ref";
3150 compatible = "qcom,mdss-dsi-ctrl";
3152 reg-names = "dsi_ctrl";
3154 interrupt-parent = <&mdss>;
3163 clock-names = "byte",
3170 operating-points-v2 = <&dsi_opp_table>;
3171 power-domains = <&rpmhpd SC8180X_MMCX>;
3174 phy-names = "dsi";
3179 #address-cells = <1>;
3180 #size-cells = <0>;
3185 remote-endpoint = <&dpu_intf2_out>;
3197 mdss_dsi1_phy: dsi-phy@ae96400 {
3198 compatible = "qcom,dsi-phy-7nm";
3202 reg-names = "dsi_phy",
3206 #clock-cells = <1>;
3207 #phy-cells = <0>;
3211 clock-names = "iface", "ref";
3216 mdss_dp0: displayport-controller@ae90000 {
3217 compatible = "qcom,sc8180x-dp";
3223 interrupt-parent = <&mdss>;
3230 clock-names = "core_iface",
3236 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3238 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3242 phy-names = "dp";
3244 #sound-dai-cells = <0>;
3246 operating-points-v2 = <&dp0_opp_table>;
3247 power-domains = <&rpmhpd SC8180X_MMCX>;
3252 #address-cells = <1>;
3253 #size-cells = <0>;
3258 remote-endpoint = <&dpu_intf0_out>;
3269 dp0_opp_table: opp-table {
3270 compatible = "operating-points-v2";
3272 opp-160000000 {
3273 opp-hz = /bits/ 64 <160000000>;
3274 required-opps = <&rpmhpd_opp_low_svs>;
3277 opp-270000000 {
3278 opp-hz = /bits/ 64 <270000000>;
3279 required-opps = <&rpmhpd_opp_svs>;
3282 opp-540000000 {
3283 opp-hz = /bits/ 64 <540000000>;
3284 required-opps = <&rpmhpd_opp_svs_l1>;
3287 opp-810000000 {
3288 opp-hz = /bits/ 64 <810000000>;
3289 required-opps = <&rpmhpd_opp_nom>;
3294 mdss_dp1: displayport-controller@ae98000 {
3295 compatible = "qcom,sc8180x-dp";
3301 interrupt-parent = <&mdss>;
3308 clock-names = "core_iface",
3314 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3316 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3320 phy-names = "dp";
3322 #sound-dai-cells = <0>;
3324 operating-points-v2 = <&dp0_opp_table>;
3325 power-domains = <&rpmhpd SC8180X_MMCX>;
3330 #address-cells = <1>;
3331 #size-cells = <0>;
3336 remote-endpoint = <&dpu_intf4_out>;
3347 dp1_opp_table: opp-table {
3348 compatible = "operating-points-v2";
3350 opp-160000000 {
3351 opp-hz = /bits/ 64 <160000000>;
3352 required-opps = <&rpmhpd_opp_low_svs>;
3355 opp-270000000 {
3356 opp-hz = /bits/ 64 <270000000>;
3357 required-opps = <&rpmhpd_opp_svs>;
3360 opp-540000000 {
3361 opp-hz = /bits/ 64 <540000000>;
3362 required-opps = <&rpmhpd_opp_svs_l1>;
3365 opp-810000000 {
3366 opp-hz = /bits/ 64 <810000000>;
3367 required-opps = <&rpmhpd_opp_nom>;
3372 mdss_edp: displayport-controller@ae9a000 {
3373 compatible = "qcom,sc8180x-edp";
3378 interrupt-parent = <&mdss>;
3385 clock-names = "core_iface",
3391 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3393 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3396 phy-names = "dp";
3398 operating-points-v2 = <&edp_opp_table>;
3399 power-domains = <&rpmhpd SC8180X_MMCX>;
3404 #address-cells = <1>;
3405 #size-cells = <0>;
3410 remote-endpoint = <&dpu_intf5_out>;
3415 edp_opp_table: opp-table {
3416 compatible = "operating-points-v2";
3418 opp-160000000 {
3419 opp-hz = /bits/ 64 <160000000>;
3420 required-opps = <&rpmhpd_opp_low_svs>;
3423 opp-270000000 {
3424 opp-hz = /bits/ 64 <270000000>;
3425 required-opps = <&rpmhpd_opp_svs>;
3428 opp-540000000 {
3429 opp-hz = /bits/ 64 <540000000>;
3430 required-opps = <&rpmhpd_opp_svs_l1>;
3433 opp-810000000 {
3434 opp-hz = /bits/ 64 <810000000>;
3435 required-opps = <&rpmhpd_opp_nom>;
3442 compatible = "qcom,sc8180x-edp-phy";
3450 clock-names = "aux", "cfg_ahb";
3452 power-domains = <&rpmhpd SC8180X_MX>;
3454 #clock-cells = <1>;
3455 #phy-cells = <0>;
3458 dispcc: clock-controller@af00000 {
3459 compatible = "qcom,sc8180x-dispcc";
3472 clock-names = "bi_tcxo",
3483 power-domains = <&rpmhpd SC8180X_MMCX>;
3484 required-opps = <&rpmhpd_opp_low_svs>;
3485 #clock-cells = <1>;
3486 #reset-cells = <1>;
3487 #power-domain-cells = <1>;
3490 pdc: interrupt-controller@b220000 {
3491 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3493 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3494 #interrupt-cells = <2>;
3495 interrupt-parent = <&intc>;
3496 interrupt-controller;
3499 tsens0: thermal-sensor@c263000 {
3500 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3506 interrupt-names = "uplow", "critical";
3507 #thermal-sensor-cells = <1>;
3510 tsens1: thermal-sensor@c265000 {
3511 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3517 interrupt-names = "uplow", "critical";
3518 #thermal-sensor-cells = <1>;
3521 aoss_qmp: power-controller@c300000 {
3522 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3527 #clock-cells = <0>;
3531 compatible = "qcom,rpmh-stats";
3536 compatible = "qcom,spmi-pmic-arb";
3542 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3543 interrupt-names = "periph_irq";
3547 #address-cells = <2>;
3548 #size-cells = <0>;
3549 interrupt-controller;
3550 #interrupt-cells = <4>;
3554 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3556 #iommu-cells = <2>;
3557 #global-interrupts = <1>;
3669 compatible = "qcom,sc8180x-adsp-pas";
3672 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3677 interrupt-names = "wdog", "fatal", "ready",
3678 "handover", "stop-ack";
3681 clock-names = "xo";
3683 power-domains = <&rpmhpd SC8180X_CX>;
3684 power-domain-names = "cx";
3688 qcom,smem-states = <&adsp_smp2p_out 0>;
3689 qcom,smem-state-names = "stop";
3693 remoteproc_adsp_glink: glink-edge {
3696 qcom,remote-pid = <2>;
3701 intc: interrupt-controller@17a00000 {
3702 compatible = "arm,gic-v3";
3703 interrupt-controller;
3704 #interrupt-cells = <3>;
3708 #redistributor-regions = <1>;
3709 redistributor-stride = <0 0x20000>;
3713 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3715 #mbox-cells = <1>;
3719 compatible = "arm,armv7-timer-mem";
3722 #address-cells = <1>;
3723 #size-cells = <1>;
3729 frame-number = <0>;
3736 frame-number = <1>;
3743 frame-number = <2>;
3750 frame-number = <3>;
3757 frame-number = <4>;
3764 frame-number = <5>;
3771 frame-number = <6>;
3778 compatible = "qcom,rpmh-rsc";
3782 reg-names = "drv-0", "drv-1", "drv-2";
3786 qcom,tcs-offset = <0xd00>;
3787 qcom,drv-id = <2>;
3788 qcom,tcs-config = <ACTIVE_TCS 2>,
3793 power-domains = <&CLUSTER_PD>;
3795 apps_bcm_voter: bcm-voter {
3796 compatible = "qcom,bcm-voter";
3799 rpmhcc: clock-controller {
3800 compatible = "qcom,sc8180x-rpmh-clk";
3801 #clock-cells = <1>;
3802 clock-names = "xo";
3806 rpmhpd: power-controller {
3807 compatible = "qcom,sc8180x-rpmhpd";
3808 #power-domain-cells = <1>;
3809 operating-points-v2 = <&rpmhpd_opp_table>;
3811 rpmhpd_opp_table: opp-table {
3812 compatible = "operating-points-v2";
3815 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3819 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3823 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3827 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3831 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3835 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3839 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3843 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3847 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3851 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3858 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3862 clock-names = "xo", "alternate";
3864 #interconnect-cells = <1>;
3868 compatible = "qcom,sc8180x-lmh";
3872 qcom,lmh-temp-arm-millicelsius = <65000>;
3873 qcom,lmh-temp-low-millicelsius = <94500>;
3874 qcom,lmh-temp-high-millicelsius = <95000>;
3875 interrupt-controller;
3876 #interrupt-cells = <1>;
3880 compatible = "qcom,sc8180x-lmh";
3884 qcom,lmh-temp-arm-millicelsius = <65000>;
3885 qcom,lmh-temp-low-millicelsius = <94500>;
3886 qcom,lmh-temp-high-millicelsius = <95000>;
3887 interrupt-controller;
3888 #interrupt-cells = <1>;
3892 compatible = "qcom,cpufreq-hw";
3894 reg-names = "freq-domain0", "freq-domain1";
3897 clock-names = "xo", "alternate";
3899 #freq-domain-cells = <1>;
3900 #clock-cells = <1>;
3904 compatible = "qcom,wcn3990-wifi";
3906 reg-names = "membase";
3907 clock-names = "cxo_ref_clk_pin";
3922 qcom,msa-fixed-perm;
3927 thermal-zones {
3928 cpu0-thermal {
3929 polling-delay-passive = <250>;
3931 thermal-sensors = <&tsens0 1>;
3934 cpu-crit {
3942 cpu1-thermal {
3943 polling-delay-passive = <250>;
3945 thermal-sensors = <&tsens0 2>;
3948 cpu-crit {
3956 cpu2-thermal {
3957 polling-delay-passive = <250>;
3959 thermal-sensors = <&tsens0 3>;
3962 cpu-crit {
3970 cpu3-thermal {
3971 polling-delay-passive = <250>;
3973 thermal-sensors = <&tsens0 4>;
3976 cpu-crit {
3984 cpu4-top-thermal {
3985 polling-delay-passive = <250>;
3987 thermal-sensors = <&tsens0 7>;
3990 cpu-crit {
3998 cpu5-top-thermal {
3999 polling-delay-passive = <250>;
4001 thermal-sensors = <&tsens0 8>;
4004 cpu-crit {
4012 cpu6-top-thermal {
4013 polling-delay-passive = <250>;
4015 thermal-sensors = <&tsens0 9>;
4018 cpu-crit {
4026 cpu7-top-thermal {
4027 polling-delay-passive = <250>;
4029 thermal-sensors = <&tsens0 10>;
4032 cpu-crit {
4040 cpu4-bottom-thermal {
4041 polling-delay-passive = <250>;
4043 thermal-sensors = <&tsens0 11>;
4046 cpu-crit {
4054 cpu5-bottom-thermal {
4055 polling-delay-passive = <250>;
4057 thermal-sensors = <&tsens0 12>;
4060 cpu-crit {
4068 cpu6-bottom-thermal {
4069 polling-delay-passive = <250>;
4071 thermal-sensors = <&tsens0 13>;
4074 cpu-crit {
4082 cpu7-bottom-thermal {
4083 polling-delay-passive = <250>;
4085 thermal-sensors = <&tsens0 14>;
4088 cpu-crit {
4096 aoss0-thermal {
4097 polling-delay-passive = <250>;
4099 thermal-sensors = <&tsens0 0>;
4102 trip-point0 {
4110 cluster0-thermal {
4111 polling-delay-passive = <250>;
4113 thermal-sensors = <&tsens0 5>;
4116 cluster-crit {
4124 cluster1-thermal {
4125 polling-delay-passive = <250>;
4127 thermal-sensors = <&tsens0 6>;
4130 cluster-crit {
4138 gpu-top-thermal {
4139 polling-delay-passive = <250>;
4141 thermal-sensors = <&tsens0 15>;
4143 cooling-maps {
4146 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4151 gpu_top_alert0: trip-point0 {
4157 trip-point1 {
4163 trip-point2 {
4171 aoss1-thermal {
4172 polling-delay-passive = <250>;
4174 thermal-sensors = <&tsens1 0>;
4177 trip-point0 {
4185 wlan-thermal {
4186 polling-delay-passive = <250>;
4188 thermal-sensors = <&tsens1 1>;
4191 trip-point0 {
4199 video-thermal {
4200 polling-delay-passive = <250>;
4202 thermal-sensors = <&tsens1 2>;
4205 trip-point0 {
4213 mem-thermal {
4214 polling-delay-passive = <250>;
4216 thermal-sensors = <&tsens1 3>;
4219 trip-point0 {
4227 q6-hvx-thermal {
4228 polling-delay-passive = <250>;
4230 thermal-sensors = <&tsens1 4>;
4233 trip-point0 {
4241 camera-thermal {
4242 polling-delay-passive = <250>;
4244 thermal-sensors = <&tsens1 5>;
4247 trip-point0 {
4255 compute-thermal {
4256 polling-delay-passive = <250>;
4258 thermal-sensors = <&tsens1 6>;
4261 trip-point0 {
4269 mdm-dsp-thermal {
4270 polling-delay-passive = <250>;
4272 thermal-sensors = <&tsens1 7>;
4275 trip-point0 {
4283 npu-thermal {
4284 polling-delay-passive = <250>;
4286 thermal-sensors = <&tsens1 8>;
4289 trip-point0 {
4297 gpu-bottom-thermal {
4298 polling-delay-passive = <250>;
4300 thermal-sensors = <&tsens1 11>;
4302 cooling-maps {
4305 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4310 gpu_bottom_alert0: trip-point0 {
4316 trip-point1 {
4322 trip-point2 {
4332 compatible = "arm,armv8-timer";