Lines Matching +full:0 +full:x18200000
29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
59 clocks = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
113 clocks = <&cpufreq_hw 0>;
126 reg = <0x0 0x300>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
137 clocks = <&cpufreq_hw 0>;
150 reg = <0x0 0x400>;
174 reg = <0x0 0x500>;
198 reg = <0x0 0x600>;
222 reg = <0x0 0x700>;
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
284 arm,psci-suspend-param = <0x40000004>;
291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
293 arm,psci-suspend-param = <0x40000004>;
302 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
304 arm,psci-suspend-param = <0x41000044>;
312 arm,psci-suspend-param = <0x4100a344>;
532 reg = <0x0 0x80000000 0x0 0x0>;
545 #power-domain-cells = <0>;
551 #power-domain-cells = <0>;
557 #power-domain-cells = <0>;
563 #power-domain-cells = <0>;
569 #power-domain-cells = <0>;
575 #power-domain-cells = <0>;
581 #power-domain-cells = <0>;
587 #power-domain-cells = <0>;
593 #power-domain-cells = <0>;
604 reg = <0x0 0x85700000 0x0 0x600000>;
609 reg = <0x0 0x85d00000 0x0 0x140000>;
614 reg = <0x0 0x85f00000 0x0 0x20000>;
620 reg = <0x0 0x85f20000 0x0 0x20000>;
625 reg = <0x0 0x85f40000 0x0 0x10000>;
631 reg = <0x0 0x86000000 0x0 0x200000>;
637 reg = <0x0 0x86200000 0x0 0x3900000>;
642 reg = <0x0 0x89b00000 0x0 0x1c00000>;
647 reg = <0x0 0x9d400000 0x0 0x1000000>;
652 reg = <0x0 0x9e400000 0x0 0x1400000>;
657 reg = <0x0 0x9f800000 0x0 0x800000>;
670 qcom,local-pid = <0>;
694 qcom,local-pid = <0>;
718 qcom,local-pid = <0>;
759 qcom,local-pid = <0>;
775 soc: soc@0 {
779 ranges = <0 0 0 0 0x10 0>;
780 dma-ranges = <0 0 0 0 0x10 0>;
784 reg = <0x0 0x00100000 0x0 0x1f0000>;
799 reg = <0 0x008c0000 0 0x6000>;
806 iommus = <&apps_smmu 0x4c3 0>;
811 reg = <0 0x00880000 0 0x4000>;
815 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
816 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
817 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
820 #size-cells = <0>;
826 reg = <0 0x00880000 0 0x4000>;
830 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
831 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
834 #size-cells = <0>;
840 reg = <0 0x00880000 0 0x4000>;
844 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
845 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
852 reg = <0 0x00884000 0 0x4000>;
856 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
857 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
858 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
861 #size-cells = <0>;
867 reg = <0 0x00884000 0 0x4000>;
871 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
872 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
875 #size-cells = <0>;
881 reg = <0 0x00884000 0 0x4000>;
885 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
886 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
893 reg = <0 0x00888000 0 0x4000>;
897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
898 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
899 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
902 #size-cells = <0>;
908 reg = <0 0x00888000 0 0x4000>;
912 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
913 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
916 #size-cells = <0>;
922 reg = <0 0x00888000 0 0x4000>;
926 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
927 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
934 reg = <0 0x0088c000 0 0x4000>;
938 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
939 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
940 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
943 #size-cells = <0>;
949 reg = <0 0x0088c000 0 0x4000>;
953 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
957 #size-cells = <0>;
963 reg = <0 0x0088c000 0 0x4000>;
967 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
968 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
975 reg = <0 0x00890000 0 0x4000>;
979 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
980 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
981 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
984 #size-cells = <0>;
990 reg = <0 0x00890000 0 0x4000>;
994 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
995 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
998 #size-cells = <0>;
1004 reg = <0 0x00890000 0 0x4000>;
1008 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1009 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1016 reg = <0 0x00894000 0 0x4000>;
1020 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1021 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1022 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1025 #size-cells = <0>;
1031 reg = <0 0x00894000 0 0x4000>;
1035 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1039 #size-cells = <0>;
1045 reg = <0 0x00894000 0 0x4000>;
1049 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1050 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1057 reg = <0 0x00898000 0 0x4000>;
1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1062 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1063 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1066 #size-cells = <0>;
1072 reg = <0 0x00898000 0 0x4000>;
1076 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1077 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1080 #size-cells = <0>;
1086 reg = <0 0x00898000 0 0x4000>;
1090 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1091 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1098 reg = <0 0x0089c000 0 0x4000>;
1102 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1104 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1107 #size-cells = <0>;
1113 reg = <0 0x0089c000 0 0x4000>;
1117 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1121 #size-cells = <0>;
1127 reg = <0 0x0089c000 0 0x4000>;
1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1132 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1140 reg = <0x0 0x00ac0000 0x0 0x6000>;
1147 iommus = <&apps_smmu 0x603 0>;
1152 reg = <0 0x00a80000 0 0x4000>;
1156 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1157 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1158 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1161 #size-cells = <0>;
1167 reg = <0 0x00a80000 0 0x4000>;
1171 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1172 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1175 #size-cells = <0>;
1181 reg = <0 0x00a80000 0 0x4000>;
1185 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1186 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1193 reg = <0 0x00a84000 0 0x4000>;
1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1198 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1202 #size-cells = <0>;
1208 reg = <0 0x00a84000 0 0x4000>;
1212 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1216 #size-cells = <0>;
1222 reg = <0 0x00a84000 0 0x4000>;
1226 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1227 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1234 reg = <0 0x00a88000 0 0x4000>;
1238 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1240 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1243 #size-cells = <0>;
1249 reg = <0 0x00a88000 0 0x4000>;
1253 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1257 #size-cells = <0>;
1263 reg = <0 0x00a88000 0 0x4000>;
1267 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1268 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1275 reg = <0 0x00a8c000 0 0x4000>;
1279 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1280 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1281 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1284 #size-cells = <0>;
1290 reg = <0 0x00a8c000 0 0x4000>;
1294 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1298 #size-cells = <0>;
1304 reg = <0 0x00a8c000 0 0x4000>;
1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1309 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1316 reg = <0 0x00a90000 0 0x4000>;
1320 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1321 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1322 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1325 #size-cells = <0>;
1331 reg = <0 0x00a90000 0 0x4000>;
1335 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1336 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1339 #size-cells = <0>;
1345 reg = <0 0x00a90000 0 0x4000>;
1349 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1350 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1357 reg = <0 0x00a94000 0 0x4000>;
1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1362 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1363 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1366 #size-cells = <0>;
1372 reg = <0 0x00a94000 0 0x4000>;
1376 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1377 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1380 #size-cells = <0>;
1386 reg = <0 0x00a94000 0 0x4000>;
1390 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1391 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1399 reg = <0x0 0x00cc0000 0x0 0x6000>;
1406 iommus = <&apps_smmu 0x7a3 0>;
1411 reg = <0 0x00c80000 0 0x4000>;
1415 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1416 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1417 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1420 #size-cells = <0>;
1426 reg = <0 0x00c80000 0 0x4000>;
1430 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1431 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1434 #size-cells = <0>;
1440 reg = <0 0x00c80000 0 0x4000>;
1444 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1445 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1452 reg = <0 0x00c84000 0 0x4000>;
1456 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1457 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1458 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1461 #size-cells = <0>;
1467 reg = <0 0x00c84000 0 0x4000>;
1471 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1472 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1475 #size-cells = <0>;
1481 reg = <0 0x00c84000 0 0x4000>;
1485 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1486 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1493 reg = <0 0x00c88000 0 0x4000>;
1497 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1498 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1499 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1502 #size-cells = <0>;
1508 reg = <0 0x00c88000 0 0x4000>;
1512 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1513 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1516 #size-cells = <0>;
1522 reg = <0 0x00c88000 0 0x4000>;
1526 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1534 reg = <0 0x00c8c000 0 0x4000>;
1538 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1539 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1540 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1543 #size-cells = <0>;
1549 reg = <0 0x00c8c000 0 0x4000>;
1553 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1554 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1557 #size-cells = <0>;
1563 reg = <0 0x00c8c000 0 0x4000>;
1567 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1568 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1575 reg = <0 0x00c90000 0 0x4000>;
1579 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1580 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1581 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1584 #size-cells = <0>;
1590 reg = <0 0x00c90000 0 0x4000>;
1594 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1598 #size-cells = <0>;
1604 reg = <0 0x00c90000 0 0x4000>;
1608 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1609 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1616 reg = <0 0x00c94000 0 0x4000>;
1620 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1621 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1622 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1625 #size-cells = <0>;
1631 reg = <0 0x00c94000 0 0x4000>;
1635 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1636 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1639 #size-cells = <0>;
1645 reg = <0 0x00c94000 0 0x4000>;
1649 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1650 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1658 reg = <0 0x01500000 0 0x7400>;
1665 reg = <0 0x01620000 0 0x19400>;
1672 reg = <0 0x016e0000 0 0xd080>;
1679 reg = <0 0x01700000 0 0x20000>;
1686 reg = <0 0x01720000 0 0x7000>;
1693 reg = <0 0x01740000 0 0x1c100>;
1700 reg = <0 0x01c00000 0 0x3000>,
1701 <0 0x60000000 0 0xf1d>,
1702 <0 0x60000f20 0 0xa8>,
1703 <0 0x60001000 0 0x1000>,
1704 <0 0x60100000 0 0x100000>;
1711 linux,pci-domain = <0>;
1712 bus-range = <0x00 0xff>;
1718 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1719 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1738 interrupt-map-mask = <0 0 0 0x7>;
1739 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1740 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1741 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1742 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1765 <0x100 &apps_smmu 0x1d81 0x1>;
1772 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1773 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1782 pcie@0 {
1784 reg = <0x0 0x0 0x0 0x0 0x0>;
1785 bus-range = <0x01 0xff>;
1795 reg = <0 0x01c06000 0 0x1000>;
1806 #clock-cells = <0>;
1808 #phy-cells = <0>;
1821 reg = <0 0x01c08000 0 0x3000>,
1822 <0 0x40000000 0 0xf1d>,
1823 <0 0x40000f20 0 0xa8>,
1824 <0 0x40001000 0 0x1000>,
1825 <0 0x40100000 0 0x100000>;
1833 bus-range = <0x00 0xff>;
1839 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1840 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1859 interrupt-map-mask = <0 0 0 0x7>;
1860 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1861 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1862 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1863 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1885 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1886 <0x100 &apps_smmu 0x1e01 0x1>;
1893 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1894 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
1903 pcie@0 {
1905 reg = <0x0 0x0 0x0 0x0 0x0>;
1906 bus-range = <0x01 0xff>;
1916 reg = <0 0x01c0c000 0 0x1000>;
1927 #clock-cells = <0>;
1930 #phy-cells = <0>;
1943 reg = <0 0x01c10000 0 0x3000>,
1944 <0 0x68000000 0 0xf1d>,
1945 <0 0x68000f20 0 0xa8>,
1946 <0 0x68001000 0 0x1000>,
1947 <0 0x68100000 0 0x100000>;
1955 bus-range = <0x00 0xff>;
1961 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1962 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1983 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1984 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1985 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2007 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2008 <0x100 &apps_smmu 0x1c81 0x1>;
2015 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2016 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
2025 pcie@0 {
2027 reg = <0x0 0x0 0x0 0x0 0x0>;
2028 bus-range = <0x01 0xff>;
2038 reg = <0 0x01c16000 0 0x1000>;
2049 #clock-cells = <0>;
2052 #phy-cells = <0>;
2065 reg = <0 0x01c18000 0 0x3000>,
2066 <0 0x70000000 0 0xf1d>,
2067 <0 0x70000f20 0 0xa8>,
2068 <0 0x70001000 0 0x1000>,
2069 <0 0x70100000 0 0x100000>;
2077 bus-range = <0x00 0xff>;
2083 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2084 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2103 interrupt-map-mask = <0 0 0 0x7>;
2104 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2105 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2106 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2107 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2129 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2130 <0x100 &apps_smmu 0x1d01 0x1>;
2137 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2138 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
2147 pcie@0 {
2149 reg = <0x0 0x0 0x0 0x0 0x0>;
2150 bus-range = <0x01 0xff>;
2160 reg = <0 0x01c1c000 0 0x1000>;
2171 #clock-cells = <0>;
2174 #phy-cells = <0>;
2188 reg = <0 0x01d84000 0 0x2500>;
2197 iommus = <&apps_smmu 0x300 0>;
2216 <0 0>,
2217 <0 0>,
2219 <0 0>,
2220 <0 0>,
2221 <0 0>,
2222 <0 0>;
2237 reg = <0 0x01d87000 0 0x1000>;
2246 resets = <&ufs_mem_hc 0>;
2251 #phy-cells = <0>;
2258 reg = <0x0 0x01f40000 0x0 0x40000>;
2265 reg = <0 0x02c00000 0 0x40000>;
2270 iommus = <&adreno_smmu 0 0xc01>;
2274 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2325 reg = <0 0x02c6a000 0 0x30000>,
2326 <0 0x0b290000 0 0x10000>,
2327 <0 0x0b490000 0 0x10000>;
2347 iommus = <&adreno_smmu 5 0xc00>;
2368 reg = <0 0x02c90000 0 0x9000>;
2383 reg = <0 0x02ca0000 0 0x10000>;
2405 reg = <0 0x03100000 0 0x300000>,
2406 <0 0x03500000 0 0x700000>,
2407 <0 0x03d00000 0 0x300000>;
2414 gpio-ranges = <&tlmm 0 0 191>;
2420 reg = <0x0 0x04080000 0x0 0x4040>;
2423 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2440 qcom,smem-states = <&modem_smp2p_out 0>;
2453 reg = <0x0 0x08300000 0x0 0x4040>;
2456 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2471 qcom,smem-states = <&cdsp_smp2p_out 0>;
2487 reg = <0 0x088e2000 0 0x400>;
2492 #phy-cells = <0>;
2500 reg = <0 0x088e3000 0 0x400>;
2505 #phy-cells = <0>;
2513 reg = <0 0x088e4000 0 0x400>;
2514 #phy-cells = <0>;
2527 reg = <0 0x088e5000 0 0x400>;
2528 #phy-cells = <0>;
2540 reg = <0 0x088e8000 0 0x3000>;
2562 #size-cells = <0>;
2564 port@0 {
2565 reg = <0>;
2588 reg = <0 0x088eb000 0 0x1000>;
2605 #clock-cells = <0>;
2608 #phy-cells = <0>;
2615 reg = <0 0x088ec000 0 0x1000>;
2632 #clock-cells = <0>;
2635 #phy-cells = <0>;
2642 reg = <0 0x088ed000 0 0x3000>;
2663 #size-cells = <0>;
2665 port@0 {
2666 reg = <0>;
2689 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2690 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2691 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
2692 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
2693 <0 0x09600000 0 0x58000>;
2702 reg = <0 0x09680000 0 0x58200>;
2709 reg = <0 0x0a4f8800 0 0x400>;
2728 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2729 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
2760 reg = <0 0x0a400000 0 0xcd00>;
2762 iommus = <&apps_smmu 0x60 0>;
2769 phy-names = "usb2-0",
2770 "usb3-0",
2779 reg = <0 0x0a6f8800 0 0x400>;
2806 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2807 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2823 reg = <0 0x0a600000 0 0xcd00>;
2825 iommus = <&apps_smmu 0x140 0>;
2833 #size-cells = <0>;
2835 port@0 {
2836 reg = <0>;
2855 reg = <0 0x0a8f8800 0 0x400>;
2887 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2888 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2900 reg = <0 0x0a800000 0 0xcd00>;
2902 iommus = <&apps_smmu 0x160 0>;
2910 #size-cells = <0>;
2912 port@0 {
2913 reg = <0>;
2932 reg = <0 0x0ae00000 0 0x1000>;
2962 iommus = <&apps_smmu 0x800 0x420>;
2972 reg = <0 0x0ae01000 0 0x8f000>,
2973 <0 0x0aeb0000 0 0x2008>;
2996 interrupts = <0>;
3000 #size-cells = <0>;
3002 port@0 {
3003 reg = <0>;
3065 reg = <0 0x0ae94000 0 0x400>;
3094 #size-cells = <0>;
3096 port@0 {
3097 reg = <0>;
3132 reg = <0 0x0ae94400 0 0x200>,
3133 <0 0x0ae94600 0 0x280>,
3134 <0 0x0ae94900 0 0x260>;
3140 #phy-cells = <0>;
3151 reg = <0 0x0ae96000 0 0x400>;
3180 #size-cells = <0>;
3182 port@0 {
3183 reg = <0>;
3199 reg = <0 0x0ae96400 0 0x200>,
3200 <0 0x0ae96600 0 0x280>,
3201 <0 0x0ae96900 0 0x260>;
3207 #phy-cells = <0>;
3218 reg = <0 0xae90000 0 0x200>,
3219 <0 0xae90200 0 0x200>,
3220 <0 0xae90400 0 0x600>,
3221 <0 0xae90a00 0 0x400>,
3222 <0 0xae91000 0 0x400>;
3244 #sound-dai-cells = <0>;
3253 #size-cells = <0>;
3255 port@0 {
3256 reg = <0>;
3296 reg = <0 0xae98000 0 0x200>,
3297 <0 0xae98200 0 0x200>,
3298 <0 0xae98400 0 0x600>,
3299 <0 0xae98a00 0 0x400>,
3300 <0 0xae99000 0 0x400>;
3322 #sound-dai-cells = <0>;
3331 #size-cells = <0>;
3333 port@0 {
3334 reg = <0>;
3374 reg = <0 0xae9a000 0 0x200>,
3375 <0 0xae9a200 0 0x200>,
3376 <0 0xae9a400 0 0x600>,
3377 <0 0xae9aa00 0 0x400>;
3393 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3405 #size-cells = <0>;
3407 port@0 {
3408 reg = <0>;
3443 reg = <0 0x0aec2a00 0 0x1c0>,
3444 <0 0x0aec2200 0 0xa0>,
3445 <0 0x0aec2600 0 0xa0>,
3446 <0 0x0aec2000 0 0x19c>;
3455 #phy-cells = <0>;
3460 reg = <0 0x0af00000 0 0x20000>;
3462 <&mdss_dsi0_phy 0>,
3464 <&mdss_dsi1_phy 0>,
3468 <&edp_phy 0>,
3492 reg = <0 0x0b220000 0 0x30000>;
3493 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3501 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3502 <0 0x0c222000 0 0x1ff>; /* SROT */
3512 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3513 <0 0x0c223000 0 0x1ff>; /* SROT */
3523 reg = <0x0 0x0c300000 0x0 0x400>;
3525 mboxes = <&apss_shared 0>;
3527 #clock-cells = <0>;
3532 reg = <0x0 0x0c3f0000 0x0 0x400>;
3537 reg = <0x0 0x0c440000 0x0 0x0001100>,
3538 <0x0 0x0c600000 0x0 0x2000000>,
3539 <0x0 0x0e600000 0x0 0x0100000>,
3540 <0x0 0x0e700000 0x0 0x00a0000>,
3541 <0x0 0x0c40a000 0x0 0x0026000>;
3545 qcom,ee = <0>;
3546 qcom,channel = <0>;
3548 #size-cells = <0>;
3555 reg = <0 0x15000000 0 0x100000>;
3670 reg = <0x0 0x17300000 0x0 0x4040>;
3673 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3688 qcom,smem-states = <&adsp_smp2p_out 0>;
3705 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3706 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3709 redistributor-stride = <0 0x20000>;
3714 reg = <0x0 0x17c00000 0x0 0x1000>;
3720 reg = <0x0 0x17c20000 0x0 0x1000>;
3724 ranges = <0 0 0 0x20000000>;
3727 reg = <0x17c21000 0x1000>,
3728 <0x17c22000 0x1000>;
3729 frame-number = <0>;
3735 reg = <0x17c23000 0x1000>;
3742 reg = <0x17c25000 0x1000>;
3749 reg = <0x17c26000 0x1000>;
3756 reg = <0x17c29000 0x1000>;
3763 reg = <0x17c2b000 0x1000>;
3770 reg = <0x17c2d000 0x1000>;
3779 reg = <0x0 0x18200000 0x0 0x10000>,
3780 <0x0 0x18210000 0x0 0x10000>,
3781 <0x0 0x18220000 0x0 0x10000>;
3782 reg-names = "drv-0", "drv-1", "drv-2";
3786 qcom,tcs-offset = <0xd00>;
3791 <CONTROL_TCS 0>;
3859 reg = <0 0x18321000 0 0x1400>;
3869 reg = <0 0x18350800 0 0x400>;
3881 reg = <0 0x18358800 0 0x400>;
3893 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3905 reg = <0 0x18800000 0 0x800000>;
3921 iommus = <&apps_smmu 0x0640 0x1>;
4099 thermal-sensors = <&tsens0 0>;
4174 thermal-sensors = <&tsens1 0>;
4336 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;