Lines Matching +full:0 +full:x0aec2a00
31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
115 clocks = <&cpufreq_hw 0>;
128 reg = <0x0 0x300>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
139 clocks = <&cpufreq_hw 0>;
152 reg = <0x0 0x400>;
176 reg = <0x0 0x500>;
200 reg = <0x0 0x600>;
224 reg = <0x0 0x700>;
284 little_cpu_sleep_0: cpu-sleep-0-0 {
286 arm,psci-suspend-param = <0x40000004>;
293 big_cpu_sleep_0: cpu-sleep-1-0 {
295 arm,psci-suspend-param = <0x40000004>;
304 cluster_sleep_apss_off: cluster-sleep-0 {
306 arm,psci-suspend-param = <0x41000044>;
314 arm,psci-suspend-param = <0x4100a344>;
534 reg = <0x0 0x80000000 0x0 0x0>;
547 #power-domain-cells = <0>;
553 #power-domain-cells = <0>;
559 #power-domain-cells = <0>;
565 #power-domain-cells = <0>;
571 #power-domain-cells = <0>;
577 #power-domain-cells = <0>;
583 #power-domain-cells = <0>;
589 #power-domain-cells = <0>;
595 #power-domain-cells = <0>;
606 reg = <0x0 0x85700000 0x0 0x600000>;
611 reg = <0x0 0x85d00000 0x0 0x140000>;
616 reg = <0x0 0x85f00000 0x0 0x20000>;
622 reg = <0x0 0x85f20000 0x0 0x20000>;
627 reg = <0x0 0x85f40000 0x0 0x10000>;
633 reg = <0x0 0x86000000 0x0 0x200000>;
639 reg = <0x0 0x86200000 0x0 0x3900000>;
644 reg = <0x0 0x89b00000 0x0 0x1c00000>;
649 reg = <0x0 0x9d400000 0x0 0x1000000>;
654 reg = <0x0 0x9e400000 0x0 0x1400000>;
659 reg = <0x0 0x9f800000 0x0 0x800000>;
672 qcom,local-pid = <0>;
696 qcom,local-pid = <0>;
720 qcom,local-pid = <0>;
761 qcom,local-pid = <0>;
777 soc: soc@0 {
781 ranges = <0 0 0 0 0x10 0>;
782 dma-ranges = <0 0 0 0 0x10 0>;
786 reg = <0x0 0x00100000 0x0 0x1f0000>;
801 reg = <0 0x008c0000 0 0x6000>;
808 iommus = <&apps_smmu 0x4c3 0>;
813 reg = <0 0x00880000 0 0x4000>;
817 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
818 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
819 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
822 #size-cells = <0>;
828 reg = <0 0x00880000 0 0x4000>;
832 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
833 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
836 #size-cells = <0>;
842 reg = <0 0x00880000 0 0x4000>;
846 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
854 reg = <0 0x00884000 0 0x4000>;
858 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
859 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
860 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
863 #size-cells = <0>;
869 reg = <0 0x00884000 0 0x4000>;
873 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
874 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
877 #size-cells = <0>;
883 reg = <0 0x00884000 0 0x4000>;
887 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
888 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
895 reg = <0 0x00888000 0 0x4000>;
899 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
901 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
904 #size-cells = <0>;
910 reg = <0 0x00888000 0 0x4000>;
914 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
918 #size-cells = <0>;
924 reg = <0 0x00888000 0 0x4000>;
928 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
929 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
936 reg = <0 0x0088c000 0 0x4000>;
940 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
941 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
942 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
945 #size-cells = <0>;
951 reg = <0 0x0088c000 0 0x4000>;
955 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
956 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
959 #size-cells = <0>;
965 reg = <0 0x0088c000 0 0x4000>;
969 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
970 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
977 reg = <0 0x00890000 0 0x4000>;
981 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
982 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
983 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
986 #size-cells = <0>;
992 reg = <0 0x00890000 0 0x4000>;
996 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
997 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1000 #size-cells = <0>;
1006 reg = <0 0x00890000 0 0x4000>;
1010 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1018 reg = <0 0x00894000 0 0x4000>;
1022 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1023 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1024 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1027 #size-cells = <0>;
1033 reg = <0 0x00894000 0 0x4000>;
1037 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1038 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1041 #size-cells = <0>;
1047 reg = <0 0x00894000 0 0x4000>;
1051 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1052 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1059 reg = <0 0x00898000 0 0x4000>;
1063 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1064 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1065 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1068 #size-cells = <0>;
1074 reg = <0 0x00898000 0 0x4000>;
1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1079 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1082 #size-cells = <0>;
1088 reg = <0 0x00898000 0 0x4000>;
1092 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1093 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1100 reg = <0 0x0089c000 0 0x4000>;
1104 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1105 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1106 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1109 #size-cells = <0>;
1115 reg = <0 0x0089c000 0 0x4000>;
1119 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1120 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1123 #size-cells = <0>;
1129 reg = <0 0x0089c000 0 0x4000>;
1133 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1142 reg = <0x0 0x00ac0000 0x0 0x6000>;
1149 iommus = <&apps_smmu 0x603 0>;
1154 reg = <0 0x00a80000 0 0x4000>;
1158 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1159 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1160 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1163 #size-cells = <0>;
1169 reg = <0 0x00a80000 0 0x4000>;
1173 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1174 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1177 #size-cells = <0>;
1183 reg = <0 0x00a80000 0 0x4000>;
1187 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1188 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1195 reg = <0 0x00a84000 0 0x4000>;
1199 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1200 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1201 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1204 #size-cells = <0>;
1210 reg = <0 0x00a84000 0 0x4000>;
1214 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1215 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1218 #size-cells = <0>;
1224 reg = <0 0x00a84000 0 0x4000>;
1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1229 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1236 reg = <0 0x00a88000 0 0x4000>;
1240 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1241 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1242 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1245 #size-cells = <0>;
1251 reg = <0 0x00a88000 0 0x4000>;
1255 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1256 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1259 #size-cells = <0>;
1265 reg = <0 0x00a88000 0 0x4000>;
1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1270 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1277 reg = <0 0x00a8c000 0 0x4000>;
1281 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1282 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1283 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1286 #size-cells = <0>;
1292 reg = <0 0x00a8c000 0 0x4000>;
1296 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1297 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1300 #size-cells = <0>;
1306 reg = <0 0x00a8c000 0 0x4000>;
1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1311 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1318 reg = <0 0x00a90000 0 0x4000>;
1322 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1323 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1324 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1327 #size-cells = <0>;
1333 reg = <0 0x00a90000 0 0x4000>;
1337 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1338 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1341 #size-cells = <0>;
1347 reg = <0 0x00a90000 0 0x4000>;
1351 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1352 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1359 reg = <0 0x00a94000 0 0x4000>;
1363 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1364 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1365 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1368 #size-cells = <0>;
1374 reg = <0 0x00a94000 0 0x4000>;
1378 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1379 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1382 #size-cells = <0>;
1388 reg = <0 0x00a94000 0 0x4000>;
1392 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1393 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1401 reg = <0x0 0x00cc0000 0x0 0x6000>;
1408 iommus = <&apps_smmu 0x7a3 0>;
1413 reg = <0 0x00c80000 0 0x4000>;
1417 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1418 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1419 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1422 #size-cells = <0>;
1428 reg = <0 0x00c80000 0 0x4000>;
1432 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1433 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1436 #size-cells = <0>;
1442 reg = <0 0x00c80000 0 0x4000>;
1446 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1447 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1454 reg = <0 0x00c84000 0 0x4000>;
1458 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1459 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1460 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1463 #size-cells = <0>;
1469 reg = <0 0x00c84000 0 0x4000>;
1473 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1474 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1477 #size-cells = <0>;
1483 reg = <0 0x00c84000 0 0x4000>;
1487 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1495 reg = <0 0x00c88000 0 0x4000>;
1499 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1500 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1501 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1504 #size-cells = <0>;
1510 reg = <0 0x00c88000 0 0x4000>;
1514 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1515 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1518 #size-cells = <0>;
1524 reg = <0 0x00c88000 0 0x4000>;
1528 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1529 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1536 reg = <0 0x00c8c000 0 0x4000>;
1540 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1541 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1542 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1545 #size-cells = <0>;
1551 reg = <0 0x00c8c000 0 0x4000>;
1555 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1556 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1559 #size-cells = <0>;
1565 reg = <0 0x00c8c000 0 0x4000>;
1569 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1570 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1577 reg = <0 0x00c90000 0 0x4000>;
1581 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1582 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1583 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1586 #size-cells = <0>;
1592 reg = <0 0x00c90000 0 0x4000>;
1596 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1597 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1600 #size-cells = <0>;
1606 reg = <0 0x00c90000 0 0x4000>;
1610 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1611 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1618 reg = <0 0x00c94000 0 0x4000>;
1622 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1623 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1624 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1627 #size-cells = <0>;
1633 reg = <0 0x00c94000 0 0x4000>;
1637 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1638 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1641 #size-cells = <0>;
1647 reg = <0 0x00c94000 0 0x4000>;
1651 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1652 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1660 reg = <0 0x01500000 0 0x7400>;
1667 reg = <0 0x01620000 0 0x19400>;
1674 reg = <0 0x016e0000 0 0xd080>;
1681 reg = <0 0x01700000 0 0x20000>;
1688 reg = <0 0x01720000 0 0x7000>;
1695 reg = <0 0x01740000 0 0x1c100>;
1702 reg = <0 0x01c00000 0 0x3000>,
1703 <0 0x60000000 0 0xf1d>,
1704 <0 0x60000f20 0 0xa8>,
1705 <0 0x60001000 0 0x1000>,
1706 <0 0x60100000 0 0x100000>;
1713 linux,pci-domain = <0>;
1714 bus-range = <0x00 0xff>;
1720 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1721 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1742 interrupt-map-mask = <0 0 0 0x7>;
1743 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1744 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1745 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1746 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1765 <0x100 &apps_smmu 0x1d81 0x1>;
1772 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1773 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1782 pcie@0 {
1784 reg = <0x0 0x0 0x0 0x0 0x0>;
1785 bus-range = <0x01 0xff>;
1795 reg = <0 0x01c06000 0 0x1000>;
1806 #clock-cells = <0>;
1808 #phy-cells = <0>;
1821 reg = <0 0x01c08000 0 0x3000>,
1822 <0 0x40000000 0 0xf1d>,
1823 <0 0x40000f20 0 0xa8>,
1824 <0 0x40001000 0 0x1000>,
1825 <0 0x40100000 0 0x100000>;
1833 bus-range = <0x00 0xff>;
1839 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1840 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1861 interrupt-map-mask = <0 0 0 0x7>;
1862 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1863 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1864 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1865 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1883 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1884 <0x100 &apps_smmu 0x1e01 0x1>;
1891 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
1901 pcie@0 {
1903 reg = <0x0 0x0 0x0 0x0 0x0>;
1904 bus-range = <0x01 0xff>;
1914 reg = <0 0x01c0c000 0 0x1000>;
1925 #clock-cells = <0>;
1928 #phy-cells = <0>;
1941 reg = <0 0x01c10000 0 0x3000>,
1942 <0 0x68000000 0 0xf1d>,
1943 <0 0x68000f20 0 0xa8>,
1944 <0 0x68001000 0 0x1000>,
1945 <0 0x68100000 0 0x100000>;
1953 bus-range = <0x00 0xff>;
1959 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1960 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1983 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1984 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1985 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2003 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2004 <0x100 &apps_smmu 0x1c81 0x1>;
2011 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2012 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
2021 pcie@0 {
2023 reg = <0x0 0x0 0x0 0x0 0x0>;
2024 bus-range = <0x01 0xff>;
2034 reg = <0 0x01c16000 0 0x1000>;
2045 #clock-cells = <0>;
2048 #phy-cells = <0>;
2061 reg = <0 0x01c18000 0 0x3000>,
2062 <0 0x70000000 0 0xf1d>,
2063 <0 0x70000f20 0 0xa8>,
2064 <0 0x70001000 0 0x1000>,
2065 <0 0x70100000 0 0x100000>;
2073 bus-range = <0x00 0xff>;
2079 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2080 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2101 interrupt-map-mask = <0 0 0 0x7>;
2102 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2103 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2104 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2105 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2123 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2124 <0x100 &apps_smmu 0x1d01 0x1>;
2131 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2132 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
2141 pcie@0 {
2143 reg = <0x0 0x0 0x0 0x0 0x0>;
2144 bus-range = <0x01 0xff>;
2154 reg = <0 0x01c1c000 0 0x1000>;
2165 #clock-cells = <0>;
2168 #phy-cells = <0>;
2182 reg = <0 0x01d84000 0 0x2500>;
2191 iommus = <&apps_smmu 0x300 0>;
2210 <0 0>,
2211 <0 0>,
2213 <0 0>,
2214 <0 0>,
2215 <0 0>,
2216 <0 0>;
2231 reg = <0 0x01d87000 0 0x1000>;
2240 resets = <&ufs_mem_hc 0>;
2245 #phy-cells = <0>;
2252 reg = <0x0 0x01f40000 0x0 0x40000>;
2259 reg = <0 0x02c00000 0 0x40000>;
2264 iommus = <&adreno_smmu 0 0xc01>;
2268 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2319 reg = <0 0x02c6a000 0 0x30000>,
2320 <0 0x0b290000 0 0x10000>,
2321 <0 0x0b490000 0 0x10000>;
2341 iommus = <&adreno_smmu 5 0xc00>;
2362 reg = <0 0x02c90000 0 0x9000>;
2377 reg = <0 0x02ca0000 0 0x10000>;
2399 reg = <0 0x03100000 0 0x300000>,
2400 <0 0x03500000 0 0x700000>,
2401 <0 0x03d00000 0 0x300000>;
2408 gpio-ranges = <&tlmm 0 0 191>;
2414 reg = <0x0 0x04080000 0x0 0x4040>;
2417 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2434 qcom,smem-states = <&modem_smp2p_out 0>;
2447 reg = <0x0 0x08300000 0x0 0x4040>;
2450 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2465 qcom,smem-states = <&cdsp_smp2p_out 0>;
2481 reg = <0 0x088e2000 0 0x400>;
2486 #phy-cells = <0>;
2494 reg = <0 0x088e3000 0 0x400>;
2499 #phy-cells = <0>;
2507 reg = <0 0x088e4000 0 0x400>;
2508 #phy-cells = <0>;
2521 reg = <0 0x088e5000 0 0x400>;
2522 #phy-cells = <0>;
2534 reg = <0 0x088e8000 0 0x3000>;
2556 #size-cells = <0>;
2558 port@0 {
2559 reg = <0>;
2582 reg = <0 0x088eb000 0 0x1000>;
2599 #clock-cells = <0>;
2602 #phy-cells = <0>;
2609 reg = <0 0x088ec000 0 0x1000>;
2626 #clock-cells = <0>;
2629 #phy-cells = <0>;
2636 reg = <0 0x088ed000 0 0x3000>;
2657 #size-cells = <0>;
2659 port@0 {
2660 reg = <0>;
2683 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2684 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2685 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
2686 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
2687 <0 0x09600000 0 0x58000>;
2696 reg = <0 0x09680000 0 0x58200>;
2703 reg = <0 0x0a4f8800 0 0x400>;
2722 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2723 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
2754 reg = <0 0x0a400000 0 0xcd00>;
2756 iommus = <&apps_smmu 0x60 0>;
2765 phy-names = "usb2-0",
2766 "usb3-0",
2775 reg = <0 0x0a6f8800 0 0x400>;
2802 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2803 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2819 reg = <0 0x0a600000 0 0xcd00>;
2821 iommus = <&apps_smmu 0x140 0>;
2831 #size-cells = <0>;
2833 port@0 {
2834 reg = <0>;
2853 reg = <0 0x0a8f8800 0 0x400>;
2885 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2886 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2898 reg = <0 0x0a800000 0 0xcd00>;
2900 iommus = <&apps_smmu 0x160 0>;
2910 #size-cells = <0>;
2912 port@0 {
2913 reg = <0>;
2932 reg = <0 0x0ad00000 0 0x20000>;
2945 reg = <0 0x0ae00000 0 0x1000>;
2975 iommus = <&apps_smmu 0x800 0x420>;
2985 reg = <0 0x0ae01000 0 0x8f000>,
2986 <0 0x0aeb0000 0 0x3000>;
3009 interrupts = <0>;
3013 #size-cells = <0>;
3015 port@0 {
3016 reg = <0>;
3078 reg = <0 0x0ae94000 0 0x400>;
3107 #size-cells = <0>;
3109 port@0 {
3110 reg = <0>;
3145 reg = <0 0x0ae94400 0 0x200>,
3146 <0 0x0ae94600 0 0x280>,
3147 <0 0x0ae94900 0 0x260>;
3153 #phy-cells = <0>;
3164 reg = <0 0x0ae96000 0 0x400>;
3193 #size-cells = <0>;
3195 port@0 {
3196 reg = <0>;
3212 reg = <0 0x0ae96400 0 0x200>,
3213 <0 0x0ae96600 0 0x280>,
3214 <0 0x0ae96900 0 0x260>;
3220 #phy-cells = <0>;
3231 reg = <0 0xae90000 0 0x200>,
3232 <0 0xae90200 0 0x200>,
3233 <0 0xae90400 0 0x600>,
3234 <0 0xae90a00 0 0x400>,
3235 <0 0xae91000 0 0x400>;
3257 #sound-dai-cells = <0>;
3266 #size-cells = <0>;
3268 port@0 {
3269 reg = <0>;
3309 reg = <0 0xae98000 0 0x200>,
3310 <0 0xae98200 0 0x200>,
3311 <0 0xae98400 0 0x600>,
3312 <0 0xae98a00 0 0x400>,
3313 <0 0xae99000 0 0x400>;
3335 #sound-dai-cells = <0>;
3344 #size-cells = <0>;
3346 port@0 {
3347 reg = <0>;
3387 reg = <0 0xae9a000 0 0x200>,
3388 <0 0xae9a200 0 0x200>,
3389 <0 0xae9a400 0 0x600>,
3390 <0 0xae9aa00 0 0x400>;
3406 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3418 #size-cells = <0>;
3420 port@0 {
3421 reg = <0>;
3456 reg = <0 0x0aec2a00 0 0x1c0>,
3457 <0 0x0aec2200 0 0xa0>,
3458 <0 0x0aec2600 0 0xa0>,
3459 <0 0x0aec2000 0 0x19c>;
3468 #phy-cells = <0>;
3473 reg = <0 0x0af00000 0 0x20000>;
3481 <&edp_phy 0>,
3505 reg = <0 0x0b220000 0 0x30000>;
3506 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3514 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3515 <0 0x0c222000 0 0x1ff>; /* SROT */
3525 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3526 <0 0x0c223000 0 0x1ff>; /* SROT */
3536 reg = <0x0 0x0c300000 0x0 0x400>;
3538 mboxes = <&apss_shared 0>;
3540 #clock-cells = <0>;
3545 reg = <0x0 0x0c3f0000 0x0 0x400>;
3550 reg = <0x0 0x0c440000 0x0 0x0001100>,
3551 <0x0 0x0c600000 0x0 0x2000000>,
3552 <0x0 0x0e600000 0x0 0x0100000>,
3553 <0x0 0x0e700000 0x0 0x00a0000>,
3554 <0x0 0x0c40a000 0x0 0x0026000>;
3558 qcom,ee = <0>;
3559 qcom,channel = <0>;
3561 #size-cells = <0>;
3568 reg = <0 0x15000000 0 0x100000>;
3683 reg = <0x0 0x17300000 0x0 0x4040>;
3686 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3701 qcom,smem-states = <&adsp_smp2p_out 0>;
3718 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3719 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3722 redistributor-stride = <0 0x20000>;
3727 reg = <0x0 0x17c00000 0x0 0x1000>;
3733 reg = <0x0 0x17c20000 0x0 0x1000>;
3737 ranges = <0 0 0 0x20000000>;
3740 reg = <0x17c21000 0x1000>,
3741 <0x17c22000 0x1000>;
3742 frame-number = <0>;
3748 reg = <0x17c23000 0x1000>;
3755 reg = <0x17c25000 0x1000>;
3762 reg = <0x17c26000 0x1000>;
3769 reg = <0x17c29000 0x1000>;
3776 reg = <0x17c2b000 0x1000>;
3783 reg = <0x17c2d000 0x1000>;
3792 reg = <0x0 0x18200000 0x0 0x10000>,
3793 <0x0 0x18210000 0x0 0x10000>,
3794 <0x0 0x18220000 0x0 0x10000>;
3795 reg-names = "drv-0", "drv-1", "drv-2";
3799 qcom,tcs-offset = <0xd00>;
3804 <CONTROL_TCS 0>;
3872 reg = <0 0x18321000 0 0x1400>;
3882 reg = <0 0x18350800 0 0x400>;
3894 reg = <0 0x18358800 0 0x400>;
3906 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3918 reg = <0 0x18800000 0 0x800000>;
3934 iommus = <&apps_smmu 0x0640 0x1>;
4112 thermal-sensors = <&tsens0 0>;
4187 thermal-sensors = <&tsens1 0>;
4349 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;