Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
13 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
16 #include <dt-bindings/dma/qcom-gpi.h>
17 #include <dt-bindings/firmware/qcom,scm.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/interconnect/qcom,icc.h>
20 #include <dt-bindings/interconnect/qcom,osm-l3.h>
21 #include <dt-bindings/interconnect/qcom,sc7280.h>
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 #include <dt-bindings/mailbox/qcom-ipcc.h>
24 #include <dt-bindings/phy/phy-qcom-qmp.h>
25 #include <dt-bindings/power/qcom-rpmpd.h>
26 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
27 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
28 #include <dt-bindings/soc/qcom,apr.h>
29 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
30 #include <dt-bindings/sound/qcom,lpass.h>
31 #include <dt-bindings/sound/qcom,q6asm.h>
32 #include <dt-bindings/thermal/thermal.h>
35 interrupt-parent = <&intc>;
37 #address-cells = <2>;
38 #size-cells = <2>;
80 xo_board: xo-board {
81 compatible = "fixed-clock";
82 clock-frequency = <76800000>;
83 #clock-cells = <0>;
86 sleep_clk: sleep-clk {
87 compatible = "fixed-clock";
88 clock-frequency = <32764>;
89 #clock-cells = <0>;
93 reserved-memory {
94 #address-cells = <2>;
95 #size-cells = <2>;
98 wlan_ce_mem: wlan-ce@4cd000 {
99 no-map;
105 no-map;
110 no-map;
115 no-map;
118 aop_cmd_db_mem: aop-cmd-db@80860000 {
120 compatible = "qcom,cmd-db";
121 no-map;
124 reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
126 no-map;
129 sec_apps_mem: sec-apps@808ff000 {
131 no-map;
136 no-map;
140 no-map;
144 wlan_fw_mem: wlan-fw@80c00000 {
146 no-map;
151 no-map;
156 no-map;
161 no-map;
164 ipa_fw_mem: ipa-fw@8b700000 {
166 no-map;
171 no-map;
176 no-map;
181 no-map;
185 compatible = "qcom,rmtfs-mem";
187 no-map;
189 qcom,client-id = <1>;
195 #address-cells = <2>;
196 #size-cells = <0>;
203 enable-method = "psci";
204 power-domains = <&cpu_pd0>;
205 power-domain-names = "psci";
206 next-level-cache = <&l2_0>;
207 operating-points-v2 = <&cpu0_opp_table>;
208 capacity-dmips-mhz = <1024>;
209 dynamic-power-coefficient = <100>;
212 qcom,freq-domain = <&cpufreq_hw 0>;
213 #cooling-cells = <2>;
214 l2_0: l2-cache {
216 cache-level = <2>;
217 cache-unified;
218 next-level-cache = <&l3_0>;
219 l3_0: l3-cache {
221 cache-level = <3>;
222 cache-unified;
232 enable-method = "psci";
233 power-domains = <&cpu_pd1>;
234 power-domain-names = "psci";
235 next-level-cache = <&l2_100>;
236 operating-points-v2 = <&cpu0_opp_table>;
237 capacity-dmips-mhz = <1024>;
238 dynamic-power-coefficient = <100>;
241 qcom,freq-domain = <&cpufreq_hw 0>;
242 #cooling-cells = <2>;
243 l2_100: l2-cache {
245 cache-level = <2>;
246 cache-unified;
247 next-level-cache = <&l3_0>;
256 enable-method = "psci";
257 power-domains = <&cpu_pd2>;
258 power-domain-names = "psci";
259 next-level-cache = <&l2_200>;
260 operating-points-v2 = <&cpu0_opp_table>;
261 capacity-dmips-mhz = <1024>;
262 dynamic-power-coefficient = <100>;
265 qcom,freq-domain = <&cpufreq_hw 0>;
266 #cooling-cells = <2>;
267 l2_200: l2-cache {
269 cache-level = <2>;
270 cache-unified;
271 next-level-cache = <&l3_0>;
280 enable-method = "psci";
281 power-domains = <&cpu_pd3>;
282 power-domain-names = "psci";
283 next-level-cache = <&l2_300>;
284 operating-points-v2 = <&cpu0_opp_table>;
285 capacity-dmips-mhz = <1024>;
286 dynamic-power-coefficient = <100>;
289 qcom,freq-domain = <&cpufreq_hw 0>;
290 #cooling-cells = <2>;
291 l2_300: l2-cache {
293 cache-level = <2>;
294 cache-unified;
295 next-level-cache = <&l3_0>;
304 enable-method = "psci";
305 power-domains = <&cpu_pd4>;
306 power-domain-names = "psci";
307 next-level-cache = <&l2_400>;
308 operating-points-v2 = <&cpu4_opp_table>;
309 capacity-dmips-mhz = <1946>;
310 dynamic-power-coefficient = <520>;
313 qcom,freq-domain = <&cpufreq_hw 1>;
314 #cooling-cells = <2>;
315 l2_400: l2-cache {
317 cache-level = <2>;
318 cache-unified;
319 next-level-cache = <&l3_0>;
328 enable-method = "psci";
329 power-domains = <&cpu_pd5>;
330 power-domain-names = "psci";
331 next-level-cache = <&l2_500>;
332 operating-points-v2 = <&cpu4_opp_table>;
333 capacity-dmips-mhz = <1946>;
334 dynamic-power-coefficient = <520>;
337 qcom,freq-domain = <&cpufreq_hw 1>;
338 #cooling-cells = <2>;
339 l2_500: l2-cache {
341 cache-level = <2>;
342 cache-unified;
343 next-level-cache = <&l3_0>;
352 enable-method = "psci";
353 power-domains = <&cpu_pd6>;
354 power-domain-names = "psci";
355 next-level-cache = <&l2_600>;
356 operating-points-v2 = <&cpu4_opp_table>;
357 capacity-dmips-mhz = <1946>;
358 dynamic-power-coefficient = <520>;
361 qcom,freq-domain = <&cpufreq_hw 1>;
362 #cooling-cells = <2>;
363 l2_600: l2-cache {
365 cache-level = <2>;
366 cache-unified;
367 next-level-cache = <&l3_0>;
376 enable-method = "psci";
377 power-domains = <&cpu_pd7>;
378 power-domain-names = "psci";
379 next-level-cache = <&l2_700>;
380 operating-points-v2 = <&cpu7_opp_table>;
381 capacity-dmips-mhz = <1985>;
382 dynamic-power-coefficient = <552>;
385 qcom,freq-domain = <&cpufreq_hw 2>;
386 #cooling-cells = <2>;
387 l2_700: l2-cache {
389 cache-level = <2>;
390 cache-unified;
391 next-level-cache = <&l3_0>;
395 cpu-map {
431 idle-states {
432 entry-method = "psci";
434 little_cpu_sleep_0: cpu-sleep-0-0 {
435 compatible = "arm,idle-state";
436 idle-state-name = "little-power-down";
437 arm,psci-suspend-param = <0x40000003>;
438 entry-latency-us = <549>;
439 exit-latency-us = <901>;
440 min-residency-us = <1774>;
441 local-timer-stop;
444 little_cpu_sleep_1: cpu-sleep-0-1 {
445 compatible = "arm,idle-state";
446 idle-state-name = "little-rail-power-down";
447 arm,psci-suspend-param = <0x40000004>;
448 entry-latency-us = <702>;
449 exit-latency-us = <915>;
450 min-residency-us = <4001>;
451 local-timer-stop;
454 big_cpu_sleep_0: cpu-sleep-1-0 {
455 compatible = "arm,idle-state";
456 idle-state-name = "big-power-down";
457 arm,psci-suspend-param = <0x40000003>;
458 entry-latency-us = <523>;
459 exit-latency-us = <1244>;
460 min-residency-us = <2207>;
461 local-timer-stop;
464 big_cpu_sleep_1: cpu-sleep-1-1 {
465 compatible = "arm,idle-state";
466 idle-state-name = "big-rail-power-down";
467 arm,psci-suspend-param = <0x40000004>;
468 entry-latency-us = <526>;
469 exit-latency-us = <1854>;
470 min-residency-us = <5555>;
471 local-timer-stop;
475 domain_idle_states: domain-idle-states {
476 cluster_sleep_apss_off: cluster-sleep-0 {
477 compatible = "domain-idle-state";
478 arm,psci-suspend-param = <0x41000044>;
479 entry-latency-us = <2752>;
480 exit-latency-us = <3048>;
481 min-residency-us = <6118>;
484 cluster_sleep_cx_ret: cluster-sleep-1 {
485 compatible = "domain-idle-state";
486 arm,psci-suspend-param = <0x41001344>;
487 entry-latency-us = <3263>;
488 exit-latency-us = <4562>;
489 min-residency-us = <8467>;
492 cluster_sleep_llcc_off: cluster-sleep-2 {
493 compatible = "domain-idle-state";
494 arm,psci-suspend-param = <0x4100b344>;
495 entry-latency-us = <3638>;
496 exit-latency-us = <6562>;
497 min-residency-us = <9826>;
502 cpu0_opp_table: opp-table-cpu0 {
503 compatible = "operating-points-v2";
504 opp-shared;
506 cpu0_opp_300mhz: opp-300000000 {
507 opp-hz = /bits/ 64 <300000000>;
508 opp-peak-kBps = <800000 9600000>;
511 cpu0_opp_691mhz: opp-691200000 {
512 opp-hz = /bits/ 64 <691200000>;
513 opp-peak-kBps = <800000 17817600>;
516 cpu0_opp_806mhz: opp-806400000 {
517 opp-hz = /bits/ 64 <806400000>;
518 opp-peak-kBps = <800000 20889600>;
521 cpu0_opp_941mhz: opp-940800000 {
522 opp-hz = /bits/ 64 <940800000>;
523 opp-peak-kBps = <1804000 24576000>;
526 cpu0_opp_1152mhz: opp-1152000000 {
527 opp-hz = /bits/ 64 <1152000000>;
528 opp-peak-kBps = <2188000 27033600>;
531 cpu0_opp_1325mhz: opp-1324800000 {
532 opp-hz = /bits/ 64 <1324800000>;
533 opp-peak-kBps = <2188000 33792000>;
536 cpu0_opp_1517mhz: opp-1516800000 {
537 opp-hz = /bits/ 64 <1516800000>;
538 opp-peak-kBps = <3072000 38092800>;
541 cpu0_opp_1651mhz: opp-1651200000 {
542 opp-hz = /bits/ 64 <1651200000>;
543 opp-peak-kBps = <3072000 41779200>;
546 cpu0_opp_1805mhz: opp-1804800000 {
547 opp-hz = /bits/ 64 <1804800000>;
548 opp-peak-kBps = <4068000 48537600>;
551 cpu0_opp_1958mhz: opp-1958400000 {
552 opp-hz = /bits/ 64 <1958400000>;
553 opp-peak-kBps = <4068000 48537600>;
556 cpu0_opp_2016mhz: opp-2016000000 {
557 opp-hz = /bits/ 64 <2016000000>;
558 opp-peak-kBps = <6220000 48537600>;
562 cpu4_opp_table: opp-table-cpu4 {
563 compatible = "operating-points-v2";
564 opp-shared;
566 cpu4_opp_691mhz: opp-691200000 {
567 opp-hz = /bits/ 64 <691200000>;
568 opp-peak-kBps = <1804000 9600000>;
571 cpu4_opp_941mhz: opp-940800000 {
572 opp-hz = /bits/ 64 <940800000>;
573 opp-peak-kBps = <2188000 17817600>;
576 cpu4_opp_1229mhz: opp-1228800000 {
577 opp-hz = /bits/ 64 <1228800000>;
578 opp-peak-kBps = <4068000 24576000>;
581 cpu4_opp_1344mhz: opp-1344000000 {
582 opp-hz = /bits/ 64 <1344000000>;
583 opp-peak-kBps = <4068000 24576000>;
586 cpu4_opp_1517mhz: opp-1516800000 {
587 opp-hz = /bits/ 64 <1516800000>;
588 opp-peak-kBps = <4068000 24576000>;
591 cpu4_opp_1651mhz: opp-1651200000 {
592 opp-hz = /bits/ 64 <1651200000>;
593 opp-peak-kBps = <6220000 38092800>;
596 cpu4_opp_1901mhz: opp-1900800000 {
597 opp-hz = /bits/ 64 <1900800000>;
598 opp-peak-kBps = <6220000 44851200>;
601 cpu4_opp_2054mhz: opp-2054400000 {
602 opp-hz = /bits/ 64 <2054400000>;
603 opp-peak-kBps = <6220000 44851200>;
606 cpu4_opp_2112mhz: opp-2112000000 {
607 opp-hz = /bits/ 64 <2112000000>;
608 opp-peak-kBps = <6220000 44851200>;
611 cpu4_opp_2131mhz: opp-2131200000 {
612 opp-hz = /bits/ 64 <2131200000>;
613 opp-peak-kBps = <6220000 44851200>;
616 cpu4_opp_2208mhz: opp-2208000000 {
617 opp-hz = /bits/ 64 <2208000000>;
618 opp-peak-kBps = <6220000 44851200>;
621 cpu4_opp_2400mhz: opp-2400000000 {
622 opp-hz = /bits/ 64 <2400000000>;
623 opp-peak-kBps = <8532000 48537600>;
626 cpu4_opp_2611mhz: opp-2611200000 {
627 opp-hz = /bits/ 64 <2611200000>;
628 opp-peak-kBps = <8532000 48537600>;
632 cpu7_opp_table: opp-table-cpu7 {
633 compatible = "operating-points-v2";
634 opp-shared;
636 cpu7_opp_806mhz: opp-806400000 {
637 opp-hz = /bits/ 64 <806400000>;
638 opp-peak-kBps = <1804000 9600000>;
641 cpu7_opp_1056mhz: opp-1056000000 {
642 opp-hz = /bits/ 64 <1056000000>;
643 opp-peak-kBps = <2188000 17817600>;
646 cpu7_opp_1325mhz: opp-1324800000 {
647 opp-hz = /bits/ 64 <1324800000>;
648 opp-peak-kBps = <4068000 24576000>;
651 cpu7_opp_1517mhz: opp-1516800000 {
652 opp-hz = /bits/ 64 <1516800000>;
653 opp-peak-kBps = <4068000 24576000>;
656 cpu7_opp_1766mhz: opp-1766400000 {
657 opp-hz = /bits/ 64 <1766400000>;
658 opp-peak-kBps = <6220000 38092800>;
661 cpu7_opp_1862mhz: opp-1862400000 {
662 opp-hz = /bits/ 64 <1862400000>;
663 opp-peak-kBps = <6220000 38092800>;
666 cpu7_opp_2035mhz: opp-2035200000 {
667 opp-hz = /bits/ 64 <2035200000>;
668 opp-peak-kBps = <6220000 38092800>;
671 cpu7_opp_2112mhz: opp-2112000000 {
672 opp-hz = /bits/ 64 <2112000000>;
673 opp-peak-kBps = <6220000 44851200>;
676 cpu7_opp_2208mhz: opp-2208000000 {
677 opp-hz = /bits/ 64 <2208000000>;
678 opp-peak-kBps = <6220000 44851200>;
681 cpu7_opp_2381mhz: opp-2380800000 {
682 opp-hz = /bits/ 64 <2380800000>;
683 opp-peak-kBps = <6832000 44851200>;
686 cpu7_opp_2400mhz: opp-2400000000 {
687 opp-hz = /bits/ 64 <2400000000>;
688 opp-peak-kBps = <8532000 48537600>;
691 cpu7_opp_2515mhz: opp-2515200000 {
692 opp-hz = /bits/ 64 <2515200000>;
693 opp-peak-kBps = <8532000 48537600>;
696 cpu7_opp_2707mhz: opp-2707200000 {
697 opp-hz = /bits/ 64 <2707200000>;
698 opp-peak-kBps = <8532000 48537600>;
701 cpu7_opp_3014mhz: opp-3014400000 {
702 opp-hz = /bits/ 64 <3014400000>;
703 opp-peak-kBps = <8532000 48537600>;
715 compatible = "qcom,scm-sc7280", "qcom,scm";
716 qcom,dload-mode = <&tcsr_2 0x13000>;
721 compatible = "qcom,sc7280-clk-virt";
722 #interconnect-cells = <2>;
723 qcom,bcm-voters = <&apps_bcm_voter>;
728 memory-region = <&smem_mem>;
732 smp2p-adsp {
735 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
741 qcom,local-pid = <0>;
742 qcom,remote-pid = <2>;
744 adsp_smp2p_out: master-kernel {
745 qcom,entry-name = "master-kernel";
746 #qcom,smem-state-cells = <1>;
749 adsp_smp2p_in: slave-kernel {
750 qcom,entry-name = "slave-kernel";
751 interrupt-controller;
752 #interrupt-cells = <2>;
756 smp2p-cdsp {
759 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
765 qcom,local-pid = <0>;
766 qcom,remote-pid = <5>;
768 cdsp_smp2p_out: master-kernel {
769 qcom,entry-name = "master-kernel";
770 #qcom,smem-state-cells = <1>;
773 cdsp_smp2p_in: slave-kernel {
774 qcom,entry-name = "slave-kernel";
775 interrupt-controller;
776 #interrupt-cells = <2>;
780 smp2p-mpss {
783 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
789 qcom,local-pid = <0>;
790 qcom,remote-pid = <1>;
792 modem_smp2p_out: master-kernel {
793 qcom,entry-name = "master-kernel";
794 #qcom,smem-state-cells = <1>;
797 modem_smp2p_in: slave-kernel {
798 qcom,entry-name = "slave-kernel";
799 interrupt-controller;
800 #interrupt-cells = <2>;
803 ipa_smp2p_out: ipa-ap-to-modem {
804 qcom,entry-name = "ipa";
805 #qcom,smem-state-cells = <1>;
808 ipa_smp2p_in: ipa-modem-to-ap {
809 qcom,entry-name = "ipa";
810 interrupt-controller;
811 #interrupt-cells = <2>;
815 smp2p-wpss {
818 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
824 qcom,local-pid = <0>;
825 qcom,remote-pid = <13>;
827 wpss_smp2p_out: master-kernel {
828 qcom,entry-name = "master-kernel";
829 #qcom,smem-state-cells = <1>;
832 wpss_smp2p_in: slave-kernel {
833 qcom,entry-name = "slave-kernel";
834 interrupt-controller;
835 #interrupt-cells = <2>;
838 wlan_smp2p_out: wlan-ap-to-wpss {
839 qcom,entry-name = "wlan";
840 #qcom,smem-state-cells = <1>;
843 wlan_smp2p_in: wlan-wpss-to-ap {
844 qcom,entry-name = "wlan";
845 interrupt-controller;
846 #interrupt-cells = <2>;
850 pmu-a55 {
851 compatible = "arm,cortex-a55-pmu";
855 pmu-a78 {
856 compatible = "arm,cortex-a78-pmu";
861 compatible = "arm,psci-1.0";
864 cpu_pd0: power-domain-cpu0 {
865 #power-domain-cells = <0>;
866 power-domains = <&cluster_pd>;
867 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
870 cpu_pd1: power-domain-cpu1 {
871 #power-domain-cells = <0>;
872 power-domains = <&cluster_pd>;
873 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
876 cpu_pd2: power-domain-cpu2 {
877 #power-domain-cells = <0>;
878 power-domains = <&cluster_pd>;
879 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
882 cpu_pd3: power-domain-cpu3 {
883 #power-domain-cells = <0>;
884 power-domains = <&cluster_pd>;
885 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
888 cpu_pd4: power-domain-cpu4 {
889 #power-domain-cells = <0>;
890 power-domains = <&cluster_pd>;
891 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
894 cpu_pd5: power-domain-cpu5 {
895 #power-domain-cells = <0>;
896 power-domains = <&cluster_pd>;
897 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
900 cpu_pd6: power-domain-cpu6 {
901 #power-domain-cells = <0>;
902 power-domains = <&cluster_pd>;
903 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
906 cpu_pd7: power-domain-cpu7 {
907 #power-domain-cells = <0>;
908 power-domains = <&cluster_pd>;
909 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
912 cluster_pd: power-domain-cluster {
913 #power-domain-cells = <0>;
914 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>;
918 qspi_opp_table: opp-table-qspi {
919 compatible = "operating-points-v2";
921 opp-75000000 {
922 opp-hz = /bits/ 64 <75000000>;
923 required-opps = <&rpmhpd_opp_low_svs>;
926 opp-150000000 {
927 opp-hz = /bits/ 64 <150000000>;
928 required-opps = <&rpmhpd_opp_svs>;
931 opp-200000000 {
932 opp-hz = /bits/ 64 <200000000>;
933 required-opps = <&rpmhpd_opp_svs_l1>;
936 opp-300000000 {
937 opp-hz = /bits/ 64 <300000000>;
938 required-opps = <&rpmhpd_opp_nom>;
942 qup_opp_table: opp-table-qup {
943 compatible = "operating-points-v2";
945 opp-75000000 {
946 opp-hz = /bits/ 64 <75000000>;
947 required-opps = <&rpmhpd_opp_low_svs>;
950 opp-100000000 {
951 opp-hz = /bits/ 64 <100000000>;
952 required-opps = <&rpmhpd_opp_svs>;
955 opp-128000000 {
956 opp-hz = /bits/ 64 <128000000>;
957 required-opps = <&rpmhpd_opp_nom>;
962 #address-cells = <2>;
963 #size-cells = <2>;
965 dma-ranges = <0 0 0 0 0x10 0>;
966 compatible = "simple-bus";
968 gcc: clock-controller@100000 {
969 compatible = "qcom,gcc-sc7280";
976 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
981 #clock-cells = <1>;
982 #reset-cells = <1>;
983 #power-domain-cells = <1>;
984 power-domains = <&rpmhpd SC7280_CX>;
988 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
991 interrupt-controller;
992 #interrupt-cells = <3>;
993 #mbox-cells = <2>;
997 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
1003 clock-names = "core";
1004 power-domains = <&rpmhpd SC7280_MX>;
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1008 gpu_speed_bin: gpu-speed-bin@1e9 {
1015 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
1016 pinctrl-names = "default", "sleep";
1017 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1018 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1023 reg-names = "hc", "cqhci";
1028 interrupt-names = "hc_irq", "pwr_irq";
1033 clock-names = "iface", "core", "xo";
1036 interconnect-names = "sdhc-ddr","cpu-sdhc";
1037 power-domains = <&rpmhpd SC7280_CX>;
1038 operating-points-v2 = <&sdhc1_opp_table>;
1040 bus-width = <8>;
1041 supports-cqe;
1042 dma-coherent;
1044 qcom,dll-config = <0x0007642c>;
1045 qcom,ddr-config = <0x80040868>;
1047 mmc-ddr-1_8v;
1048 mmc-hs200-1_8v;
1049 mmc-hs400-1_8v;
1050 mmc-hs400-enhanced-strobe;
1054 sdhc1_opp_table: opp-table {
1055 compatible = "operating-points-v2";
1057 opp-100000000 {
1058 opp-hz = /bits/ 64 <100000000>;
1059 required-opps = <&rpmhpd_opp_low_svs>;
1060 opp-peak-kBps = <1800000 400000>;
1061 opp-avg-kBps = <100000 0>;
1064 opp-384000000 {
1065 opp-hz = /bits/ 64 <384000000>;
1066 required-opps = <&rpmhpd_opp_nom>;
1067 opp-peak-kBps = <5400000 1600000>;
1068 opp-avg-kBps = <390000 0>;
1073 gpi_dma0: dma-controller@900000 {
1074 #dma-cells = <3>;
1075 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1089 dma-channels = <12>;
1090 dma-channel-mask = <0x7f>;
1096 compatible = "qcom,geni-se-qup";
1100 clock-names = "m-ahb", "s-ahb";
1101 #address-cells = <2>;
1102 #size-cells = <2>;
1108 compatible = "qcom,geni-i2c";
1111 clock-names = "se";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&qup_i2c0_data_clk>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1120 interconnect-names = "qup-core", "qup-config",
1121 "qup-memory";
1122 power-domains = <&rpmhpd SC7280_CX>;
1123 required-opps = <&rpmhpd_opp_low_svs>;
1126 dma-names = "tx", "rx";
1131 compatible = "qcom,geni-spi";
1134 clock-names = "se";
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 power-domains = <&rpmhpd SC7280_CX>;
1141 operating-points-v2 = <&qup_opp_table>;
1144 interconnect-names = "qup-core", "qup-config";
1147 dma-names = "tx", "rx";
1152 compatible = "qcom,geni-uart";
1155 clock-names = "se";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1159 power-domains = <&rpmhpd SC7280_CX>;
1160 operating-points-v2 = <&qup_opp_table>;
1163 interconnect-names = "qup-core", "qup-config";
1168 compatible = "qcom,geni-i2c";
1171 clock-names = "se";
1172 pinctrl-names = "default";
1173 pinctrl-0 = <&qup_i2c1_data_clk>;
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1180 interconnect-names = "qup-core", "qup-config",
1181 "qup-memory";
1182 power-domains = <&rpmhpd SC7280_CX>;
1183 required-opps = <&rpmhpd_opp_low_svs>;
1186 dma-names = "tx", "rx";
1191 compatible = "qcom,geni-spi";
1194 clock-names = "se";
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 power-domains = <&rpmhpd SC7280_CX>;
1201 operating-points-v2 = <&qup_opp_table>;
1204 interconnect-names = "qup-core", "qup-config";
1207 dma-names = "tx", "rx";
1212 compatible = "qcom,geni-uart";
1215 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1219 power-domains = <&rpmhpd SC7280_CX>;
1220 operating-points-v2 = <&qup_opp_table>;
1223 interconnect-names = "qup-core", "qup-config";
1228 compatible = "qcom,geni-i2c";
1231 clock-names = "se";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_i2c2_data_clk>;
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1240 interconnect-names = "qup-core", "qup-config",
1241 "qup-memory";
1242 power-domains = <&rpmhpd SC7280_CX>;
1243 required-opps = <&rpmhpd_opp_low_svs>;
1246 dma-names = "tx", "rx";
1251 compatible = "qcom,geni-spi";
1254 clock-names = "se";
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1260 power-domains = <&rpmhpd SC7280_CX>;
1261 operating-points-v2 = <&qup_opp_table>;
1264 interconnect-names = "qup-core", "qup-config";
1267 dma-names = "tx", "rx";
1272 compatible = "qcom,geni-uart";
1275 clock-names = "se";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1279 power-domains = <&rpmhpd SC7280_CX>;
1280 operating-points-v2 = <&qup_opp_table>;
1283 interconnect-names = "qup-core", "qup-config";
1288 compatible = "qcom,geni-i2c";
1291 clock-names = "se";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&qup_i2c3_data_clk>;
1295 #address-cells = <1>;
1296 #size-cells = <0>;
1300 interconnect-names = "qup-core", "qup-config",
1301 "qup-memory";
1302 power-domains = <&rpmhpd SC7280_CX>;
1303 required-opps = <&rpmhpd_opp_low_svs>;
1306 dma-names = "tx", "rx";
1311 compatible = "qcom,geni-spi";
1314 clock-names = "se";
1315 pinctrl-names = "default";
1316 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1318 #address-cells = <1>;
1319 #size-cells = <0>;
1320 power-domains = <&rpmhpd SC7280_CX>;
1321 operating-points-v2 = <&qup_opp_table>;
1324 interconnect-names = "qup-core", "qup-config";
1327 dma-names = "tx", "rx";
1332 compatible = "qcom,geni-uart";
1335 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1339 power-domains = <&rpmhpd SC7280_CX>;
1340 operating-points-v2 = <&qup_opp_table>;
1343 interconnect-names = "qup-core", "qup-config";
1348 compatible = "qcom,geni-i2c";
1351 clock-names = "se";
1352 pinctrl-names = "default";
1353 pinctrl-0 = <&qup_i2c4_data_clk>;
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1360 interconnect-names = "qup-core", "qup-config",
1361 "qup-memory";
1362 power-domains = <&rpmhpd SC7280_CX>;
1363 required-opps = <&rpmhpd_opp_low_svs>;
1366 dma-names = "tx", "rx";
1371 compatible = "qcom,geni-spi";
1374 clock-names = "se";
1375 pinctrl-names = "default";
1376 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1380 power-domains = <&rpmhpd SC7280_CX>;
1381 operating-points-v2 = <&qup_opp_table>;
1384 interconnect-names = "qup-core", "qup-config";
1387 dma-names = "tx", "rx";
1392 compatible = "qcom,geni-uart";
1395 clock-names = "se";
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1399 power-domains = <&rpmhpd SC7280_CX>;
1400 operating-points-v2 = <&qup_opp_table>;
1403 interconnect-names = "qup-core", "qup-config";
1408 compatible = "qcom,geni-i2c";
1411 clock-names = "se";
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&qup_i2c5_data_clk>;
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1420 interconnect-names = "qup-core", "qup-config",
1421 "qup-memory";
1422 power-domains = <&rpmhpd SC7280_CX>;
1423 required-opps = <&rpmhpd_opp_low_svs>;
1426 dma-names = "tx", "rx";
1431 compatible = "qcom,geni-spi";
1434 clock-names = "se";
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1438 #address-cells = <1>;
1439 #size-cells = <0>;
1440 power-domains = <&rpmhpd SC7280_CX>;
1441 operating-points-v2 = <&qup_opp_table>;
1444 interconnect-names = "qup-core", "qup-config";
1447 dma-names = "tx", "rx";
1452 compatible = "qcom,geni-debug-uart";
1455 clock-names = "se";
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1459 power-domains = <&rpmhpd SC7280_CX>;
1460 operating-points-v2 = <&qup_opp_table>;
1463 interconnect-names = "qup-core", "qup-config";
1468 compatible = "qcom,geni-i2c";
1471 clock-names = "se";
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&qup_i2c6_data_clk>;
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1480 interconnect-names = "qup-core", "qup-config",
1481 "qup-memory";
1482 power-domains = <&rpmhpd SC7280_CX>;
1483 required-opps = <&rpmhpd_opp_low_svs>;
1486 dma-names = "tx", "rx";
1491 compatible = "qcom,geni-spi";
1494 clock-names = "se";
1495 pinctrl-names = "default";
1496 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1500 power-domains = <&rpmhpd SC7280_CX>;
1501 operating-points-v2 = <&qup_opp_table>;
1504 interconnect-names = "qup-core", "qup-config";
1507 dma-names = "tx", "rx";
1512 compatible = "qcom,geni-uart";
1515 clock-names = "se";
1516 pinctrl-names = "default";
1517 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1519 power-domains = <&rpmhpd SC7280_CX>;
1520 operating-points-v2 = <&qup_opp_table>;
1523 interconnect-names = "qup-core", "qup-config";
1528 compatible = "qcom,geni-i2c";
1531 clock-names = "se";
1532 pinctrl-names = "default";
1533 pinctrl-0 = <&qup_i2c7_data_clk>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1540 interconnect-names = "qup-core", "qup-config",
1541 "qup-memory";
1542 power-domains = <&rpmhpd SC7280_CX>;
1543 required-opps = <&rpmhpd_opp_low_svs>;
1546 dma-names = "tx", "rx";
1551 compatible = "qcom,geni-spi";
1554 clock-names = "se";
1555 pinctrl-names = "default";
1556 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1560 power-domains = <&rpmhpd SC7280_CX>;
1561 operating-points-v2 = <&qup_opp_table>;
1564 interconnect-names = "qup-core", "qup-config";
1567 dma-names = "tx", "rx";
1572 compatible = "qcom,geni-uart";
1575 clock-names = "se";
1576 pinctrl-names = "default";
1577 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1579 power-domains = <&rpmhpd SC7280_CX>;
1580 operating-points-v2 = <&qup_opp_table>;
1583 interconnect-names = "qup-core", "qup-config";
1588 gpi_dma1: dma-controller@a00000 {
1589 #dma-cells = <3>;
1590 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1604 dma-channels = <12>;
1605 dma-channel-mask = <0x1e>;
1611 compatible = "qcom,geni-se-qup";
1615 clock-names = "m-ahb", "s-ahb";
1616 #address-cells = <2>;
1617 #size-cells = <2>;
1623 compatible = "qcom,geni-i2c";
1626 clock-names = "se";
1627 pinctrl-names = "default";
1628 pinctrl-0 = <&qup_i2c8_data_clk>;
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1635 interconnect-names = "qup-core", "qup-config",
1636 "qup-memory";
1637 power-domains = <&rpmhpd SC7280_CX>;
1638 required-opps = <&rpmhpd_opp_low_svs>;
1641 dma-names = "tx", "rx";
1646 compatible = "qcom,geni-spi";
1649 clock-names = "se";
1650 pinctrl-names = "default";
1651 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1653 #address-cells = <1>;
1654 #size-cells = <0>;
1655 power-domains = <&rpmhpd SC7280_CX>;
1656 operating-points-v2 = <&qup_opp_table>;
1659 interconnect-names = "qup-core", "qup-config";
1662 dma-names = "tx", "rx";
1667 compatible = "qcom,geni-uart";
1670 clock-names = "se";
1671 pinctrl-names = "default";
1672 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1674 power-domains = <&rpmhpd SC7280_CX>;
1675 operating-points-v2 = <&qup_opp_table>;
1678 interconnect-names = "qup-core", "qup-config";
1683 compatible = "qcom,geni-i2c";
1686 clock-names = "se";
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&qup_i2c9_data_clk>;
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1695 interconnect-names = "qup-core", "qup-config",
1696 "qup-memory";
1697 power-domains = <&rpmhpd SC7280_CX>;
1698 required-opps = <&rpmhpd_opp_low_svs>;
1701 dma-names = "tx", "rx";
1706 compatible = "qcom,geni-spi";
1709 clock-names = "se";
1710 pinctrl-names = "default";
1711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1713 #address-cells = <1>;
1714 #size-cells = <0>;
1715 power-domains = <&rpmhpd SC7280_CX>;
1716 operating-points-v2 = <&qup_opp_table>;
1719 interconnect-names = "qup-core", "qup-config";
1722 dma-names = "tx", "rx";
1727 compatible = "qcom,geni-uart";
1730 clock-names = "se";
1731 pinctrl-names = "default";
1732 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1734 power-domains = <&rpmhpd SC7280_CX>;
1735 operating-points-v2 = <&qup_opp_table>;
1738 interconnect-names = "qup-core", "qup-config";
1743 compatible = "qcom,geni-i2c";
1746 clock-names = "se";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_i2c10_data_clk>;
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1755 interconnect-names = "qup-core", "qup-config",
1756 "qup-memory";
1757 power-domains = <&rpmhpd SC7280_CX>;
1758 required-opps = <&rpmhpd_opp_low_svs>;
1761 dma-names = "tx", "rx";
1766 compatible = "qcom,geni-spi";
1769 clock-names = "se";
1770 pinctrl-names = "default";
1771 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1773 #address-cells = <1>;
1774 #size-cells = <0>;
1775 power-domains = <&rpmhpd SC7280_CX>;
1776 operating-points-v2 = <&qup_opp_table>;
1779 interconnect-names = "qup-core", "qup-config";
1782 dma-names = "tx", "rx";
1787 compatible = "qcom,geni-uart";
1790 clock-names = "se";
1791 pinctrl-names = "default";
1792 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1794 power-domains = <&rpmhpd SC7280_CX>;
1795 operating-points-v2 = <&qup_opp_table>;
1798 interconnect-names = "qup-core", "qup-config";
1803 compatible = "qcom,geni-i2c";
1806 clock-names = "se";
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&qup_i2c11_data_clk>;
1810 #address-cells = <1>;
1811 #size-cells = <0>;
1815 interconnect-names = "qup-core", "qup-config",
1816 "qup-memory";
1817 power-domains = <&rpmhpd SC7280_CX>;
1818 required-opps = <&rpmhpd_opp_low_svs>;
1821 dma-names = "tx", "rx";
1826 compatible = "qcom,geni-spi";
1829 clock-names = "se";
1830 pinctrl-names = "default";
1831 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1835 power-domains = <&rpmhpd SC7280_CX>;
1836 operating-points-v2 = <&qup_opp_table>;
1839 interconnect-names = "qup-core", "qup-config";
1842 dma-names = "tx", "rx";
1847 compatible = "qcom,geni-uart";
1850 clock-names = "se";
1851 pinctrl-names = "default";
1852 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1854 power-domains = <&rpmhpd SC7280_CX>;
1855 operating-points-v2 = <&qup_opp_table>;
1858 interconnect-names = "qup-core", "qup-config";
1863 compatible = "qcom,geni-i2c";
1866 clock-names = "se";
1867 pinctrl-names = "default";
1868 pinctrl-0 = <&qup_i2c12_data_clk>;
1870 #address-cells = <1>;
1871 #size-cells = <0>;
1875 interconnect-names = "qup-core", "qup-config",
1876 "qup-memory";
1877 power-domains = <&rpmhpd SC7280_CX>;
1878 required-opps = <&rpmhpd_opp_low_svs>;
1881 dma-names = "tx", "rx";
1886 compatible = "qcom,geni-spi";
1889 clock-names = "se";
1890 pinctrl-names = "default";
1891 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1893 #address-cells = <1>;
1894 #size-cells = <0>;
1895 power-domains = <&rpmhpd SC7280_CX>;
1896 operating-points-v2 = <&qup_opp_table>;
1899 interconnect-names = "qup-core", "qup-config";
1902 dma-names = "tx", "rx";
1907 compatible = "qcom,geni-uart";
1910 clock-names = "se";
1911 pinctrl-names = "default";
1912 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1914 power-domains = <&rpmhpd SC7280_CX>;
1915 operating-points-v2 = <&qup_opp_table>;
1918 interconnect-names = "qup-core", "qup-config";
1923 compatible = "qcom,geni-i2c";
1926 clock-names = "se";
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&qup_i2c13_data_clk>;
1930 #address-cells = <1>;
1931 #size-cells = <0>;
1935 interconnect-names = "qup-core", "qup-config",
1936 "qup-memory";
1937 power-domains = <&rpmhpd SC7280_CX>;
1938 required-opps = <&rpmhpd_opp_low_svs>;
1941 dma-names = "tx", "rx";
1946 compatible = "qcom,geni-spi";
1949 clock-names = "se";
1950 pinctrl-names = "default";
1951 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1953 #address-cells = <1>;
1954 #size-cells = <0>;
1955 power-domains = <&rpmhpd SC7280_CX>;
1956 operating-points-v2 = <&qup_opp_table>;
1959 interconnect-names = "qup-core", "qup-config";
1962 dma-names = "tx", "rx";
1967 compatible = "qcom,geni-uart";
1970 clock-names = "se";
1971 pinctrl-names = "default";
1972 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1974 power-domains = <&rpmhpd SC7280_CX>;
1975 operating-points-v2 = <&qup_opp_table>;
1978 interconnect-names = "qup-core", "qup-config";
1983 compatible = "qcom,geni-i2c";
1986 clock-names = "se";
1987 pinctrl-names = "default";
1988 pinctrl-0 = <&qup_i2c14_data_clk>;
1990 #address-cells = <1>;
1991 #size-cells = <0>;
1995 interconnect-names = "qup-core", "qup-config",
1996 "qup-memory";
1997 power-domains = <&rpmhpd SC7280_CX>;
1998 required-opps = <&rpmhpd_opp_low_svs>;
2001 dma-names = "tx", "rx";
2006 compatible = "qcom,geni-spi";
2009 clock-names = "se";
2010 pinctrl-names = "default";
2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2013 #address-cells = <1>;
2014 #size-cells = <0>;
2015 power-domains = <&rpmhpd SC7280_CX>;
2016 operating-points-v2 = <&qup_opp_table>;
2019 interconnect-names = "qup-core", "qup-config";
2022 dma-names = "tx", "rx";
2027 compatible = "qcom,geni-uart";
2030 clock-names = "se";
2031 pinctrl-names = "default";
2032 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2034 power-domains = <&rpmhpd SC7280_CX>;
2035 operating-points-v2 = <&qup_opp_table>;
2038 interconnect-names = "qup-core", "qup-config";
2043 compatible = "qcom,geni-i2c";
2046 clock-names = "se";
2047 pinctrl-names = "default";
2048 pinctrl-0 = <&qup_i2c15_data_clk>;
2050 #address-cells = <1>;
2051 #size-cells = <0>;
2055 interconnect-names = "qup-core", "qup-config",
2056 "qup-memory";
2057 power-domains = <&rpmhpd SC7280_CX>;
2058 required-opps = <&rpmhpd_opp_low_svs>;
2061 dma-names = "tx", "rx";
2066 compatible = "qcom,geni-spi";
2069 clock-names = "se";
2070 pinctrl-names = "default";
2071 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2073 #address-cells = <1>;
2074 #size-cells = <0>;
2075 power-domains = <&rpmhpd SC7280_CX>;
2076 operating-points-v2 = <&qup_opp_table>;
2079 interconnect-names = "qup-core", "qup-config";
2082 dma-names = "tx", "rx";
2087 compatible = "qcom,geni-uart";
2090 clock-names = "se";
2091 pinctrl-names = "default";
2092 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2094 power-domains = <&rpmhpd SC7280_CX>;
2095 operating-points-v2 = <&qup_opp_table>;
2098 interconnect-names = "qup-core", "qup-config";
2104 compatible = "qcom,sc7280-trng", "qcom,trng";
2110 compatible = "qcom,sc7280-cnoc2";
2111 #interconnect-cells = <2>;
2112 qcom,bcm-voters = <&apps_bcm_voter>;
2117 compatible = "qcom,sc7280-cnoc3";
2118 #interconnect-cells = <2>;
2119 qcom,bcm-voters = <&apps_bcm_voter>;
2124 compatible = "qcom,sc7280-mc-virt";
2125 #interconnect-cells = <2>;
2126 qcom,bcm-voters = <&apps_bcm_voter>;
2131 compatible = "qcom,sc7280-system-noc";
2132 #interconnect-cells = <2>;
2133 qcom,bcm-voters = <&apps_bcm_voter>;
2137 compatible = "qcom,sc7280-aggre1-noc";
2139 #interconnect-cells = <2>;
2140 qcom,bcm-voters = <&apps_bcm_voter>;
2147 compatible = "qcom,sc7280-aggre2-noc";
2148 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&apps_bcm_voter>;
2155 compatible = "qcom,sc7280-mmss-noc";
2156 #interconnect-cells = <2>;
2157 qcom,bcm-voters = <&apps_bcm_voter>;
2161 compatible = "qcom,wcn6750-wifi";
2197 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2199 qcom,smem-states = <&wlan_smp2p_out 0>;
2200 qcom,smem-state-names = "wlan-smp2p-out";
2204 compatible = "qcom,pcie-sc7280";
2211 reg-names = "parf", "dbi", "elbi", "atu", "config";
2213 linux,pci-domain = <1>;
2214 bus-range = <0x00 0xff>;
2215 num-lanes = <2>;
2217 #address-cells = <3>;
2218 #size-cells = <2>;
2231 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2233 #interrupt-cells = <1>;
2234 interrupt-map-mask = <0 0 0 0x7>;
2235 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2254 clock-names = "pipe",
2268 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2269 assigned-clock-rates = <19200000>;
2272 reset-names = "pci";
2274 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2277 phy-names = "pciephy";
2279 pinctrl-names = "default";
2280 pinctrl-0 = <&pcie1_clkreq_n>;
2282 dma-coherent;
2284 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2292 bus-range = <0x01 0xff>;
2294 #address-cells = <3>;
2295 #size-cells = <2>;
2301 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2308 clock-names = "aux",
2314 clock-output-names = "pcie_1_pipe_clk";
2315 #clock-cells = <0>;
2317 #phy-cells = <0>;
2320 reset-names = "phy";
2322 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2323 assigned-clock-rates = <100000000>;
2329 compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
2330 "jedec,ufs-2.0";
2334 phy-names = "ufsphy";
2335 lanes-per-direction = <2>;
2336 #reset-cells = <1>;
2338 reset-names = "rst";
2340 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2341 required-opps = <&rpmhpd_opp_nom>;
2344 dma-coherent;
2350 interconnect-names = "ufs-ddr", "cpu-ufs";
2360 clock-names = "core_clk",
2369 operating-points-v2 = <&ufs_opp_table>;
2375 ufs_opp_table: opp-table {
2376 compatible = "operating-points-v2";
2378 opp-75000000 {
2379 opp-hz = /bits/ 64 <75000000>,
2387 required-opps = <&rpmhpd_opp_low_svs>;
2390 opp-150000000 {
2391 opp-hz = /bits/ 64 <150000000>,
2399 required-opps = <&rpmhpd_opp_svs>;
2402 opp-300000000 {
2403 opp-hz = /bits/ 64 <300000000>,
2411 required-opps = <&rpmhpd_opp_nom>;
2417 compatible = "qcom,sc7280-qmp-ufs-phy";
2422 clock-names = "ref", "ref_aux", "qref";
2424 power-domains = <&rpmhpd SC7280_MX>;
2427 reset-names = "ufsphy";
2429 #clock-cells = <1>;
2430 #phy-cells = <0>;
2436 compatible = "qcom,sc7280-inline-crypto-engine",
2437 "qcom,inline-crypto-engine";
2442 cryptobam: dma-controller@1dc4000 {
2443 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2446 #dma-cells = <1>;
2450 qcom,controlled-remotely;
2451 num-channels = <16>;
2452 qcom,num-ees = <4>;
2456 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
2459 dma-names = "rx", "tx";
2463 interconnect-names = "memory";
2467 compatible = "qcom,sc7280-ipa";
2474 reg-names = "ipa-reg",
2475 "ipa-shared",
2478 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2482 interrupt-names = "ipa",
2484 "ipa-clock-query",
2485 "ipa-setup-ready";
2488 clock-names = "core";
2492 interconnect-names = "memory",
2497 qcom,smem-states = <&ipa_smp2p_out 0>,
2499 qcom,smem-state-names = "ipa-clock-enabled-valid",
2500 "ipa-clock-enabled";
2506 compatible = "qcom,tcsr-mutex";
2508 #hwlock-cells = <1>;
2512 compatible = "qcom,sc7280-tcsr", "syscon";
2517 compatible = "qcom,sc7280-tcsr", "syscon";
2522 compatible = "qcom,sc7280-lpasscc";
2525 reg-names = "qdsp6ss", "top_cc";
2527 clock-names = "iface";
2528 #clock-cells = <1>;
2533 compatible = "qcom,sc7280-lpass-rx-macro";
2536 pinctrl-names = "default";
2537 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2542 clock-names = "mclk", "npl", "fsgen";
2544 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2546 power-domain-names = "macro", "dcodec";
2548 #clock-cells = <0>;
2549 #sound-dai-cells = <1>;
2555 compatible = "qcom,soundwire-v1.6.0";
2560 clock-names = "iface";
2562 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5>;
2566 reset-names = "swr_audio_cgcr";
2568 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2569 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2570 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2571 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2572 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2573 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2574 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2575 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2576 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2578 #sound-dai-cells = <1>;
2579 #address-cells = <2>;
2580 #size-cells = <0>;
2586 compatible = "qcom,sc7280-lpass-tx-macro";
2589 pinctrl-names = "default";
2590 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2595 clock-names = "mclk", "npl", "fsgen";
2597 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2599 power-domain-names = "macro", "dcodec";
2601 #clock-cells = <0>;
2602 #sound-dai-cells = <1>;
2608 compatible = "qcom,soundwire-v1.6.0";
2611 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2614 clock-names = "iface";
2616 qcom,din-ports = <3>;
2617 qcom,dout-ports = <0>;
2620 reset-names = "swr_audio_cgcr";
2622 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2623 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2624 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2625 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2626 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2627 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2628 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2629 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2630 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2632 #sound-dai-cells = <1>;
2633 #address-cells = <2>;
2634 #size-cells = <0>;
2639 lpass_audiocc: clock-controller@3300000 {
2640 compatible = "qcom,sc7280-lpassaudiocc";
2645 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2646 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2647 #clock-cells = <1>;
2648 #power-domain-cells = <1>;
2649 #reset-cells = <1>;
2653 compatible = "qcom,sc7280-lpass-va-macro";
2657 clock-names = "mclk";
2659 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2661 power-domain-names = "macro", "dcodec";
2663 #clock-cells = <0>;
2664 #sound-dai-cells = <1>;
2669 lpass_aon: clock-controller@3380000 {
2670 compatible = "qcom,sc7280-lpassaoncc";
2675 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2676 #clock-cells = <1>;
2677 #power-domain-cells = <1>;
2681 lpass_core: clock-controller@3900000 {
2682 compatible = "qcom,sc7280-lpasscorecc";
2685 clock-names = "bi_tcxo";
2686 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2687 #clock-cells = <1>;
2688 #power-domain-cells = <1>;
2693 compatible = "qcom,sc7280-lpass-cpu";
2701 reg-names = "lpass-hdmiif",
2702 "lpass-lpaif",
2703 "lpass-rxtx-cdc-dma-lpm",
2704 "lpass-rxtx-lpaif",
2705 "lpass-va-lpaif",
2706 "lpass-va-cdc-dma-lpm";
2712 power-domains = <&rpmhpd SC7280_LCX>;
2713 power-domain-names = "lcx";
2714 required-opps = <&rpmhpd_opp_nom>;
2726 clock-names = "aon_cc_audio_hm_h",
2737 #sound-dai-cells = <1>;
2738 #address-cells = <1>;
2739 #size-cells = <0>;
2745 interrupt-names = "lpass-irq-lpaif",
2746 "lpass-irq-hdmi",
2747 "lpass-irq-vaif",
2748 "lpass-irq-rxtxif";
2753 slimbam: dma-controller@3a84000 {
2754 compatible = "qcom,bam-v1.7.0";
2757 #dma-cells = <1>;
2758 qcom,controlled-remotely;
2759 num-channels = <31>;
2761 qcom,num-ees = <2>;
2766 slim: slim-ngd@3ac0000 {
2767 compatible = "qcom,slim-ngd-v1.5.0";
2771 dma-names = "rx", "tx";
2773 #address-cells = <1>;
2774 #size-cells = <0>;
2778 lpass_hm: clock-controller@3c00000 {
2779 compatible = "qcom,sc7280-lpasshm";
2782 clock-names = "bi_tcxo";
2783 #clock-cells = <1>;
2784 #power-domain-cells = <1>;
2790 compatible = "qcom,sc7280-lpass-ag-noc";
2791 #interconnect-cells = <2>;
2792 qcom,bcm-voters = <&apps_bcm_voter>;
2796 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2799 gpio-controller;
2800 #gpio-cells = <2>;
2801 gpio-ranges = <&lpass_tlmm 0 0 15>;
2803 lpass_dmic01_clk: dmic01-clk-state {
2808 lpass_dmic01_data: dmic01-data-state {
2813 lpass_dmic23_clk: dmic23-clk-state {
2818 lpass_dmic23_data: dmic23-data-state {
2823 lpass_rx_swr_clk: rx-swr-clk-state {
2828 lpass_rx_swr_data: rx-swr-data-state {
2833 lpass_tx_swr_clk: tx-swr-clk-state {
2838 lpass_tx_swr_data: tx-swr-data-state {
2845 compatible = "qcom,adreno-635.0", "qcom,adreno";
2849 reg-names = "kgsl_3d0_reg_memory",
2855 operating-points-v2 = <&gpu_opp_table>;
2858 interconnect-names = "gfx-mem";
2859 #cooling-cells = <2>;
2861 nvmem-cells = <&gpu_speed_bin>;
2862 nvmem-cell-names = "speed_bin";
2866 gpu_zap_shader: zap-shader {
2867 memory-region = <&gpu_zap_mem>;
2870 gpu_opp_table: opp-table {
2871 compatible = "operating-points-v2";
2873 opp-315000000 {
2874 opp-hz = /bits/ 64 <315000000>;
2875 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2876 opp-peak-kBps = <1804000>;
2877 opp-supported-hw = <0x17>;
2880 opp-450000000 {
2881 opp-hz = /bits/ 64 <450000000>;
2882 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2883 opp-peak-kBps = <4068000>;
2884 opp-supported-hw = <0x17>;
2888 opp-550000000-0 {
2889 opp-hz = /bits/ 64 <550000000>;
2890 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2891 opp-peak-kBps = <8368000>;
2892 opp-supported-hw = <0x01>;
2895 opp-550000000-1 {
2896 opp-hz = /bits/ 64 <550000000>;
2897 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2898 opp-peak-kBps = <6832000>;
2899 opp-supported-hw = <0x16>;
2902 opp-608000000 {
2903 opp-hz = /bits/ 64 <608000000>;
2904 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2905 opp-peak-kBps = <8368000>;
2906 opp-supported-hw = <0x16>;
2909 opp-700000000 {
2910 opp-hz = /bits/ 64 <700000000>;
2911 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2912 opp-peak-kBps = <8532000>;
2913 opp-supported-hw = <0x06>;
2916 opp-812000000 {
2917 opp-hz = /bits/ 64 <812000000>;
2918 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2919 opp-peak-kBps = <8532000>;
2920 opp-supported-hw = <0x06>;
2923 opp-840000000 {
2924 opp-hz = /bits/ 64 <840000000>;
2925 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2926 opp-peak-kBps = <8532000>;
2927 opp-supported-hw = <0x02>;
2930 opp-900000000 {
2931 opp-hz = /bits/ 64 <900000000>;
2932 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2933 opp-peak-kBps = <8532000>;
2934 opp-supported-hw = <0x02>;
2940 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2944 reg-names = "gmu", "rscc", "gmu_pdc";
2947 interrupt-names = "hfi", "gmu";
2955 clock-names = "gmu",
2962 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2964 power-domain-names = "cx",
2967 operating-points-v2 = <&gmu_opp_table>;
2969 gmu_opp_table: opp-table {
2970 compatible = "operating-points-v2";
2972 opp-200000000 {
2973 opp-hz = /bits/ 64 <200000000>;
2974 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2979 gpucc: clock-controller@3d90000 {
2980 compatible = "qcom,sc7280-gpucc";
2985 clock-names = "bi_tcxo",
2988 #clock-cells = <1>;
2989 #reset-cells = <1>;
2990 #power-domain-cells = <1>;
2994 compatible = "qcom,sc7280-dcc", "qcom,dcc";
3000 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
3001 "qcom,smmu-500", "arm,mmu-500";
3003 #iommu-cells = <2>;
3004 #global-interrupts = <2>;
3025 clock-names = "gcc_gpu_memnoc_gfx_clk",
3033 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3034 dma-coherent;
3038 compatible = "qcom,sc7280-tbu";
3040 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3044 compatible = "qcom,sc7280-tbu";
3046 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3050 compatible = "qcom,sc7280-mpss-pas";
3053 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3059 interrupt-names = "wdog", "fatal", "ready", "handover",
3060 "stop-ack", "shutdown-ack";
3063 clock-names = "xo";
3065 power-domains = <&rpmhpd SC7280_CX>,
3067 power-domain-names = "cx", "mss";
3069 memory-region = <&mpss_mem>;
3073 qcom,smem-states = <&modem_smp2p_out 0>;
3074 qcom,smem-state-names = "stop";
3078 glink-edge {
3079 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3085 qcom,remote-pid = <1>;
3090 compatible = "arm,coresight-stm", "arm,primecell";
3093 reg-names = "stm-base", "stm-stimulus-base";
3096 clock-names = "apb_pclk";
3098 out-ports {
3101 remote-endpoint = <&funnel0_in7>;
3108 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3112 clock-names = "apb_pclk";
3114 out-ports {
3117 remote-endpoint = <&merge_funnel_in0>;
3122 in-ports {
3123 #address-cells = <1>;
3124 #size-cells = <0>;
3129 remote-endpoint = <&stm_out>;
3136 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3140 clock-names = "apb_pclk";
3142 out-ports {
3145 remote-endpoint = <&merge_funnel_in1>;
3150 in-ports {
3151 #address-cells = <1>;
3152 #size-cells = <0>;
3157 remote-endpoint = <&apss_merge_funnel_out>;
3164 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3168 clock-names = "apb_pclk";
3170 out-ports {
3173 remote-endpoint = <&swao_funnel_in>;
3178 in-ports {
3179 #address-cells = <1>;
3180 #size-cells = <0>;
3185 remote-endpoint = <&funnel0_out>;
3192 remote-endpoint = <&funnel1_out>;
3199 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3203 clock-names = "apb_pclk";
3205 out-ports {
3208 remote-endpoint = <&etr_in>;
3213 in-ports {
3216 remote-endpoint = <&swao_replicator_out>;
3223 compatible = "arm,coresight-tmc", "arm,primecell";
3228 clock-names = "apb_pclk";
3229 arm,scatter-gather;
3231 in-ports {
3234 remote-endpoint = <&replicator_out>;
3241 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3245 clock-names = "apb_pclk";
3247 out-ports {
3250 remote-endpoint = <&etf_in>;
3255 in-ports {
3256 #address-cells = <1>;
3257 #size-cells = <0>;
3262 remote-endpoint = <&merge_funnel_out>;
3269 compatible = "arm,coresight-tmc", "arm,primecell";
3273 clock-names = "apb_pclk";
3275 out-ports {
3278 remote-endpoint = <&swao_replicator_in>;
3283 in-ports {
3286 remote-endpoint = <&swao_funnel_out>;
3293 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3297 clock-names = "apb_pclk";
3298 qcom,replicator-loses-context;
3300 out-ports {
3303 remote-endpoint = <&replicator_in>;
3308 in-ports {
3311 remote-endpoint = <&etf_out>;
3318 compatible = "arm,coresight-etm4x", "arm,primecell";
3324 clock-names = "apb_pclk";
3325 arm,coresight-loses-context-with-cpu;
3326 qcom,skip-power-up;
3328 out-ports {
3331 remote-endpoint = <&apss_funnel_in0>;
3338 compatible = "arm,coresight-etm4x", "arm,primecell";
3344 clock-names = "apb_pclk";
3345 arm,coresight-loses-context-with-cpu;
3346 qcom,skip-power-up;
3348 out-ports {
3351 remote-endpoint = <&apss_funnel_in1>;
3358 compatible = "arm,coresight-etm4x", "arm,primecell";
3364 clock-names = "apb_pclk";
3365 arm,coresight-loses-context-with-cpu;
3366 qcom,skip-power-up;
3368 out-ports {
3371 remote-endpoint = <&apss_funnel_in2>;
3378 compatible = "arm,coresight-etm4x", "arm,primecell";
3384 clock-names = "apb_pclk";
3385 arm,coresight-loses-context-with-cpu;
3386 qcom,skip-power-up;
3388 out-ports {
3391 remote-endpoint = <&apss_funnel_in3>;
3398 compatible = "arm,coresight-etm4x", "arm,primecell";
3404 clock-names = "apb_pclk";
3405 arm,coresight-loses-context-with-cpu;
3406 qcom,skip-power-up;
3408 out-ports {
3411 remote-endpoint = <&apss_funnel_in4>;
3418 compatible = "arm,coresight-etm4x", "arm,primecell";
3424 clock-names = "apb_pclk";
3425 arm,coresight-loses-context-with-cpu;
3426 qcom,skip-power-up;
3428 out-ports {
3431 remote-endpoint = <&apss_funnel_in5>;
3438 compatible = "arm,coresight-etm4x", "arm,primecell";
3444 clock-names = "apb_pclk";
3445 arm,coresight-loses-context-with-cpu;
3446 qcom,skip-power-up;
3448 out-ports {
3451 remote-endpoint = <&apss_funnel_in6>;
3458 compatible = "arm,coresight-etm4x", "arm,primecell";
3464 clock-names = "apb_pclk";
3465 arm,coresight-loses-context-with-cpu;
3466 qcom,skip-power-up;
3468 out-ports {
3471 remote-endpoint = <&apss_funnel_in7>;
3478 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3482 clock-names = "apb_pclk";
3484 out-ports {
3487 remote-endpoint = <&apss_merge_funnel_in>;
3492 in-ports {
3493 #address-cells = <1>;
3494 #size-cells = <0>;
3499 remote-endpoint = <&etm0_out>;
3506 remote-endpoint = <&etm1_out>;
3513 remote-endpoint = <&etm2_out>;
3520 remote-endpoint = <&etm3_out>;
3527 remote-endpoint = <&etm4_out>;
3534 remote-endpoint = <&etm5_out>;
3541 remote-endpoint = <&etm6_out>;
3548 remote-endpoint = <&etm7_out>;
3555 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3559 clock-names = "apb_pclk";
3561 out-ports {
3564 remote-endpoint = <&funnel1_in4>;
3569 in-ports {
3572 remote-endpoint = <&apss_funnel_out>;
3579 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3580 pinctrl-names = "default", "sleep";
3581 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3582 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3590 interrupt-names = "hc_irq", "pwr_irq";
3595 clock-names = "iface", "core", "xo";
3598 interconnect-names = "sdhc-ddr","cpu-sdhc";
3599 power-domains = <&rpmhpd SC7280_CX>;
3600 operating-points-v2 = <&sdhc2_opp_table>;
3602 bus-width = <4>;
3603 dma-coherent;
3605 qcom,dll-config = <0x0007642c>;
3609 sdhc2_opp_table: opp-table {
3610 compatible = "operating-points-v2";
3612 opp-100000000 {
3613 opp-hz = /bits/ 64 <100000000>;
3614 required-opps = <&rpmhpd_opp_low_svs>;
3615 opp-peak-kBps = <1800000 400000>;
3616 opp-avg-kBps = <100000 0>;
3619 opp-202000000 {
3620 opp-hz = /bits/ 64 <202000000>;
3621 required-opps = <&rpmhpd_opp_nom>;
3622 opp-peak-kBps = <5400000 1600000>;
3623 opp-avg-kBps = <200000 0>;
3629 compatible = "qcom,sc7280-usb-hs-phy",
3630 "qcom,usb-snps-hs-7nm-phy";
3633 #phy-cells = <0>;
3636 clock-names = "ref";
3642 compatible = "qcom,sc7280-usb-hs-phy",
3643 "qcom,usb-snps-hs-7nm-phy";
3646 #phy-cells = <0>;
3649 clock-names = "ref";
3655 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3663 clock-names = "aux",
3670 reset-names = "phy", "common";
3672 #clock-cells = <1>;
3673 #phy-cells = <1>;
3675 orientation-switch;
3678 #address-cells = <1>;
3679 #size-cells = <0>;
3692 remote-endpoint = <&usb_1_dwc3_ss>;
3700 remote-endpoint = <&mdss_dp_out>;
3707 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3710 #address-cells = <2>;
3711 #size-cells = <2>;
3713 dma-ranges;
3720 clock-names = "cfg_noc",
3726 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3728 assigned-clock-rates = <19200000>, <200000000>;
3730 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3734 interrupt-names = "pwr_event",
3739 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3740 required-opps = <&rpmhpd_opp_nom>;
3746 interconnect-names = "usb-ddr", "apps-usb";
3755 snps,dis-u1-entry-quirk;
3756 snps,dis-u2-entry-quirk;
3758 phy-names = "usb2-phy";
3759 maximum-speed = "high-speed";
3760 usb-role-switch;
3764 remote-endpoint = <&eud_ep>;
3771 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3774 #address-cells = <1>;
3775 #size-cells = <0>;
3779 clock-names = "iface", "core";
3782 interconnect-names = "qspi-config";
3783 power-domains = <&rpmhpd SC7280_CX>;
3784 operating-points-v2 = <&qspi_opp_table>;
3789 compatible = "qcom,sc7280-adsp-pas";
3792 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3798 interrupt-names = "wdog", "fatal", "ready", "handover",
3799 "stop-ack", "shutdown-ack";
3802 clock-names = "xo";
3804 power-domains = <&rpmhpd SC7280_LCX>,
3806 power-domain-names = "lcx", "lmx";
3808 memory-region = <&adsp_mem>;
3812 qcom,smem-states = <&adsp_smp2p_out 0>;
3813 qcom,smem-state-names = "stop";
3817 glink-edge {
3818 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3826 qcom,remote-pid = <2>;
3829 compatible = "qcom,apr-v2";
3830 qcom,glink-channels = "apr_audio_svc";
3832 #address-cells = <1>;
3833 #size-cells = <0>;
3838 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3844 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3847 compatible = "qcom,q6afe-dais";
3848 #address-cells = <1>;
3849 #size-cells = <0>;
3850 #sound-dai-cells = <1>;
3853 q6afecc: clock-controller {
3854 compatible = "qcom,q6afe-clocks";
3855 #clock-cells = <2>;
3862 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3865 compatible = "qcom,q6asm-dais";
3866 #address-cells = <1>;
3867 #size-cells = <0>;
3868 #sound-dai-cells = <1>;
3888 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3891 compatible = "qcom,q6adm-routing";
3892 #sound-dai-cells = <0>;
3899 qcom,glink-channels = "fastrpcglink-apps-dsp";
3901 qcom,non-secure-domain;
3902 #address-cells = <1>;
3903 #size-cells = <0>;
3905 compute-cb@3 {
3906 compatible = "qcom,fastrpc-compute-cb";
3909 dma-coherent;
3912 compute-cb@4 {
3913 compatible = "qcom,fastrpc-compute-cb";
3916 dma-coherent;
3919 compute-cb@5 {
3920 compatible = "qcom,fastrpc-compute-cb";
3923 dma-coherent;
3930 compatible = "qcom,sc7280-wpss-pas";
3933 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3939 interrupt-names = "wdog", "fatal", "ready", "handover",
3940 "stop-ack", "shutdown-ack";
3943 clock-names = "xo";
3945 power-domains = <&rpmhpd SC7280_CX>,
3947 power-domain-names = "cx", "mx";
3949 memory-region = <&wpss_mem>;
3953 qcom,smem-states = <&wpss_smp2p_out 0>;
3954 qcom,smem-state-names = "stop";
3959 glink-edge {
3960 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3967 qcom,remote-pid = <13>;
3972 compatible = "qcom,sc7280-llcc-bwmon";
3979 operating-points-v2 = <&llcc_bwmon_opp_table>;
3981 llcc_bwmon_opp_table: opp-table {
3982 compatible = "operating-points-v2";
3984 opp-0 {
3985 opp-peak-kBps = <800000>;
3987 opp-1 {
3988 opp-peak-kBps = <1804000>;
3990 opp-2 {
3991 opp-peak-kBps = <2188000>;
3993 opp-3 {
3994 opp-peak-kBps = <3072000>;
3996 opp-4 {
3997 opp-peak-kBps = <4068000>;
3999 opp-5 {
4000 opp-peak-kBps = <6220000>;
4002 opp-6 {
4003 opp-peak-kBps = <6832000>;
4005 opp-7 {
4006 opp-peak-kBps = <8532000>;
4012 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
4018 operating-points-v2 = <&cpu_bwmon_opp_table>;
4020 cpu_bwmon_opp_table: opp-table {
4021 compatible = "operating-points-v2";
4023 opp-0 {
4024 opp-peak-kBps = <2400000>;
4026 opp-1 {
4027 opp-peak-kBps = <4800000>;
4029 opp-2 {
4030 opp-peak-kBps = <7456000>;
4032 opp-3 {
4033 opp-peak-kBps = <9600000>;
4035 opp-4 {
4036 opp-peak-kBps = <12896000>;
4038 opp-5 {
4039 opp-peak-kBps = <14928000>;
4041 opp-6 {
4042 opp-peak-kBps = <17056000>;
4049 compatible = "qcom,sc7280-dc-noc";
4050 #interconnect-cells = <2>;
4051 qcom,bcm-voters = <&apps_bcm_voter>;
4056 compatible = "qcom,sc7280-gem-noc";
4057 #interconnect-cells = <2>;
4058 qcom,bcm-voters = <&apps_bcm_voter>;
4061 system-cache-controller@9200000 {
4062 compatible = "qcom,sc7280-llcc";
4065 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
4070 compatible = "qcom,sc7280-eud", "qcom,eud";
4073 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
4078 #address-cells = <1>;
4079 #size-cells = <0>;
4084 remote-endpoint = <&usb2_role_switch>;
4092 compatible = "qcom,sc7280-nsp-noc";
4093 #interconnect-cells = <2>;
4094 qcom,bcm-voters = <&apps_bcm_voter>;
4098 compatible = "qcom,sc7280-cdsp-pas";
4101 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4107 interrupt-names = "wdog", "fatal", "ready", "handover",
4108 "stop-ack", "shutdown-ack";
4111 clock-names = "xo";
4113 power-domains = <&rpmhpd SC7280_CX>,
4115 power-domain-names = "cx", "mx";
4119 memory-region = <&cdsp_mem>;
4123 qcom,smem-states = <&cdsp_smp2p_out 0>;
4124 qcom,smem-state-names = "stop";
4128 glink-edge {
4129 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4136 qcom,remote-pid = <5>;
4140 qcom,glink-channels = "fastrpcglink-apps-dsp";
4142 qcom,non-secure-domain;
4143 #address-cells = <1>;
4144 #size-cells = <0>;
4146 compute-cb@1 {
4147 compatible = "qcom,fastrpc-compute-cb";
4151 dma-coherent;
4154 compute-cb@2 {
4155 compatible = "qcom,fastrpc-compute-cb";
4159 dma-coherent;
4162 compute-cb@3 {
4163 compatible = "qcom,fastrpc-compute-cb";
4167 dma-coherent;
4170 compute-cb@4 {
4171 compatible = "qcom,fastrpc-compute-cb";
4175 dma-coherent;
4178 compute-cb@5 {
4179 compatible = "qcom,fastrpc-compute-cb";
4183 dma-coherent;
4186 compute-cb@6 {
4187 compatible = "qcom,fastrpc-compute-cb";
4191 dma-coherent;
4194 compute-cb@7 {
4195 compatible = "qcom,fastrpc-compute-cb";
4199 dma-coherent;
4202 compute-cb@8 {
4203 compatible = "qcom,fastrpc-compute-cb";
4207 dma-coherent;
4212 compute-cb@11 {
4213 compatible = "qcom,fastrpc-compute-cb";
4217 dma-coherent;
4220 compute-cb@12 {
4221 compatible = "qcom,fastrpc-compute-cb";
4225 dma-coherent;
4228 compute-cb@13 {
4229 compatible = "qcom,fastrpc-compute-cb";
4233 dma-coherent;
4236 compute-cb@14 {
4237 compatible = "qcom,fastrpc-compute-cb";
4241 dma-coherent;
4248 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
4251 #address-cells = <2>;
4252 #size-cells = <2>;
4254 dma-ranges;
4261 clock-names = "cfg_noc",
4267 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4269 assigned-clock-rates = <19200000>, <200000000>;
4271 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4276 interrupt-names = "pwr_event",
4282 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4283 required-opps = <&rpmhpd_opp_nom>;
4289 interconnect-names = "usb-ddr", "apps-usb";
4291 wakeup-source;
4300 snps,parkmode-disable-ss-quirk;
4301 snps,dis-u1-entry-quirk;
4302 snps,dis-u2-entry-quirk;
4304 phy-names = "usb2-phy", "usb3-phy";
4305 maximum-speed = "super-speed";
4308 #address-cells = <1>;
4309 #size-cells = <0>;
4322 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
4329 venus: video-codec@aa00000 {
4330 compatible = "qcom,sc7280-venus";
4339 clock-names = "core", "bus", "iface",
4342 power-domains = <&videocc MVSC_GDSC>,
4345 power-domain-names = "venus", "vcodec0", "cx";
4346 operating-points-v2 = <&venus_opp_table>;
4350 interconnect-names = "cpu-cfg", "video-mem";
4353 memory-region = <&video_mem>;
4357 venus_opp_table: opp-table {
4358 compatible = "operating-points-v2";
4360 opp-133330000 {
4361 opp-hz = /bits/ 64 <133330000>;
4362 required-opps = <&rpmhpd_opp_low_svs>;
4365 opp-240000000 {
4366 opp-hz = /bits/ 64 <240000000>;
4367 required-opps = <&rpmhpd_opp_svs>;
4370 opp-335000000 {
4371 opp-hz = /bits/ 64 <335000000>;
4372 required-opps = <&rpmhpd_opp_svs_l1>;
4375 opp-424000000 {
4376 opp-hz = /bits/ 64 <424000000>;
4377 required-opps = <&rpmhpd_opp_nom>;
4380 opp-460000048 {
4381 opp-hz = /bits/ 64 <460000048>;
4382 required-opps = <&rpmhpd_opp_turbo>;
4387 videocc: clock-controller@aaf0000 {
4388 compatible = "qcom,sc7280-videocc";
4392 clock-names = "bi_tcxo", "bi_tcxo_ao";
4393 #clock-cells = <1>;
4394 #reset-cells = <1>;
4395 #power-domain-cells = <1>;
4399 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4402 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4409 clock-names = "camnoc_axi",
4414 pinctrl-0 = <&cci0_default &cci1_default>;
4415 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4416 pinctrl-names = "default", "sleep";
4418 #address-cells = <1>;
4419 #size-cells = <0>;
4423 cci0_i2c0: i2c-bus@0 {
4425 clock-frequency = <1000000>;
4426 #address-cells = <1>;
4427 #size-cells = <0>;
4430 cci0_i2c1: i2c-bus@1 {
4432 clock-frequency = <1000000>;
4433 #address-cells = <1>;
4434 #size-cells = <0>;
4439 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4442 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4449 clock-names = "camnoc_axi",
4454 pinctrl-0 = <&cci2_default &cci3_default>;
4455 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4456 pinctrl-names = "default", "sleep";
4458 #address-cells = <1>;
4459 #size-cells = <0>;
4463 cci1_i2c0: i2c-bus@0 {
4465 clock-frequency = <1000000>;
4466 #address-cells = <1>;
4467 #size-cells = <0>;
4470 cci1_i2c1: i2c-bus@1 {
4472 clock-frequency = <1000000>;
4473 #address-cells = <1>;
4474 #size-cells = <0>;
4479 compatible = "qcom,sc7280-camss";
4496 reg-names = "csid0",
4545 clock-names = "camnoc_axi",
4594 interrupt-names = "csid0",
4614 interconnect-names = "ahb",
4619 power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
4623 power-domain-names = "ife0",
4631 #address-cells = <1>;
4632 #size-cells = <0>;
4656 camcc: clock-controller@ad00000 {
4657 compatible = "qcom,sc7280-camcc";
4662 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4663 #clock-cells = <1>;
4664 #reset-cells = <1>;
4665 #power-domain-cells = <1>;
4668 dispcc: clock-controller@af00000 {
4669 compatible = "qcom,sc7280-dispcc";
4679 clock-names = "bi_tcxo",
4687 #clock-cells = <1>;
4688 #reset-cells = <1>;
4689 #power-domain-cells = <1>;
4692 mdss: display-subsystem@ae00000 {
4693 compatible = "qcom,sc7280-mdss";
4695 reg-names = "mdss";
4697 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
4702 clock-names = "iface",
4707 interrupt-controller;
4708 #interrupt-cells = <1>;
4714 interconnect-names = "mdp0-mem",
4715 "cpu-cfg";
4719 #address-cells = <2>;
4720 #size-cells = <2>;
4725 mdss_mdp: display-controller@ae01000 {
4726 compatible = "qcom,sc7280-dpu";
4729 reg-names = "mdp", "vbif";
4737 clock-names = "bus",
4743 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
4745 assigned-clock-rates = <19200000>,
4747 operating-points-v2 = <&mdp_opp_table>;
4748 power-domains = <&rpmhpd SC7280_CX>;
4750 interrupt-parent = <&mdss>;
4754 #address-cells = <1>;
4755 #size-cells = <0>;
4760 remote-endpoint = <&mdss_dsi0_in>;
4767 remote-endpoint = <&edp_in>;
4774 remote-endpoint = <&dp_in>;
4779 mdp_opp_table: opp-table {
4780 compatible = "operating-points-v2";
4782 opp-200000000 {
4783 opp-hz = /bits/ 64 <200000000>;
4784 required-opps = <&rpmhpd_opp_low_svs>;
4787 opp-300000000 {
4788 opp-hz = /bits/ 64 <300000000>;
4789 required-opps = <&rpmhpd_opp_svs>;
4792 opp-380000000 {
4793 opp-hz = /bits/ 64 <380000000>;
4794 required-opps = <&rpmhpd_opp_svs_l1>;
4797 opp-506666667 {
4798 opp-hz = /bits/ 64 <506666667>;
4799 required-opps = <&rpmhpd_opp_nom>;
4802 opp-608000000 {
4803 opp-hz = /bits/ 64 <608000000>;
4804 required-opps = <&rpmhpd_opp_turbo>;
4810 compatible = "qcom,sc7280-dsi-ctrl",
4811 "qcom,mdss-dsi-ctrl";
4813 reg-names = "dsi_ctrl";
4815 interrupt-parent = <&mdss>;
4824 clock-names = "byte",
4831 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
4833 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>,
4836 operating-points-v2 = <&dsi_opp_table>;
4837 power-domains = <&rpmhpd SC7280_CX>;
4841 #address-cells = <1>;
4842 #size-cells = <0>;
4847 #address-cells = <1>;
4848 #size-cells = <0>;
4853 remote-endpoint = <&dpu_intf1_out>;
4864 dsi_opp_table: opp-table {
4865 compatible = "operating-points-v2";
4867 opp-187500000 {
4868 opp-hz = /bits/ 64 <187500000>;
4869 required-opps = <&rpmhpd_opp_low_svs>;
4872 opp-300000000 {
4873 opp-hz = /bits/ 64 <300000000>;
4874 required-opps = <&rpmhpd_opp_svs>;
4877 opp-358000000 {
4878 opp-hz = /bits/ 64 <358000000>;
4879 required-opps = <&rpmhpd_opp_svs_l1>;
4885 compatible = "qcom,sc7280-dsi-phy-7nm";
4889 reg-names = "dsi_phy",
4893 #clock-cells = <1>;
4894 #phy-cells = <0>;
4898 clock-names = "iface", "ref";
4904 compatible = "qcom,sc7280-edp";
4905 pinctrl-names = "default";
4906 pinctrl-0 = <&edp_hot_plug_det>;
4913 interrupt-parent = <&mdss>;
4921 clock-names = "core_iface",
4926 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4928 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4931 phy-names = "dp";
4933 operating-points-v2 = <&edp_opp_table>;
4934 power-domains = <&rpmhpd SC7280_CX>;
4939 #address-cells = <1>;
4940 #size-cells = <0>;
4945 remote-endpoint = <&dpu_intf5_out>;
4955 edp_opp_table: opp-table {
4956 compatible = "operating-points-v2";
4958 opp-160000000 {
4959 opp-hz = /bits/ 64 <160000000>;
4960 required-opps = <&rpmhpd_opp_low_svs>;
4963 opp-270000000 {
4964 opp-hz = /bits/ 64 <270000000>;
4965 required-opps = <&rpmhpd_opp_svs>;
4968 opp-540000000 {
4969 opp-hz = /bits/ 64 <540000000>;
4970 required-opps = <&rpmhpd_opp_nom>;
4973 opp-810000000 {
4974 opp-hz = /bits/ 64 <810000000>;
4975 required-opps = <&rpmhpd_opp_nom>;
4981 compatible = "qcom,sc7280-edp-phy";
4990 clock-names = "aux",
4993 #clock-cells = <1>;
4994 #phy-cells = <0>;
4999 mdss_dp: displayport-controller@ae90000 {
5000 compatible = "qcom,sc7280-dp";
5008 interrupt-parent = <&mdss>;
5016 clock-names = "core_iface",
5021 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
5023 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5026 phy-names = "dp";
5028 operating-points-v2 = <&dp_opp_table>;
5029 power-domains = <&rpmhpd SC7280_CX>;
5031 #sound-dai-cells = <0>;
5036 #address-cells = <1>;
5037 #size-cells = <0>;
5042 remote-endpoint = <&dpu_intf0_out>;
5049 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
5054 dp_opp_table: opp-table {
5055 compatible = "operating-points-v2";
5057 opp-160000000 {
5058 opp-hz = /bits/ 64 <160000000>;
5059 required-opps = <&rpmhpd_opp_low_svs>;
5062 opp-270000000 {
5063 opp-hz = /bits/ 64 <270000000>;
5064 required-opps = <&rpmhpd_opp_svs>;
5067 opp-540000000 {
5068 opp-hz = /bits/ 64 <540000000>;
5069 required-opps = <&rpmhpd_opp_svs_l1>;
5072 opp-810000000 {
5073 opp-hz = /bits/ 64 <810000000>;
5074 required-opps = <&rpmhpd_opp_nom>;
5080 pdc: interrupt-controller@b220000 {
5081 compatible = "qcom,sc7280-pdc", "qcom,pdc";
5083 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
5088 #interrupt-cells = <2>;
5089 interrupt-parent = <&intc>;
5090 interrupt-controller;
5093 pdc_reset: reset-controller@b5e0000 {
5094 compatible = "qcom,sc7280-pdc-global";
5096 #reset-cells = <1>;
5100 tsens0: thermal-sensor@c263000 {
5101 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
5107 interrupt-names = "uplow","critical";
5108 #thermal-sensor-cells = <1>;
5111 tsens1: thermal-sensor@c265000 {
5112 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
5118 interrupt-names = "uplow","critical";
5119 #thermal-sensor-cells = <1>;
5122 aoss_reset: reset-controller@c2a0000 {
5123 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
5125 #reset-cells = <1>;
5128 aoss_qmp: power-management@c300000 {
5129 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
5131 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5137 #clock-cells = <0>;
5141 compatible = "qcom,rpmh-stats";
5146 compatible = "qcom,spmi-pmic-arb";
5152 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5153 interrupt-names = "periph_irq";
5154 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5157 #address-cells = <2>;
5158 #size-cells = <0>;
5159 interrupt-controller;
5160 #interrupt-cells = <4>;
5164 compatible = "qcom,sc7280-pinctrl";
5167 gpio-controller;
5168 #gpio-cells = <2>;
5169 interrupt-controller;
5170 #interrupt-cells = <2>;
5171 gpio-ranges = <&tlmm 0 0 175>;
5172 wakeup-parent = <&pdc>;
5174 cci0_default: cci0-default-state {
5177 drive-strength = <2>;
5178 bias-pull-up;
5181 cci0_sleep: cci0-sleep-state {
5184 drive-strength = <2>;
5185 bias-pull-down;
5188 cci1_default: cci1-default-state {
5191 drive-strength = <2>;
5192 bias-pull-up;
5195 cci1_sleep: cci1-sleep-state {
5198 drive-strength = <2>;
5199 bias-pull-down;
5202 cci2_default: cci2-default-state {
5205 drive-strength = <2>;
5206 bias-pull-up;
5209 cci2_sleep: cci2-sleep-state {
5212 drive-strength = <2>;
5213 bias-pull-down;
5216 cci3_default: cci3-default-state {
5219 drive-strength = <2>;
5220 bias-pull-up;
5223 cci3_sleep: cci3-sleep-state {
5226 drive-strength = <2>;
5227 bias-pull-down;
5230 dp_hot_plug_det: dp-hot-plug-det-state {
5235 edp_hot_plug_det: edp-hot-plug-det-state {
5240 mi2s0_data0: mi2s0-data0-state {
5245 mi2s0_data1: mi2s0-data1-state {
5250 mi2s0_mclk: mi2s0-mclk-state {
5255 mi2s0_sclk: mi2s0-sclk-state {
5260 mi2s0_ws: mi2s0-ws-state {
5265 mi2s1_data0: mi2s1-data0-state {
5270 mi2s1_sclk: mi2s1-sclk-state {
5275 mi2s1_ws: mi2s1-ws-state {
5280 pcie1_clkreq_n: pcie1-clkreq-n-state {
5285 qspi_clk: qspi-clk-state {
5290 qspi_cs0: qspi-cs0-state {
5295 qspi_cs1: qspi-cs1-state {
5300 qspi_data0: qspi-data0-state {
5305 qspi_data1: qspi-data1-state {
5310 qspi_data23: qspi-data23-state {
5315 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5320 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5325 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5330 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5335 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5340 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5345 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5350 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5355 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5360 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5365 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5370 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5375 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5380 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5385 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5390 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5395 qup_spi0_data_clk: qup-spi0-data-clk-state {
5400 qup_spi0_cs: qup-spi0-cs-state {
5405 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5410 qup_spi1_data_clk: qup-spi1-data-clk-state {
5415 qup_spi1_cs: qup-spi1-cs-state {
5420 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5425 qup_spi2_data_clk: qup-spi2-data-clk-state {
5430 qup_spi2_cs: qup-spi2-cs-state {
5435 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5440 qup_spi3_data_clk: qup-spi3-data-clk-state {
5445 qup_spi3_cs: qup-spi3-cs-state {
5450 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5455 qup_spi4_data_clk: qup-spi4-data-clk-state {
5460 qup_spi4_cs: qup-spi4-cs-state {
5465 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5470 qup_spi5_data_clk: qup-spi5-data-clk-state {
5475 qup_spi5_cs: qup-spi5-cs-state {
5480 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5485 qup_spi6_data_clk: qup-spi6-data-clk-state {
5490 qup_spi6_cs: qup-spi6-cs-state {
5495 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5500 qup_spi7_data_clk: qup-spi7-data-clk-state {
5505 qup_spi7_cs: qup-spi7-cs-state {
5510 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5515 qup_spi8_data_clk: qup-spi8-data-clk-state {
5520 qup_spi8_cs: qup-spi8-cs-state {
5525 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5530 qup_spi9_data_clk: qup-spi9-data-clk-state {
5535 qup_spi9_cs: qup-spi9-cs-state {
5540 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5545 qup_spi10_data_clk: qup-spi10-data-clk-state {
5550 qup_spi10_cs: qup-spi10-cs-state {
5555 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5560 qup_spi11_data_clk: qup-spi11-data-clk-state {
5565 qup_spi11_cs: qup-spi11-cs-state {
5570 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 qup_spi12_data_clk: qup-spi12-data-clk-state {
5580 qup_spi12_cs: qup-spi12-cs-state {
5585 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5590 qup_spi13_data_clk: qup-spi13-data-clk-state {
5595 qup_spi13_cs: qup-spi13-cs-state {
5600 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5605 qup_spi14_data_clk: qup-spi14-data-clk-state {
5610 qup_spi14_cs: qup-spi14-cs-state {
5615 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5620 qup_spi15_data_clk: qup-spi15-data-clk-state {
5625 qup_spi15_cs: qup-spi15-cs-state {
5630 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5635 qup_uart0_cts: qup-uart0-cts-state {
5640 qup_uart0_rts: qup-uart0-rts-state {
5645 qup_uart0_tx: qup-uart0-tx-state {
5650 qup_uart0_rx: qup-uart0-rx-state {
5655 qup_uart1_cts: qup-uart1-cts-state {
5660 qup_uart1_rts: qup-uart1-rts-state {
5665 qup_uart1_tx: qup-uart1-tx-state {
5670 qup_uart1_rx: qup-uart1-rx-state {
5675 qup_uart2_cts: qup-uart2-cts-state {
5680 qup_uart2_rts: qup-uart2-rts-state {
5685 qup_uart2_tx: qup-uart2-tx-state {
5690 qup_uart2_rx: qup-uart2-rx-state {
5695 qup_uart3_cts: qup-uart3-cts-state {
5700 qup_uart3_rts: qup-uart3-rts-state {
5705 qup_uart3_tx: qup-uart3-tx-state {
5710 qup_uart3_rx: qup-uart3-rx-state {
5715 qup_uart4_cts: qup-uart4-cts-state {
5720 qup_uart4_rts: qup-uart4-rts-state {
5725 qup_uart4_tx: qup-uart4-tx-state {
5730 qup_uart4_rx: qup-uart4-rx-state {
5735 qup_uart5_tx: qup-uart5-tx-state {
5740 qup_uart5_rx: qup-uart5-rx-state {
5745 qup_uart6_cts: qup-uart6-cts-state {
5750 qup_uart6_rts: qup-uart6-rts-state {
5755 qup_uart6_tx: qup-uart6-tx-state {
5760 qup_uart6_rx: qup-uart6-rx-state {
5765 qup_uart7_cts: qup-uart7-cts-state {
5770 qup_uart7_rts: qup-uart7-rts-state {
5775 qup_uart7_tx: qup-uart7-tx-state {
5780 qup_uart7_rx: qup-uart7-rx-state {
5785 qup_uart8_cts: qup-uart8-cts-state {
5790 qup_uart8_rts: qup-uart8-rts-state {
5795 qup_uart8_tx: qup-uart8-tx-state {
5800 qup_uart8_rx: qup-uart8-rx-state {
5805 qup_uart9_cts: qup-uart9-cts-state {
5810 qup_uart9_rts: qup-uart9-rts-state {
5815 qup_uart9_tx: qup-uart9-tx-state {
5820 qup_uart9_rx: qup-uart9-rx-state {
5825 qup_uart10_cts: qup-uart10-cts-state {
5830 qup_uart10_rts: qup-uart10-rts-state {
5835 qup_uart10_tx: qup-uart10-tx-state {
5840 qup_uart10_rx: qup-uart10-rx-state {
5845 qup_uart11_cts: qup-uart11-cts-state {
5850 qup_uart11_rts: qup-uart11-rts-state {
5855 qup_uart11_tx: qup-uart11-tx-state {
5860 qup_uart11_rx: qup-uart11-rx-state {
5865 qup_uart12_cts: qup-uart12-cts-state {
5870 qup_uart12_rts: qup-uart12-rts-state {
5875 qup_uart12_tx: qup-uart12-tx-state {
5880 qup_uart12_rx: qup-uart12-rx-state {
5885 qup_uart13_cts: qup-uart13-cts-state {
5890 qup_uart13_rts: qup-uart13-rts-state {
5895 qup_uart13_tx: qup-uart13-tx-state {
5900 qup_uart13_rx: qup-uart13-rx-state {
5905 qup_uart14_cts: qup-uart14-cts-state {
5910 qup_uart14_rts: qup-uart14-rts-state {
5915 qup_uart14_tx: qup-uart14-tx-state {
5920 qup_uart14_rx: qup-uart14-rx-state {
5925 qup_uart15_cts: qup-uart15-cts-state {
5930 qup_uart15_rts: qup-uart15-rts-state {
5935 qup_uart15_tx: qup-uart15-tx-state {
5940 qup_uart15_rx: qup-uart15-rx-state {
5945 sdc1_clk: sdc1-clk-state {
5949 sdc1_cmd: sdc1-cmd-state {
5953 sdc1_data: sdc1-data-state {
5957 sdc1_rclk: sdc1-rclk-state {
5961 sdc1_clk_sleep: sdc1-clk-sleep-state {
5963 drive-strength = <2>;
5964 bias-bus-hold;
5967 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5969 drive-strength = <2>;
5970 bias-bus-hold;
5973 sdc1_data_sleep: sdc1-data-sleep-state {
5975 drive-strength = <2>;
5976 bias-bus-hold;
5979 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5981 drive-strength = <2>;
5982 bias-bus-hold;
5985 sdc2_clk: sdc2-clk-state {
5989 sdc2_cmd: sdc2-cmd-state {
5993 sdc2_data: sdc2-data-state {
5997 sdc2_clk_sleep: sdc2-clk-sleep-state {
5999 drive-strength = <2>;
6000 bias-bus-hold;
6003 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
6005 drive-strength = <2>;
6006 bias-bus-hold;
6009 sdc2_data_sleep: sdc2-data-sleep-state {
6011 drive-strength = <2>;
6012 bias-bus-hold;
6017 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
6020 #address-cells = <1>;
6021 #size-cells = <1>;
6025 pil-reloc@594c {
6026 compatible = "qcom,pil-reloc-info";
6032 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
6034 #iommu-cells = <2>;
6035 #global-interrupts = <1>;
6036 dma-coherent;
6121 compatible = "qcom,sc7280-tbu";
6125 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
6129 compatible = "qcom,sc7280-tbu";
6133 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
6137 compatible = "qcom,sc7280-tbu";
6141 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
6142 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
6146 compatible = "qcom,sc7280-tbu";
6150 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
6151 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
6155 compatible = "qcom,sc7280-tbu";
6159 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
6160 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
6164 compatible = "qcom,sc7280-tbu";
6168 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
6169 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
6173 compatible = "qcom,sc7280-tbu";
6177 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
6181 compatible = "qcom,sc7280-tbu";
6185 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
6189 compatible = "qcom,sc7280-tbu";
6193 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
6194 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
6197 intc: interrupt-controller@17a00000 {
6198 compatible = "arm,gic-v3";
6202 #interrupt-cells = <3>;
6203 interrupt-controller;
6204 #address-cells = <2>;
6205 #size-cells = <2>;
6208 msi-controller@17a40000 {
6209 compatible = "arm,gic-v3-its";
6211 msi-controller;
6212 #msi-cells = <1>;
6218 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
6226 #address-cells = <1>;
6227 #size-cells = <1>;
6229 compatible = "arm,armv7-timer-mem";
6233 frame-number = <0>;
6241 frame-number = <1>;
6248 frame-number = <2>;
6255 frame-number = <3>;
6262 frame-number = <4>;
6269 frame-number = <5>;
6276 frame-number = <6>;
6284 compatible = "qcom,rpmh-rsc";
6288 reg-names = "drv-0", "drv-1", "drv-2";
6292 qcom,tcs-offset = <0xd00>;
6293 qcom,drv-id = <2>;
6294 qcom,tcs-config = <ACTIVE_TCS 2>,
6298 power-domains = <&cluster_pd>;
6300 apps_bcm_voter: bcm-voter {
6301 compatible = "qcom,bcm-voter";
6304 rpmhpd: power-controller {
6305 compatible = "qcom,sc7280-rpmhpd";
6306 #power-domain-cells = <1>;
6307 operating-points-v2 = <&rpmhpd_opp_table>;
6309 rpmhpd_opp_table: opp-table {
6310 compatible = "operating-points-v2";
6313 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6321 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6325 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6329 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
6333 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6337 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6350 rpmhcc: clock-controller {
6351 compatible = "qcom,sc7280-rpmh-clk";
6353 clock-names = "xo";
6354 #clock-cells = <1>;
6359 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
6362 clock-names = "xo", "alternate";
6363 #interconnect-cells = <1>;
6367 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
6375 interrupt-names = "dcvsh-irq-0",
6376 "dcvsh-irq-1",
6377 "dcvsh-irq-2";
6380 clock-names = "xo", "alternate";
6381 #freq-domain-cells = <1>;
6382 #clock-cells = <1>;
6389 thermal_zones: thermal-zones {
6390 cpu0-thermal {
6391 polling-delay-passive = <250>;
6393 thermal-sensors = <&tsens0 1>;
6396 cpu0_alert0: trip-point0 {
6402 cpu0_alert1: trip-point1 {
6408 cpu0_crit: cpu-crit {
6415 cooling-maps {
6418 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6425 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6433 cpu1-thermal {
6434 polling-delay-passive = <250>;
6436 thermal-sensors = <&tsens0 2>;
6439 cpu1_alert0: trip-point0 {
6445 cpu1_alert1: trip-point1 {
6451 cpu1_crit: cpu-crit {
6458 cooling-maps {
6461 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6468 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6476 cpu2-thermal {
6477 polling-delay-passive = <250>;
6479 thermal-sensors = <&tsens0 3>;
6482 cpu2_alert0: trip-point0 {
6488 cpu2_alert1: trip-point1 {
6494 cpu2_crit: cpu-crit {
6501 cooling-maps {
6504 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6511 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6519 cpu3-thermal {
6520 polling-delay-passive = <250>;
6522 thermal-sensors = <&tsens0 4>;
6525 cpu3_alert0: trip-point0 {
6531 cpu3_alert1: trip-point1 {
6537 cpu3_crit: cpu-crit {
6544 cooling-maps {
6547 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6554 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6562 cpu4-thermal {
6563 polling-delay-passive = <250>;
6565 thermal-sensors = <&tsens0 7>;
6568 cpu4_alert0: trip-point0 {
6574 cpu4_alert1: trip-point1 {
6580 cpu4_crit: cpu-crit {
6587 cooling-maps {
6590 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6597 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6605 cpu5-thermal {
6606 polling-delay-passive = <250>;
6608 thermal-sensors = <&tsens0 8>;
6611 cpu5_alert0: trip-point0 {
6617 cpu5_alert1: trip-point1 {
6623 cpu5_crit: cpu-crit {
6630 cooling-maps {
6633 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6640 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6648 cpu6-thermal {
6649 polling-delay-passive = <250>;
6651 thermal-sensors = <&tsens0 9>;
6654 cpu6_alert0: trip-point0 {
6660 cpu6_alert1: trip-point1 {
6666 cpu6_crit: cpu-crit {
6673 cooling-maps {
6676 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6683 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6691 cpu7-thermal {
6692 polling-delay-passive = <250>;
6694 thermal-sensors = <&tsens0 10>;
6697 cpu7_alert0: trip-point0 {
6703 cpu7_alert1: trip-point1 {
6709 cpu7_crit: cpu-crit {
6716 cooling-maps {
6719 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6726 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6734 cpu8-thermal {
6735 polling-delay-passive = <250>;
6737 thermal-sensors = <&tsens0 11>;
6740 cpu8_alert0: trip-point0 {
6746 cpu8_alert1: trip-point1 {
6752 cpu8_crit: cpu-crit {
6759 cooling-maps {
6762 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6769 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6777 cpu9-thermal {
6778 polling-delay-passive = <250>;
6780 thermal-sensors = <&tsens0 12>;
6783 cpu9_alert0: trip-point0 {
6789 cpu9_alert1: trip-point1 {
6795 cpu9_crit: cpu-crit {
6802 cooling-maps {
6805 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6812 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6820 cpu10-thermal {
6821 polling-delay-passive = <250>;
6823 thermal-sensors = <&tsens0 13>;
6826 cpu10_alert0: trip-point0 {
6832 cpu10_alert1: trip-point1 {
6838 cpu10_crit: cpu-crit {
6845 cooling-maps {
6848 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6855 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6863 cpu11-thermal {
6864 polling-delay-passive = <250>;
6866 thermal-sensors = <&tsens0 14>;
6869 cpu11_alert0: trip-point0 {
6875 cpu11_alert1: trip-point1 {
6881 cpu11_crit: cpu-crit {
6888 cooling-maps {
6891 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6898 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6906 aoss0-thermal {
6907 polling-delay-passive = <0>;
6909 thermal-sensors = <&tsens0 0>;
6912 aoss0_alert0: trip-point0 {
6918 aoss0_crit: aoss0-crit {
6926 aoss1-thermal {
6927 polling-delay-passive = <0>;
6929 thermal-sensors = <&tsens1 0>;
6932 aoss1_alert0: trip-point0 {
6938 aoss1_crit: aoss1-crit {
6946 cpuss0-thermal {
6947 polling-delay-passive = <0>;
6949 thermal-sensors = <&tsens0 5>;
6952 cpuss0_alert0: trip-point0 {
6957 cpuss0_crit: cluster0-crit {
6965 cpuss1-thermal {
6966 polling-delay-passive = <0>;
6968 thermal-sensors = <&tsens0 6>;
6971 cpuss1_alert0: trip-point0 {
6976 cpuss1_crit: cluster0-crit {
6984 gpuss0-thermal {
6985 polling-delay-passive = <100>;
6987 thermal-sensors = <&tsens1 1>;
6990 gpuss0_alert0: trip-point0 {
6996 gpuss0_crit: gpuss0-crit {
7003 cooling-maps {
7006 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7011 gpuss1-thermal {
7012 polling-delay-passive = <100>;
7014 thermal-sensors = <&tsens1 2>;
7017 gpuss1_alert0: trip-point0 {
7023 gpuss1_crit: gpuss1-crit {
7030 cooling-maps {
7033 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7038 nspss0-thermal {
7039 thermal-sensors = <&tsens1 3>;
7042 nspss0_alert0: trip-point0 {
7048 nspss0_crit: nspss0-crit {
7056 nspss1-thermal {
7057 thermal-sensors = <&tsens1 4>;
7060 nspss1_alert0: trip-point0 {
7066 nspss1_crit: nspss1-crit {
7074 video-thermal {
7075 thermal-sensors = <&tsens1 5>;
7078 video_alert0: trip-point0 {
7084 video_crit: video-crit {
7092 ddr-thermal {
7093 thermal-sensors = <&tsens1 6>;
7096 ddr_alert0: trip-point0 {
7102 ddr_crit: ddr-crit {
7110 mdmss0-thermal {
7111 thermal-sensors = <&tsens1 7>;
7114 mdmss0_alert0: trip-point0 {
7120 mdmss0_crit: mdmss0-crit {
7128 mdmss1-thermal {
7129 thermal-sensors = <&tsens1 8>;
7132 mdmss1_alert0: trip-point0 {
7138 mdmss1_crit: mdmss1-crit {
7146 mdmss2-thermal {
7147 thermal-sensors = <&tsens1 9>;
7150 mdmss2_alert0: trip-point0 {
7156 mdmss2_crit: mdmss2-crit {
7164 mdmss3-thermal {
7165 thermal-sensors = <&tsens1 10>;
7168 mdmss3_alert0: trip-point0 {
7174 mdmss3_crit: mdmss3-crit {
7182 camera0-thermal {
7183 thermal-sensors = <&tsens1 11>;
7186 camera0_alert0: trip-point0 {
7192 camera0_crit: camera0-crit {
7202 compatible = "arm,armv8-timer";