Lines Matching +full:opp +full:- +full:160000000
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
13 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
16 #include <dt-bindings/dma/qcom-gpi.h>
17 #include <dt-bindings/firmware/qcom,scm.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/interconnect/qcom,icc.h>
20 #include <dt-bindings/interconnect/qcom,osm-l3.h>
21 #include <dt-bindings/interconnect/qcom,sc7280.h>
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 #include <dt-bindings/mailbox/qcom-ipcc.h>
24 #include <dt-bindings/phy/phy-qcom-qmp.h>
25 #include <dt-bindings/power/qcom-rpmpd.h>
26 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
27 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
28 #include <dt-bindings/soc/qcom,apr.h>
29 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
30 #include <dt-bindings/sound/qcom,lpass.h>
31 #include <dt-bindings/sound/qcom,q6asm.h>
32 #include <dt-bindings/thermal/thermal.h>
35 interrupt-parent = <&intc>;
37 #address-cells = <2>;
38 #size-cells = <2>;
80 xo_board: xo-board {
81 compatible = "fixed-clock";
82 clock-frequency = <76800000>;
83 #clock-cells = <0>;
86 sleep_clk: sleep-clk {
87 compatible = "fixed-clock";
88 clock-frequency = <32764>;
89 #clock-cells = <0>;
93 reserved-memory {
94 #address-cells = <2>;
95 #size-cells = <2>;
98 wlan_ce_mem: wlan-ce@4cd000 {
99 no-map;
105 no-map;
110 no-map;
115 no-map;
118 aop_cmd_db_mem: aop-cmd-db@80860000 {
120 compatible = "qcom,cmd-db";
121 no-map;
124 reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
126 no-map;
129 sec_apps_mem: sec-apps@808ff000 {
131 no-map;
136 no-map;
140 no-map;
144 wlan_fw_mem: wlan-fw@80c00000 {
146 no-map;
151 no-map;
156 no-map;
161 no-map;
164 ipa_fw_mem: ipa-fw@8b700000 {
166 no-map;
171 no-map;
176 no-map;
181 no-map;
185 compatible = "qcom,rmtfs-mem";
187 no-map;
189 qcom,client-id = <1>;
195 #address-cells = <2>;
196 #size-cells = <0>;
203 enable-method = "psci";
204 power-domains = <&cpu_pd0>;
205 power-domain-names = "psci";
206 next-level-cache = <&l2_0>;
207 operating-points-v2 = <&cpu0_opp_table>;
208 capacity-dmips-mhz = <1024>;
209 dynamic-power-coefficient = <100>;
212 qcom,freq-domain = <&cpufreq_hw 0>;
213 #cooling-cells = <2>;
214 l2_0: l2-cache {
216 cache-level = <2>;
217 cache-unified;
218 next-level-cache = <&l3_0>;
219 l3_0: l3-cache {
221 cache-level = <3>;
222 cache-unified;
232 enable-method = "psci";
233 power-domains = <&cpu_pd1>;
234 power-domain-names = "psci";
235 next-level-cache = <&l2_100>;
236 operating-points-v2 = <&cpu0_opp_table>;
237 capacity-dmips-mhz = <1024>;
238 dynamic-power-coefficient = <100>;
241 qcom,freq-domain = <&cpufreq_hw 0>;
242 #cooling-cells = <2>;
243 l2_100: l2-cache {
245 cache-level = <2>;
246 cache-unified;
247 next-level-cache = <&l3_0>;
256 enable-method = "psci";
257 power-domains = <&cpu_pd2>;
258 power-domain-names = "psci";
259 next-level-cache = <&l2_200>;
260 operating-points-v2 = <&cpu0_opp_table>;
261 capacity-dmips-mhz = <1024>;
262 dynamic-power-coefficient = <100>;
265 qcom,freq-domain = <&cpufreq_hw 0>;
266 #cooling-cells = <2>;
267 l2_200: l2-cache {
269 cache-level = <2>;
270 cache-unified;
271 next-level-cache = <&l3_0>;
280 enable-method = "psci";
281 power-domains = <&cpu_pd3>;
282 power-domain-names = "psci";
283 next-level-cache = <&l2_300>;
284 operating-points-v2 = <&cpu0_opp_table>;
285 capacity-dmips-mhz = <1024>;
286 dynamic-power-coefficient = <100>;
289 qcom,freq-domain = <&cpufreq_hw 0>;
290 #cooling-cells = <2>;
291 l2_300: l2-cache {
293 cache-level = <2>;
294 cache-unified;
295 next-level-cache = <&l3_0>;
304 enable-method = "psci";
305 power-domains = <&cpu_pd4>;
306 power-domain-names = "psci";
307 next-level-cache = <&l2_400>;
308 operating-points-v2 = <&cpu4_opp_table>;
309 capacity-dmips-mhz = <1946>;
310 dynamic-power-coefficient = <520>;
313 qcom,freq-domain = <&cpufreq_hw 1>;
314 #cooling-cells = <2>;
315 l2_400: l2-cache {
317 cache-level = <2>;
318 cache-unified;
319 next-level-cache = <&l3_0>;
328 enable-method = "psci";
329 power-domains = <&cpu_pd5>;
330 power-domain-names = "psci";
331 next-level-cache = <&l2_500>;
332 operating-points-v2 = <&cpu4_opp_table>;
333 capacity-dmips-mhz = <1946>;
334 dynamic-power-coefficient = <520>;
337 qcom,freq-domain = <&cpufreq_hw 1>;
338 #cooling-cells = <2>;
339 l2_500: l2-cache {
341 cache-level = <2>;
342 cache-unified;
343 next-level-cache = <&l3_0>;
352 enable-method = "psci";
353 power-domains = <&cpu_pd6>;
354 power-domain-names = "psci";
355 next-level-cache = <&l2_600>;
356 operating-points-v2 = <&cpu4_opp_table>;
357 capacity-dmips-mhz = <1946>;
358 dynamic-power-coefficient = <520>;
361 qcom,freq-domain = <&cpufreq_hw 1>;
362 #cooling-cells = <2>;
363 l2_600: l2-cache {
365 cache-level = <2>;
366 cache-unified;
367 next-level-cache = <&l3_0>;
376 enable-method = "psci";
377 power-domains = <&cpu_pd7>;
378 power-domain-names = "psci";
379 next-level-cache = <&l2_700>;
380 operating-points-v2 = <&cpu7_opp_table>;
381 capacity-dmips-mhz = <1985>;
382 dynamic-power-coefficient = <552>;
385 qcom,freq-domain = <&cpufreq_hw 2>;
386 #cooling-cells = <2>;
387 l2_700: l2-cache {
389 cache-level = <2>;
390 cache-unified;
391 next-level-cache = <&l3_0>;
395 cpu-map {
431 idle-states {
432 entry-method = "psci";
434 little_cpu_sleep_0: cpu-sleep-0-0 {
435 compatible = "arm,idle-state";
436 idle-state-name = "little-power-down";
437 arm,psci-suspend-param = <0x40000003>;
438 entry-latency-us = <549>;
439 exit-latency-us = <901>;
440 min-residency-us = <1774>;
441 local-timer-stop;
444 little_cpu_sleep_1: cpu-sleep-0-1 {
445 compatible = "arm,idle-state";
446 idle-state-name = "little-rail-power-down";
447 arm,psci-suspend-param = <0x40000004>;
448 entry-latency-us = <702>;
449 exit-latency-us = <915>;
450 min-residency-us = <4001>;
451 local-timer-stop;
454 big_cpu_sleep_0: cpu-sleep-1-0 {
455 compatible = "arm,idle-state";
456 idle-state-name = "big-power-down";
457 arm,psci-suspend-param = <0x40000003>;
458 entry-latency-us = <523>;
459 exit-latency-us = <1244>;
460 min-residency-us = <2207>;
461 local-timer-stop;
464 big_cpu_sleep_1: cpu-sleep-1-1 {
465 compatible = "arm,idle-state";
466 idle-state-name = "big-rail-power-down";
467 arm,psci-suspend-param = <0x40000004>;
468 entry-latency-us = <526>;
469 exit-latency-us = <1854>;
470 min-residency-us = <5555>;
471 local-timer-stop;
475 domain_idle_states: domain-idle-states {
476 cluster_sleep_apss_off: cluster-sleep-0 {
477 compatible = "domain-idle-state";
478 arm,psci-suspend-param = <0x41000044>;
479 entry-latency-us = <2752>;
480 exit-latency-us = <3048>;
481 min-residency-us = <6118>;
484 cluster_sleep_cx_ret: cluster-sleep-1 {
485 compatible = "domain-idle-state";
486 arm,psci-suspend-param = <0x41001344>;
487 entry-latency-us = <3263>;
488 exit-latency-us = <4562>;
489 min-residency-us = <8467>;
492 cluster_sleep_llcc_off: cluster-sleep-2 {
493 compatible = "domain-idle-state";
494 arm,psci-suspend-param = <0x4100b344>;
495 entry-latency-us = <3638>;
496 exit-latency-us = <6562>;
497 min-residency-us = <9826>;
502 cpu0_opp_table: opp-table-cpu0 {
503 compatible = "operating-points-v2";
504 opp-shared;
506 cpu0_opp_300mhz: opp-300000000 {
507 opp-hz = /bits/ 64 <300000000>;
508 opp-peak-kBps = <800000 9600000>;
511 cpu0_opp_691mhz: opp-691200000 {
512 opp-hz = /bits/ 64 <691200000>;
513 opp-peak-kBps = <800000 17817600>;
516 cpu0_opp_806mhz: opp-806400000 {
517 opp-hz = /bits/ 64 <806400000>;
518 opp-peak-kBps = <800000 20889600>;
521 cpu0_opp_941mhz: opp-940800000 {
522 opp-hz = /bits/ 64 <940800000>;
523 opp-peak-kBps = <1804000 24576000>;
526 cpu0_opp_1152mhz: opp-1152000000 {
527 opp-hz = /bits/ 64 <1152000000>;
528 opp-peak-kBps = <2188000 27033600>;
531 cpu0_opp_1325mhz: opp-1324800000 {
532 opp-hz = /bits/ 64 <1324800000>;
533 opp-peak-kBps = <2188000 33792000>;
536 cpu0_opp_1517mhz: opp-1516800000 {
537 opp-hz = /bits/ 64 <1516800000>;
538 opp-peak-kBps = <3072000 38092800>;
541 cpu0_opp_1651mhz: opp-1651200000 {
542 opp-hz = /bits/ 64 <1651200000>;
543 opp-peak-kBps = <3072000 41779200>;
546 cpu0_opp_1805mhz: opp-1804800000 {
547 opp-hz = /bits/ 64 <1804800000>;
548 opp-peak-kBps = <4068000 48537600>;
551 cpu0_opp_1958mhz: opp-1958400000 {
552 opp-hz = /bits/ 64 <1958400000>;
553 opp-peak-kBps = <4068000 48537600>;
556 cpu0_opp_2016mhz: opp-2016000000 {
557 opp-hz = /bits/ 64 <2016000000>;
558 opp-peak-kBps = <6220000 48537600>;
562 cpu4_opp_table: opp-table-cpu4 {
563 compatible = "operating-points-v2";
564 opp-shared;
566 cpu4_opp_691mhz: opp-691200000 {
567 opp-hz = /bits/ 64 <691200000>;
568 opp-peak-kBps = <1804000 9600000>;
571 cpu4_opp_941mhz: opp-940800000 {
572 opp-hz = /bits/ 64 <940800000>;
573 opp-peak-kBps = <2188000 17817600>;
576 cpu4_opp_1229mhz: opp-1228800000 {
577 opp-hz = /bits/ 64 <1228800000>;
578 opp-peak-kBps = <4068000 24576000>;
581 cpu4_opp_1344mhz: opp-1344000000 {
582 opp-hz = /bits/ 64 <1344000000>;
583 opp-peak-kBps = <4068000 24576000>;
586 cpu4_opp_1517mhz: opp-1516800000 {
587 opp-hz = /bits/ 64 <1516800000>;
588 opp-peak-kBps = <4068000 24576000>;
591 cpu4_opp_1651mhz: opp-1651200000 {
592 opp-hz = /bits/ 64 <1651200000>;
593 opp-peak-kBps = <6220000 38092800>;
596 cpu4_opp_1901mhz: opp-1900800000 {
597 opp-hz = /bits/ 64 <1900800000>;
598 opp-peak-kBps = <6220000 44851200>;
601 cpu4_opp_2054mhz: opp-2054400000 {
602 opp-hz = /bits/ 64 <2054400000>;
603 opp-peak-kBps = <6220000 44851200>;
606 cpu4_opp_2112mhz: opp-2112000000 {
607 opp-hz = /bits/ 64 <2112000000>;
608 opp-peak-kBps = <6220000 44851200>;
611 cpu4_opp_2131mhz: opp-2131200000 {
612 opp-hz = /bits/ 64 <2131200000>;
613 opp-peak-kBps = <6220000 44851200>;
616 cpu4_opp_2208mhz: opp-2208000000 {
617 opp-hz = /bits/ 64 <2208000000>;
618 opp-peak-kBps = <6220000 44851200>;
621 cpu4_opp_2400mhz: opp-2400000000 {
622 opp-hz = /bits/ 64 <2400000000>;
623 opp-peak-kBps = <8532000 48537600>;
626 cpu4_opp_2611mhz: opp-2611200000 {
627 opp-hz = /bits/ 64 <2611200000>;
628 opp-peak-kBps = <8532000 48537600>;
632 cpu7_opp_table: opp-table-cpu7 {
633 compatible = "operating-points-v2";
634 opp-shared;
636 cpu7_opp_806mhz: opp-806400000 {
637 opp-hz = /bits/ 64 <806400000>;
638 opp-peak-kBps = <1804000 9600000>;
641 cpu7_opp_1056mhz: opp-1056000000 {
642 opp-hz = /bits/ 64 <1056000000>;
643 opp-peak-kBps = <2188000 17817600>;
646 cpu7_opp_1325mhz: opp-1324800000 {
647 opp-hz = /bits/ 64 <1324800000>;
648 opp-peak-kBps = <4068000 24576000>;
651 cpu7_opp_1517mhz: opp-1516800000 {
652 opp-hz = /bits/ 64 <1516800000>;
653 opp-peak-kBps = <4068000 24576000>;
656 cpu7_opp_1766mhz: opp-1766400000 {
657 opp-hz = /bits/ 64 <1766400000>;
658 opp-peak-kBps = <6220000 38092800>;
661 cpu7_opp_1862mhz: opp-1862400000 {
662 opp-hz = /bits/ 64 <1862400000>;
663 opp-peak-kBps = <6220000 38092800>;
666 cpu7_opp_2035mhz: opp-2035200000 {
667 opp-hz = /bits/ 64 <2035200000>;
668 opp-peak-kBps = <6220000 38092800>;
671 cpu7_opp_2112mhz: opp-2112000000 {
672 opp-hz = /bits/ 64 <2112000000>;
673 opp-peak-kBps = <6220000 44851200>;
676 cpu7_opp_2208mhz: opp-2208000000 {
677 opp-hz = /bits/ 64 <2208000000>;
678 opp-peak-kBps = <6220000 44851200>;
681 cpu7_opp_2381mhz: opp-2380800000 {
682 opp-hz = /bits/ 64 <2380800000>;
683 opp-peak-kBps = <6832000 44851200>;
686 cpu7_opp_2400mhz: opp-2400000000 {
687 opp-hz = /bits/ 64 <2400000000>;
688 opp-peak-kBps = <8532000 48537600>;
691 cpu7_opp_2515mhz: opp-2515200000 {
692 opp-hz = /bits/ 64 <2515200000>;
693 opp-peak-kBps = <8532000 48537600>;
696 cpu7_opp_2707mhz: opp-2707200000 {
697 opp-hz = /bits/ 64 <2707200000>;
698 opp-peak-kBps = <8532000 48537600>;
701 cpu7_opp_3014mhz: opp-3014400000 {
702 opp-hz = /bits/ 64 <3014400000>;
703 opp-peak-kBps = <8532000 48537600>;
715 compatible = "qcom,scm-sc7280", "qcom,scm";
716 qcom,dload-mode = <&tcsr_2 0x13000>;
721 compatible = "qcom,sc7280-clk-virt";
722 #interconnect-cells = <2>;
723 qcom,bcm-voters = <&apps_bcm_voter>;
728 memory-region = <&smem_mem>;
732 smp2p-adsp {
735 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
741 qcom,local-pid = <0>;
742 qcom,remote-pid = <2>;
744 adsp_smp2p_out: master-kernel {
745 qcom,entry-name = "master-kernel";
746 #qcom,smem-state-cells = <1>;
749 adsp_smp2p_in: slave-kernel {
750 qcom,entry-name = "slave-kernel";
751 interrupt-controller;
752 #interrupt-cells = <2>;
756 smp2p-cdsp {
759 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
765 qcom,local-pid = <0>;
766 qcom,remote-pid = <5>;
768 cdsp_smp2p_out: master-kernel {
769 qcom,entry-name = "master-kernel";
770 #qcom,smem-state-cells = <1>;
773 cdsp_smp2p_in: slave-kernel {
774 qcom,entry-name = "slave-kernel";
775 interrupt-controller;
776 #interrupt-cells = <2>;
780 smp2p-mpss {
783 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
789 qcom,local-pid = <0>;
790 qcom,remote-pid = <1>;
792 modem_smp2p_out: master-kernel {
793 qcom,entry-name = "master-kernel";
794 #qcom,smem-state-cells = <1>;
797 modem_smp2p_in: slave-kernel {
798 qcom,entry-name = "slave-kernel";
799 interrupt-controller;
800 #interrupt-cells = <2>;
803 ipa_smp2p_out: ipa-ap-to-modem {
804 qcom,entry-name = "ipa";
805 #qcom,smem-state-cells = <1>;
808 ipa_smp2p_in: ipa-modem-to-ap {
809 qcom,entry-name = "ipa";
810 interrupt-controller;
811 #interrupt-cells = <2>;
815 smp2p-wpss {
818 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
824 qcom,local-pid = <0>;
825 qcom,remote-pid = <13>;
827 wpss_smp2p_out: master-kernel {
828 qcom,entry-name = "master-kernel";
829 #qcom,smem-state-cells = <1>;
832 wpss_smp2p_in: slave-kernel {
833 qcom,entry-name = "slave-kernel";
834 interrupt-controller;
835 #interrupt-cells = <2>;
838 wlan_smp2p_out: wlan-ap-to-wpss {
839 qcom,entry-name = "wlan";
840 #qcom,smem-state-cells = <1>;
843 wlan_smp2p_in: wlan-wpss-to-ap {
844 qcom,entry-name = "wlan";
845 interrupt-controller;
846 #interrupt-cells = <2>;
850 pmu-a55 {
851 compatible = "arm,cortex-a55-pmu";
855 pmu-a78 {
856 compatible = "arm,cortex-a78-pmu";
861 compatible = "arm,psci-1.0";
864 cpu_pd0: power-domain-cpu0 {
865 #power-domain-cells = <0>;
866 power-domains = <&cluster_pd>;
867 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
870 cpu_pd1: power-domain-cpu1 {
871 #power-domain-cells = <0>;
872 power-domains = <&cluster_pd>;
873 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
876 cpu_pd2: power-domain-cpu2 {
877 #power-domain-cells = <0>;
878 power-domains = <&cluster_pd>;
879 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
882 cpu_pd3: power-domain-cpu3 {
883 #power-domain-cells = <0>;
884 power-domains = <&cluster_pd>;
885 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
888 cpu_pd4: power-domain-cpu4 {
889 #power-domain-cells = <0>;
890 power-domains = <&cluster_pd>;
891 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
894 cpu_pd5: power-domain-cpu5 {
895 #power-domain-cells = <0>;
896 power-domains = <&cluster_pd>;
897 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
900 cpu_pd6: power-domain-cpu6 {
901 #power-domain-cells = <0>;
902 power-domains = <&cluster_pd>;
903 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
906 cpu_pd7: power-domain-cpu7 {
907 #power-domain-cells = <0>;
908 power-domains = <&cluster_pd>;
909 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
912 cluster_pd: power-domain-cluster {
913 #power-domain-cells = <0>;
914 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>;
918 qspi_opp_table: opp-table-qspi {
919 compatible = "operating-points-v2";
921 opp-75000000 {
922 opp-hz = /bits/ 64 <75000000>;
923 required-opps = <&rpmhpd_opp_low_svs>;
926 opp-150000000 {
927 opp-hz = /bits/ 64 <150000000>;
928 required-opps = <&rpmhpd_opp_svs>;
931 opp-200000000 {
932 opp-hz = /bits/ 64 <200000000>;
933 required-opps = <&rpmhpd_opp_svs_l1>;
936 opp-300000000 {
937 opp-hz = /bits/ 64 <300000000>;
938 required-opps = <&rpmhpd_opp_nom>;
942 qup_opp_table: opp-table-qup {
943 compatible = "operating-points-v2";
945 opp-75000000 {
946 opp-hz = /bits/ 64 <75000000>;
947 required-opps = <&rpmhpd_opp_low_svs>;
950 opp-100000000 {
951 opp-hz = /bits/ 64 <100000000>;
952 required-opps = <&rpmhpd_opp_svs>;
955 opp-128000000 {
956 opp-hz = /bits/ 64 <128000000>;
957 required-opps = <&rpmhpd_opp_nom>;
962 #address-cells = <2>;
963 #size-cells = <2>;
965 dma-ranges = <0 0 0 0 0x10 0>;
966 compatible = "simple-bus";
968 gcc: clock-controller@100000 {
969 compatible = "qcom,gcc-sc7280";
976 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
981 #clock-cells = <1>;
982 #reset-cells = <1>;
983 #power-domain-cells = <1>;
984 power-domains = <&rpmhpd SC7280_CX>;
988 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
991 interrupt-controller;
992 #interrupt-cells = <3>;
993 #mbox-cells = <2>;
997 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
1003 clock-names = "core";
1004 power-domains = <&rpmhpd SC7280_MX>;
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1008 gpu_speed_bin: gpu-speed-bin@1e9 {
1015 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
1016 pinctrl-names = "default", "sleep";
1017 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1018 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1023 reg-names = "hc", "cqhci";
1028 interrupt-names = "hc_irq", "pwr_irq";
1033 clock-names = "iface", "core", "xo";
1036 interconnect-names = "sdhc-ddr","cpu-sdhc";
1037 power-domains = <&rpmhpd SC7280_CX>;
1038 operating-points-v2 = <&sdhc1_opp_table>;
1040 bus-width = <8>;
1041 supports-cqe;
1042 dma-coherent;
1044 qcom,dll-config = <0x0007642c>;
1045 qcom,ddr-config = <0x80040868>;
1047 mmc-ddr-1_8v;
1048 mmc-hs200-1_8v;
1049 mmc-hs400-1_8v;
1050 mmc-hs400-enhanced-strobe;
1054 sdhc1_opp_table: opp-table {
1055 compatible = "operating-points-v2";
1057 opp-100000000 {
1058 opp-hz = /bits/ 64 <100000000>;
1059 required-opps = <&rpmhpd_opp_low_svs>;
1060 opp-peak-kBps = <1800000 400000>;
1061 opp-avg-kBps = <100000 0>;
1064 opp-384000000 {
1065 opp-hz = /bits/ 64 <384000000>;
1066 required-opps = <&rpmhpd_opp_nom>;
1067 opp-peak-kBps = <5400000 1600000>;
1068 opp-avg-kBps = <390000 0>;
1073 gpi_dma0: dma-controller@900000 {
1074 #dma-cells = <3>;
1075 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1089 dma-channels = <12>;
1090 dma-channel-mask = <0x7f>;
1096 compatible = "qcom,geni-se-qup";
1100 clock-names = "m-ahb", "s-ahb";
1101 #address-cells = <2>;
1102 #size-cells = <2>;
1108 compatible = "qcom,geni-i2c";
1111 clock-names = "se";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&qup_i2c0_data_clk>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1120 interconnect-names = "qup-core", "qup-config",
1121 "qup-memory";
1122 power-domains = <&rpmhpd SC7280_CX>;
1123 required-opps = <&rpmhpd_opp_low_svs>;
1126 dma-names = "tx", "rx";
1131 compatible = "qcom,geni-spi";
1134 clock-names = "se";
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 power-domains = <&rpmhpd SC7280_CX>;
1141 operating-points-v2 = <&qup_opp_table>;
1144 interconnect-names = "qup-core", "qup-config";
1147 dma-names = "tx", "rx";
1152 compatible = "qcom,geni-uart";
1155 clock-names = "se";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1159 power-domains = <&rpmhpd SC7280_CX>;
1160 operating-points-v2 = <&qup_opp_table>;
1163 interconnect-names = "qup-core", "qup-config";
1168 compatible = "qcom,geni-i2c";
1171 clock-names = "se";
1172 pinctrl-names = "default";
1173 pinctrl-0 = <&qup_i2c1_data_clk>;
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1180 interconnect-names = "qup-core", "qup-config",
1181 "qup-memory";
1182 power-domains = <&rpmhpd SC7280_CX>;
1183 required-opps = <&rpmhpd_opp_low_svs>;
1186 dma-names = "tx", "rx";
1191 compatible = "qcom,geni-spi";
1194 clock-names = "se";
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 power-domains = <&rpmhpd SC7280_CX>;
1201 operating-points-v2 = <&qup_opp_table>;
1204 interconnect-names = "qup-core", "qup-config";
1207 dma-names = "tx", "rx";
1212 compatible = "qcom,geni-uart";
1215 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1219 power-domains = <&rpmhpd SC7280_CX>;
1220 operating-points-v2 = <&qup_opp_table>;
1223 interconnect-names = "qup-core", "qup-config";
1228 compatible = "qcom,geni-i2c";
1231 clock-names = "se";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_i2c2_data_clk>;
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1240 interconnect-names = "qup-core", "qup-config",
1241 "qup-memory";
1242 power-domains = <&rpmhpd SC7280_CX>;
1243 required-opps = <&rpmhpd_opp_low_svs>;
1246 dma-names = "tx", "rx";
1251 compatible = "qcom,geni-spi";
1254 clock-names = "se";
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1260 power-domains = <&rpmhpd SC7280_CX>;
1261 operating-points-v2 = <&qup_opp_table>;
1264 interconnect-names = "qup-core", "qup-config";
1267 dma-names = "tx", "rx";
1272 compatible = "qcom,geni-uart";
1275 clock-names = "se";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1279 power-domains = <&rpmhpd SC7280_CX>;
1280 operating-points-v2 = <&qup_opp_table>;
1283 interconnect-names = "qup-core", "qup-config";
1288 compatible = "qcom,geni-i2c";
1291 clock-names = "se";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&qup_i2c3_data_clk>;
1295 #address-cells = <1>;
1296 #size-cells = <0>;
1300 interconnect-names = "qup-core", "qup-config",
1301 "qup-memory";
1302 power-domains = <&rpmhpd SC7280_CX>;
1303 required-opps = <&rpmhpd_opp_low_svs>;
1306 dma-names = "tx", "rx";
1311 compatible = "qcom,geni-spi";
1314 clock-names = "se";
1315 pinctrl-names = "default";
1316 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1318 #address-cells = <1>;
1319 #size-cells = <0>;
1320 power-domains = <&rpmhpd SC7280_CX>;
1321 operating-points-v2 = <&qup_opp_table>;
1324 interconnect-names = "qup-core", "qup-config";
1327 dma-names = "tx", "rx";
1332 compatible = "qcom,geni-uart";
1335 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1339 power-domains = <&rpmhpd SC7280_CX>;
1340 operating-points-v2 = <&qup_opp_table>;
1343 interconnect-names = "qup-core", "qup-config";
1348 compatible = "qcom,geni-i2c";
1351 clock-names = "se";
1352 pinctrl-names = "default";
1353 pinctrl-0 = <&qup_i2c4_data_clk>;
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1360 interconnect-names = "qup-core", "qup-config",
1361 "qup-memory";
1362 power-domains = <&rpmhpd SC7280_CX>;
1363 required-opps = <&rpmhpd_opp_low_svs>;
1366 dma-names = "tx", "rx";
1371 compatible = "qcom,geni-spi";
1374 clock-names = "se";
1375 pinctrl-names = "default";
1376 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1380 power-domains = <&rpmhpd SC7280_CX>;
1381 operating-points-v2 = <&qup_opp_table>;
1384 interconnect-names = "qup-core", "qup-config";
1387 dma-names = "tx", "rx";
1392 compatible = "qcom,geni-uart";
1395 clock-names = "se";
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1399 power-domains = <&rpmhpd SC7280_CX>;
1400 operating-points-v2 = <&qup_opp_table>;
1403 interconnect-names = "qup-core", "qup-config";
1408 compatible = "qcom,geni-i2c";
1411 clock-names = "se";
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&qup_i2c5_data_clk>;
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1420 interconnect-names = "qup-core", "qup-config",
1421 "qup-memory";
1422 power-domains = <&rpmhpd SC7280_CX>;
1423 required-opps = <&rpmhpd_opp_low_svs>;
1426 dma-names = "tx", "rx";
1431 compatible = "qcom,geni-spi";
1434 clock-names = "se";
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1438 #address-cells = <1>;
1439 #size-cells = <0>;
1440 power-domains = <&rpmhpd SC7280_CX>;
1441 operating-points-v2 = <&qup_opp_table>;
1444 interconnect-names = "qup-core", "qup-config";
1447 dma-names = "tx", "rx";
1452 compatible = "qcom,geni-debug-uart";
1455 clock-names = "se";
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1459 power-domains = <&rpmhpd SC7280_CX>;
1460 operating-points-v2 = <&qup_opp_table>;
1463 interconnect-names = "qup-core", "qup-config";
1468 compatible = "qcom,geni-i2c";
1471 clock-names = "se";
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&qup_i2c6_data_clk>;
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1480 interconnect-names = "qup-core", "qup-config",
1481 "qup-memory";
1482 power-domains = <&rpmhpd SC7280_CX>;
1483 required-opps = <&rpmhpd_opp_low_svs>;
1486 dma-names = "tx", "rx";
1491 compatible = "qcom,geni-spi";
1494 clock-names = "se";
1495 pinctrl-names = "default";
1496 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1500 power-domains = <&rpmhpd SC7280_CX>;
1501 operating-points-v2 = <&qup_opp_table>;
1504 interconnect-names = "qup-core", "qup-config";
1507 dma-names = "tx", "rx";
1512 compatible = "qcom,geni-uart";
1515 clock-names = "se";
1516 pinctrl-names = "default";
1517 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1519 power-domains = <&rpmhpd SC7280_CX>;
1520 operating-points-v2 = <&qup_opp_table>;
1523 interconnect-names = "qup-core", "qup-config";
1528 compatible = "qcom,geni-i2c";
1531 clock-names = "se";
1532 pinctrl-names = "default";
1533 pinctrl-0 = <&qup_i2c7_data_clk>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1540 interconnect-names = "qup-core", "qup-config",
1541 "qup-memory";
1542 power-domains = <&rpmhpd SC7280_CX>;
1543 required-opps = <&rpmhpd_opp_low_svs>;
1546 dma-names = "tx", "rx";
1551 compatible = "qcom,geni-spi";
1554 clock-names = "se";
1555 pinctrl-names = "default";
1556 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1560 power-domains = <&rpmhpd SC7280_CX>;
1561 operating-points-v2 = <&qup_opp_table>;
1564 interconnect-names = "qup-core", "qup-config";
1567 dma-names = "tx", "rx";
1572 compatible = "qcom,geni-uart";
1575 clock-names = "se";
1576 pinctrl-names = "default";
1577 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1579 power-domains = <&rpmhpd SC7280_CX>;
1580 operating-points-v2 = <&qup_opp_table>;
1583 interconnect-names = "qup-core", "qup-config";
1588 gpi_dma1: dma-controller@a00000 {
1589 #dma-cells = <3>;
1590 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1604 dma-channels = <12>;
1605 dma-channel-mask = <0x1e>;
1611 compatible = "qcom,geni-se-qup";
1615 clock-names = "m-ahb", "s-ahb";
1616 #address-cells = <2>;
1617 #size-cells = <2>;
1623 compatible = "qcom,geni-i2c";
1626 clock-names = "se";
1627 pinctrl-names = "default";
1628 pinctrl-0 = <&qup_i2c8_data_clk>;
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1635 interconnect-names = "qup-core", "qup-config",
1636 "qup-memory";
1637 power-domains = <&rpmhpd SC7280_CX>;
1638 required-opps = <&rpmhpd_opp_low_svs>;
1641 dma-names = "tx", "rx";
1646 compatible = "qcom,geni-spi";
1649 clock-names = "se";
1650 pinctrl-names = "default";
1651 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1653 #address-cells = <1>;
1654 #size-cells = <0>;
1655 power-domains = <&rpmhpd SC7280_CX>;
1656 operating-points-v2 = <&qup_opp_table>;
1659 interconnect-names = "qup-core", "qup-config";
1662 dma-names = "tx", "rx";
1667 compatible = "qcom,geni-uart";
1670 clock-names = "se";
1671 pinctrl-names = "default";
1672 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1674 power-domains = <&rpmhpd SC7280_CX>;
1675 operating-points-v2 = <&qup_opp_table>;
1678 interconnect-names = "qup-core", "qup-config";
1683 compatible = "qcom,geni-i2c";
1686 clock-names = "se";
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&qup_i2c9_data_clk>;
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1695 interconnect-names = "qup-core", "qup-config",
1696 "qup-memory";
1697 power-domains = <&rpmhpd SC7280_CX>;
1698 required-opps = <&rpmhpd_opp_low_svs>;
1701 dma-names = "tx", "rx";
1706 compatible = "qcom,geni-spi";
1709 clock-names = "se";
1710 pinctrl-names = "default";
1711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1713 #address-cells = <1>;
1714 #size-cells = <0>;
1715 power-domains = <&rpmhpd SC7280_CX>;
1716 operating-points-v2 = <&qup_opp_table>;
1719 interconnect-names = "qup-core", "qup-config";
1722 dma-names = "tx", "rx";
1727 compatible = "qcom,geni-uart";
1730 clock-names = "se";
1731 pinctrl-names = "default";
1732 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1734 power-domains = <&rpmhpd SC7280_CX>;
1735 operating-points-v2 = <&qup_opp_table>;
1738 interconnect-names = "qup-core", "qup-config";
1743 compatible = "qcom,geni-i2c";
1746 clock-names = "se";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_i2c10_data_clk>;
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1755 interconnect-names = "qup-core", "qup-config",
1756 "qup-memory";
1757 power-domains = <&rpmhpd SC7280_CX>;
1758 required-opps = <&rpmhpd_opp_low_svs>;
1761 dma-names = "tx", "rx";
1766 compatible = "qcom,geni-spi";
1769 clock-names = "se";
1770 pinctrl-names = "default";
1771 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1773 #address-cells = <1>;
1774 #size-cells = <0>;
1775 power-domains = <&rpmhpd SC7280_CX>;
1776 operating-points-v2 = <&qup_opp_table>;
1779 interconnect-names = "qup-core", "qup-config";
1782 dma-names = "tx", "rx";
1787 compatible = "qcom,geni-uart";
1790 clock-names = "se";
1791 pinctrl-names = "default";
1792 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1794 power-domains = <&rpmhpd SC7280_CX>;
1795 operating-points-v2 = <&qup_opp_table>;
1798 interconnect-names = "qup-core", "qup-config";
1803 compatible = "qcom,geni-i2c";
1806 clock-names = "se";
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&qup_i2c11_data_clk>;
1810 #address-cells = <1>;
1811 #size-cells = <0>;
1815 interconnect-names = "qup-core", "qup-config",
1816 "qup-memory";
1817 power-domains = <&rpmhpd SC7280_CX>;
1818 required-opps = <&rpmhpd_opp_low_svs>;
1821 dma-names = "tx", "rx";
1826 compatible = "qcom,geni-spi";
1829 clock-names = "se";
1830 pinctrl-names = "default";
1831 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1835 power-domains = <&rpmhpd SC7280_CX>;
1836 operating-points-v2 = <&qup_opp_table>;
1839 interconnect-names = "qup-core", "qup-config";
1842 dma-names = "tx", "rx";
1847 compatible = "qcom,geni-uart";
1850 clock-names = "se";
1851 pinctrl-names = "default";
1852 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1854 power-domains = <&rpmhpd SC7280_CX>;
1855 operating-points-v2 = <&qup_opp_table>;
1858 interconnect-names = "qup-core", "qup-config";
1863 compatible = "qcom,geni-i2c";
1866 clock-names = "se";
1867 pinctrl-names = "default";
1868 pinctrl-0 = <&qup_i2c12_data_clk>;
1870 #address-cells = <1>;
1871 #size-cells = <0>;
1875 interconnect-names = "qup-core", "qup-config",
1876 "qup-memory";
1877 power-domains = <&rpmhpd SC7280_CX>;
1878 required-opps = <&rpmhpd_opp_low_svs>;
1881 dma-names = "tx", "rx";
1886 compatible = "qcom,geni-spi";
1889 clock-names = "se";
1890 pinctrl-names = "default";
1891 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1893 #address-cells = <1>;
1894 #size-cells = <0>;
1895 power-domains = <&rpmhpd SC7280_CX>;
1896 operating-points-v2 = <&qup_opp_table>;
1899 interconnect-names = "qup-core", "qup-config";
1902 dma-names = "tx", "rx";
1907 compatible = "qcom,geni-uart";
1910 clock-names = "se";
1911 pinctrl-names = "default";
1912 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1914 power-domains = <&rpmhpd SC7280_CX>;
1915 operating-points-v2 = <&qup_opp_table>;
1918 interconnect-names = "qup-core", "qup-config";
1923 compatible = "qcom,geni-i2c";
1926 clock-names = "se";
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&qup_i2c13_data_clk>;
1930 #address-cells = <1>;
1931 #size-cells = <0>;
1935 interconnect-names = "qup-core", "qup-config",
1936 "qup-memory";
1937 power-domains = <&rpmhpd SC7280_CX>;
1938 required-opps = <&rpmhpd_opp_low_svs>;
1941 dma-names = "tx", "rx";
1946 compatible = "qcom,geni-spi";
1949 clock-names = "se";
1950 pinctrl-names = "default";
1951 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1953 #address-cells = <1>;
1954 #size-cells = <0>;
1955 power-domains = <&rpmhpd SC7280_CX>;
1956 operating-points-v2 = <&qup_opp_table>;
1959 interconnect-names = "qup-core", "qup-config";
1962 dma-names = "tx", "rx";
1967 compatible = "qcom,geni-uart";
1970 clock-names = "se";
1971 pinctrl-names = "default";
1972 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1974 power-domains = <&rpmhpd SC7280_CX>;
1975 operating-points-v2 = <&qup_opp_table>;
1978 interconnect-names = "qup-core", "qup-config";
1983 compatible = "qcom,geni-i2c";
1986 clock-names = "se";
1987 pinctrl-names = "default";
1988 pinctrl-0 = <&qup_i2c14_data_clk>;
1990 #address-cells = <1>;
1991 #size-cells = <0>;
1995 interconnect-names = "qup-core", "qup-config",
1996 "qup-memory";
1997 power-domains = <&rpmhpd SC7280_CX>;
1998 required-opps = <&rpmhpd_opp_low_svs>;
2001 dma-names = "tx", "rx";
2006 compatible = "qcom,geni-spi";
2009 clock-names = "se";
2010 pinctrl-names = "default";
2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2013 #address-cells = <1>;
2014 #size-cells = <0>;
2015 power-domains = <&rpmhpd SC7280_CX>;
2016 operating-points-v2 = <&qup_opp_table>;
2019 interconnect-names = "qup-core", "qup-config";
2022 dma-names = "tx", "rx";
2027 compatible = "qcom,geni-uart";
2030 clock-names = "se";
2031 pinctrl-names = "default";
2032 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2034 power-domains = <&rpmhpd SC7280_CX>;
2035 operating-points-v2 = <&qup_opp_table>;
2038 interconnect-names = "qup-core", "qup-config";
2043 compatible = "qcom,geni-i2c";
2046 clock-names = "se";
2047 pinctrl-names = "default";
2048 pinctrl-0 = <&qup_i2c15_data_clk>;
2050 #address-cells = <1>;
2051 #size-cells = <0>;
2055 interconnect-names = "qup-core", "qup-config",
2056 "qup-memory";
2057 power-domains = <&rpmhpd SC7280_CX>;
2058 required-opps = <&rpmhpd_opp_low_svs>;
2061 dma-names = "tx", "rx";
2066 compatible = "qcom,geni-spi";
2069 clock-names = "se";
2070 pinctrl-names = "default";
2071 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2073 #address-cells = <1>;
2074 #size-cells = <0>;
2075 power-domains = <&rpmhpd SC7280_CX>;
2076 operating-points-v2 = <&qup_opp_table>;
2079 interconnect-names = "qup-core", "qup-config";
2082 dma-names = "tx", "rx";
2087 compatible = "qcom,geni-uart";
2090 clock-names = "se";
2091 pinctrl-names = "default";
2092 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2094 power-domains = <&rpmhpd SC7280_CX>;
2095 operating-points-v2 = <&qup_opp_table>;
2098 interconnect-names = "qup-core", "qup-config";
2104 compatible = "qcom,sc7280-trng", "qcom,trng";
2110 compatible = "qcom,sc7280-cnoc2";
2111 #interconnect-cells = <2>;
2112 qcom,bcm-voters = <&apps_bcm_voter>;
2117 compatible = "qcom,sc7280-cnoc3";
2118 #interconnect-cells = <2>;
2119 qcom,bcm-voters = <&apps_bcm_voter>;
2124 compatible = "qcom,sc7280-mc-virt";
2125 #interconnect-cells = <2>;
2126 qcom,bcm-voters = <&apps_bcm_voter>;
2131 compatible = "qcom,sc7280-system-noc";
2132 #interconnect-cells = <2>;
2133 qcom,bcm-voters = <&apps_bcm_voter>;
2137 compatible = "qcom,sc7280-aggre1-noc";
2139 #interconnect-cells = <2>;
2140 qcom,bcm-voters = <&apps_bcm_voter>;
2147 compatible = "qcom,sc7280-aggre2-noc";
2148 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&apps_bcm_voter>;
2155 compatible = "qcom,sc7280-mmss-noc";
2156 #interconnect-cells = <2>;
2157 qcom,bcm-voters = <&apps_bcm_voter>;
2161 compatible = "qcom,wcn6750-wifi";
2197 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2199 qcom,smem-states = <&wlan_smp2p_out 0>;
2200 qcom,smem-state-names = "wlan-smp2p-out";
2204 compatible = "qcom,pcie-sc7280";
2211 reg-names = "parf", "dbi", "elbi", "atu", "config";
2213 linux,pci-domain = <1>;
2214 bus-range = <0x00 0xff>;
2215 num-lanes = <2>;
2217 #address-cells = <3>;
2218 #size-cells = <2>;
2232 interrupt-names = "msi0",
2241 #interrupt-cells = <1>;
2242 interrupt-map-mask = <0 0 0 0x7>;
2243 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2262 clock-names = "pipe",
2276 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2277 assigned-clock-rates = <19200000>;
2280 reset-names = "pci";
2282 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2285 phy-names = "pciephy";
2287 pinctrl-names = "default";
2288 pinctrl-0 = <&pcie1_clkreq_n>;
2290 dma-coherent;
2292 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2300 bus-range = <0x01 0xff>;
2302 #address-cells = <3>;
2303 #size-cells = <2>;
2309 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2316 clock-names = "aux",
2322 clock-output-names = "pcie_1_pipe_clk";
2323 #clock-cells = <0>;
2325 #phy-cells = <0>;
2328 reset-names = "phy";
2330 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2331 assigned-clock-rates = <100000000>;
2337 compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
2338 "jedec,ufs-2.0";
2342 phy-names = "ufsphy";
2343 lanes-per-direction = <2>;
2344 #reset-cells = <1>;
2346 reset-names = "rst";
2348 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2349 required-opps = <&rpmhpd_opp_nom>;
2352 dma-coherent;
2358 interconnect-names = "ufs-ddr", "cpu-ufs";
2368 clock-names = "core_clk",
2377 operating-points-v2 = <&ufs_opp_table>;
2383 ufs_opp_table: opp-table {
2384 compatible = "operating-points-v2";
2386 opp-75000000 {
2387 opp-hz = /bits/ 64 <75000000>,
2395 required-opps = <&rpmhpd_opp_low_svs>;
2398 opp-150000000 {
2399 opp-hz = /bits/ 64 <150000000>,
2407 required-opps = <&rpmhpd_opp_svs>;
2410 opp-300000000 {
2411 opp-hz = /bits/ 64 <300000000>,
2419 required-opps = <&rpmhpd_opp_nom>;
2425 compatible = "qcom,sc7280-qmp-ufs-phy";
2430 clock-names = "ref", "ref_aux", "qref";
2432 power-domains = <&rpmhpd SC7280_MX>;
2435 reset-names = "ufsphy";
2437 #clock-cells = <1>;
2438 #phy-cells = <0>;
2444 compatible = "qcom,sc7280-inline-crypto-engine",
2445 "qcom,inline-crypto-engine";
2450 cryptobam: dma-controller@1dc4000 {
2451 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2454 #dma-cells = <1>;
2458 qcom,controlled-remotely;
2459 num-channels = <16>;
2460 qcom,num-ees = <4>;
2464 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
2467 dma-names = "rx", "tx";
2471 interconnect-names = "memory";
2475 compatible = "qcom,sc7280-ipa";
2482 reg-names = "ipa-reg",
2483 "ipa-shared",
2486 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2490 interrupt-names = "ipa",
2492 "ipa-clock-query",
2493 "ipa-setup-ready";
2496 clock-names = "core";
2500 interconnect-names = "memory",
2505 qcom,smem-states = <&ipa_smp2p_out 0>,
2507 qcom,smem-state-names = "ipa-clock-enabled-valid",
2508 "ipa-clock-enabled";
2514 compatible = "qcom,tcsr-mutex";
2516 #hwlock-cells = <1>;
2520 compatible = "qcom,sc7280-tcsr", "syscon";
2525 compatible = "qcom,sc7280-tcsr", "syscon";
2530 compatible = "qcom,sc7280-lpasscc";
2533 reg-names = "qdsp6ss", "top_cc";
2535 clock-names = "iface";
2536 #clock-cells = <1>;
2541 compatible = "qcom,sc7280-lpass-rx-macro";
2544 pinctrl-names = "default";
2545 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2550 clock-names = "mclk", "npl", "fsgen";
2552 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2554 power-domain-names = "macro", "dcodec";
2556 #clock-cells = <0>;
2557 #sound-dai-cells = <1>;
2563 compatible = "qcom,soundwire-v1.6.0";
2568 clock-names = "iface";
2570 qcom,din-ports = <0>;
2571 qcom,dout-ports = <5>;
2574 reset-names = "swr_audio_cgcr";
2576 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2577 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2578 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2579 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2580 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2581 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2582 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2583 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2584 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2586 #sound-dai-cells = <1>;
2587 #address-cells = <2>;
2588 #size-cells = <0>;
2594 compatible = "qcom,sc7280-lpass-tx-macro";
2597 pinctrl-names = "default";
2598 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2603 clock-names = "mclk", "npl", "fsgen";
2605 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2607 power-domain-names = "macro", "dcodec";
2609 #clock-cells = <0>;
2610 #sound-dai-cells = <1>;
2616 compatible = "qcom,soundwire-v1.6.0";
2619 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2622 clock-names = "iface";
2624 qcom,din-ports = <3>;
2625 qcom,dout-ports = <0>;
2628 reset-names = "swr_audio_cgcr";
2630 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2631 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2632 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2633 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2634 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2635 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2636 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2637 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2638 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2640 #sound-dai-cells = <1>;
2641 #address-cells = <2>;
2642 #size-cells = <0>;
2647 lpass_audiocc: clock-controller@3300000 {
2648 compatible = "qcom,sc7280-lpassaudiocc";
2653 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2654 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2655 #clock-cells = <1>;
2656 #power-domain-cells = <1>;
2657 #reset-cells = <1>;
2661 compatible = "qcom,sc7280-lpass-va-macro";
2665 clock-names = "mclk";
2667 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2669 power-domain-names = "macro", "dcodec";
2671 #clock-cells = <0>;
2672 #sound-dai-cells = <1>;
2677 lpass_aon: clock-controller@3380000 {
2678 compatible = "qcom,sc7280-lpassaoncc";
2683 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2684 #clock-cells = <1>;
2685 #power-domain-cells = <1>;
2689 lpass_core: clock-controller@3900000 {
2690 compatible = "qcom,sc7280-lpasscorecc";
2693 clock-names = "bi_tcxo";
2694 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2695 #clock-cells = <1>;
2696 #power-domain-cells = <1>;
2701 compatible = "qcom,sc7280-lpass-cpu";
2709 reg-names = "lpass-hdmiif",
2710 "lpass-lpaif",
2711 "lpass-rxtx-cdc-dma-lpm",
2712 "lpass-rxtx-lpaif",
2713 "lpass-va-lpaif",
2714 "lpass-va-cdc-dma-lpm";
2720 power-domains = <&rpmhpd SC7280_LCX>;
2721 power-domain-names = "lcx";
2722 required-opps = <&rpmhpd_opp_nom>;
2734 clock-names = "aon_cc_audio_hm_h",
2745 #sound-dai-cells = <1>;
2746 #address-cells = <1>;
2747 #size-cells = <0>;
2753 interrupt-names = "lpass-irq-lpaif",
2754 "lpass-irq-hdmi",
2755 "lpass-irq-vaif",
2756 "lpass-irq-rxtxif";
2761 slimbam: dma-controller@3a84000 {
2762 compatible = "qcom,bam-v1.7.0";
2765 #dma-cells = <1>;
2766 qcom,controlled-remotely;
2767 num-channels = <31>;
2769 qcom,num-ees = <2>;
2774 slim: slim-ngd@3ac0000 {
2775 compatible = "qcom,slim-ngd-v1.5.0";
2779 dma-names = "rx", "tx";
2781 #address-cells = <1>;
2782 #size-cells = <0>;
2786 lpass_hm: clock-controller@3c00000 {
2787 compatible = "qcom,sc7280-lpasshm";
2790 clock-names = "bi_tcxo";
2791 #clock-cells = <1>;
2792 #power-domain-cells = <1>;
2798 compatible = "qcom,sc7280-lpass-ag-noc";
2799 #interconnect-cells = <2>;
2800 qcom,bcm-voters = <&apps_bcm_voter>;
2804 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2807 gpio-controller;
2808 #gpio-cells = <2>;
2809 gpio-ranges = <&lpass_tlmm 0 0 15>;
2811 lpass_dmic01_clk: dmic01-clk-state {
2816 lpass_dmic01_data: dmic01-data-state {
2821 lpass_dmic23_clk: dmic23-clk-state {
2826 lpass_dmic23_data: dmic23-data-state {
2831 lpass_rx_swr_clk: rx-swr-clk-state {
2836 lpass_rx_swr_data: rx-swr-data-state {
2841 lpass_tx_swr_clk: tx-swr-clk-state {
2846 lpass_tx_swr_data: tx-swr-data-state {
2853 compatible = "qcom,adreno-635.0", "qcom,adreno";
2857 reg-names = "kgsl_3d0_reg_memory",
2863 operating-points-v2 = <&gpu_opp_table>;
2866 interconnect-names = "gfx-mem";
2867 #cooling-cells = <2>;
2869 nvmem-cells = <&gpu_speed_bin>;
2870 nvmem-cell-names = "speed_bin";
2874 gpu_zap_shader: zap-shader {
2875 memory-region = <&gpu_zap_mem>;
2878 gpu_opp_table: opp-table {
2879 compatible = "operating-points-v2";
2881 opp-315000000 {
2882 opp-hz = /bits/ 64 <315000000>;
2883 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2884 opp-peak-kBps = <1804000>;
2885 opp-supported-hw = <0x17>;
2888 opp-450000000 {
2889 opp-hz = /bits/ 64 <450000000>;
2890 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2891 opp-peak-kBps = <4068000>;
2892 opp-supported-hw = <0x17>;
2896 opp-550000000-0 {
2897 opp-hz = /bits/ 64 <550000000>;
2898 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2899 opp-peak-kBps = <8368000>;
2900 opp-supported-hw = <0x01>;
2903 opp-550000000-1 {
2904 opp-hz = /bits/ 64 <550000000>;
2905 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2906 opp-peak-kBps = <6832000>;
2907 opp-supported-hw = <0x16>;
2910 opp-608000000 {
2911 opp-hz = /bits/ 64 <608000000>;
2912 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2913 opp-peak-kBps = <8368000>;
2914 opp-supported-hw = <0x16>;
2917 opp-700000000 {
2918 opp-hz = /bits/ 64 <700000000>;
2919 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2920 opp-peak-kBps = <8532000>;
2921 opp-supported-hw = <0x06>;
2924 opp-812000000 {
2925 opp-hz = /bits/ 64 <812000000>;
2926 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2927 opp-peak-kBps = <8532000>;
2928 opp-supported-hw = <0x06>;
2931 opp-840000000 {
2932 opp-hz = /bits/ 64 <840000000>;
2933 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2934 opp-peak-kBps = <8532000>;
2935 opp-supported-hw = <0x02>;
2938 opp-900000000 {
2939 opp-hz = /bits/ 64 <900000000>;
2940 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2941 opp-peak-kBps = <8532000>;
2942 opp-supported-hw = <0x02>;
2948 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2952 reg-names = "gmu", "rscc", "gmu_pdc";
2955 interrupt-names = "hfi", "gmu";
2963 clock-names = "gmu",
2970 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2972 power-domain-names = "cx",
2975 operating-points-v2 = <&gmu_opp_table>;
2977 gmu_opp_table: opp-table {
2978 compatible = "operating-points-v2";
2980 opp-200000000 {
2981 opp-hz = /bits/ 64 <200000000>;
2982 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2987 gpucc: clock-controller@3d90000 {
2988 compatible = "qcom,sc7280-gpucc";
2993 clock-names = "bi_tcxo",
2996 #clock-cells = <1>;
2997 #reset-cells = <1>;
2998 #power-domain-cells = <1>;
3002 compatible = "qcom,sc7280-dcc", "qcom,dcc";
3008 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
3009 "qcom,smmu-500", "arm,mmu-500";
3011 #iommu-cells = <2>;
3012 #global-interrupts = <2>;
3033 clock-names = "gcc_gpu_memnoc_gfx_clk",
3041 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3042 dma-coherent;
3046 compatible = "qcom,sc7280-tbu";
3048 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3052 compatible = "qcom,sc7280-tbu";
3054 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3058 compatible = "qcom,sc7280-mpss-pas";
3061 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3067 interrupt-names = "wdog", "fatal", "ready", "handover",
3068 "stop-ack", "shutdown-ack";
3071 clock-names = "xo";
3073 power-domains = <&rpmhpd SC7280_CX>,
3075 power-domain-names = "cx", "mss";
3077 memory-region = <&mpss_mem>;
3081 qcom,smem-states = <&modem_smp2p_out 0>;
3082 qcom,smem-state-names = "stop";
3086 glink-edge {
3087 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3093 qcom,remote-pid = <1>;
3098 compatible = "arm,coresight-stm", "arm,primecell";
3101 reg-names = "stm-base", "stm-stimulus-base";
3104 clock-names = "apb_pclk";
3106 out-ports {
3109 remote-endpoint = <&funnel0_in7>;
3116 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3120 clock-names = "apb_pclk";
3122 out-ports {
3125 remote-endpoint = <&merge_funnel_in0>;
3130 in-ports {
3131 #address-cells = <1>;
3132 #size-cells = <0>;
3137 remote-endpoint = <&stm_out>;
3144 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3148 clock-names = "apb_pclk";
3150 out-ports {
3153 remote-endpoint = <&merge_funnel_in1>;
3158 in-ports {
3159 #address-cells = <1>;
3160 #size-cells = <0>;
3165 remote-endpoint = <&apss_merge_funnel_out>;
3172 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3176 clock-names = "apb_pclk";
3178 out-ports {
3181 remote-endpoint = <&swao_funnel_in>;
3186 in-ports {
3187 #address-cells = <1>;
3188 #size-cells = <0>;
3193 remote-endpoint = <&funnel0_out>;
3200 remote-endpoint = <&funnel1_out>;
3207 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3211 clock-names = "apb_pclk";
3213 out-ports {
3216 remote-endpoint = <&etr_in>;
3221 in-ports {
3224 remote-endpoint = <&swao_replicator_out>;
3231 compatible = "arm,coresight-tmc", "arm,primecell";
3236 clock-names = "apb_pclk";
3237 arm,scatter-gather;
3239 in-ports {
3242 remote-endpoint = <&replicator_out>;
3249 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3253 clock-names = "apb_pclk";
3255 out-ports {
3258 remote-endpoint = <&etf_in>;
3263 in-ports {
3264 #address-cells = <1>;
3265 #size-cells = <0>;
3270 remote-endpoint = <&merge_funnel_out>;
3277 compatible = "arm,coresight-tmc", "arm,primecell";
3281 clock-names = "apb_pclk";
3283 out-ports {
3286 remote-endpoint = <&swao_replicator_in>;
3291 in-ports {
3294 remote-endpoint = <&swao_funnel_out>;
3301 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3305 clock-names = "apb_pclk";
3306 qcom,replicator-loses-context;
3308 out-ports {
3311 remote-endpoint = <&replicator_in>;
3316 in-ports {
3319 remote-endpoint = <&etf_out>;
3326 compatible = "arm,coresight-etm4x", "arm,primecell";
3332 clock-names = "apb_pclk";
3333 arm,coresight-loses-context-with-cpu;
3334 qcom,skip-power-up;
3336 out-ports {
3339 remote-endpoint = <&apss_funnel_in0>;
3346 compatible = "arm,coresight-etm4x", "arm,primecell";
3352 clock-names = "apb_pclk";
3353 arm,coresight-loses-context-with-cpu;
3354 qcom,skip-power-up;
3356 out-ports {
3359 remote-endpoint = <&apss_funnel_in1>;
3366 compatible = "arm,coresight-etm4x", "arm,primecell";
3372 clock-names = "apb_pclk";
3373 arm,coresight-loses-context-with-cpu;
3374 qcom,skip-power-up;
3376 out-ports {
3379 remote-endpoint = <&apss_funnel_in2>;
3386 compatible = "arm,coresight-etm4x", "arm,primecell";
3392 clock-names = "apb_pclk";
3393 arm,coresight-loses-context-with-cpu;
3394 qcom,skip-power-up;
3396 out-ports {
3399 remote-endpoint = <&apss_funnel_in3>;
3406 compatible = "arm,coresight-etm4x", "arm,primecell";
3412 clock-names = "apb_pclk";
3413 arm,coresight-loses-context-with-cpu;
3414 qcom,skip-power-up;
3416 out-ports {
3419 remote-endpoint = <&apss_funnel_in4>;
3426 compatible = "arm,coresight-etm4x", "arm,primecell";
3432 clock-names = "apb_pclk";
3433 arm,coresight-loses-context-with-cpu;
3434 qcom,skip-power-up;
3436 out-ports {
3439 remote-endpoint = <&apss_funnel_in5>;
3446 compatible = "arm,coresight-etm4x", "arm,primecell";
3452 clock-names = "apb_pclk";
3453 arm,coresight-loses-context-with-cpu;
3454 qcom,skip-power-up;
3456 out-ports {
3459 remote-endpoint = <&apss_funnel_in6>;
3466 compatible = "arm,coresight-etm4x", "arm,primecell";
3472 clock-names = "apb_pclk";
3473 arm,coresight-loses-context-with-cpu;
3474 qcom,skip-power-up;
3476 out-ports {
3479 remote-endpoint = <&apss_funnel_in7>;
3486 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3490 clock-names = "apb_pclk";
3492 out-ports {
3495 remote-endpoint = <&apss_merge_funnel_in>;
3500 in-ports {
3501 #address-cells = <1>;
3502 #size-cells = <0>;
3507 remote-endpoint = <&etm0_out>;
3514 remote-endpoint = <&etm1_out>;
3521 remote-endpoint = <&etm2_out>;
3528 remote-endpoint = <&etm3_out>;
3535 remote-endpoint = <&etm4_out>;
3542 remote-endpoint = <&etm5_out>;
3549 remote-endpoint = <&etm6_out>;
3556 remote-endpoint = <&etm7_out>;
3563 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3567 clock-names = "apb_pclk";
3569 out-ports {
3572 remote-endpoint = <&funnel1_in4>;
3577 in-ports {
3580 remote-endpoint = <&apss_funnel_out>;
3587 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3588 pinctrl-names = "default", "sleep";
3589 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3590 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3598 interrupt-names = "hc_irq", "pwr_irq";
3603 clock-names = "iface", "core", "xo";
3606 interconnect-names = "sdhc-ddr","cpu-sdhc";
3607 power-domains = <&rpmhpd SC7280_CX>;
3608 operating-points-v2 = <&sdhc2_opp_table>;
3610 bus-width = <4>;
3611 dma-coherent;
3613 qcom,dll-config = <0x0007642c>;
3617 sdhc2_opp_table: opp-table {
3618 compatible = "operating-points-v2";
3620 opp-100000000 {
3621 opp-hz = /bits/ 64 <100000000>;
3622 required-opps = <&rpmhpd_opp_low_svs>;
3623 opp-peak-kBps = <1800000 400000>;
3624 opp-avg-kBps = <100000 0>;
3627 opp-202000000 {
3628 opp-hz = /bits/ 64 <202000000>;
3629 required-opps = <&rpmhpd_opp_nom>;
3630 opp-peak-kBps = <5400000 1600000>;
3631 opp-avg-kBps = <200000 0>;
3637 compatible = "qcom,sc7280-usb-hs-phy",
3638 "qcom,usb-snps-hs-7nm-phy";
3641 #phy-cells = <0>;
3644 clock-names = "ref";
3650 compatible = "qcom,sc7280-usb-hs-phy",
3651 "qcom,usb-snps-hs-7nm-phy";
3654 #phy-cells = <0>;
3657 clock-names = "ref";
3663 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3671 clock-names = "aux",
3678 reset-names = "phy", "common";
3680 #clock-cells = <1>;
3681 #phy-cells = <1>;
3683 orientation-switch;
3686 #address-cells = <1>;
3687 #size-cells = <0>;
3700 remote-endpoint = <&usb_1_dwc3_ss>;
3708 remote-endpoint = <&mdss_dp_out>;
3715 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3718 #address-cells = <2>;
3719 #size-cells = <2>;
3721 dma-ranges;
3728 clock-names = "cfg_noc",
3734 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3736 assigned-clock-rates = <19200000>, <200000000>;
3738 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3742 interrupt-names = "pwr_event",
3747 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3748 required-opps = <&rpmhpd_opp_nom>;
3754 interconnect-names = "usb-ddr", "apps-usb";
3763 snps,dis-u1-entry-quirk;
3764 snps,dis-u2-entry-quirk;
3766 phy-names = "usb2-phy";
3767 maximum-speed = "high-speed";
3768 usb-role-switch;
3772 remote-endpoint = <&eud_ep>;
3779 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3782 #address-cells = <1>;
3783 #size-cells = <0>;
3787 clock-names = "iface", "core";
3790 interconnect-names = "qspi-config";
3791 power-domains = <&rpmhpd SC7280_CX>;
3792 operating-points-v2 = <&qspi_opp_table>;
3797 compatible = "qcom,sc7280-adsp-pas";
3800 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3806 interrupt-names = "wdog", "fatal", "ready", "handover",
3807 "stop-ack", "shutdown-ack";
3810 clock-names = "xo";
3812 power-domains = <&rpmhpd SC7280_LCX>,
3814 power-domain-names = "lcx", "lmx";
3816 memory-region = <&adsp_mem>;
3820 qcom,smem-states = <&adsp_smp2p_out 0>;
3821 qcom,smem-state-names = "stop";
3825 glink-edge {
3826 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3834 qcom,remote-pid = <2>;
3837 compatible = "qcom,apr-v2";
3838 qcom,glink-channels = "apr_audio_svc";
3840 #address-cells = <1>;
3841 #size-cells = <0>;
3846 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3852 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3855 compatible = "qcom,q6afe-dais";
3856 #address-cells = <1>;
3857 #size-cells = <0>;
3858 #sound-dai-cells = <1>;
3861 q6afecc: clock-controller {
3862 compatible = "qcom,q6afe-clocks";
3863 #clock-cells = <2>;
3870 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3873 compatible = "qcom,q6asm-dais";
3874 #address-cells = <1>;
3875 #size-cells = <0>;
3876 #sound-dai-cells = <1>;
3896 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3899 compatible = "qcom,q6adm-routing";
3900 #sound-dai-cells = <0>;
3907 qcom,glink-channels = "fastrpcglink-apps-dsp";
3909 qcom,non-secure-domain;
3910 #address-cells = <1>;
3911 #size-cells = <0>;
3913 compute-cb@3 {
3914 compatible = "qcom,fastrpc-compute-cb";
3917 dma-coherent;
3920 compute-cb@4 {
3921 compatible = "qcom,fastrpc-compute-cb";
3924 dma-coherent;
3927 compute-cb@5 {
3928 compatible = "qcom,fastrpc-compute-cb";
3931 dma-coherent;
3938 compatible = "qcom,sc7280-wpss-pas";
3941 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3947 interrupt-names = "wdog", "fatal", "ready", "handover",
3948 "stop-ack", "shutdown-ack";
3951 clock-names = "xo";
3953 power-domains = <&rpmhpd SC7280_CX>,
3955 power-domain-names = "cx", "mx";
3957 memory-region = <&wpss_mem>;
3961 qcom,smem-states = <&wpss_smp2p_out 0>;
3962 qcom,smem-state-names = "stop";
3967 glink-edge {
3968 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3975 qcom,remote-pid = <13>;
3980 compatible = "qcom,sc7280-llcc-bwmon";
3987 operating-points-v2 = <&llcc_bwmon_opp_table>;
3989 llcc_bwmon_opp_table: opp-table {
3990 compatible = "operating-points-v2";
3992 opp-0 {
3993 opp-peak-kBps = <800000>;
3995 opp-1 {
3996 opp-peak-kBps = <1804000>;
3998 opp-2 {
3999 opp-peak-kBps = <2188000>;
4001 opp-3 {
4002 opp-peak-kBps = <3072000>;
4004 opp-4 {
4005 opp-peak-kBps = <4068000>;
4007 opp-5 {
4008 opp-peak-kBps = <6220000>;
4010 opp-6 {
4011 opp-peak-kBps = <6832000>;
4013 opp-7 {
4014 opp-peak-kBps = <8532000>;
4020 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
4026 operating-points-v2 = <&cpu_bwmon_opp_table>;
4028 cpu_bwmon_opp_table: opp-table {
4029 compatible = "operating-points-v2";
4031 opp-0 {
4032 opp-peak-kBps = <2400000>;
4034 opp-1 {
4035 opp-peak-kBps = <4800000>;
4037 opp-2 {
4038 opp-peak-kBps = <7456000>;
4040 opp-3 {
4041 opp-peak-kBps = <9600000>;
4043 opp-4 {
4044 opp-peak-kBps = <12896000>;
4046 opp-5 {
4047 opp-peak-kBps = <14928000>;
4049 opp-6 {
4050 opp-peak-kBps = <17056000>;
4057 compatible = "qcom,sc7280-dc-noc";
4058 #interconnect-cells = <2>;
4059 qcom,bcm-voters = <&apps_bcm_voter>;
4064 compatible = "qcom,sc7280-gem-noc";
4065 #interconnect-cells = <2>;
4066 qcom,bcm-voters = <&apps_bcm_voter>;
4069 system-cache-controller@9200000 {
4070 compatible = "qcom,sc7280-llcc";
4073 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
4078 compatible = "qcom,sc7280-eud", "qcom,eud";
4081 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
4086 #address-cells = <1>;
4087 #size-cells = <0>;
4092 remote-endpoint = <&usb2_role_switch>;
4100 compatible = "qcom,sc7280-nsp-noc";
4101 #interconnect-cells = <2>;
4102 qcom,bcm-voters = <&apps_bcm_voter>;
4106 compatible = "qcom,sc7280-cdsp-pas";
4109 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4115 interrupt-names = "wdog", "fatal", "ready", "handover",
4116 "stop-ack", "shutdown-ack";
4119 clock-names = "xo";
4121 power-domains = <&rpmhpd SC7280_CX>,
4123 power-domain-names = "cx", "mx";
4127 memory-region = <&cdsp_mem>;
4131 qcom,smem-states = <&cdsp_smp2p_out 0>;
4132 qcom,smem-state-names = "stop";
4136 glink-edge {
4137 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4144 qcom,remote-pid = <5>;
4148 qcom,glink-channels = "fastrpcglink-apps-dsp";
4150 qcom,non-secure-domain;
4151 #address-cells = <1>;
4152 #size-cells = <0>;
4154 compute-cb@1 {
4155 compatible = "qcom,fastrpc-compute-cb";
4159 dma-coherent;
4162 compute-cb@2 {
4163 compatible = "qcom,fastrpc-compute-cb";
4167 dma-coherent;
4170 compute-cb@3 {
4171 compatible = "qcom,fastrpc-compute-cb";
4175 dma-coherent;
4178 compute-cb@4 {
4179 compatible = "qcom,fastrpc-compute-cb";
4183 dma-coherent;
4186 compute-cb@5 {
4187 compatible = "qcom,fastrpc-compute-cb";
4191 dma-coherent;
4194 compute-cb@6 {
4195 compatible = "qcom,fastrpc-compute-cb";
4199 dma-coherent;
4202 compute-cb@7 {
4203 compatible = "qcom,fastrpc-compute-cb";
4207 dma-coherent;
4210 compute-cb@8 {
4211 compatible = "qcom,fastrpc-compute-cb";
4215 dma-coherent;
4220 compute-cb@11 {
4221 compatible = "qcom,fastrpc-compute-cb";
4225 dma-coherent;
4228 compute-cb@12 {
4229 compatible = "qcom,fastrpc-compute-cb";
4233 dma-coherent;
4236 compute-cb@13 {
4237 compatible = "qcom,fastrpc-compute-cb";
4241 dma-coherent;
4244 compute-cb@14 {
4245 compatible = "qcom,fastrpc-compute-cb";
4249 dma-coherent;
4256 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
4259 #address-cells = <2>;
4260 #size-cells = <2>;
4262 dma-ranges;
4269 clock-names = "cfg_noc",
4275 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4277 assigned-clock-rates = <19200000>, <200000000>;
4279 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4284 interrupt-names = "pwr_event",
4290 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4291 required-opps = <&rpmhpd_opp_nom>;
4297 interconnect-names = "usb-ddr", "apps-usb";
4299 wakeup-source;
4308 snps,parkmode-disable-ss-quirk;
4309 snps,dis-u1-entry-quirk;
4310 snps,dis-u2-entry-quirk;
4312 phy-names = "usb2-phy", "usb3-phy";
4313 maximum-speed = "super-speed";
4316 #address-cells = <1>;
4317 #size-cells = <0>;
4330 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
4337 venus: video-codec@aa00000 {
4338 compatible = "qcom,sc7280-venus";
4347 clock-names = "core", "bus", "iface",
4350 power-domains = <&videocc MVSC_GDSC>,
4353 power-domain-names = "venus", "vcodec0", "cx";
4354 operating-points-v2 = <&venus_opp_table>;
4358 interconnect-names = "cpu-cfg", "video-mem";
4361 memory-region = <&video_mem>;
4365 venus_opp_table: opp-table {
4366 compatible = "operating-points-v2";
4368 opp-133330000 {
4369 opp-hz = /bits/ 64 <133330000>;
4370 required-opps = <&rpmhpd_opp_low_svs>;
4373 opp-240000000 {
4374 opp-hz = /bits/ 64 <240000000>;
4375 required-opps = <&rpmhpd_opp_svs>;
4378 opp-335000000 {
4379 opp-hz = /bits/ 64 <335000000>;
4380 required-opps = <&rpmhpd_opp_svs_l1>;
4383 opp-424000000 {
4384 opp-hz = /bits/ 64 <424000000>;
4385 required-opps = <&rpmhpd_opp_nom>;
4388 opp-460000048 {
4389 opp-hz = /bits/ 64 <460000048>;
4390 required-opps = <&rpmhpd_opp_turbo>;
4395 videocc: clock-controller@aaf0000 {
4396 compatible = "qcom,sc7280-videocc";
4400 clock-names = "bi_tcxo", "bi_tcxo_ao";
4401 #clock-cells = <1>;
4402 #reset-cells = <1>;
4403 #power-domain-cells = <1>;
4407 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4410 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4417 clock-names = "camnoc_axi",
4422 pinctrl-0 = <&cci0_default &cci1_default>;
4423 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4424 pinctrl-names = "default", "sleep";
4426 #address-cells = <1>;
4427 #size-cells = <0>;
4431 cci0_i2c0: i2c-bus@0 {
4433 clock-frequency = <1000000>;
4434 #address-cells = <1>;
4435 #size-cells = <0>;
4438 cci0_i2c1: i2c-bus@1 {
4440 clock-frequency = <1000000>;
4441 #address-cells = <1>;
4442 #size-cells = <0>;
4447 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4450 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4457 clock-names = "camnoc_axi",
4462 pinctrl-0 = <&cci2_default &cci3_default>;
4463 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4464 pinctrl-names = "default", "sleep";
4466 #address-cells = <1>;
4467 #size-cells = <0>;
4471 cci1_i2c0: i2c-bus@0 {
4473 clock-frequency = <1000000>;
4474 #address-cells = <1>;
4475 #size-cells = <0>;
4478 cci1_i2c1: i2c-bus@1 {
4480 clock-frequency = <1000000>;
4481 #address-cells = <1>;
4482 #size-cells = <0>;
4487 compatible = "qcom,sc7280-camss";
4504 reg-names = "csid0",
4553 clock-names = "camnoc_axi",
4602 interrupt-names = "csid0",
4622 interconnect-names = "ahb",
4627 power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
4631 power-domain-names = "ife0",
4639 #address-cells = <1>;
4640 #size-cells = <0>;
4664 camcc: clock-controller@ad00000 {
4665 compatible = "qcom,sc7280-camcc";
4670 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4671 #clock-cells = <1>;
4672 #reset-cells = <1>;
4673 #power-domain-cells = <1>;
4676 dispcc: clock-controller@af00000 {
4677 compatible = "qcom,sc7280-dispcc";
4687 clock-names = "bi_tcxo",
4695 #clock-cells = <1>;
4696 #reset-cells = <1>;
4697 #power-domain-cells = <1>;
4700 mdss: display-subsystem@ae00000 {
4701 compatible = "qcom,sc7280-mdss";
4703 reg-names = "mdss";
4705 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
4710 clock-names = "iface",
4715 interrupt-controller;
4716 #interrupt-cells = <1>;
4722 interconnect-names = "mdp0-mem",
4723 "cpu-cfg";
4727 #address-cells = <2>;
4728 #size-cells = <2>;
4733 mdss_mdp: display-controller@ae01000 {
4734 compatible = "qcom,sc7280-dpu";
4737 reg-names = "mdp", "vbif";
4745 clock-names = "bus",
4751 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
4753 assigned-clock-rates = <19200000>,
4755 operating-points-v2 = <&mdp_opp_table>;
4756 power-domains = <&rpmhpd SC7280_CX>;
4758 interrupt-parent = <&mdss>;
4762 #address-cells = <1>;
4763 #size-cells = <0>;
4768 remote-endpoint = <&mdss_dsi0_in>;
4775 remote-endpoint = <&edp_in>;
4782 remote-endpoint = <&dp_in>;
4787 mdp_opp_table: opp-table {
4788 compatible = "operating-points-v2";
4790 opp-200000000 {
4791 opp-hz = /bits/ 64 <200000000>;
4792 required-opps = <&rpmhpd_opp_low_svs>;
4795 opp-300000000 {
4796 opp-hz = /bits/ 64 <300000000>;
4797 required-opps = <&rpmhpd_opp_svs>;
4800 opp-380000000 {
4801 opp-hz = /bits/ 64 <380000000>;
4802 required-opps = <&rpmhpd_opp_svs_l1>;
4805 opp-506666667 {
4806 opp-hz = /bits/ 64 <506666667>;
4807 required-opps = <&rpmhpd_opp_nom>;
4810 opp-608000000 {
4811 opp-hz = /bits/ 64 <608000000>;
4812 required-opps = <&rpmhpd_opp_turbo>;
4818 compatible = "qcom,sc7280-dsi-ctrl",
4819 "qcom,mdss-dsi-ctrl";
4821 reg-names = "dsi_ctrl";
4823 interrupt-parent = <&mdss>;
4832 clock-names = "byte",
4839 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
4841 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>,
4844 operating-points-v2 = <&dsi_opp_table>;
4845 power-domains = <&rpmhpd SC7280_CX>;
4849 #address-cells = <1>;
4850 #size-cells = <0>;
4855 #address-cells = <1>;
4856 #size-cells = <0>;
4861 remote-endpoint = <&dpu_intf1_out>;
4872 dsi_opp_table: opp-table {
4873 compatible = "operating-points-v2";
4875 opp-187500000 {
4876 opp-hz = /bits/ 64 <187500000>;
4877 required-opps = <&rpmhpd_opp_low_svs>;
4880 opp-300000000 {
4881 opp-hz = /bits/ 64 <300000000>;
4882 required-opps = <&rpmhpd_opp_svs>;
4885 opp-358000000 {
4886 opp-hz = /bits/ 64 <358000000>;
4887 required-opps = <&rpmhpd_opp_svs_l1>;
4893 compatible = "qcom,sc7280-dsi-phy-7nm";
4897 reg-names = "dsi_phy",
4901 #clock-cells = <1>;
4902 #phy-cells = <0>;
4906 clock-names = "iface", "ref";
4912 compatible = "qcom,sc7280-edp";
4913 pinctrl-names = "default";
4914 pinctrl-0 = <&edp_hot_plug_det>;
4921 interrupt-parent = <&mdss>;
4929 clock-names = "core_iface",
4934 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4936 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4939 phy-names = "dp";
4941 operating-points-v2 = <&edp_opp_table>;
4942 power-domains = <&rpmhpd SC7280_CX>;
4947 #address-cells = <1>;
4948 #size-cells = <0>;
4953 remote-endpoint = <&dpu_intf5_out>;
4963 edp_opp_table: opp-table {
4964 compatible = "operating-points-v2";
4966 opp-160000000 {
4967 opp-hz = /bits/ 64 <160000000>;
4968 required-opps = <&rpmhpd_opp_low_svs>;
4971 opp-270000000 {
4972 opp-hz = /bits/ 64 <270000000>;
4973 required-opps = <&rpmhpd_opp_svs>;
4976 opp-540000000 {
4977 opp-hz = /bits/ 64 <540000000>;
4978 required-opps = <&rpmhpd_opp_nom>;
4981 opp-810000000 {
4982 opp-hz = /bits/ 64 <810000000>;
4983 required-opps = <&rpmhpd_opp_nom>;
4989 compatible = "qcom,sc7280-edp-phy";
4998 clock-names = "aux",
5001 #clock-cells = <1>;
5002 #phy-cells = <0>;
5007 mdss_dp: displayport-controller@ae90000 {
5008 compatible = "qcom,sc7280-dp";
5016 interrupt-parent = <&mdss>;
5024 clock-names = "core_iface",
5029 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
5031 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5034 phy-names = "dp";
5036 operating-points-v2 = <&dp_opp_table>;
5037 power-domains = <&rpmhpd SC7280_CX>;
5039 #sound-dai-cells = <0>;
5044 #address-cells = <1>;
5045 #size-cells = <0>;
5050 remote-endpoint = <&dpu_intf0_out>;
5057 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
5062 dp_opp_table: opp-table {
5063 compatible = "operating-points-v2";
5065 opp-160000000 {
5066 opp-hz = /bits/ 64 <160000000>;
5067 required-opps = <&rpmhpd_opp_low_svs>;
5070 opp-270000000 {
5071 opp-hz = /bits/ 64 <270000000>;
5072 required-opps = <&rpmhpd_opp_svs>;
5075 opp-540000000 {
5076 opp-hz = /bits/ 64 <540000000>;
5077 required-opps = <&rpmhpd_opp_svs_l1>;
5080 opp-810000000 {
5081 opp-hz = /bits/ 64 <810000000>;
5082 required-opps = <&rpmhpd_opp_nom>;
5088 pdc: interrupt-controller@b220000 {
5089 compatible = "qcom,sc7280-pdc", "qcom,pdc";
5091 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
5096 #interrupt-cells = <2>;
5097 interrupt-parent = <&intc>;
5098 interrupt-controller;
5101 pdc_reset: reset-controller@b5e0000 {
5102 compatible = "qcom,sc7280-pdc-global";
5104 #reset-cells = <1>;
5108 tsens0: thermal-sensor@c263000 {
5109 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
5115 interrupt-names = "uplow","critical";
5116 #thermal-sensor-cells = <1>;
5119 tsens1: thermal-sensor@c265000 {
5120 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
5126 interrupt-names = "uplow","critical";
5127 #thermal-sensor-cells = <1>;
5130 aoss_reset: reset-controller@c2a0000 {
5131 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
5133 #reset-cells = <1>;
5136 aoss_qmp: power-management@c300000 {
5137 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
5139 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5145 #clock-cells = <0>;
5149 compatible = "qcom,rpmh-stats";
5154 compatible = "qcom,spmi-pmic-arb";
5160 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5161 interrupt-names = "periph_irq";
5162 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5165 #address-cells = <2>;
5166 #size-cells = <0>;
5167 interrupt-controller;
5168 #interrupt-cells = <4>;
5172 compatible = "qcom,sc7280-pinctrl";
5175 gpio-controller;
5176 #gpio-cells = <2>;
5177 interrupt-controller;
5178 #interrupt-cells = <2>;
5179 gpio-ranges = <&tlmm 0 0 175>;
5180 wakeup-parent = <&pdc>;
5182 cci0_default: cci0-default-state {
5185 drive-strength = <2>;
5186 bias-pull-up;
5189 cci0_sleep: cci0-sleep-state {
5192 drive-strength = <2>;
5193 bias-pull-down;
5196 cci1_default: cci1-default-state {
5199 drive-strength = <2>;
5200 bias-pull-up;
5203 cci1_sleep: cci1-sleep-state {
5206 drive-strength = <2>;
5207 bias-pull-down;
5210 cci2_default: cci2-default-state {
5213 drive-strength = <2>;
5214 bias-pull-up;
5217 cci2_sleep: cci2-sleep-state {
5220 drive-strength = <2>;
5221 bias-pull-down;
5224 cci3_default: cci3-default-state {
5227 drive-strength = <2>;
5228 bias-pull-up;
5231 cci3_sleep: cci3-sleep-state {
5234 drive-strength = <2>;
5235 bias-pull-down;
5238 dp_hot_plug_det: dp-hot-plug-det-state {
5243 edp_hot_plug_det: edp-hot-plug-det-state {
5248 mi2s0_data0: mi2s0-data0-state {
5253 mi2s0_data1: mi2s0-data1-state {
5258 mi2s0_mclk: mi2s0-mclk-state {
5263 mi2s0_sclk: mi2s0-sclk-state {
5268 mi2s0_ws: mi2s0-ws-state {
5273 mi2s1_data0: mi2s1-data0-state {
5278 mi2s1_sclk: mi2s1-sclk-state {
5283 mi2s1_ws: mi2s1-ws-state {
5288 pcie1_clkreq_n: pcie1-clkreq-n-state {
5293 qspi_clk: qspi-clk-state {
5298 qspi_cs0: qspi-cs0-state {
5303 qspi_cs1: qspi-cs1-state {
5308 qspi_data0: qspi-data0-state {
5313 qspi_data1: qspi-data1-state {
5318 qspi_data23: qspi-data23-state {
5323 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5328 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5333 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5338 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5343 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5348 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5353 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5358 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5363 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5368 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5373 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5378 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5383 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5388 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5393 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5398 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5403 qup_spi0_data_clk: qup-spi0-data-clk-state {
5408 qup_spi0_cs: qup-spi0-cs-state {
5413 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5418 qup_spi1_data_clk: qup-spi1-data-clk-state {
5423 qup_spi1_cs: qup-spi1-cs-state {
5428 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5433 qup_spi2_data_clk: qup-spi2-data-clk-state {
5438 qup_spi2_cs: qup-spi2-cs-state {
5443 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5448 qup_spi3_data_clk: qup-spi3-data-clk-state {
5453 qup_spi3_cs: qup-spi3-cs-state {
5458 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5463 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 qup_spi4_cs: qup-spi4-cs-state {
5473 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5478 qup_spi5_data_clk: qup-spi5-data-clk-state {
5483 qup_spi5_cs: qup-spi5-cs-state {
5488 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5493 qup_spi6_data_clk: qup-spi6-data-clk-state {
5498 qup_spi6_cs: qup-spi6-cs-state {
5503 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5508 qup_spi7_data_clk: qup-spi7-data-clk-state {
5513 qup_spi7_cs: qup-spi7-cs-state {
5518 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5523 qup_spi8_data_clk: qup-spi8-data-clk-state {
5528 qup_spi8_cs: qup-spi8-cs-state {
5533 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5538 qup_spi9_data_clk: qup-spi9-data-clk-state {
5543 qup_spi9_cs: qup-spi9-cs-state {
5548 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5553 qup_spi10_data_clk: qup-spi10-data-clk-state {
5558 qup_spi10_cs: qup-spi10-cs-state {
5563 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5568 qup_spi11_data_clk: qup-spi11-data-clk-state {
5573 qup_spi11_cs: qup-spi11-cs-state {
5578 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5583 qup_spi12_data_clk: qup-spi12-data-clk-state {
5588 qup_spi12_cs: qup-spi12-cs-state {
5593 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5598 qup_spi13_data_clk: qup-spi13-data-clk-state {
5603 qup_spi13_cs: qup-spi13-cs-state {
5608 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5613 qup_spi14_data_clk: qup-spi14-data-clk-state {
5618 qup_spi14_cs: qup-spi14-cs-state {
5623 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5628 qup_spi15_data_clk: qup-spi15-data-clk-state {
5633 qup_spi15_cs: qup-spi15-cs-state {
5638 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5643 qup_uart0_cts: qup-uart0-cts-state {
5648 qup_uart0_rts: qup-uart0-rts-state {
5653 qup_uart0_tx: qup-uart0-tx-state {
5658 qup_uart0_rx: qup-uart0-rx-state {
5663 qup_uart1_cts: qup-uart1-cts-state {
5668 qup_uart1_rts: qup-uart1-rts-state {
5673 qup_uart1_tx: qup-uart1-tx-state {
5678 qup_uart1_rx: qup-uart1-rx-state {
5683 qup_uart2_cts: qup-uart2-cts-state {
5688 qup_uart2_rts: qup-uart2-rts-state {
5693 qup_uart2_tx: qup-uart2-tx-state {
5698 qup_uart2_rx: qup-uart2-rx-state {
5703 qup_uart3_cts: qup-uart3-cts-state {
5708 qup_uart3_rts: qup-uart3-rts-state {
5713 qup_uart3_tx: qup-uart3-tx-state {
5718 qup_uart3_rx: qup-uart3-rx-state {
5723 qup_uart4_cts: qup-uart4-cts-state {
5728 qup_uart4_rts: qup-uart4-rts-state {
5733 qup_uart4_tx: qup-uart4-tx-state {
5738 qup_uart4_rx: qup-uart4-rx-state {
5743 qup_uart5_tx: qup-uart5-tx-state {
5748 qup_uart5_rx: qup-uart5-rx-state {
5753 qup_uart6_cts: qup-uart6-cts-state {
5758 qup_uart6_rts: qup-uart6-rts-state {
5763 qup_uart6_tx: qup-uart6-tx-state {
5768 qup_uart6_rx: qup-uart6-rx-state {
5773 qup_uart7_cts: qup-uart7-cts-state {
5778 qup_uart7_rts: qup-uart7-rts-state {
5783 qup_uart7_tx: qup-uart7-tx-state {
5788 qup_uart7_rx: qup-uart7-rx-state {
5793 qup_uart8_cts: qup-uart8-cts-state {
5798 qup_uart8_rts: qup-uart8-rts-state {
5803 qup_uart8_tx: qup-uart8-tx-state {
5808 qup_uart8_rx: qup-uart8-rx-state {
5813 qup_uart9_cts: qup-uart9-cts-state {
5818 qup_uart9_rts: qup-uart9-rts-state {
5823 qup_uart9_tx: qup-uart9-tx-state {
5828 qup_uart9_rx: qup-uart9-rx-state {
5833 qup_uart10_cts: qup-uart10-cts-state {
5838 qup_uart10_rts: qup-uart10-rts-state {
5843 qup_uart10_tx: qup-uart10-tx-state {
5848 qup_uart10_rx: qup-uart10-rx-state {
5853 qup_uart11_cts: qup-uart11-cts-state {
5858 qup_uart11_rts: qup-uart11-rts-state {
5863 qup_uart11_tx: qup-uart11-tx-state {
5868 qup_uart11_rx: qup-uart11-rx-state {
5873 qup_uart12_cts: qup-uart12-cts-state {
5878 qup_uart12_rts: qup-uart12-rts-state {
5883 qup_uart12_tx: qup-uart12-tx-state {
5888 qup_uart12_rx: qup-uart12-rx-state {
5893 qup_uart13_cts: qup-uart13-cts-state {
5898 qup_uart13_rts: qup-uart13-rts-state {
5903 qup_uart13_tx: qup-uart13-tx-state {
5908 qup_uart13_rx: qup-uart13-rx-state {
5913 qup_uart14_cts: qup-uart14-cts-state {
5918 qup_uart14_rts: qup-uart14-rts-state {
5923 qup_uart14_tx: qup-uart14-tx-state {
5928 qup_uart14_rx: qup-uart14-rx-state {
5933 qup_uart15_cts: qup-uart15-cts-state {
5938 qup_uart15_rts: qup-uart15-rts-state {
5943 qup_uart15_tx: qup-uart15-tx-state {
5948 qup_uart15_rx: qup-uart15-rx-state {
5953 sdc1_clk: sdc1-clk-state {
5957 sdc1_cmd: sdc1-cmd-state {
5961 sdc1_data: sdc1-data-state {
5965 sdc1_rclk: sdc1-rclk-state {
5969 sdc1_clk_sleep: sdc1-clk-sleep-state {
5971 drive-strength = <2>;
5972 bias-bus-hold;
5975 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5977 drive-strength = <2>;
5978 bias-bus-hold;
5981 sdc1_data_sleep: sdc1-data-sleep-state {
5983 drive-strength = <2>;
5984 bias-bus-hold;
5987 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5989 drive-strength = <2>;
5990 bias-bus-hold;
5993 sdc2_clk: sdc2-clk-state {
5997 sdc2_cmd: sdc2-cmd-state {
6001 sdc2_data: sdc2-data-state {
6005 sdc2_clk_sleep: sdc2-clk-sleep-state {
6007 drive-strength = <2>;
6008 bias-bus-hold;
6011 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
6013 drive-strength = <2>;
6014 bias-bus-hold;
6017 sdc2_data_sleep: sdc2-data-sleep-state {
6019 drive-strength = <2>;
6020 bias-bus-hold;
6025 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
6028 #address-cells = <1>;
6029 #size-cells = <1>;
6033 pil-reloc@594c {
6034 compatible = "qcom,pil-reloc-info";
6040 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
6042 #iommu-cells = <2>;
6043 #global-interrupts = <1>;
6044 dma-coherent;
6129 compatible = "qcom,sc7280-tbu";
6133 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
6137 compatible = "qcom,sc7280-tbu";
6141 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
6145 compatible = "qcom,sc7280-tbu";
6149 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
6150 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
6154 compatible = "qcom,sc7280-tbu";
6158 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
6159 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
6163 compatible = "qcom,sc7280-tbu";
6167 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
6168 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
6172 compatible = "qcom,sc7280-tbu";
6176 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
6177 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
6181 compatible = "qcom,sc7280-tbu";
6185 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
6189 compatible = "qcom,sc7280-tbu";
6193 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
6197 compatible = "qcom,sc7280-tbu";
6201 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
6202 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
6205 intc: interrupt-controller@17a00000 {
6206 compatible = "arm,gic-v3";
6210 #interrupt-cells = <3>;
6211 interrupt-controller;
6212 #address-cells = <2>;
6213 #size-cells = <2>;
6216 msi-controller@17a40000 {
6217 compatible = "arm,gic-v3-its";
6219 msi-controller;
6220 #msi-cells = <1>;
6226 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
6234 #address-cells = <1>;
6235 #size-cells = <1>;
6237 compatible = "arm,armv7-timer-mem";
6241 frame-number = <0>;
6249 frame-number = <1>;
6256 frame-number = <2>;
6263 frame-number = <3>;
6270 frame-number = <4>;
6277 frame-number = <5>;
6284 frame-number = <6>;
6292 compatible = "qcom,rpmh-rsc";
6296 reg-names = "drv-0", "drv-1", "drv-2";
6300 qcom,tcs-offset = <0xd00>;
6301 qcom,drv-id = <2>;
6302 qcom,tcs-config = <ACTIVE_TCS 2>,
6306 power-domains = <&cluster_pd>;
6308 apps_bcm_voter: bcm-voter {
6309 compatible = "qcom,bcm-voter";
6312 rpmhpd: power-controller {
6313 compatible = "qcom,sc7280-rpmhpd";
6314 #power-domain-cells = <1>;
6315 operating-points-v2 = <&rpmhpd_opp_table>;
6317 rpmhpd_opp_table: opp-table {
6318 compatible = "operating-points-v2";
6321 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6325 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6329 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6333 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6337 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
6341 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6345 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6349 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6353 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6358 rpmhcc: clock-controller {
6359 compatible = "qcom,sc7280-rpmh-clk";
6361 clock-names = "xo";
6362 #clock-cells = <1>;
6367 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
6370 clock-names = "xo", "alternate";
6371 #interconnect-cells = <1>;
6375 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
6383 interrupt-names = "dcvsh-irq-0",
6384 "dcvsh-irq-1",
6385 "dcvsh-irq-2";
6388 clock-names = "xo", "alternate";
6389 #freq-domain-cells = <1>;
6390 #clock-cells = <1>;
6397 thermal_zones: thermal-zones {
6398 cpu0-thermal {
6399 polling-delay-passive = <250>;
6401 thermal-sensors = <&tsens0 1>;
6404 cpu0_alert0: trip-point0 {
6410 cpu0_alert1: trip-point1 {
6416 cpu0_crit: cpu-crit {
6423 cooling-maps {
6426 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6433 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6441 cpu1-thermal {
6442 polling-delay-passive = <250>;
6444 thermal-sensors = <&tsens0 2>;
6447 cpu1_alert0: trip-point0 {
6453 cpu1_alert1: trip-point1 {
6459 cpu1_crit: cpu-crit {
6466 cooling-maps {
6469 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6476 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6484 cpu2-thermal {
6485 polling-delay-passive = <250>;
6487 thermal-sensors = <&tsens0 3>;
6490 cpu2_alert0: trip-point0 {
6496 cpu2_alert1: trip-point1 {
6502 cpu2_crit: cpu-crit {
6509 cooling-maps {
6512 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6519 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6527 cpu3-thermal {
6528 polling-delay-passive = <250>;
6530 thermal-sensors = <&tsens0 4>;
6533 cpu3_alert0: trip-point0 {
6539 cpu3_alert1: trip-point1 {
6545 cpu3_crit: cpu-crit {
6552 cooling-maps {
6555 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6562 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6570 cpu4-thermal {
6571 polling-delay-passive = <250>;
6573 thermal-sensors = <&tsens0 7>;
6576 cpu4_alert0: trip-point0 {
6582 cpu4_alert1: trip-point1 {
6588 cpu4_crit: cpu-crit {
6595 cooling-maps {
6598 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6605 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6613 cpu5-thermal {
6614 polling-delay-passive = <250>;
6616 thermal-sensors = <&tsens0 8>;
6619 cpu5_alert0: trip-point0 {
6625 cpu5_alert1: trip-point1 {
6631 cpu5_crit: cpu-crit {
6638 cooling-maps {
6641 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6648 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6656 cpu6-thermal {
6657 polling-delay-passive = <250>;
6659 thermal-sensors = <&tsens0 9>;
6662 cpu6_alert0: trip-point0 {
6668 cpu6_alert1: trip-point1 {
6674 cpu6_crit: cpu-crit {
6681 cooling-maps {
6684 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6691 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6699 cpu7-thermal {
6700 polling-delay-passive = <250>;
6702 thermal-sensors = <&tsens0 10>;
6705 cpu7_alert0: trip-point0 {
6711 cpu7_alert1: trip-point1 {
6717 cpu7_crit: cpu-crit {
6724 cooling-maps {
6727 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6734 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6742 cpu8-thermal {
6743 polling-delay-passive = <250>;
6745 thermal-sensors = <&tsens0 11>;
6748 cpu8_alert0: trip-point0 {
6754 cpu8_alert1: trip-point1 {
6760 cpu8_crit: cpu-crit {
6767 cooling-maps {
6770 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6777 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6785 cpu9-thermal {
6786 polling-delay-passive = <250>;
6788 thermal-sensors = <&tsens0 12>;
6791 cpu9_alert0: trip-point0 {
6797 cpu9_alert1: trip-point1 {
6803 cpu9_crit: cpu-crit {
6810 cooling-maps {
6813 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6820 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6828 cpu10-thermal {
6829 polling-delay-passive = <250>;
6831 thermal-sensors = <&tsens0 13>;
6834 cpu10_alert0: trip-point0 {
6840 cpu10_alert1: trip-point1 {
6846 cpu10_crit: cpu-crit {
6853 cooling-maps {
6856 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6863 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6871 cpu11-thermal {
6872 polling-delay-passive = <250>;
6874 thermal-sensors = <&tsens0 14>;
6877 cpu11_alert0: trip-point0 {
6883 cpu11_alert1: trip-point1 {
6889 cpu11_crit: cpu-crit {
6896 cooling-maps {
6899 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6906 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6914 aoss0-thermal {
6915 polling-delay-passive = <0>;
6917 thermal-sensors = <&tsens0 0>;
6920 aoss0_alert0: trip-point0 {
6926 aoss0_crit: aoss0-crit {
6934 aoss1-thermal {
6935 polling-delay-passive = <0>;
6937 thermal-sensors = <&tsens1 0>;
6940 aoss1_alert0: trip-point0 {
6946 aoss1_crit: aoss1-crit {
6954 cpuss0-thermal {
6955 polling-delay-passive = <0>;
6957 thermal-sensors = <&tsens0 5>;
6960 cpuss0_alert0: trip-point0 {
6965 cpuss0_crit: cluster0-crit {
6973 cpuss1-thermal {
6974 polling-delay-passive = <0>;
6976 thermal-sensors = <&tsens0 6>;
6979 cpuss1_alert0: trip-point0 {
6984 cpuss1_crit: cluster0-crit {
6992 gpuss0-thermal {
6993 polling-delay-passive = <100>;
6995 thermal-sensors = <&tsens1 1>;
6998 gpuss0_alert0: trip-point0 {
7004 gpuss0_crit: gpuss0-crit {
7011 cooling-maps {
7014 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7019 gpuss1-thermal {
7020 polling-delay-passive = <100>;
7022 thermal-sensors = <&tsens1 2>;
7025 gpuss1_alert0: trip-point0 {
7031 gpuss1_crit: gpuss1-crit {
7038 cooling-maps {
7041 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7046 nspss0-thermal {
7047 thermal-sensors = <&tsens1 3>;
7050 nspss0_alert0: trip-point0 {
7056 nspss0_crit: nspss0-crit {
7064 nspss1-thermal {
7065 thermal-sensors = <&tsens1 4>;
7068 nspss1_alert0: trip-point0 {
7074 nspss1_crit: nspss1-crit {
7082 video-thermal {
7083 thermal-sensors = <&tsens1 5>;
7086 video_alert0: trip-point0 {
7092 video_crit: video-crit {
7100 ddr-thermal {
7101 thermal-sensors = <&tsens1 6>;
7104 ddr_alert0: trip-point0 {
7110 ddr_crit: ddr-crit {
7118 mdmss0-thermal {
7119 thermal-sensors = <&tsens1 7>;
7122 mdmss0_alert0: trip-point0 {
7128 mdmss0_crit: mdmss0-crit {
7136 mdmss1-thermal {
7137 thermal-sensors = <&tsens1 8>;
7140 mdmss1_alert0: trip-point0 {
7146 mdmss1_crit: mdmss1-crit {
7154 mdmss2-thermal {
7155 thermal-sensors = <&tsens1 9>;
7158 mdmss2_alert0: trip-point0 {
7164 mdmss2_crit: mdmss2-crit {
7172 mdmss3-thermal {
7173 thermal-sensors = <&tsens1 10>;
7176 mdmss3_alert0: trip-point0 {
7182 mdmss3_crit: mdmss3-crit {
7190 camera0-thermal {
7191 thermal-sensors = <&tsens1 11>;
7194 camera0_alert0: trip-point0 {
7200 camera0_crit: camera0-crit {
7210 compatible = "arm,armv8-timer";