Lines Matching +full:0 +full:x18220000
81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
139 reg = <0x0 0x80b00000 0x0 0x100000>;
143 reg = <0x0 0x80c00000 0x0 0xc00000>;
148 reg = <0x0 0x86700000 0x0 0x2800000>;
153 reg = <0x0 0x8b200000 0x0 0x500000>;
158 reg = <0x0 0x88f00000 0x0 0x1e00000>;
163 reg = <0 0x8b700000 0 0x10000>;
168 reg = <0 0x8b71a000 0 0x2000>;
173 reg = <0x0 0x8b800000 0x0 0xf600000>;
178 reg = <0x0 0x9ae00000 0x0 0x1900000>;
184 reg = <0x0 0x9c900000 0x0 0x280000>;
194 #size-cells = <0>;
196 CPU0: cpu@0 {
199 reg = <0x0 0x0>;
200 clocks = <&cpufreq_hw 0>;
210 qcom,freq-domain = <&cpufreq_hw 0>;
228 reg = <0x0 0x100>;
229 clocks = <&cpufreq_hw 0>;
239 qcom,freq-domain = <&cpufreq_hw 0>;
252 reg = <0x0 0x200>;
253 clocks = <&cpufreq_hw 0>;
263 qcom,freq-domain = <&cpufreq_hw 0>;
276 reg = <0x0 0x300>;
277 clocks = <&cpufreq_hw 0>;
287 qcom,freq-domain = <&cpufreq_hw 0>;
300 reg = <0x0 0x400>;
324 reg = <0x0 0x500>;
348 reg = <0x0 0x600>;
372 reg = <0x0 0x700>;
432 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
435 arm,psci-suspend-param = <0x40000003>;
442 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
445 arm,psci-suspend-param = <0x40000004>;
452 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
455 arm,psci-suspend-param = <0x40000003>;
465 arm,psci-suspend-param = <0x40000004>;
474 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
476 arm,psci-suspend-param = <0x41000044>;
484 arm,psci-suspend-param = <0x41001344>;
492 arm,psci-suspend-param = <0x4100b344>;
708 reg = <0 0x80000000 0 0>;
714 qcom,dload-mode = <&tcsr_2 0x13000>;
739 qcom,local-pid = <0>;
763 qcom,local-pid = <0>;
787 qcom,local-pid = <0>;
822 qcom,local-pid = <0>;
858 #power-domain-cells = <0>;
864 #power-domain-cells = <0>;
870 #power-domain-cells = <0>;
876 #power-domain-cells = <0>;
882 #power-domain-cells = <0>;
888 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
900 #power-domain-cells = <0>;
906 #power-domain-cells = <0>;
954 soc: soc@0 {
957 ranges = <0 0 0 0 0x10 0>;
958 dma-ranges = <0 0 0 0 0x10 0>;
963 reg = <0 0x00100000 0 0x1f0000>;
966 <0>, <&pcie1_phy>,
967 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
982 reg = <0 0x00408000 0 0x1000>;
991 reg = <0 0x00784000 0 0xa20>,
992 <0 0x00780000 0 0xa20>,
993 <0 0x00782000 0 0x120>,
994 <0 0x00786000 0 0x1fff>;
1002 reg = <0x1e9 0x2>;
1010 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1014 reg = <0 0x007c4000 0 0x1000>,
1015 <0 0x007c5000 0 0x1000>;
1018 iommus = <&apps_smmu 0xc0 0x0>;
1027 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
1028 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
1037 qcom,dll-config = <0x0007642c>;
1038 qcom,ddr-config = <0x80040868>;
1054 opp-avg-kBps = <100000 0>;
1061 opp-avg-kBps = <390000 0>;
1069 reg = <0 0x00900000 0 0x60000>;
1083 dma-channel-mask = <0x7f>;
1084 iommus = <&apps_smmu 0x0136 0x0>;
1090 reg = <0 0x009c0000 0 0x2000>;
1097 iommus = <&apps_smmu 0x123 0x0>;
1102 reg = <0 0x00980000 0 0x4000>;
1106 pinctrl-0 = <&qup_i2c0_data_clk>;
1109 #size-cells = <0>;
1110 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1111 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1112 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1117 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1118 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1125 reg = <0 0x00980000 0 0x4000>;
1129 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1132 #size-cells = <0>;
1135 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1136 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1138 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1139 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1146 reg = <0 0x00980000 0 0x4000>;
1150 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1154 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1155 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1162 reg = <0 0x00984000 0 0x4000>;
1166 pinctrl-0 = <&qup_i2c1_data_clk>;
1169 #size-cells = <0>;
1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1171 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1172 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1177 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1185 reg = <0 0x00984000 0 0x4000>;
1189 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1192 #size-cells = <0>;
1195 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1196 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1198 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1206 reg = <0 0x00984000 0 0x4000>;
1210 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1214 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1215 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1222 reg = <0 0x00988000 0 0x4000>;
1226 pinctrl-0 = <&qup_i2c2_data_clk>;
1229 #size-cells = <0>;
1230 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1231 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1232 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1237 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1245 reg = <0 0x00988000 0 0x4000>;
1249 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1252 #size-cells = <0>;
1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1256 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1258 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1266 reg = <0 0x00988000 0 0x4000>;
1270 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1275 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1282 reg = <0 0x0098c000 0 0x4000>;
1286 pinctrl-0 = <&qup_i2c3_data_clk>;
1289 #size-cells = <0>;
1290 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1291 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1292 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1297 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1305 reg = <0 0x0098c000 0 0x4000>;
1309 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1312 #size-cells = <0>;
1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1316 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1318 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1326 reg = <0 0x0098c000 0 0x4000>;
1330 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1334 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1335 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1342 reg = <0 0x00990000 0 0x4000>;
1346 pinctrl-0 = <&qup_i2c4_data_clk>;
1349 #size-cells = <0>;
1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1352 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1357 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1365 reg = <0 0x00990000 0 0x4000>;
1369 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1372 #size-cells = <0>;
1375 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1376 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1378 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1386 reg = <0 0x00990000 0 0x4000>;
1390 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1395 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1402 reg = <0 0x00994000 0 0x4000>;
1406 pinctrl-0 = <&qup_i2c5_data_clk>;
1409 #size-cells = <0>;
1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1411 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1412 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1417 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1425 reg = <0 0x00994000 0 0x4000>;
1429 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1432 #size-cells = <0>;
1435 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1436 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1438 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1446 reg = <0 0x00994000 0 0x4000>;
1450 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1454 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1462 reg = <0 0x00998000 0 0x4000>;
1466 pinctrl-0 = <&qup_i2c6_data_clk>;
1469 #size-cells = <0>;
1470 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1471 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1472 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1477 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1485 reg = <0 0x00998000 0 0x4000>;
1489 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1492 #size-cells = <0>;
1495 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1496 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1498 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1506 reg = <0 0x00998000 0 0x4000>;
1510 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1514 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1515 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1522 reg = <0 0x0099c000 0 0x4000>;
1526 pinctrl-0 = <&qup_i2c7_data_clk>;
1529 #size-cells = <0>;
1530 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1531 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1532 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1537 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1545 reg = <0 0x0099c000 0 0x4000>;
1549 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1552 #size-cells = <0>;
1555 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1556 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1558 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1566 reg = <0 0x0099c000 0 0x4000>;
1570 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1574 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1575 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1584 reg = <0 0x00a00000 0 0x60000>;
1598 dma-channel-mask = <0x1e>;
1599 iommus = <&apps_smmu 0x56 0x0>;
1605 reg = <0 0x00ac0000 0 0x2000>;
1612 iommus = <&apps_smmu 0x43 0x0>;
1617 reg = <0 0x00a80000 0 0x4000>;
1621 pinctrl-0 = <&qup_i2c8_data_clk>;
1624 #size-cells = <0>;
1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1626 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1627 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1632 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1633 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1640 reg = <0 0x00a80000 0 0x4000>;
1644 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1647 #size-cells = <0>;
1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1651 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1653 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1654 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1661 reg = <0 0x00a80000 0 0x4000>;
1665 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1669 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1670 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1677 reg = <0 0x00a84000 0 0x4000>;
1681 pinctrl-0 = <&qup_i2c9_data_clk>;
1684 #size-cells = <0>;
1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1686 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1687 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1692 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1700 reg = <0 0x00a84000 0 0x4000>;
1704 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1707 #size-cells = <0>;
1710 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1711 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1713 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1721 reg = <0 0x00a84000 0 0x4000>;
1725 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1729 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1730 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1737 reg = <0 0x00a88000 0 0x4000>;
1741 pinctrl-0 = <&qup_i2c10_data_clk>;
1744 #size-cells = <0>;
1745 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1746 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1747 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1752 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1760 reg = <0 0x00a88000 0 0x4000>;
1764 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1767 #size-cells = <0>;
1770 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1771 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1773 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1781 reg = <0 0x00a88000 0 0x4000>;
1785 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1789 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1790 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1797 reg = <0 0x00a8c000 0 0x4000>;
1801 pinctrl-0 = <&qup_i2c11_data_clk>;
1804 #size-cells = <0>;
1805 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1807 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1812 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1820 reg = <0 0x00a8c000 0 0x4000>;
1824 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1827 #size-cells = <0>;
1830 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1831 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1833 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1841 reg = <0 0x00a8c000 0 0x4000>;
1845 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1850 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1857 reg = <0 0x00a90000 0 0x4000>;
1861 pinctrl-0 = <&qup_i2c12_data_clk>;
1864 #size-cells = <0>;
1865 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1866 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1867 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1872 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1880 reg = <0 0x00a90000 0 0x4000>;
1884 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1887 #size-cells = <0>;
1890 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1891 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1893 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1901 reg = <0 0x00a90000 0 0x4000>;
1905 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1909 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1910 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1917 reg = <0 0x00a94000 0 0x4000>;
1921 pinctrl-0 = <&qup_i2c13_data_clk>;
1924 #size-cells = <0>;
1925 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1926 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1927 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1932 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1940 reg = <0 0x00a94000 0 0x4000>;
1944 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1947 #size-cells = <0>;
1950 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1951 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1953 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1961 reg = <0 0x00a94000 0 0x4000>;
1965 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1969 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1970 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1977 reg = <0 0x00a98000 0 0x4000>;
1981 pinctrl-0 = <&qup_i2c14_data_clk>;
1984 #size-cells = <0>;
1985 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1986 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1987 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1992 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2000 reg = <0 0x00a98000 0 0x4000>;
2004 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2007 #size-cells = <0>;
2010 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2011 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2013 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2021 reg = <0 0x00a98000 0 0x4000>;
2025 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2029 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2037 reg = <0 0x00a9c000 0 0x4000>;
2041 pinctrl-0 = <&qup_i2c15_data_clk>;
2044 #size-cells = <0>;
2045 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
2047 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
2052 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2060 reg = <0 0x00a9c000 0 0x4000>;
2064 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2067 #size-cells = <0>;
2070 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2071 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2073 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2081 reg = <0 0x00a9c000 0 0x4000>;
2085 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2089 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2090 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2098 reg = <0 0x010d3000 0 0x1000>;
2102 reg = <0 0x01500000 0 0x1000>;
2109 reg = <0 0x01502000 0 0x1000>;
2116 reg = <0 0x01580000 0 0x4>;
2123 reg = <0 0x01680000 0 0x15480>;
2131 reg = <0 0x016e0000 0 0x1c080>;
2139 reg = <0 0x01700000 0 0x2b080>;
2147 reg = <0 0x01740000 0 0x1e080>;
2155 reg = <0 0x17a10040 0 0x0>;
2156 iommus = <&apps_smmu 0x1c00 0x1>;
2192 qcom,smem-states = <&wlan_smp2p_out 0>;
2198 reg = <0 0x01c08000 0 0x3000>,
2199 <0 0x40000000 0 0xf1d>,
2200 <0 0x40000f20 0 0xa8>,
2201 <0 0x40001000 0 0x1000>,
2202 <0 0x40100000 0 0x100000>;
2207 bus-range = <0x00 0xff>;
2213 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2214 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2227 interrupt-map-mask = <0 0 0 0x7>;
2228 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2229 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2230 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2231 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2273 pinctrl-0 = <&pcie1_clkreq_n>;
2277 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2278 <0x100 &apps_smmu 0x1c81 0x1>;
2282 pcie@0 {
2284 reg = <0x0 0x0 0x0 0x0 0x0>;
2285 bus-range = <0x01 0xff>;
2295 reg = <0 0x01c0e000 0 0x1000>;
2308 #clock-cells = <0>;
2310 #phy-cells = <0>;
2324 reg = <0x0 0x01d84000 0x0 0x3000>;
2336 iommus = <&apps_smmu 0x80 0x0>;
2363 <0 0>,
2364 <0 0>,
2366 <0 0>,
2367 <0 0>,
2368 <0 0>,
2369 <0 0>;
2377 reg = <0x0 0x01d87000 0x0 0xe00>;
2385 resets = <&ufs_mem_hc 0>;
2389 #phy-cells = <0>;
2397 reg = <0 0x01d88000 0 0x8000>;
2403 reg = <0x0 0x01dc4000 0x0 0x28000>;
2406 iommus = <&apps_smmu 0x4e4 0x0011>,
2407 <&apps_smmu 0x4e6 0x0011>;
2408 qcom,ee = <0>;
2416 reg = <0x0 0x01dfa000 0x0 0x6000>;
2419 iommus = <&apps_smmu 0x4e4 0x0011>,
2420 <&apps_smmu 0x4e4 0x0011>;
2421 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
2428 iommus = <&apps_smmu 0x480 0x0>,
2429 <&apps_smmu 0x482 0x0>;
2430 reg = <0 0x01e40000 0 0x8000>,
2431 <0 0x01e50000 0 0x4ad0>,
2432 <0 0x01e04000 0 0x23000>;
2439 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2449 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2456 qcom,smem-states = <&ipa_smp2p_out 0>,
2466 reg = <0 0x01f40000 0 0x20000>;
2472 reg = <0 0x01f60000 0 0x20000>;
2477 reg = <0 0x01fc0000 0 0x30000>;
2482 reg = <0 0x03000000 0 0x40>,
2483 <0 0x03c04000 0 0x4>;
2493 reg = <0 0x03200000 0 0x1000>;
2496 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2507 #clock-cells = <0>;
2515 reg = <0 0x03210000 0 0x2000>;
2521 qcom,din-ports = <0>;
2527 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2528 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2529 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2530 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2531 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2532 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2533 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2534 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2535 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2539 #size-cells = <0>;
2546 reg = <0 0x03220000 0 0x1000>;
2549 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2560 #clock-cells = <0>;
2568 reg = <0 0x03230000 0 0x2000>;
2576 qcom,dout-ports = <0>;
2581 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2582 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2583 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2584 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2585 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2586 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2587 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2588 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2589 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2593 #size-cells = <0>;
2600 reg = <0 0x03300000 0 0x30000>,
2601 <0 0x032a9000 0 0x1000>;
2613 reg = <0 0x03370000 0 0x1000>;
2616 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2625 #clock-cells = <0>;
2633 reg = <0 0x03380000 0 0x30000>;
2645 reg = <0 0x03900000 0 0x50000>;
2657 reg = <0 0x03987000 0 0x68000>,
2658 <0 0x03b00000 0 0x29000>,
2659 <0 0x03260000 0 0xc000>,
2660 <0 0x03280000 0 0x29000>,
2661 <0 0x03340000 0 0x29000>,
2662 <0 0x0336c000 0 0x3000>;
2670 iommus = <&apps_smmu 0x1820 0>,
2671 <&apps_smmu 0x1821 0>,
2672 <&apps_smmu 0x1832 0>;
2701 #size-cells = <0>;
2717 reg = <0 0x03a84000 0 0x20000>;
2724 iommus = <&apps_smmu 0x1826 0x0>;
2730 reg = <0 0x03ac0000 0 0x2c000>;
2734 iommus = <&apps_smmu 0x1826 0x0>;
2736 #size-cells = <0>;
2742 reg = <0 0x03c00000 0 0x28>;
2751 reg = <0 0x03c40000 0 0xf080>;
2759 reg = <0 0x033c0000 0x0 0x20000>,
2760 <0 0x03550000 0x0 0x10000>;
2763 gpio-ranges = <&lpass_tlmm 0 0 15>;
2808 reg = <0 0x03d00000 0 0x40000>,
2809 <0 0x03d9e000 0 0x1000>,
2810 <0 0x03d61000 0 0x800>;
2815 iommus = <&adreno_smmu 0 0x400>,
2816 <&adreno_smmu 1 0x400>;
2819 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2837 opp-supported-hw = <0x07>;
2844 opp-supported-hw = <0x07>;
2848 opp-550000000-0 {
2852 opp-supported-hw = <0x01>;
2859 opp-supported-hw = <0x06>;
2866 opp-supported-hw = <0x06>;
2873 opp-supported-hw = <0x06>;
2880 opp-supported-hw = <0x06>;
2887 opp-supported-hw = <0x02>;
2894 opp-supported-hw = <0x02>;
2901 reg = <0 0x03d6a000 0 0x34000>,
2902 <0 0x3de0000 0 0x10000>,
2903 <0 0x0b290000 0 0x10000>;
2926 iommus = <&adreno_smmu 5 0x400>;
2941 reg = <0 0x03d90000 0 0x9000>;
2955 reg = <0x0 0x0117f000 0x0 0x1000>,
2956 <0x0 0x01112000 0x0 0x6000>;
2962 reg = <0 0x03da0000 0 0x20000>;
2999 reg = <0x0 0x3dd9000 0x0 0x1000>;
3000 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3005 reg = <0x0 0x3ddd000 0x0 0x1000>;
3006 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3011 reg = <0 0x04080000 0 0x10000>;
3014 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3033 qcom,smem-states = <&modem_smp2p_out 0>;
3051 reg = <0 0x06002000 0 0x1000>,
3052 <0 0x16280000 0 0x180000>;
3069 reg = <0 0x06041000 0 0x1000>;
3084 #size-cells = <0>;
3097 reg = <0 0x06042000 0 0x1000>;
3112 #size-cells = <0>;
3125 reg = <0 0x06045000 0 0x1000>;
3140 #size-cells = <0>;
3142 port@0 {
3143 reg = <0>;
3160 reg = <0 0x06046000 0 0x1000>;
3184 reg = <0 0x06048000 0 0x1000>;
3185 iommus = <&apps_smmu 0x04c0 0>;
3202 reg = <0 0x06b04000 0 0x1000>;
3217 #size-cells = <0>;
3230 reg = <0 0x06b05000 0 0x1000>;
3254 reg = <0 0x06b06000 0 0x1000>;
3279 reg = <0 0x07040000 0 0x1000>;
3299 reg = <0 0x07140000 0 0x1000>;
3319 reg = <0 0x07240000 0 0x1000>;
3339 reg = <0 0x07340000 0 0x1000>;
3359 reg = <0 0x07440000 0 0x1000>;
3379 reg = <0 0x07540000 0 0x1000>;
3399 reg = <0 0x07640000 0 0x1000>;
3419 reg = <0 0x07740000 0 0x1000>;
3439 reg = <0 0x07800000 0 0x1000>;
3454 #size-cells = <0>;
3456 port@0 {
3457 reg = <0>;
3516 reg = <0 0x07810000 0 0x1000>;
3541 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3545 reg = <0 0x08804000 0 0x1000>;
3547 iommus = <&apps_smmu 0x100 0x0>;
3556 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3557 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3565 qcom,dll-config = <0x0007642c>;
3576 opp-avg-kBps = <100000 0>;
3583 opp-avg-kBps = <200000 0>;
3591 reg = <0 0x088e3000 0 0x400>;
3593 #phy-cells = <0>;
3604 reg = <0 0x088e4000 0 0x400>;
3606 #phy-cells = <0>;
3616 reg = <0 0x088e8000 0 0x3000>;
3637 #size-cells = <0>;
3639 port@0 {
3640 reg = <0>;
3664 reg = <0 0x08cf8800 0 0x400>;
3700 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3701 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3706 reg = <0 0x08c00000 0 0xe000>;
3708 iommus = <&apps_smmu 0xa0 0x0>;
3726 reg = <0 0x088dc000 0 0x1000>;
3727 iommus = <&apps_smmu 0x20 0x0>;
3729 #size-cells = <0>;
3734 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3735 &cnoc2 SLAVE_QSPI_0 0>;
3744 reg = <0 0x03700000 0 0x100>;
3747 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3766 qcom,smem-states = <&adsp_smp2p_out 0>;
3787 #size-cells = <0>;
3803 #size-cells = <0>;
3821 #size-cells = <0>;
3823 iommus = <&apps_smmu 0x1801 0x0>;
3825 dai@0 {
3826 reg = <0>;
3846 #sound-dai-cells = <0>;
3857 #size-cells = <0>;
3862 iommus = <&apps_smmu 0x1803 0x0>;
3868 iommus = <&apps_smmu 0x1804 0x0>;
3874 iommus = <&apps_smmu 0x1805 0x0>;
3882 reg = <0 0x08a00000 0 0x10000>;
3885 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3904 qcom,smem-states = <&wpss_smp2p_out 0>;
3924 reg = <0 0x09091000 0 0x1000>;
3935 opp-0 {
3964 reg = <0 0x090b6400 0 0x600>;
3974 opp-0 {
3999 reg = <0 0x090e0000 0 0x5080>;
4006 reg = <0 0x09100000 0 0xe2200>;
4014 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
4015 <0 0x09600000 0 0x58000>;
4022 reg = <0 0x88e0000 0 0x2000>,
4023 <0 0x88e2000 0 0x1000>;
4030 #size-cells = <0>;
4032 port@0 {
4033 reg = <0>;
4042 reg = <0 0x0a0c0000 0 0x10000>;
4050 reg = <0 0x0a300000 0 0x10000>;
4053 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4068 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4074 qcom,smem-states = <&cdsp_smp2p_out 0>;
4095 #size-cells = <0>;
4100 iommus = <&apps_smmu 0x11a1 0x0420>,
4101 <&apps_smmu 0x1181 0x0420>;
4107 iommus = <&apps_smmu 0x11a2 0x0420>,
4108 <&apps_smmu 0x1182 0x0420>;
4114 iommus = <&apps_smmu 0x11a3 0x0420>,
4115 <&apps_smmu 0x1183 0x0420>;
4121 iommus = <&apps_smmu 0x11a4 0x0420>,
4122 <&apps_smmu 0x1184 0x0420>;
4128 iommus = <&apps_smmu 0x11a5 0x0420>,
4129 <&apps_smmu 0x1185 0x0420>;
4135 iommus = <&apps_smmu 0x11a6 0x0420>,
4136 <&apps_smmu 0x1186 0x0420>;
4142 iommus = <&apps_smmu 0x11a7 0x0420>,
4143 <&apps_smmu 0x1187 0x0420>;
4149 iommus = <&apps_smmu 0x11a8 0x0420>,
4150 <&apps_smmu 0x1188 0x0420>;
4158 iommus = <&apps_smmu 0x11ab 0x0420>,
4159 <&apps_smmu 0x118b 0x0420>;
4165 iommus = <&apps_smmu 0x11ac 0x0420>,
4166 <&apps_smmu 0x118c 0x0420>;
4172 iommus = <&apps_smmu 0x11ad 0x0420>,
4173 <&apps_smmu 0x118d 0x0420>;
4179 iommus = <&apps_smmu 0x11ae 0x0420>,
4180 <&apps_smmu 0x118e 0x0420>;
4188 reg = <0 0x0a6f8800 0 0x400>;
4226 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4227 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
4234 reg = <0 0x0a600000 0 0xe000>;
4236 iommus = <&apps_smmu 0xe0 0x0>;
4246 #size-cells = <0>;
4248 port@0 {
4249 reg = <0>;
4267 reg = <0 0x0aa00000 0 0xd0600>;
4284 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
4285 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
4288 iommus = <&apps_smmu 0x2180 0x20>;
4333 reg = <0 0x0aaf0000 0 0x10000>;
4344 reg = <0 0x0ac4a000 0 0x1000>;
4358 pinctrl-0 = <&cci0_default &cci1_default>;
4363 #size-cells = <0>;
4367 cci0_i2c0: i2c-bus@0 {
4368 reg = <0>;
4371 #size-cells = <0>;
4378 #size-cells = <0>;
4384 reg = <0 0x0ac4b000 0 0x1000>;
4398 pinctrl-0 = <&cci2_default &cci3_default>;
4403 #size-cells = <0>;
4407 cci1_i2c0: i2c-bus@0 {
4408 reg = <0>;
4411 #size-cells = <0>;
4418 #size-cells = <0>;
4424 reg = <0 0x0ad00000 0 0x10000>;
4436 reg = <0 0x0af00000 0 0x20000>;
4439 <&mdss_dsi_phy 0>,
4443 <&mdss_edp_phy 0>,
4460 reg = <0 0x0ae00000 0 0x1000>;
4483 iommus = <&apps_smmu 0x900 0x402>;
4493 reg = <0 0x0ae01000 0 0x8f030>,
4494 <0 0x0aeb0000 0 0x2008>;
4517 interrupts = <0>;
4521 #size-cells = <0>;
4523 port@0 {
4524 reg = <0>;
4578 reg = <0 0x0ae94000 0 0x400>;
4598 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4606 #size-cells = <0>;
4612 #size-cells = <0>;
4614 port@0 {
4615 reg = <0>;
4650 reg = <0 0x0ae94400 0 0x200>,
4651 <0 0x0ae94600 0 0x280>,
4652 <0 0x0ae94900 0 0x280>;
4658 #phy-cells = <0>;
4670 pinctrl-0 = <&edp_hot_plug_det>;
4672 reg = <0 0x0aea0000 0 0x200>,
4673 <0 0x0aea0200 0 0x200>,
4674 <0 0x0aea0400 0 0xc00>,
4675 <0 0x0aea1000 0 0x400>;
4692 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4704 #size-cells = <0>;
4706 port@0 {
4707 reg = <0>;
4747 reg = <0 0x0aec2a00 0 0x19c>,
4748 <0 0x0aec2200 0 0xa0>,
4749 <0 0x0aec2600 0 0xa0>,
4750 <0 0x0aec2000 0 0x1c0>;
4758 #phy-cells = <0>;
4766 reg = <0 0x0ae90000 0 0x200>,
4767 <0 0x0ae90200 0 0x200>,
4768 <0 0x0ae90400 0 0xc00>,
4769 <0 0x0ae91000 0 0x400>,
4770 <0 0x0ae91400 0 0x400>;
4795 #sound-dai-cells = <0>;
4801 #size-cells = <0>;
4803 port@0 {
4804 reg = <0>;
4844 reg = <0 0x0b220000 0 0x30000>;
4845 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4857 reg = <0 0x0b5e0000 0 0x20000>;
4864 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4865 <0 0x0c222000 0 0x1ff>; /* SROT */
4875 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4876 <0 0x0c223000 0 0x1ff>; /* SROT */
4886 reg = <0 0x0c2a0000 0 0x31000>;
4892 reg = <0 0x0c300000 0 0x400>;
4899 #clock-cells = <0>;
4904 reg = <0 0x0c3f0000 0 0x400>;
4909 reg = <0 0x0c440000 0 0x1100>,
4910 <0 0x0c600000 0 0x2000000>,
4911 <0 0x0e600000 0 0x100000>,
4912 <0 0x0e700000 0 0xa0000>,
4913 <0 0x0c40a000 0 0x26000>;
4917 qcom,ee = <0>;
4918 qcom,channel = <0>;
4920 #size-cells = <0>;
4927 reg = <0 0x0f100000 0 0x300000>;
4933 gpio-ranges = <&tlmm 0 0 175>;
5780 reg = <0 0x146a5000 0 0x6000>;
5785 ranges = <0 0 0x146a5000 0x6000>;
5789 reg = <0x594c 0xc8>;
5795 reg = <0 0x15000000 0 0x100000>;
5884 reg = <0x0 0x151dd000 0x0 0x1000>;
5887 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5892 reg = <0x0 0x151e1000 0x0 0x1000>;
5895 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5900 reg = <0x0 0x151e5000 0x0 0x1000>;
5904 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5909 reg = <0x0 0x151e9000 0x0 0x1000>;
5913 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5918 reg = <0x0 0x151ed000 0x0 0x1000>;
5922 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5927 reg = <0x0 0x151f1000 0x0 0x1000>;
5931 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5936 reg = <0x0 0x151f5000 0x0 0x1000>;
5939 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5944 reg = <0x0 0x151f9000 0x0 0x1000>;
5947 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5952 reg = <0x0 0x151fd000 0x0 0x1000>;
5956 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
5961 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5962 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5972 reg = <0 0x17a40000 0 0x20000>;
5981 reg = <0 0x17c10000 0 0x1000>;
5983 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5990 ranges = <0 0 0 0x20000000>;
5992 reg = <0 0x17c20000 0 0x1000>;
5995 frame-number = <0>;
5998 reg = <0x17c21000 0x1000>,
5999 <0x17c22000 0x1000>;
6005 reg = <0x17c23000 0x1000>;
6012 reg = <0x17c25000 0x1000>;
6019 reg = <0x17c27000 0x1000>;
6026 reg = <0x17c29000 0x1000>;
6033 reg = <0x17c2b000 0x1000>;
6040 reg = <0x17c2d000 0x1000>;
6047 reg = <0 0x18200000 0 0x10000>,
6048 <0 0x18210000 0 0x10000>,
6049 <0 0x18220000 0 0x10000>;
6050 reg-names = "drv-0", "drv-1", "drv-2";
6054 qcom,tcs-offset = <0xd00>;
6122 reg = <0 0x18590000 0 0x1000>;
6130 reg = <0 0x18591000 0 0x1000>,
6131 <0 0x18592000 0 0x1000>,
6132 <0 0x18593000 0 0x1000>;
6137 interrupt-names = "dcvsh-irq-0",
6172 hysteresis = <0>;
6215 hysteresis = <0>;
6258 hysteresis = <0>;
6301 hysteresis = <0>;
6344 hysteresis = <0>;
6387 hysteresis = <0>;
6430 hysteresis = <0>;
6473 hysteresis = <0>;
6516 hysteresis = <0>;
6559 hysteresis = <0>;
6602 hysteresis = <0>;
6645 hysteresis = <0>;
6669 polling-delay-passive = <0>;
6671 thermal-sensors = <&tsens0 0>;
6682 hysteresis = <0>;
6689 polling-delay-passive = <0>;
6691 thermal-sensors = <&tsens1 0>;
6702 hysteresis = <0>;
6709 polling-delay-passive = <0>;
6721 hysteresis = <0>;
6728 polling-delay-passive = <0>;
6740 hysteresis = <0>;
6760 hysteresis = <0>;
6787 hysteresis = <0>;
6812 hysteresis = <0>;
6830 hysteresis = <0>;
6848 hysteresis = <0>;
6866 hysteresis = <0>;
6884 hysteresis = <0>;
6902 hysteresis = <0>;
6920 hysteresis = <0>;
6938 hysteresis = <0>;
6956 hysteresis = <0>;