Lines Matching +full:0 +full:x0aec2a00
83 #clock-cells = <0>;
89 #clock-cells = <0>;
100 reg = <0x0 0x004cd000 0x0 0x1000>;
104 reg = <0x0 0x80000000 0x0 0x600000>;
109 reg = <0x0 0x80600000 0x0 0x200000>;
114 reg = <0x0 0x80800000 0x0 0x60000>;
119 reg = <0x0 0x80860000 0x0 0x20000>;
125 reg = <0x0 0x80884000 0x0 0x10000>;
130 reg = <0x0 0x808ff000 0x0 0x1000>;
135 reg = <0x0 0x80900000 0x0 0x200000>;
141 reg = <0x0 0x80b00000 0x0 0x100000>;
145 reg = <0x0 0x80c00000 0x0 0xc00000>;
150 reg = <0x0 0x86700000 0x0 0x2800000>;
155 reg = <0x0 0x8b200000 0x0 0x500000>;
160 reg = <0x0 0x88f00000 0x0 0x1e00000>;
165 reg = <0 0x8b700000 0 0x10000>;
170 reg = <0 0x8b71a000 0 0x2000>;
175 reg = <0x0 0x8b800000 0x0 0xf600000>;
180 reg = <0x0 0x9ae00000 0x0 0x1900000>;
186 reg = <0x0 0x9c900000 0x0 0x280000>;
196 #size-cells = <0>;
198 cpu0: cpu@0 {
201 reg = <0x0 0x0>;
202 clocks = <&cpufreq_hw 0>;
212 qcom,freq-domain = <&cpufreq_hw 0>;
230 reg = <0x0 0x100>;
231 clocks = <&cpufreq_hw 0>;
241 qcom,freq-domain = <&cpufreq_hw 0>;
254 reg = <0x0 0x200>;
255 clocks = <&cpufreq_hw 0>;
265 qcom,freq-domain = <&cpufreq_hw 0>;
278 reg = <0x0 0x300>;
279 clocks = <&cpufreq_hw 0>;
289 qcom,freq-domain = <&cpufreq_hw 0>;
302 reg = <0x0 0x400>;
326 reg = <0x0 0x500>;
350 reg = <0x0 0x600>;
374 reg = <0x0 0x700>;
434 little_cpu_sleep_0: cpu-sleep-0-0 {
437 arm,psci-suspend-param = <0x40000003>;
444 little_cpu_sleep_1: cpu-sleep-0-1 {
447 arm,psci-suspend-param = <0x40000004>;
454 big_cpu_sleep_0: cpu-sleep-1-0 {
457 arm,psci-suspend-param = <0x40000003>;
467 arm,psci-suspend-param = <0x40000004>;
476 cluster_sleep_apss_off: cluster-sleep-0 {
478 arm,psci-suspend-param = <0x41000044>;
486 arm,psci-suspend-param = <0x41001344>;
494 arm,psci-suspend-param = <0x4100b344>;
710 reg = <0 0x80000000 0 0>;
716 qcom,dload-mode = <&tcsr_2 0x13000>;
741 qcom,local-pid = <0>;
765 qcom,local-pid = <0>;
789 qcom,local-pid = <0>;
824 qcom,local-pid = <0>;
865 #power-domain-cells = <0>;
871 #power-domain-cells = <0>;
877 #power-domain-cells = <0>;
883 #power-domain-cells = <0>;
889 #power-domain-cells = <0>;
895 #power-domain-cells = <0>;
901 #power-domain-cells = <0>;
907 #power-domain-cells = <0>;
913 #power-domain-cells = <0>;
961 soc: soc@0 {
964 ranges = <0 0 0 0 0x10 0>;
965 dma-ranges = <0 0 0 0 0x10 0>;
970 reg = <0 0x00100000 0 0x1f0000>;
973 <0>, <&pcie1_phy>,
974 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
989 reg = <0 0x00408000 0 0x1000>;
998 reg = <0 0x00784000 0 0xa20>,
999 <0 0x00780000 0 0xa20>,
1000 <0 0x00782000 0 0x120>,
1001 <0 0x00786000 0 0x1fff>;
1009 reg = <0x1e9 0x2>;
1017 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1021 reg = <0 0x007c4000 0 0x1000>,
1022 <0 0x007c5000 0 0x1000>;
1025 iommus = <&apps_smmu 0xc0 0x0>;
1034 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
1035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
1044 qcom,dll-config = <0x0007642c>;
1045 qcom,ddr-config = <0x80040868>;
1061 opp-avg-kBps = <100000 0>;
1068 opp-avg-kBps = <390000 0>;
1076 reg = <0 0x00900000 0 0x60000>;
1090 dma-channel-mask = <0x7f>;
1091 iommus = <&apps_smmu 0x0136 0x0>;
1097 reg = <0 0x009c0000 0 0x2000>;
1104 iommus = <&apps_smmu 0x123 0x0>;
1109 reg = <0 0x00980000 0 0x4000>;
1113 pinctrl-0 = <&qup_i2c0_data_clk>;
1116 #size-cells = <0>;
1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1118 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1119 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1124 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1125 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1132 reg = <0 0x00980000 0 0x4000>;
1136 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1139 #size-cells = <0>;
1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1145 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1146 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1153 reg = <0 0x00980000 0 0x4000>;
1157 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1162 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1169 reg = <0 0x00984000 0 0x4000>;
1173 pinctrl-0 = <&qup_i2c1_data_clk>;
1176 #size-cells = <0>;
1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1178 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1179 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1184 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 reg = <0 0x00984000 0 0x4000>;
1196 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1199 #size-cells = <0>;
1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1203 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1205 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1213 reg = <0 0x00984000 0 0x4000>;
1217 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1229 reg = <0 0x00988000 0 0x4000>;
1233 pinctrl-0 = <&qup_i2c2_data_clk>;
1236 #size-cells = <0>;
1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1239 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1244 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1252 reg = <0 0x00988000 0 0x4000>;
1256 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1259 #size-cells = <0>;
1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1263 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1265 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1273 reg = <0 0x00988000 0 0x4000>;
1277 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1281 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1282 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1289 reg = <0 0x0098c000 0 0x4000>;
1293 pinctrl-0 = <&qup_i2c3_data_clk>;
1296 #size-cells = <0>;
1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1299 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1304 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1312 reg = <0 0x0098c000 0 0x4000>;
1316 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1319 #size-cells = <0>;
1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1323 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1325 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1333 reg = <0 0x0098c000 0 0x4000>;
1337 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1341 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1342 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1349 reg = <0 0x00990000 0 0x4000>;
1353 pinctrl-0 = <&qup_i2c4_data_clk>;
1356 #size-cells = <0>;
1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1358 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1359 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1364 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1372 reg = <0 0x00990000 0 0x4000>;
1376 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1379 #size-cells = <0>;
1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1383 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1385 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1393 reg = <0 0x00990000 0 0x4000>;
1397 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1401 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1402 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1409 reg = <0 0x00994000 0 0x4000>;
1413 pinctrl-0 = <&qup_i2c5_data_clk>;
1416 #size-cells = <0>;
1417 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1419 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1424 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1432 reg = <0 0x00994000 0 0x4000>;
1436 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1439 #size-cells = <0>;
1442 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1443 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1445 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1453 reg = <0 0x00994000 0 0x4000>;
1457 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1461 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1462 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1469 reg = <0 0x00998000 0 0x4000>;
1473 pinctrl-0 = <&qup_i2c6_data_clk>;
1476 #size-cells = <0>;
1477 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1478 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1479 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1484 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1492 reg = <0 0x00998000 0 0x4000>;
1496 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1499 #size-cells = <0>;
1502 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1503 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1505 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1513 reg = <0 0x00998000 0 0x4000>;
1517 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1521 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1529 reg = <0 0x0099c000 0 0x4000>;
1533 pinctrl-0 = <&qup_i2c7_data_clk>;
1536 #size-cells = <0>;
1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1538 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1539 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1544 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1552 reg = <0 0x0099c000 0 0x4000>;
1556 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1559 #size-cells = <0>;
1562 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1565 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1573 reg = <0 0x0099c000 0 0x4000>;
1577 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1581 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1582 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1591 reg = <0 0x00a00000 0 0x60000>;
1605 dma-channel-mask = <0x1e>;
1606 iommus = <&apps_smmu 0x56 0x0>;
1612 reg = <0 0x00ac0000 0 0x2000>;
1619 iommus = <&apps_smmu 0x43 0x0>;
1624 reg = <0 0x00a80000 0 0x4000>;
1628 pinctrl-0 = <&qup_i2c8_data_clk>;
1631 #size-cells = <0>;
1632 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1633 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1634 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1639 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1640 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1647 reg = <0 0x00a80000 0 0x4000>;
1651 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1654 #size-cells = <0>;
1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1658 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1660 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1661 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1668 reg = <0 0x00a80000 0 0x4000>;
1672 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1677 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1684 reg = <0 0x00a84000 0 0x4000>;
1688 pinctrl-0 = <&qup_i2c9_data_clk>;
1691 #size-cells = <0>;
1692 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1694 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1699 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1707 reg = <0 0x00a84000 0 0x4000>;
1711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1714 #size-cells = <0>;
1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1720 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1728 reg = <0 0x00a84000 0 0x4000>;
1732 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1737 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1744 reg = <0 0x00a88000 0 0x4000>;
1748 pinctrl-0 = <&qup_i2c10_data_clk>;
1751 #size-cells = <0>;
1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1759 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1767 reg = <0 0x00a88000 0 0x4000>;
1771 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1774 #size-cells = <0>;
1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1778 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1780 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1788 reg = <0 0x00a88000 0 0x4000>;
1792 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1804 reg = <0 0x00a8c000 0 0x4000>;
1808 pinctrl-0 = <&qup_i2c11_data_clk>;
1811 #size-cells = <0>;
1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1814 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1819 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1827 reg = <0 0x00a8c000 0 0x4000>;
1831 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1834 #size-cells = <0>;
1837 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1838 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1840 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1848 reg = <0 0x00a8c000 0 0x4000>;
1852 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1856 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1857 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1864 reg = <0 0x00a90000 0 0x4000>;
1868 pinctrl-0 = <&qup_i2c12_data_clk>;
1871 #size-cells = <0>;
1872 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1874 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1879 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1887 reg = <0 0x00a90000 0 0x4000>;
1891 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1894 #size-cells = <0>;
1897 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1898 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1900 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1908 reg = <0 0x00a90000 0 0x4000>;
1912 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1916 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1917 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1924 reg = <0 0x00a94000 0 0x4000>;
1928 pinctrl-0 = <&qup_i2c13_data_clk>;
1931 #size-cells = <0>;
1932 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1933 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1934 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1939 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1947 reg = <0 0x00a94000 0 0x4000>;
1951 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1954 #size-cells = <0>;
1957 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1958 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1960 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1968 reg = <0 0x00a94000 0 0x4000>;
1972 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1976 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1984 reg = <0 0x00a98000 0 0x4000>;
1988 pinctrl-0 = <&qup_i2c14_data_clk>;
1991 #size-cells = <0>;
1992 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1994 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1999 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2007 reg = <0 0x00a98000 0 0x4000>;
2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2014 #size-cells = <0>;
2017 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2018 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2020 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2028 reg = <0 0x00a98000 0 0x4000>;
2032 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2036 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2044 reg = <0 0x00a9c000 0 0x4000>;
2048 pinctrl-0 = <&qup_i2c15_data_clk>;
2051 #size-cells = <0>;
2052 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2053 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
2054 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
2059 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2067 reg = <0 0x00a9c000 0 0x4000>;
2071 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2074 #size-cells = <0>;
2077 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2080 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2088 reg = <0 0x00a9c000 0 0x4000>;
2092 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2096 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2105 reg = <0 0x010d3000 0 0x1000>;
2109 reg = <0 0x01500000 0 0x1000>;
2116 reg = <0 0x01502000 0 0x1000>;
2123 reg = <0 0x01580000 0 0x4>;
2130 reg = <0 0x01680000 0 0x15480>;
2138 reg = <0 0x016e0000 0 0x1c080>;
2146 reg = <0 0x01700000 0 0x2b080>;
2154 reg = <0 0x01740000 0 0x1e080>;
2162 reg = <0 0x17a10040 0 0x0>;
2163 iommus = <&apps_smmu 0x1c00 0x1>;
2199 qcom,smem-states = <&wlan_smp2p_out 0>;
2205 reg = <0 0x01c08000 0 0x3000>,
2206 <0 0x40000000 0 0xf1d>,
2207 <0 0x40000f20 0 0xa8>,
2208 <0 0x40001000 0 0x1000>,
2209 <0 0x40100000 0 0x100000>;
2214 bus-range = <0x00 0xff>;
2220 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2221 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2242 interrupt-map-mask = <0 0 0 0x7>;
2243 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2244 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2245 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2246 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2288 pinctrl-0 = <&pcie1_clkreq_n>;
2292 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2293 <0x100 &apps_smmu 0x1c81 0x1>;
2297 pcie@0 {
2299 reg = <0x0 0x0 0x0 0x0 0x0>;
2300 bus-range = <0x01 0xff>;
2310 reg = <0 0x01c0e000 0 0x1000>;
2323 #clock-cells = <0>;
2325 #phy-cells = <0>;
2339 reg = <0x0 0x01d84000 0x0 0x3000>;
2351 iommus = <&apps_smmu 0x80 0x0>;
2388 /bits/ 64 <0>,
2389 /bits/ 64 <0>,
2391 /bits/ 64 <0>,
2392 /bits/ 64 <0>,
2393 /bits/ 64 <0>,
2394 /bits/ 64 <0>;
2400 /bits/ 64 <0>,
2401 /bits/ 64 <0>,
2403 /bits/ 64 <0>,
2404 /bits/ 64 <0>,
2405 /bits/ 64 <0>,
2406 /bits/ 64 <0>;
2412 /bits/ 64 <0>,
2413 /bits/ 64 <0>,
2415 /bits/ 64 <0>,
2416 /bits/ 64 <0>,
2417 /bits/ 64 <0>,
2418 /bits/ 64 <0>;
2426 reg = <0x0 0x01d87000 0x0 0xe00>;
2434 resets = <&ufs_mem_hc 0>;
2438 #phy-cells = <0>;
2446 reg = <0 0x01d88000 0 0x8000>;
2452 reg = <0x0 0x01dc4000 0x0 0x28000>;
2455 iommus = <&apps_smmu 0x4e4 0x0011>,
2456 <&apps_smmu 0x4e6 0x0011>;
2457 qcom,ee = <0>;
2465 reg = <0x0 0x01dfa000 0x0 0x6000>;
2468 iommus = <&apps_smmu 0x4e4 0x0011>,
2469 <&apps_smmu 0x4e4 0x0011>;
2470 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
2477 iommus = <&apps_smmu 0x480 0x0>,
2478 <&apps_smmu 0x482 0x0>;
2479 reg = <0 0x01e40000 0 0x8000>,
2480 <0 0x01e50000 0 0x4ad0>,
2481 <0 0x01e04000 0 0x23000>;
2488 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2498 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2499 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2505 qcom,smem-states = <&ipa_smp2p_out 0>,
2515 reg = <0 0x01f40000 0 0x20000>;
2521 reg = <0 0x01f60000 0 0x20000>;
2526 reg = <0 0x01fc0000 0 0x30000>;
2531 reg = <0 0x03000000 0 0x40>,
2532 <0 0x03c04000 0 0x4>;
2542 reg = <0 0x03200000 0 0x1000>;
2545 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2556 #clock-cells = <0>;
2564 reg = <0 0x03210000 0 0x2000>;
2570 qcom,din-ports = <0>;
2576 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2577 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2578 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2579 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2580 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2581 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2582 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2583 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2584 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2588 #size-cells = <0>;
2595 reg = <0 0x03220000 0 0x1000>;
2598 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2609 #clock-cells = <0>;
2617 reg = <0 0x03230000 0 0x2000>;
2625 qcom,dout-ports = <0>;
2630 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2631 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2632 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2633 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2634 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2635 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2636 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2637 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2638 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2642 #size-cells = <0>;
2649 reg = <0 0x03300000 0 0x30000>,
2650 <0 0x032a9000 0 0x1000>;
2662 reg = <0 0x03370000 0 0x1000>;
2671 #clock-cells = <0>;
2679 reg = <0 0x03380000 0 0x30000>;
2691 reg = <0 0x03900000 0 0x50000>;
2703 reg = <0 0x03987000 0 0x68000>,
2704 <0 0x03b00000 0 0x29000>,
2705 <0 0x03260000 0 0xc000>,
2706 <0 0x03280000 0 0x29000>,
2707 <0 0x03340000 0 0x29000>,
2708 <0 0x0336c000 0 0x3000>;
2716 iommus = <&apps_smmu 0x1820 0>,
2717 <&apps_smmu 0x1821 0>,
2718 <&apps_smmu 0x1832 0>;
2747 #size-cells = <0>;
2763 reg = <0 0x03a84000 0 0x20000>;
2770 iommus = <&apps_smmu 0x1826 0x0>;
2776 reg = <0 0x03ac0000 0 0x2c000>;
2780 iommus = <&apps_smmu 0x1826 0x0>;
2782 #size-cells = <0>;
2788 reg = <0 0x03c00000 0 0x28>;
2797 reg = <0 0x03c40000 0 0xf080>;
2805 reg = <0 0x033c0000 0x0 0x20000>,
2806 <0 0x03550000 0x0 0x10000>;
2809 gpio-ranges = <&lpass_tlmm 0 0 15>;
2854 reg = <0 0x03d00000 0 0x40000>,
2855 <0 0x03d9e000 0 0x1000>,
2856 <0 0x03d61000 0 0x800>;
2861 iommus = <&adreno_smmu 0 0x400>,
2862 <&adreno_smmu 1 0x400>;
2865 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2885 opp-supported-hw = <0x17>;
2892 opp-supported-hw = <0x17>;
2896 opp-550000000-0 {
2900 opp-supported-hw = <0x01>;
2907 opp-supported-hw = <0x16>;
2914 opp-supported-hw = <0x16>;
2921 opp-supported-hw = <0x06>;
2928 opp-supported-hw = <0x06>;
2935 opp-supported-hw = <0x02>;
2942 opp-supported-hw = <0x02>;
2949 reg = <0 0x03d6a000 0 0x34000>,
2950 <0 0x3de0000 0 0x10000>,
2951 <0 0x0b290000 0 0x10000>;
2974 iommus = <&adreno_smmu 5 0x400>;
2989 reg = <0 0x03d90000 0 0x9000>;
3003 reg = <0x0 0x0117f000 0x0 0x1000>,
3004 <0x0 0x01112000 0x0 0x6000>;
3010 reg = <0 0x03da0000 0 0x20000>;
3047 reg = <0x0 0x3dd9000 0x0 0x1000>;
3048 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3053 reg = <0x0 0x3ddd000 0x0 0x1000>;
3054 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3059 reg = <0 0x04080000 0 0x10000>;
3062 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3081 qcom,smem-states = <&modem_smp2p_out 0>;
3099 reg = <0 0x06002000 0 0x1000>,
3100 <0 0x16280000 0 0x180000>;
3117 reg = <0 0x06041000 0 0x1000>;
3132 #size-cells = <0>;
3145 reg = <0 0x06042000 0 0x1000>;
3160 #size-cells = <0>;
3173 reg = <0 0x06045000 0 0x1000>;
3188 #size-cells = <0>;
3190 port@0 {
3191 reg = <0>;
3208 reg = <0 0x06046000 0 0x1000>;
3232 reg = <0 0x06048000 0 0x1000>;
3233 iommus = <&apps_smmu 0x04c0 0>;
3250 reg = <0 0x06b04000 0 0x1000>;
3265 #size-cells = <0>;
3278 reg = <0 0x06b05000 0 0x1000>;
3302 reg = <0 0x06b06000 0 0x1000>;
3327 reg = <0 0x07040000 0 0x1000>;
3347 reg = <0 0x07140000 0 0x1000>;
3367 reg = <0 0x07240000 0 0x1000>;
3387 reg = <0 0x07340000 0 0x1000>;
3407 reg = <0 0x07440000 0 0x1000>;
3427 reg = <0 0x07540000 0 0x1000>;
3447 reg = <0 0x07640000 0 0x1000>;
3467 reg = <0 0x07740000 0 0x1000>;
3487 reg = <0 0x07800000 0 0x1000>;
3502 #size-cells = <0>;
3504 port@0 {
3505 reg = <0>;
3564 reg = <0 0x07810000 0 0x1000>;
3589 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3593 reg = <0 0x08804000 0 0x1000>;
3595 iommus = <&apps_smmu 0x100 0x0>;
3604 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3613 qcom,dll-config = <0x0007642c>;
3624 opp-avg-kBps = <100000 0>;
3631 opp-avg-kBps = <200000 0>;
3639 reg = <0 0x088e3000 0 0x400>;
3641 #phy-cells = <0>;
3652 reg = <0 0x088e4000 0 0x400>;
3654 #phy-cells = <0>;
3664 reg = <0 0x088e8000 0 0x3000>;
3687 #size-cells = <0>;
3689 port@0 {
3690 reg = <0>;
3716 reg = <0 0x08cf8800 0 0x400>;
3752 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3758 reg = <0 0x08c00000 0 0xe000>;
3760 iommus = <&apps_smmu 0xa0 0x0>;
3780 reg = <0 0x088dc000 0 0x1000>;
3781 iommus = <&apps_smmu 0x20 0x0>;
3783 #size-cells = <0>;
3788 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3789 &cnoc2 SLAVE_QSPI_0 0>;
3798 reg = <0 0x03700000 0 0x100>;
3801 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3820 qcom,smem-states = <&adsp_smp2p_out 0>;
3841 #size-cells = <0>;
3857 #size-cells = <0>;
3875 #size-cells = <0>;
3877 iommus = <&apps_smmu 0x1801 0x0>;
3879 dai@0 {
3900 #sound-dai-cells = <0>;
3911 #size-cells = <0>;
3916 iommus = <&apps_smmu 0x1803 0x0>;
3923 iommus = <&apps_smmu 0x1804 0x0>;
3930 iommus = <&apps_smmu 0x1805 0x0>;
3939 reg = <0 0x08a00000 0 0x10000>;
3942 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3961 qcom,smem-states = <&wpss_smp2p_out 0>;
3981 reg = <0 0x09091000 0 0x1000>;
3992 opp-0 {
4021 reg = <0 0x090b6400 0 0x600>;
4031 opp-0 {
4056 reg = <0 0x090e0000 0 0x5080>;
4063 reg = <0 0x09100000 0 0xe2200>;
4071 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
4072 <0 0x09600000 0 0x58000>;
4079 reg = <0 0x88e0000 0 0x2000>,
4080 <0 0x88e2000 0 0x1000>;
4087 #size-cells = <0>;
4089 port@0 {
4090 reg = <0>;
4099 reg = <0 0x0a0c0000 0 0x10000>;
4107 reg = <0 0x0a300000 0 0x10000>;
4110 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4125 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4131 qcom,smem-states = <&cdsp_smp2p_out 0>;
4152 #size-cells = <0>;
4157 iommus = <&apps_smmu 0x11a1 0x0420>,
4158 <&apps_smmu 0x1181 0x0420>;
4165 iommus = <&apps_smmu 0x11a2 0x0420>,
4166 <&apps_smmu 0x1182 0x0420>;
4173 iommus = <&apps_smmu 0x11a3 0x0420>,
4174 <&apps_smmu 0x1183 0x0420>;
4181 iommus = <&apps_smmu 0x11a4 0x0420>,
4182 <&apps_smmu 0x1184 0x0420>;
4189 iommus = <&apps_smmu 0x11a5 0x0420>,
4190 <&apps_smmu 0x1185 0x0420>;
4197 iommus = <&apps_smmu 0x11a6 0x0420>,
4198 <&apps_smmu 0x1186 0x0420>;
4205 iommus = <&apps_smmu 0x11a7 0x0420>,
4206 <&apps_smmu 0x1187 0x0420>;
4213 iommus = <&apps_smmu 0x11a8 0x0420>,
4214 <&apps_smmu 0x1188 0x0420>;
4223 iommus = <&apps_smmu 0x11ab 0x0420>,
4224 <&apps_smmu 0x118b 0x0420>;
4231 iommus = <&apps_smmu 0x11ac 0x0420>,
4232 <&apps_smmu 0x118c 0x0420>;
4239 iommus = <&apps_smmu 0x11ad 0x0420>,
4240 <&apps_smmu 0x118d 0x0420>;
4247 iommus = <&apps_smmu 0x11ae 0x0420>,
4248 <&apps_smmu 0x118e 0x0420>;
4257 reg = <0 0x0a6f8800 0 0x400>;
4295 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
4303 reg = <0 0x0a600000 0 0xe000>;
4305 iommus = <&apps_smmu 0xe0 0x0>;
4317 #size-cells = <0>;
4319 port@0 {
4320 reg = <0>;
4339 reg = <0 0x0aa00000 0 0xd0600>;
4356 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
4357 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
4360 iommus = <&apps_smmu 0x2180 0x20>;
4397 reg = <0 0x0aaf0000 0 0x10000>;
4408 reg = <0 0x0ac4a000 0 0x1000>;
4422 pinctrl-0 = <&cci0_default &cci1_default>;
4427 #size-cells = <0>;
4431 cci0_i2c0: i2c-bus@0 {
4432 reg = <0>;
4435 #size-cells = <0>;
4442 #size-cells = <0>;
4448 reg = <0 0x0ac4b000 0 0x1000>;
4462 pinctrl-0 = <&cci2_default &cci3_default>;
4467 #size-cells = <0>;
4471 cci1_i2c0: i2c-bus@0 {
4472 reg = <0>;
4475 #size-cells = <0>;
4482 #size-cells = <0>;
4489 reg = <0x0 0x0acb3000 0x0 0x1000>,
4490 <0x0 0x0acba000 0x0 0x1000>,
4491 <0x0 0x0acc1000 0x0 0x1000>,
4492 <0x0 0x0acc8000 0x0 0x1000>,
4493 <0x0 0x0accf000 0x0 0x1000>,
4494 <0x0 0x0ace0000 0x0 0x2000>,
4495 <0x0 0x0ace2000 0x0 0x2000>,
4496 <0x0 0x0ace4000 0x0 0x2000>,
4497 <0x0 0x0ace6000 0x0 0x2000>,
4498 <0x0 0x0ace8000 0x0 0x2000>,
4499 <0x0 0x0acaf000 0x0 0x4000>,
4500 <0x0 0x0acb6000 0x0 0x4000>,
4501 <0x0 0x0acbd000 0x0 0x4000>,
4502 <0x0 0x0acc4000 0x0 0x4000>,
4503 <0x0 0x0accb000 0x0 0x4000>;
4625 iommus = <&apps_smmu 0x800 0x4e0>;
4640 #size-cells = <0>;
4642 port@0 {
4643 reg = <0>;
4666 reg = <0 0x0ad00000 0 0x10000>;
4678 reg = <0 0x0af00000 0 0x20000>;
4685 <&mdss_edp_phy 0>,
4702 reg = <0 0x0ae00000 0 0x1000>;
4725 iommus = <&apps_smmu 0x900 0x402>;
4735 reg = <0 0x0ae01000 0 0x8f030>,
4736 <0 0x0aeb0000 0 0x3000>;
4759 interrupts = <0>;
4763 #size-cells = <0>;
4765 port@0 {
4766 reg = <0>;
4820 reg = <0 0x0ae94000 0 0x400>;
4850 #size-cells = <0>;
4856 #size-cells = <0>;
4858 port@0 {
4859 reg = <0>;
4894 reg = <0 0x0ae94400 0 0x200>,
4895 <0 0x0ae94600 0 0x280>,
4896 <0 0x0ae94900 0 0x280>;
4902 #phy-cells = <0>;
4914 pinctrl-0 = <&edp_hot_plug_det>;
4916 reg = <0 0x0aea0000 0 0x200>,
4917 <0 0x0aea0200 0 0x200>,
4918 <0 0x0aea0400 0 0xc00>,
4919 <0 0x0aea1000 0 0x400>;
4936 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4948 #size-cells = <0>;
4950 port@0 {
4951 reg = <0>;
4991 reg = <0 0x0aec2a00 0 0x19c>,
4992 <0 0x0aec2200 0 0xa0>,
4993 <0 0x0aec2600 0 0xa0>,
4994 <0 0x0aec2000 0 0x1c0>;
5002 #phy-cells = <0>;
5010 reg = <0 0x0ae90000 0 0x200>,
5011 <0 0x0ae90200 0 0x200>,
5012 <0 0x0ae90400 0 0xc00>,
5013 <0 0x0ae91000 0 0x400>,
5014 <0 0x0ae91400 0 0x400>;
5039 #sound-dai-cells = <0>;
5045 #size-cells = <0>;
5047 port@0 {
5048 reg = <0>;
5090 reg = <0 0x0b220000 0 0x30000>;
5091 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
5103 reg = <0 0x0b5e0000 0 0x20000>;
5110 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5111 <0 0x0c222000 0 0x1ff>; /* SROT */
5121 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5122 <0 0x0c223000 0 0x1ff>; /* SROT */
5132 reg = <0 0x0c2a0000 0 0x31000>;
5138 reg = <0 0x0c300000 0 0x400>;
5145 #clock-cells = <0>;
5150 reg = <0 0x0c3f0000 0 0x400>;
5155 reg = <0 0x0c440000 0 0x1100>,
5156 <0 0x0c600000 0 0x2000000>,
5157 <0 0x0e600000 0 0x100000>,
5158 <0 0x0e700000 0 0xa0000>,
5159 <0 0x0c40a000 0 0x26000>;
5163 qcom,ee = <0>;
5164 qcom,channel = <0>;
5166 #size-cells = <0>;
5173 reg = <0 0x0f100000 0 0x300000>;
5179 gpio-ranges = <&tlmm 0 0 175>;
6026 reg = <0 0x146a5000 0 0x6000>;
6031 ranges = <0 0 0x146a5000 0x6000>;
6035 reg = <0x594c 0xc8>;
6041 reg = <0 0x15000000 0 0x100000>;
6130 reg = <0x0 0x151dd000 0x0 0x1000>;
6133 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
6138 reg = <0x0 0x151e1000 0x0 0x1000>;
6141 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
6146 reg = <0x0 0x151e5000 0x0 0x1000>;
6150 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
6155 reg = <0x0 0x151e9000 0x0 0x1000>;
6159 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
6164 reg = <0x0 0x151ed000 0x0 0x1000>;
6168 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
6173 reg = <0x0 0x151f1000 0x0 0x1000>;
6177 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
6182 reg = <0x0 0x151f5000 0x0 0x1000>;
6185 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
6190 reg = <0x0 0x151f9000 0x0 0x1000>;
6193 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
6198 reg = <0x0 0x151fd000 0x0 0x1000>;
6202 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
6207 reg = <0 0x17a00000 0 0x10000>, /* GICD */
6208 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
6218 reg = <0 0x17a40000 0 0x20000>;
6227 reg = <0 0x17c10000 0 0x1000>;
6229 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6236 ranges = <0 0 0 0x20000000>;
6238 reg = <0 0x17c20000 0 0x1000>;
6241 frame-number = <0>;
6244 reg = <0x17c21000 0x1000>,
6245 <0x17c22000 0x1000>;
6251 reg = <0x17c23000 0x1000>;
6258 reg = <0x17c25000 0x1000>;
6265 reg = <0x17c27000 0x1000>;
6272 reg = <0x17c29000 0x1000>;
6279 reg = <0x17c2b000 0x1000>;
6286 reg = <0x17c2d000 0x1000>;
6293 reg = <0 0x18200000 0 0x10000>,
6294 <0 0x18210000 0 0x10000>,
6295 <0 0x18220000 0 0x10000>;
6296 reg-names = "drv-0", "drv-1", "drv-2";
6300 qcom,tcs-offset = <0xd00>;
6368 reg = <0 0x18590000 0 0x1000>;
6376 reg = <0 0x18591000 0 0x1000>,
6377 <0 0x18592000 0 0x1000>,
6378 <0 0x18593000 0 0x1000>;
6383 interrupt-names = "dcvsh-irq-0",
6418 hysteresis = <0>;
6461 hysteresis = <0>;
6504 hysteresis = <0>;
6547 hysteresis = <0>;
6590 hysteresis = <0>;
6633 hysteresis = <0>;
6676 hysteresis = <0>;
6719 hysteresis = <0>;
6762 hysteresis = <0>;
6805 hysteresis = <0>;
6848 hysteresis = <0>;
6891 hysteresis = <0>;
6915 polling-delay-passive = <0>;
6917 thermal-sensors = <&tsens0 0>;
6928 hysteresis = <0>;
6935 polling-delay-passive = <0>;
6937 thermal-sensors = <&tsens1 0>;
6948 hysteresis = <0>;
6955 polling-delay-passive = <0>;
6967 hysteresis = <0>;
6974 polling-delay-passive = <0>;
6986 hysteresis = <0>;
7006 hysteresis = <0>;
7033 hysteresis = <0>;
7058 hysteresis = <0>;
7076 hysteresis = <0>;
7094 hysteresis = <0>;
7112 hysteresis = <0>;
7130 hysteresis = <0>;
7148 hysteresis = <0>;
7166 hysteresis = <0>;
7184 hysteresis = <0>;
7202 hysteresis = <0>;