Lines Matching +full:q6afe +full:- +full:clocks
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/sound/qcom,q6afe.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
62 clocks {
63 xo_board: xo-board {
64 compatible = "fixed-clock";
65 clock-frequency = <38400000>;
66 #clock-cells = <0>;
69 sleep_clk: sleep-clk {
70 compatible = "fixed-clock";
71 clock-frequency = <32764>;
72 #clock-cells = <0>;
77 #address-cells = <2>;
78 #size-cells = <0>;
84 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci";
86 power-domains = <&CPU_PD0>;
87 power-domain-names = "psci";
88 capacity-dmips-mhz = <415>;
89 dynamic-power-coefficient = <137>;
90 operating-points-v2 = <&cpu0_opp_table>;
93 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache {
98 cache-level = <2>;
99 cache-unified;
100 next-level-cache = <&L3_0>;
101 L3_0: l3-cache {
103 cache-level = <3>;
104 cache-unified;
113 clocks = <&cpufreq_hw 0>;
114 enable-method = "psci";
115 power-domains = <&CPU_PD1>;
116 power-domain-names = "psci";
117 capacity-dmips-mhz = <415>;
118 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L2_100>;
120 operating-points-v2 = <&cpu0_opp_table>;
123 #cooling-cells = <2>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache {
127 cache-level = <2>;
128 cache-unified;
129 next-level-cache = <&L3_0>;
137 clocks = <&cpufreq_hw 0>;
138 enable-method = "psci";
139 power-domains = <&CPU_PD2>;
140 power-domain-names = "psci";
141 capacity-dmips-mhz = <415>;
142 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L2_200>;
144 operating-points-v2 = <&cpu0_opp_table>;
147 #cooling-cells = <2>;
148 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache {
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&L3_0>;
161 clocks = <&cpufreq_hw 0>;
162 enable-method = "psci";
163 power-domains = <&CPU_PD3>;
164 power-domain-names = "psci";
165 capacity-dmips-mhz = <415>;
166 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L2_300>;
168 operating-points-v2 = <&cpu0_opp_table>;
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache {
175 cache-level = <2>;
176 cache-unified;
177 next-level-cache = <&L3_0>;
185 clocks = <&cpufreq_hw 0>;
186 enable-method = "psci";
187 power-domains = <&CPU_PD4>;
188 power-domain-names = "psci";
189 capacity-dmips-mhz = <415>;
190 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L2_400>;
192 operating-points-v2 = <&cpu0_opp_table>;
195 #cooling-cells = <2>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache {
199 cache-level = <2>;
200 cache-unified;
201 next-level-cache = <&L3_0>;
209 clocks = <&cpufreq_hw 0>;
210 enable-method = "psci";
211 power-domains = <&CPU_PD5>;
212 power-domain-names = "psci";
213 capacity-dmips-mhz = <415>;
214 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L2_500>;
216 operating-points-v2 = <&cpu0_opp_table>;
219 #cooling-cells = <2>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache {
223 cache-level = <2>;
224 cache-unified;
225 next-level-cache = <&L3_0>;
233 clocks = <&cpufreq_hw 1>;
234 enable-method = "psci";
235 power-domains = <&CPU_PD6>;
236 power-domain-names = "psci";
237 capacity-dmips-mhz = <1024>;
238 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L2_600>;
240 operating-points-v2 = <&cpu6_opp_table>;
243 #cooling-cells = <2>;
244 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache {
247 cache-level = <2>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
257 clocks = <&cpufreq_hw 1>;
258 enable-method = "psci";
259 power-domains = <&CPU_PD7>;
260 power-domain-names = "psci";
261 capacity-dmips-mhz = <1024>;
262 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L2_700>;
264 operating-points-v2 = <&cpu6_opp_table>;
267 #cooling-cells = <2>;
268 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache {
271 cache-level = <2>;
272 cache-unified;
273 next-level-cache = <&L3_0>;
277 cpu-map {
313 idle_states: idle-states {
314 entry-method = "psci";
316 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = "arm,idle-state";
318 idle-state-name = "little-power-down";
319 arm,psci-suspend-param = <0x40000003>;
320 entry-latency-us = <549>;
321 exit-latency-us = <901>;
322 min-residency-us = <1774>;
323 local-timer-stop;
326 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = "arm,idle-state";
328 idle-state-name = "little-rail-power-down";
329 arm,psci-suspend-param = <0x40000004>;
330 entry-latency-us = <702>;
331 exit-latency-us = <915>;
332 min-residency-us = <4001>;
333 local-timer-stop;
336 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = "arm,idle-state";
338 idle-state-name = "big-power-down";
339 arm,psci-suspend-param = <0x40000003>;
340 entry-latency-us = <523>;
341 exit-latency-us = <1244>;
342 min-residency-us = <2207>;
343 local-timer-stop;
346 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = "arm,idle-state";
348 idle-state-name = "big-rail-power-down";
349 arm,psci-suspend-param = <0x40000004>;
350 entry-latency-us = <526>;
351 exit-latency-us = <1854>;
352 min-residency-us = <5555>;
353 local-timer-stop;
357 domain_idle_states: domain-idle-states {
358 CLUSTER_SLEEP_PC: cluster-sleep-0 {
359 compatible = "domain-idle-state";
360 idle-state-name = "cluster-l3-power-collapse";
361 arm,psci-suspend-param = <0x41000044>;
362 entry-latency-us = <2752>;
363 exit-latency-us = <3048>;
364 min-residency-us = <6118>;
367 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
368 compatible = "domain-idle-state";
369 idle-state-name = "cluster-cx-retention";
370 arm,psci-suspend-param = <0x41001244>;
371 entry-latency-us = <3638>;
372 exit-latency-us = <4562>;
373 min-residency-us = <8467>;
376 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
377 compatible = "domain-idle-state";
378 idle-state-name = "cluster-power-down";
379 arm,psci-suspend-param = <0x4100b244>;
380 entry-latency-us = <3263>;
381 exit-latency-us = <6562>;
382 min-residency-us = <9826>;
389 compatible = "qcom,scm-sc7180", "qcom,scm";
399 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points-v2";
401 opp-shared;
403 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <1200000 4800000>;
408 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <1200000 4800000>;
413 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <1200000 4800000>;
418 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <1804000 8908800>;
423 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <2188000 12902400>;
428 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <2188000 12902400>;
433 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <3072000 15052800>;
438 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <3072000 15052800>;
443 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <3072000 15052800>;
448 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <4068000 22425600>;
454 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points-v2";
456 opp-shared;
458 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <2188000 8908800>;
463 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <2188000 8908800>;
468 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <2188000 8908800>;
473 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <2188000 8908800>;
478 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <2188000 8908800>;
483 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <4068000 12902400>;
488 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <4068000 15052800>;
493 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <6220000 19353600>;
498 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <6220000 19353600>;
503 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <6220000 22425600>;
508 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <6220000 22425600>;
513 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <6220000 22425600>;
518 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <7216000 22425600>;
523 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <7216000 22425600>;
528 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <8532000 23347200>;
533 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <8532000 23347200>;
539 qspi_opp_table: opp-table-qspi {
540 compatible = "operating-points-v2";
542 opp-75000000 {
543 opp-hz = /bits/ 64 <75000000>;
544 required-opps = <&rpmhpd_opp_low_svs>;
547 opp-150000000 {
548 opp-hz = /bits/ 64 <150000000>;
549 required-opps = <&rpmhpd_opp_svs>;
552 opp-300000000 {
553 opp-hz = /bits/ 64 <300000000>;
554 required-opps = <&rpmhpd_opp_nom>;
558 qup_opp_table: opp-table-qup {
559 compatible = "operating-points-v2";
561 opp-75000000 {
562 opp-hz = /bits/ 64 <75000000>;
563 required-opps = <&rpmhpd_opp_low_svs>;
566 opp-100000000 {
567 opp-hz = /bits/ 64 <100000000>;
568 required-opps = <&rpmhpd_opp_svs>;
571 opp-128000000 {
572 opp-hz = /bits/ 64 <128000000>;
573 required-opps = <&rpmhpd_opp_nom>;
578 compatible = "arm,armv8-pmuv3";
583 compatible = "arm,psci-1.0";
587 #power-domain-cells = <0>;
588 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
593 #power-domain-cells = <0>;
594 power-domains = <&CLUSTER_PD>;
595 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
599 #power-domain-cells = <0>;
600 power-domains = <&CLUSTER_PD>;
601 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
605 #power-domain-cells = <0>;
606 power-domains = <&CLUSTER_PD>;
607 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
611 #power-domain-cells = <0>;
612 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
617 #power-domain-cells = <0>;
618 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
623 #power-domain-cells = <0>;
624 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
629 #power-domain-cells = <0>;
630 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
634 CLUSTER_PD: cpu-cluster0 {
635 #power-domain-cells = <0>;
636 domain-idle-states = <&CLUSTER_SLEEP_PC
642 reserved_memory: reserved-memory {
643 #address-cells = <2>;
644 #size-cells = <2>;
649 no-map;
654 no-map;
659 no-map;
664 compatible = "qcom,cmd-db";
665 no-map;
670 no-map;
675 no-map;
680 no-map;
685 no-map;
689 compatible = "qcom,rmtfs-mem";
691 no-map;
693 qcom,client-id = <1>;
700 memory-region = <&smem_mem>;
704 smp2p-cdsp {
712 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>;
715 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells = <1>;
720 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "slave-kernel";
723 interrupt-controller;
724 #interrupt-cells = <2>;
728 smp2p-lpass {
736 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>;
739 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells = <1>;
744 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "slave-kernel";
747 interrupt-controller;
748 #interrupt-cells = <2>;
752 smp2p-mpss {
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>;
760 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells = <1>;
765 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "slave-kernel";
767 interrupt-controller;
768 #interrupt-cells = <2>;
771 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells = <1>;
776 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa";
778 interrupt-controller;
779 #interrupt-cells = <2>;
784 #address-cells = <2>;
785 #size-cells = <2>;
787 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus";
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc-sc7180";
793 clocks = <&rpmhcc RPMH_CXO_CLK>,
796 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>;
798 #reset-cells = <1>;
799 #power-domain-cells = <1>;
800 power-domains = <&rpmhpd SC7180_CX>;
804 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
810 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core";
812 #address-cells = <1>;
813 #size-cells = <1>;
815 qusb2p_hstx_trim: hstx-trim-primary@25b {
820 gpu_speed_bin: gpu-speed-bin@1d2 {
827 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
830 reg-names = "hc", "cqhci";
835 interrupt-names = "hc_irq", "pwr_irq";
837 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
840 clock-names = "iface", "core", "xo";
843 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = <&sdhc1_opp_table>;
847 bus-width = <8>;
848 non-removable;
849 supports-cqe;
851 mmc-ddr-1_8v;
852 mmc-hs200-1_8v;
853 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-strobe;
858 sdhc1_opp_table: opp-table {
859 compatible = "operating-points-v2";
861 opp-100000000 {
862 opp-hz = /bits/ 64 <100000000>;
863 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-peak-kBps = <1800000 600000>;
865 opp-avg-kBps = <100000 0>;
868 opp-384000000 {
869 opp-hz = /bits/ 64 <384000000>;
870 required-opps = <&rpmhpd_opp_nom>;
871 opp-peak-kBps = <5400000 1600000>;
872 opp-avg-kBps = <390000 0>;
878 compatible = "qcom,geni-se-qup";
880 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
883 #address-cells = <2>;
884 #size-cells = <2>;
890 compatible = "qcom,geni-i2c";
892 clock-names = "se";
893 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names = "default";
895 pinctrl-0 = <&qup_i2c0_default>;
897 #address-cells = <1>;
898 #size-cells = <0>;
902 interconnect-names = "qup-core", "qup-config",
903 "qup-memory";
904 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps = <&rpmhpd_opp_low_svs>;
910 compatible = "qcom,geni-spi";
912 clock-names = "se";
913 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names = "default";
915 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
917 #address-cells = <1>;
918 #size-cells = <0>;
919 power-domains = <&rpmhpd SC7180_CX>;
920 operating-points-v2 = <&qup_opp_table>;
923 interconnect-names = "qup-core", "qup-config";
928 compatible = "qcom,geni-uart";
930 clock-names = "se";
931 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names = "default";
933 pinctrl-0 = <&qup_uart0_default>;
935 power-domains = <&rpmhpd SC7180_CX>;
936 operating-points-v2 = <&qup_opp_table>;
939 interconnect-names = "qup-core", "qup-config";
944 compatible = "qcom,geni-i2c";
946 clock-names = "se";
947 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_i2c1_default>;
951 #address-cells = <1>;
952 #size-cells = <0>;
956 interconnect-names = "qup-core", "qup-config",
957 "qup-memory";
958 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps = <&rpmhpd_opp_low_svs>;
964 compatible = "qcom,geni-spi";
966 clock-names = "se";
967 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
971 #address-cells = <1>;
972 #size-cells = <0>;
973 power-domains = <&rpmhpd SC7180_CX>;
974 operating-points-v2 = <&qup_opp_table>;
977 interconnect-names = "qup-core", "qup-config";
982 compatible = "qcom,geni-uart";
984 clock-names = "se";
985 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&qup_uart1_default>;
989 power-domains = <&rpmhpd SC7180_CX>;
990 operating-points-v2 = <&qup_opp_table>;
993 interconnect-names = "qup-core", "qup-config";
998 compatible = "qcom,geni-i2c";
1000 clock-names = "se";
1001 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_i2c2_default>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1010 interconnect-names = "qup-core", "qup-config",
1011 "qup-memory";
1012 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps = <&rpmhpd_opp_low_svs>;
1018 compatible = "qcom,geni-uart";
1020 clock-names = "se";
1021 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_uart2_default>;
1025 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-points-v2 = <&qup_opp_table>;
1029 interconnect-names = "qup-core", "qup-config";
1034 compatible = "qcom,geni-i2c";
1036 clock-names = "se";
1037 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&qup_i2c3_default>;
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1046 interconnect-names = "qup-core", "qup-config",
1047 "qup-memory";
1048 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps = <&rpmhpd_opp_low_svs>;
1054 compatible = "qcom,geni-spi";
1056 clock-names = "se";
1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-points-v2 = <&qup_opp_table>;
1067 interconnect-names = "qup-core", "qup-config";
1072 compatible = "qcom,geni-uart";
1074 clock-names = "se";
1075 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_uart3_default>;
1079 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-points-v2 = <&qup_opp_table>;
1083 interconnect-names = "qup-core", "qup-config";
1088 compatible = "qcom,geni-i2c";
1090 clock-names = "se";
1091 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&qup_i2c4_default>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1100 interconnect-names = "qup-core", "qup-config",
1101 "qup-memory";
1102 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps = <&rpmhpd_opp_low_svs>;
1108 compatible = "qcom,geni-uart";
1110 clock-names = "se";
1111 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&qup_uart4_default>;
1115 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-points-v2 = <&qup_opp_table>;
1119 interconnect-names = "qup-core", "qup-config";
1124 compatible = "qcom,geni-i2c";
1126 clock-names = "se";
1127 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&qup_i2c5_default>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1136 interconnect-names = "qup-core", "qup-config",
1137 "qup-memory";
1138 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps = <&rpmhpd_opp_low_svs>;
1144 compatible = "qcom,geni-spi";
1146 clock-names = "se";
1147 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-points-v2 = <&qup_opp_table>;
1157 interconnect-names = "qup-core", "qup-config";
1162 compatible = "qcom,geni-uart";
1164 clock-names = "se";
1165 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_uart5_default>;
1169 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-points-v2 = <&qup_opp_table>;
1173 interconnect-names = "qup-core", "qup-config";
1179 compatible = "qcom,geni-se-qup";
1181 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1184 #address-cells = <2>;
1185 #size-cells = <2>;
1191 compatible = "qcom,geni-i2c";
1193 clock-names = "se";
1194 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_i2c6_default>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1203 interconnect-names = "qup-core", "qup-config",
1204 "qup-memory";
1205 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps = <&rpmhpd_opp_low_svs>;
1211 compatible = "qcom,geni-spi";
1213 clock-names = "se";
1214 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-points-v2 = <&qup_opp_table>;
1224 interconnect-names = "qup-core", "qup-config";
1229 compatible = "qcom,geni-uart";
1231 clock-names = "se";
1232 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&qup_uart6_default>;
1236 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-points-v2 = <&qup_opp_table>;
1240 interconnect-names = "qup-core", "qup-config";
1245 compatible = "qcom,geni-i2c";
1247 clock-names = "se";
1248 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_i2c7_default>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1257 interconnect-names = "qup-core", "qup-config",
1258 "qup-memory";
1259 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps = <&rpmhpd_opp_low_svs>;
1265 compatible = "qcom,geni-uart";
1267 clock-names = "se";
1268 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&qup_uart7_default>;
1272 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-points-v2 = <&qup_opp_table>;
1276 interconnect-names = "qup-core", "qup-config";
1281 compatible = "qcom,geni-i2c";
1283 clock-names = "se";
1284 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_i2c8_default>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1293 interconnect-names = "qup-core", "qup-config",
1294 "qup-memory";
1295 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps = <&rpmhpd_opp_low_svs>;
1301 compatible = "qcom,geni-spi";
1303 clock-names = "se";
1304 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names = "default";
1306 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-points-v2 = <&qup_opp_table>;
1314 interconnect-names = "qup-core", "qup-config";
1319 compatible = "qcom,geni-debug-uart";
1321 clock-names = "se";
1322 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_uart8_default>;
1326 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-points-v2 = <&qup_opp_table>;
1330 interconnect-names = "qup-core", "qup-config";
1335 compatible = "qcom,geni-i2c";
1337 clock-names = "se";
1338 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c9_default>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1347 interconnect-names = "qup-core", "qup-config",
1348 "qup-memory";
1349 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps = <&rpmhpd_opp_low_svs>;
1355 compatible = "qcom,geni-uart";
1357 clock-names = "se";
1358 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_uart9_default>;
1362 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-points-v2 = <&qup_opp_table>;
1366 interconnect-names = "qup-core", "qup-config";
1371 compatible = "qcom,geni-i2c";
1373 clock-names = "se";
1374 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names = "default";
1376 pinctrl-0 = <&qup_i2c10_default>;
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1383 interconnect-names = "qup-core", "qup-config",
1384 "qup-memory";
1385 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps = <&rpmhpd_opp_low_svs>;
1391 compatible = "qcom,geni-spi";
1393 clock-names = "se";
1394 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names = "default";
1396 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-points-v2 = <&qup_opp_table>;
1404 interconnect-names = "qup-core", "qup-config";
1409 compatible = "qcom,geni-uart";
1411 clock-names = "se";
1412 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&qup_uart10_default>;
1416 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-points-v2 = <&qup_opp_table>;
1420 interconnect-names = "qup-core", "qup-config";
1425 compatible = "qcom,geni-i2c";
1427 clock-names = "se";
1428 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&qup_i2c11_default>;
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1437 interconnect-names = "qup-core", "qup-config",
1438 "qup-memory";
1439 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps = <&rpmhpd_opp_low_svs>;
1445 compatible = "qcom,geni-spi";
1447 clock-names = "se";
1448 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1454 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-points-v2 = <&qup_opp_table>;
1458 interconnect-names = "qup-core", "qup-config";
1463 compatible = "qcom,geni-uart";
1465 clock-names = "se";
1466 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names = "default";
1468 pinctrl-0 = <&qup_uart11_default>;
1470 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-points-v2 = <&qup_opp_table>;
1474 interconnect-names = "qup-core", "qup-config";
1480 compatible = "qcom,sc7180-config-noc";
1482 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&apps_bcm_voter>;
1487 compatible = "qcom,sc7180-system-noc";
1489 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&apps_bcm_voter>;
1494 compatible = "qcom,sc7180-mc-virt";
1496 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&apps_bcm_voter>;
1501 compatible = "qcom,sc7180-qup-virt";
1503 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&apps_bcm_voter>;
1508 compatible = "qcom,sc7180-aggre1-noc";
1510 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&apps_bcm_voter>;
1515 compatible = "qcom,sc7180-aggre2-noc";
1517 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&apps_bcm_voter>;
1522 compatible = "qcom,sc7180-compute-noc";
1524 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&apps_bcm_voter>;
1529 compatible = "qcom,sc7180-mmss-noc";
1531 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&apps_bcm_voter>;
1536 compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
1537 "jedec,ufs-2.0";
1541 phy-names = "ufsphy";
1542 lanes-per-direction = <1>;
1543 #reset-cells = <1>;
1545 reset-names = "rst";
1547 power-domains = <&gcc UFS_PHY_GDSC>;
1551 clock-names = "core_clk",
1558 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1565 freq-table-hz = <50000000 200000000>,
1577 interconnect-names = "ufs-ddr", "cpu-ufs";
1585 compatible = "qcom,sc7180-qmp-ufs-phy";
1587 clocks = <&rpmhcc RPMH_CXO_CLK>,
1590 clock-names = "ref",
1593 power-domains = <&gcc UFS_PHY_GDSC>;
1595 reset-names = "ufsphy";
1596 #phy-cells = <0>;
1601 compatible = "qcom,sc7180-inline-crypto-engine",
1602 "qcom,inline-crypto-engine";
1604 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1608 compatible = "qcom,sc7180-ipa";
1615 reg-names = "ipa-reg",
1616 "ipa-shared",
1619 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1623 interrupt-names = "ipa",
1625 "ipa-clock-query",
1626 "ipa-setup-ready";
1628 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core";
1634 interconnect-names = "memory",
1640 qcom,smem-states = <&ipa_smp2p_out 0>,
1642 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 "ipa-clock-enabled";
1649 compatible = "qcom,tcsr-mutex";
1651 #hwlock-cells = <1>;
1655 compatible = "qcom,sc7180-tcsr", "syscon";
1660 compatible = "qcom,sc7180-tcsr", "syscon";
1665 compatible = "qcom,sc7180-pinctrl";
1669 reg-names = "west", "north", "south";
1671 gpio-controller;
1672 #gpio-cells = <2>;
1673 interrupt-controller;
1674 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc>;
1678 dp_hot_plug_det: dp-hot-plug-det-state {
1683 qspi_clk: qspi-clk-state {
1688 qspi_cs0: qspi-cs0-state {
1693 qspi_cs1: qspi-cs1-state {
1698 qspi_data0: qspi-data0-state {
1703 qspi_data1: qspi-data1-state {
1708 qspi_data23: qspi-data23-state {
1713 qup_i2c0_default: qup-i2c0-default-state {
1718 qup_i2c1_default: qup-i2c1-default-state {
1723 qup_i2c2_default: qup-i2c2-default-state {
1728 qup_i2c3_default: qup-i2c3-default-state {
1733 qup_i2c4_default: qup-i2c4-default-state {
1738 qup_i2c5_default: qup-i2c5-default-state {
1743 qup_i2c6_default: qup-i2c6-default-state {
1748 qup_i2c7_default: qup-i2c7-default-state {
1753 qup_i2c8_default: qup-i2c8-default-state {
1758 qup_i2c9_default: qup-i2c9-default-state {
1763 qup_i2c10_default: qup-i2c10-default-state {
1768 qup_i2c11_default: qup-i2c11-default-state {
1773 qup_spi0_spi: qup-spi0-spi-state {
1778 qup_spi0_cs: qup-spi0-cs-state {
1783 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1788 qup_spi1_spi: qup-spi1-spi-state {
1793 qup_spi1_cs: qup-spi1-cs-state {
1798 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1803 qup_spi3_spi: qup-spi3-spi-state {
1808 qup_spi3_cs: qup-spi3-cs-state {
1813 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1818 qup_spi5_spi: qup-spi5-spi-state {
1823 qup_spi5_cs: qup-spi5-cs-state {
1828 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1833 qup_spi6_spi: qup-spi6-spi-state {
1838 qup_spi6_cs: qup-spi6-cs-state {
1843 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1848 qup_spi8_spi: qup-spi8-spi-state {
1853 qup_spi8_cs: qup-spi8-cs-state {
1858 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1863 qup_spi10_spi: qup-spi10-spi-state {
1868 qup_spi10_cs: qup-spi10-cs-state {
1873 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1878 qup_spi11_spi: qup-spi11-spi-state {
1883 qup_spi11_cs: qup-spi11-cs-state {
1888 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1893 qup_uart0_default: qup-uart0-default-state {
1894 qup_uart0_cts: cts-pins {
1899 qup_uart0_rts: rts-pins {
1904 qup_uart0_tx: tx-pins {
1909 qup_uart0_rx: rx-pins {
1915 qup_uart1_default: qup-uart1-default-state {
1916 qup_uart1_cts: cts-pins {
1921 qup_uart1_rts: rts-pins {
1926 qup_uart1_tx: tx-pins {
1931 qup_uart1_rx: rx-pins {
1937 qup_uart2_default: qup-uart2-default-state {
1938 qup_uart2_tx: tx-pins {
1943 qup_uart2_rx: rx-pins {
1949 qup_uart3_default: qup-uart3-default-state {
1950 qup_uart3_cts: cts-pins {
1955 qup_uart3_rts: rts-pins {
1960 qup_uart3_tx: tx-pins {
1965 qup_uart3_rx: rx-pins {
1971 qup_uart4_default: qup-uart4-default-state {
1972 qup_uart4_tx: tx-pins {
1977 qup_uart4_rx: rx-pins {
1983 qup_uart5_default: qup-uart5-default-state {
1984 qup_uart5_cts: cts-pins {
1989 qup_uart5_rts: rts-pins {
1994 qup_uart5_tx: tx-pins {
1999 qup_uart5_rx: rx-pins {
2005 qup_uart6_default: qup-uart6-default-state {
2006 qup_uart6_cts: cts-pins {
2011 qup_uart6_rts: rts-pins {
2016 qup_uart6_tx: tx-pins {
2021 qup_uart6_rx: rx-pins {
2027 qup_uart7_default: qup-uart7-default-state {
2028 qup_uart7_tx: tx-pins {
2033 qup_uart7_rx: rx-pins {
2039 qup_uart8_default: qup-uart8-default-state {
2040 qup_uart8_tx: tx-pins {
2045 qup_uart8_rx: rx-pins {
2051 qup_uart9_default: qup-uart9-default-state {
2052 qup_uart9_tx: tx-pins {
2057 qup_uart9_rx: rx-pins {
2063 qup_uart10_default: qup-uart10-default-state {
2064 qup_uart10_cts: cts-pins {
2069 qup_uart10_rts: rts-pins {
2074 qup_uart10_tx: tx-pins {
2079 qup_uart10_rx: rx-pins {
2085 qup_uart11_default: qup-uart11-default-state {
2086 qup_uart11_cts: cts-pins {
2091 qup_uart11_rts: rts-pins {
2096 qup_uart11_tx: tx-pins {
2101 qup_uart11_rx: rx-pins {
2107 sec_mi2s_active: sec-mi2s-active-state {
2112 pri_mi2s_active: pri-mi2s-active-state {
2117 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2122 ter_mi2s_active: ter-mi2s-active-state {
2129 compatible = "qcom,sc7180-mpss-pas";
2132 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2138 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "stop-ack", "shutdown-ack";
2141 clocks = <&rpmhcc RPMH_CXO_CLK>;
2142 clock-names = "xo";
2144 power-domains = <&rpmhpd SC7180_CX>,
2147 power-domain-names = "cx", "mx", "mss";
2149 memory-region = <&mpss_mem>;
2153 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names = "stop";
2158 glink-edge {
2161 qcom,remote-pid = <1>;
2167 compatible = "qcom,adreno-618.0", "qcom,adreno";
2170 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2173 operating-points-v2 = <&gpu_opp_table>;
2176 #cooling-cells = <2>;
2178 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "speed_bin";
2182 interconnect-names = "gfx-mem";
2184 gpu_opp_table: opp-table {
2185 compatible = "operating-points-v2";
2187 opp-825000000 {
2188 opp-hz = /bits/ 64 <825000000>;
2189 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-peak-kBps = <8532000>;
2191 opp-supported-hw = <0x04>;
2194 opp-800000000 {
2195 opp-hz = /bits/ 64 <800000000>;
2196 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-peak-kBps = <8532000>;
2198 opp-supported-hw = <0x07>;
2201 opp-650000000 {
2202 opp-hz = /bits/ 64 <650000000>;
2203 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-peak-kBps = <7216000>;
2205 opp-supported-hw = <0x07>;
2208 opp-565000000 {
2209 opp-hz = /bits/ 64 <565000000>;
2210 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-peak-kBps = <5412000>;
2212 opp-supported-hw = <0x07>;
2215 opp-430000000 {
2216 opp-hz = /bits/ 64 <430000000>;
2217 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-peak-kBps = <5412000>;
2219 opp-supported-hw = <0x07>;
2222 opp-355000000 {
2223 opp-hz = /bits/ 64 <355000000>;
2224 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-peak-kBps = <3072000>;
2226 opp-supported-hw = <0x07>;
2229 opp-267000000 {
2230 opp-hz = /bits/ 64 <267000000>;
2231 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-peak-kBps = <3072000>;
2233 opp-supported-hw = <0x07>;
2236 opp-180000000 {
2237 opp-hz = /bits/ 64 <180000000>;
2238 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-peak-kBps = <1804000>;
2240 opp-supported-hw = <0x07>;
2246 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2248 #iommu-cells = <1>;
2249 #global-interrupts = <2>;
2261 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2263 clock-names = "bus", "iface";
2265 power-domains = <&gpucc CX_GDSC>;
2269 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2272 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2275 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2280 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = "cx", "gx";
2284 operating-points-v2 = <&gmu_opp_table>;
2286 gmu_opp_table: opp-table {
2287 compatible = "operating-points-v2";
2289 opp-200000000 {
2290 opp-hz = /bits/ 64 <200000000>;
2291 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2296 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc7180-gpucc";
2299 clocks = <&rpmhcc RPMH_CXO_CLK>,
2302 clock-names = "bi_tcxo",
2305 #clock-cells = <1>;
2306 #reset-cells = <1>;
2307 #power-domain-cells = <1>;
2311 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2318 compatible = "arm,coresight-stm", "arm,primecell";
2321 reg-names = "stm-base", "stm-stimulus-base";
2323 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pclk";
2326 out-ports {
2329 remote-endpoint = <&funnel0_in7>;
2336 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2339 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pclk";
2342 out-ports {
2345 remote-endpoint = <&merge_funnel_in0>;
2350 in-ports {
2351 #address-cells = <1>;
2352 #size-cells = <0>;
2357 remote-endpoint = <&stm_out>;
2364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2367 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pclk";
2370 out-ports {
2373 remote-endpoint = <&merge_funnel_in1>;
2378 in-ports {
2379 #address-cells = <1>;
2380 #size-cells = <0>;
2385 remote-endpoint = <&apss_merge_funnel_out>;
2392 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2395 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pclk";
2398 out-ports {
2401 remote-endpoint = <&swao_funnel_in>;
2406 in-ports {
2407 #address-cells = <1>;
2408 #size-cells = <0>;
2413 remote-endpoint = <&funnel0_out>;
2420 remote-endpoint = <&funnel1_out>;
2427 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2430 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pclk";
2433 out-ports {
2436 remote-endpoint = <&etr_in>;
2441 in-ports {
2444 remote-endpoint = <&swao_replicator_out>;
2451 compatible = "arm,coresight-tmc", "arm,primecell";
2455 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pclk";
2457 arm,scatter-gather;
2459 in-ports {
2462 remote-endpoint = <&replicator_out>;
2469 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2472 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pclk";
2475 out-ports {
2478 remote-endpoint = <&etf_in>;
2483 in-ports {
2484 #address-cells = <1>;
2485 #size-cells = <0>;
2490 remote-endpoint = <&merge_funnel_out>;
2497 compatible = "arm,coresight-tmc", "arm,primecell";
2500 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pclk";
2503 out-ports {
2506 remote-endpoint = <&swao_replicator_in>;
2511 in-ports {
2514 remote-endpoint = <&swao_funnel_out>;
2521 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2524 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pclk";
2526 qcom,replicator-loses-context;
2528 out-ports {
2531 remote-endpoint = <&replicator_in>;
2536 in-ports {
2539 remote-endpoint = <&etf_out>;
2546 compatible = "arm,coresight-etm4x", "arm,primecell";
2551 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pclk";
2553 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up;
2556 out-ports {
2559 remote-endpoint = <&apss_funnel_in0>;
2566 compatible = "arm,coresight-etm4x", "arm,primecell";
2571 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pclk";
2573 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up;
2576 out-ports {
2579 remote-endpoint = <&apss_funnel_in1>;
2586 compatible = "arm,coresight-etm4x", "arm,primecell";
2591 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pclk";
2593 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up;
2596 out-ports {
2599 remote-endpoint = <&apss_funnel_in2>;
2606 compatible = "arm,coresight-etm4x", "arm,primecell";
2611 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pclk";
2613 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up;
2616 out-ports {
2619 remote-endpoint = <&apss_funnel_in3>;
2626 compatible = "arm,coresight-etm4x", "arm,primecell";
2631 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pclk";
2633 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up;
2636 out-ports {
2639 remote-endpoint = <&apss_funnel_in4>;
2646 compatible = "arm,coresight-etm4x", "arm,primecell";
2651 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pclk";
2653 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up;
2656 out-ports {
2659 remote-endpoint = <&apss_funnel_in5>;
2666 compatible = "arm,coresight-etm4x", "arm,primecell";
2671 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pclk";
2673 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up;
2676 out-ports {
2679 remote-endpoint = <&apss_funnel_in6>;
2686 compatible = "arm,coresight-etm4x", "arm,primecell";
2691 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pclk";
2693 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up;
2696 out-ports {
2699 remote-endpoint = <&apss_funnel_in7>;
2706 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2709 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pclk";
2712 out-ports {
2715 remote-endpoint = <&apss_merge_funnel_in>;
2720 in-ports {
2721 #address-cells = <1>;
2722 #size-cells = <0>;
2727 remote-endpoint = <&etm0_out>;
2734 remote-endpoint = <&etm1_out>;
2741 remote-endpoint = <&etm2_out>;
2748 remote-endpoint = <&etm3_out>;
2755 remote-endpoint = <&etm4_out>;
2762 remote-endpoint = <&etm5_out>;
2769 remote-endpoint = <&etm6_out>;
2776 remote-endpoint = <&etm7_out>;
2783 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2786 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pclk";
2789 out-ports {
2792 remote-endpoint = <&funnel1_in4>;
2797 in-ports {
2800 remote-endpoint = <&apss_funnel_out>;
2807 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2813 interrupt-names = "hc_irq", "pwr_irq";
2815 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2818 clock-names = "iface", "core", "xo";
2822 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = <&sdhc2_opp_table>;
2826 bus-width = <4>;
2830 sdhc2_opp_table: opp-table {
2831 compatible = "operating-points-v2";
2833 opp-100000000 {
2834 opp-hz = /bits/ 64 <100000000>;
2835 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-peak-kBps = <1800000 600000>;
2837 opp-avg-kBps = <100000 0>;
2840 opp-202000000 {
2841 opp-hz = /bits/ 64 <202000000>;
2842 required-opps = <&rpmhpd_opp_nom>;
2843 opp-peak-kBps = <5400000 1600000>;
2844 opp-avg-kBps = <200000 0>;
2850 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2853 #address-cells = <1>;
2854 #size-cells = <0>;
2856 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2858 clock-names = "iface", "core";
2861 interconnect-names = "qspi-config";
2862 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = <&qspi_opp_table>;
2868 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2871 #phy-cells = <0>;
2872 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2874 clock-names = "cfg_ahb", "ref";
2877 nvmem-cells = <&qusb2p_hstx_trim>;
2881 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2885 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2890 clock-names = "aux",
2898 reset-names = "phy", "common";
2900 #clock-cells = <1>;
2901 #phy-cells = <1>;
2905 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2911 operating-points-v2 = <&cpu_bwmon_opp_table>;
2913 cpu_bwmon_opp_table: opp-table {
2914 compatible = "operating-points-v2";
2916 opp-0 {
2917 opp-peak-kBps = <2288000>;
2920 opp-1 {
2921 opp-peak-kBps = <4577000>;
2924 opp-2 {
2925 opp-peak-kBps = <7110000>;
2928 opp-3 {
2929 opp-peak-kBps = <9155000>;
2932 opp-4 {
2933 opp-peak-kBps = <12298000>;
2936 opp-5 {
2937 opp-peak-kBps = <14236000>;
2943 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2949 operating-points-v2 = <&llcc_bwmon_opp_table>;
2951 llcc_bwmon_opp_table: opp-table {
2952 compatible = "operating-points-v2";
2954 opp-0 {
2955 opp-peak-kBps = <1144000>;
2958 opp-1 {
2959 opp-peak-kBps = <1720000>;
2962 opp-2 {
2963 opp-peak-kBps = <2086000>;
2966 opp-3 {
2967 opp-peak-kBps = <2929000>;
2970 opp-4 {
2971 opp-peak-kBps = <3879000>;
2974 opp-5 {
2975 opp-peak-kBps = <5931000>;
2978 opp-6 {
2979 opp-peak-kBps = <6881000>;
2982 opp-7 {
2983 opp-peak-kBps = <8137000>;
2989 compatible = "qcom,sc7180-dc-noc";
2991 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&apps_bcm_voter>;
2995 system-cache-controller@9200000 {
2996 compatible = "qcom,sc7180-llcc";
2998 reg-names = "llcc0_base", "llcc_broadcast_base";
3003 compatible = "qcom,sc7180-gem-noc";
3005 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&apps_bcm_voter>;
3010 compatible = "qcom,sc7180-npu-noc";
3012 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&apps_bcm_voter>;
3017 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3020 #address-cells = <2>;
3021 #size-cells = <2>;
3023 dma-ranges;
3025 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3030 clock-names = "cfg_noc",
3036 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3038 assigned-clock-rates = <19200000>, <150000000>;
3040 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3045 interrupt-names = "pwr_event",
3051 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpmhpd_opp_nom>;
3058 interconnect-names = "usb-ddr", "apps-usb";
3060 wakeup-source;
3069 snps,parkmode-disable-ss-quirk;
3071 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed = "super-speed";
3076 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc7180-venus";
3080 power-domains = <&videocc VENUS_GDSC>,
3083 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3090 clock-names = "core", "iface", "bus",
3093 memory-region = <&venus_mem>;
3096 interconnect-names = "video-mem", "cpu-cfg";
3098 video-decoder {
3099 compatible = "venus-decoder";
3102 video-encoder {
3103 compatible = "venus-encoder";
3106 venus_opp_table: opp-table {
3107 compatible = "operating-points-v2";
3109 opp-150000000 {
3110 opp-hz = /bits/ 64 <150000000>;
3111 required-opps = <&rpmhpd_opp_low_svs>;
3114 opp-270000000 {
3115 opp-hz = /bits/ 64 <270000000>;
3116 required-opps = <&rpmhpd_opp_svs>;
3119 opp-340000000 {
3120 opp-hz = /bits/ 64 <340000000>;
3121 required-opps = <&rpmhpd_opp_svs_l1>;
3124 opp-434000000 {
3125 opp-hz = /bits/ 64 <434000000>;
3126 required-opps = <&rpmhpd_opp_nom>;
3129 opp-500000097 {
3130 opp-hz = /bits/ 64 <500000097>;
3131 required-opps = <&rpmhpd_opp_turbo>;
3136 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc7180-videocc";
3139 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcxo";
3141 #clock-cells = <1>;
3142 #reset-cells = <1>;
3143 #power-domain-cells = <1>;
3147 compatible = "qcom,sc7180-camnoc-virt";
3149 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&apps_bcm_voter>;
3153 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc7180-camcc";
3156 clocks = <&rpmhcc RPMH_CXO_CLK>,
3159 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>;
3161 #reset-cells = <1>;
3162 #power-domain-cells = <1>;
3165 mdss: display-subsystem@ae00000 {
3166 compatible = "qcom,sc7180-mdss";
3168 reg-names = "mdss";
3170 power-domains = <&dispcc MDSS_GDSC>;
3172 clocks = <&gcc GCC_DISP_AHB_CLK>,
3175 clock-names = "iface", "ahb", "core";
3178 interrupt-controller;
3179 #interrupt-cells = <1>;
3185 interconnect-names = "mdp0-mem",
3186 "cpu-cfg";
3190 #address-cells = <2>;
3191 #size-cells = <2>;
3196 mdp: display-controller@ae01000 {
3197 compatible = "qcom,sc7180-dpu";
3200 reg-names = "mdp", "vbif";
3202 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3208 clock-names = "bus", "iface", "rot", "lut", "core",
3210 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3213 assigned-clock-rates = <19200000>,
3216 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains = <&rpmhpd SC7180_CX>;
3219 interrupt-parent = <&mdss>;
3223 #address-cells = <1>;
3224 #size-cells = <0>;
3229 remote-endpoint = <&mdss_dsi0_in>;
3236 remote-endpoint = <&dp_in>;
3241 mdp_opp_table: opp-table {
3242 compatible = "operating-points-v2";
3244 opp-200000000 {
3245 opp-hz = /bits/ 64 <200000000>;
3246 required-opps = <&rpmhpd_opp_low_svs>;
3249 opp-300000000 {
3250 opp-hz = /bits/ 64 <300000000>;
3251 required-opps = <&rpmhpd_opp_svs>;
3254 opp-345000000 {
3255 opp-hz = /bits/ 64 <345000000>;
3256 required-opps = <&rpmhpd_opp_svs_l1>;
3259 opp-460000000 {
3260 opp-hz = /bits/ 64 <460000000>;
3261 required-opps = <&rpmhpd_opp_nom>;
3267 compatible = "qcom,sc7180-dsi-ctrl",
3268 "qcom,mdss-dsi-ctrl";
3270 reg-names = "dsi_ctrl";
3272 interrupt-parent = <&mdss>;
3275 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3281 clock-names = "byte",
3288 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3291 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains = <&rpmhpd SC7180_CX>;
3296 #address-cells = <1>;
3297 #size-cells = <0>;
3302 #address-cells = <1>;
3303 #size-cells = <0>;
3308 remote-endpoint = <&dpu_intf1_out>;
3319 dsi_opp_table: opp-table {
3320 compatible = "operating-points-v2";
3322 opp-187500000 {
3323 opp-hz = /bits/ 64 <187500000>;
3324 required-opps = <&rpmhpd_opp_low_svs>;
3327 opp-300000000 {
3328 opp-hz = /bits/ 64 <300000000>;
3329 required-opps = <&rpmhpd_opp_svs>;
3332 opp-358000000 {
3333 opp-hz = /bits/ 64 <358000000>;
3334 required-opps = <&rpmhpd_opp_svs_l1>;
3340 compatible = "qcom,dsi-phy-10nm";
3344 reg-names = "dsi_phy",
3348 #clock-cells = <1>;
3349 #phy-cells = <0>;
3351 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 clock-names = "iface", "ref";
3358 mdss_dp: displayport-controller@ae90000 {
3359 compatible = "qcom,sc7180-dp";
3368 interrupt-parent = <&mdss>;
3371 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3376 clock-names = "core_iface", "core_aux", "ctrl_link",
3378 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3380 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3383 phy-names = "dp";
3385 operating-points-v2 = <&dp_opp_table>;
3386 power-domains = <&rpmhpd SC7180_CX>;
3388 #sound-dai-cells = <0>;
3391 #address-cells = <1>;
3392 #size-cells = <0>;
3396 remote-endpoint = <&dpu_intf0_out>;
3406 dp_opp_table: opp-table {
3407 compatible = "operating-points-v2";
3409 opp-160000000 {
3410 opp-hz = /bits/ 64 <160000000>;
3411 required-opps = <&rpmhpd_opp_low_svs>;
3414 opp-270000000 {
3415 opp-hz = /bits/ 64 <270000000>;
3416 required-opps = <&rpmhpd_opp_svs>;
3419 opp-540000000 {
3420 opp-hz = /bits/ 64 <540000000>;
3421 required-opps = <&rpmhpd_opp_svs_l1>;
3424 opp-810000000 {
3425 opp-hz = /bits/ 64 <810000000>;
3426 required-opps = <&rpmhpd_opp_nom>;
3432 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc7180-dispcc";
3435 clocks = <&rpmhcc RPMH_CXO_CLK>,
3441 clock-names = "bi_tcxo",
3447 #clock-cells = <1>;
3448 #reset-cells = <1>;
3449 #power-domain-cells = <1>;
3452 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3455 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2>;
3457 interrupt-parent = <&intc>;
3458 interrupt-controller;
3461 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3464 #reset-cells = <1>;
3467 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3474 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells = <1>;
3478 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3485 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells = <1>;
3489 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3492 #reset-cells = <1>;
3495 aoss_qmp: power-management@c300000 {
3496 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3501 #clock-cells = <0>;
3505 compatible = "qcom,rpmh-stats";
3510 compatible = "qcom,spmi-pmic-arb";
3516 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "periph_irq";
3518 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3521 #address-cells = <2>;
3522 #size-cells = <0>;
3523 interrupt-controller;
3524 #interrupt-cells = <4>;
3528 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3531 #address-cells = <1>;
3532 #size-cells = <1>;
3536 pil-reloc@94c {
3537 compatible = "qcom,pil-reloc-info";
3543 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3545 #iommu-cells = <2>;
3546 #global-interrupts = <1>;
3630 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic-v3";
3632 #address-cells = <2>;
3633 #size-cells = <2>;
3635 #interrupt-cells = <3>;
3636 interrupt-controller;
3641 msi-controller@17a40000 {
3642 compatible = "arm,gic-v3-its";
3643 msi-controller;
3644 #msi-cells = <1>;
3651 compatible = "qcom,sc7180-apss-shared",
3652 "qcom,sdm845-apss-shared";
3654 #mbox-cells = <1>;
3658 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3660 clocks = <&sleep_clk>;
3665 #address-cells = <1>;
3666 #size-cells = <1>;
3668 compatible = "arm,armv7-timer-mem";
3672 frame-number = <0>;
3680 frame-number = <1>;
3687 frame-number = <2>;
3694 frame-number = <3>;
3701 frame-number = <4>;
3708 frame-number = <5>;
3715 frame-number = <6>;
3723 compatible = "qcom,rpmh-rsc";
3727 reg-names = "drv-0", "drv-1", "drv-2";
3731 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>;
3733 qcom,tcs-config = <ACTIVE_TCS 2>,
3737 power-domains = <&CLUSTER_PD>;
3739 rpmhcc: clock-controller {
3740 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo_board>;
3742 clock-names = "xo";
3743 #clock-cells = <1>;
3746 rpmhpd: power-controller {
3747 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain-cells = <1>;
3749 operating-points-v2 = <&rpmhpd_opp_table>;
3751 rpmhpd_opp_table: opp-table {
3752 compatible = "operating-points-v2";
3755 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3759 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3763 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3767 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3771 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3775 opp-level = <224>;
3779 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3800 apps_bcm_voter: bcm-voter {
3801 compatible = "qcom,bcm-voter";
3806 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3809 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", "alternate";
3812 #interconnect-cells = <1>;
3816 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3818 reg-names = "freq-domain0", "freq-domain1";
3820 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", "alternate";
3823 #freq-domain-cells = <1>;
3824 #clock-cells = <1>;
3828 compatible = "qcom,wcn3990-wifi";
3830 reg-names = "membase";
3845 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm;
3851 compatible = "qcom,sc7180-adsp-pas";
3854 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3859 interrupt-names = "wdog",
3863 "stop-ack";
3865 clocks = <&rpmhcc RPMH_CXO_CLK>;
3866 clock-names = "xo";
3868 power-domains = <&rpmhpd SC7180_LCX>,
3870 power-domain-names = "lcx", "lmx";
3873 qcom,smem-states = <&adsp_smp2p_out 0>;
3874 qcom,smem-state-names = "stop";
3878 glink-edge {
3881 qcom,remote-pid = <2>;
3885 compatible = "qcom,apr-v2";
3886 qcom,glink-channels = "apr_audio_svc";
3888 #address-cells = <1>;
3889 #size-cells = <0>;
3894 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3897 q6afe: service@4 { label
3898 compatible = "qcom,q6afe";
3900 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3903 compatible = "qcom,q6afe-dais";
3904 #address-cells = <1>;
3905 #size-cells = <0>;
3906 #sound-dai-cells = <1>;
3909 q6afecc: clock-controller {
3910 compatible = "qcom,q6afe-clocks";
3911 #clock-cells = <2>;
3918 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3921 compatible = "qcom,q6asm-dais";
3922 #address-cells = <1>;
3923 #size-cells = <0>;
3924 #sound-dai-cells = <1>;
3932 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3935 compatible = "qcom,q6adm-routing";
3936 #sound-dai-cells = <0>;
3943 qcom,glink-channels = "fastrpcglink-apps-dsp";
3945 #address-cells = <1>;
3946 #size-cells = <0>;
3948 compute-cb@3 {
3949 compatible = "qcom,fastrpc-compute-cb";
3954 compute-cb@4 {
3955 compatible = "qcom,fastrpc-compute-cb";
3960 compute-cb@5 {
3961 compatible = "qcom,fastrpc-compute-cb";
3970 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc7180-lpasscorecc";
3974 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3977 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>;
3980 #power-domain-cells = <1>;
3986 compatible = "qcom,sc7180-lpass-cpu";
3989 reg-names = "lpass-hdmiif", "lpass-lpaif";
3995 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpmhpd_opp_nom>;
4000 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4007 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk0", "pcnoc-mport-clk",
4009 "mi2s-bit-clk0", "mi2s-bit-clk1";
4012 #sound-dai-cells = <1>;
4013 #address-cells = <1>;
4014 #size-cells = <0>;
4018 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4021 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc7180-lpasshm";
4024 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4026 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpmhpd SC7180_CX>;
4029 #clock-cells = <1>;
4030 #power-domain-cells = <1>;
4036 thermal-zones {
4037 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive = <250>;
4040 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = <1052>;
4044 cpu0_alert0: trip-point0 {
4050 cpu0_alert1: trip-point1 {
4056 cpu0_crit: cpu-crit {
4063 cooling-maps {
4066 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4075 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4085 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive = <250>;
4088 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = <1052>;
4092 cpu1_alert0: trip-point0 {
4098 cpu1_alert1: trip-point1 {
4104 cpu1_crit: cpu-crit {
4111 cooling-maps {
4114 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4123 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4133 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive = <250>;
4136 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = <1052>;
4140 cpu2_alert0: trip-point0 {
4146 cpu2_alert1: trip-point1 {
4152 cpu2_crit: cpu-crit {
4159 cooling-maps {
4162 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4171 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4181 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive = <250>;
4184 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = <1052>;
4188 cpu3_alert0: trip-point0 {
4194 cpu3_alert1: trip-point1 {
4200 cpu3_crit: cpu-crit {
4207 cooling-maps {
4210 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4219 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4229 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive = <250>;
4232 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = <1052>;
4236 cpu4_alert0: trip-point0 {
4242 cpu4_alert1: trip-point1 {
4248 cpu4_crit: cpu-crit {
4255 cooling-maps {
4258 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4267 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4277 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive = <250>;
4280 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = <1052>;
4284 cpu5_alert0: trip-point0 {
4290 cpu5_alert1: trip-point1 {
4296 cpu5_crit: cpu-crit {
4303 cooling-maps {
4306 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4315 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4325 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive = <250>;
4328 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = <1425>;
4332 cpu6_alert0: trip-point0 {
4338 cpu6_alert1: trip-point1 {
4344 cpu6_crit: cpu-crit {
4351 cooling-maps {
4354 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4359 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4365 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive = <250>;
4368 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = <1425>;
4372 cpu7_alert0: trip-point0 {
4378 cpu7_alert1: trip-point1 {
4384 cpu7_crit: cpu-crit {
4391 cooling-maps {
4394 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4399 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4405 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive = <250>;
4408 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = <1425>;
4412 cpu8_alert0: trip-point0 {
4418 cpu8_alert1: trip-point1 {
4424 cpu8_crit: cpu-crit {
4431 cooling-maps {
4434 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4439 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4445 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive = <250>;
4448 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = <1425>;
4452 cpu9_alert0: trip-point0 {
4458 cpu9_alert1: trip-point1 {
4464 cpu9_crit: cpu-crit {
4471 cooling-maps {
4474 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4479 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4485 aoss0-thermal {
4486 polling-delay-passive = <250>;
4488 thermal-sensors = <&tsens0 0>;
4491 aoss0_alert0: trip-point0 {
4497 aoss0_crit: aoss0-crit {
4505 cpuss0-thermal {
4506 polling-delay-passive = <250>;
4508 thermal-sensors = <&tsens0 7>;
4511 cpuss0_alert0: trip-point0 {
4516 cpuss0_crit: cluster0-crit {
4524 cpuss1-thermal {
4525 polling-delay-passive = <250>;
4527 thermal-sensors = <&tsens0 8>;
4530 cpuss1_alert0: trip-point0 {
4535 cpuss1_crit: cluster0-crit {
4543 gpuss0-thermal {
4544 polling-delay-passive = <250>;
4546 thermal-sensors = <&tsens0 13>;
4549 gpuss0_alert0: trip-point0 {
4555 gpuss0_crit: gpuss0-crit {
4562 cooling-maps {
4565 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4570 gpuss1-thermal {
4571 polling-delay-passive = <250>;
4573 thermal-sensors = <&tsens0 14>;
4576 gpuss1_alert0: trip-point0 {
4582 gpuss1_crit: gpuss1-crit {
4589 cooling-maps {
4592 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4597 aoss1-thermal {
4598 polling-delay-passive = <250>;
4600 thermal-sensors = <&tsens1 0>;
4603 aoss1_alert0: trip-point0 {
4609 aoss1_crit: aoss1-crit {
4617 cwlan-thermal {
4618 polling-delay-passive = <250>;
4620 thermal-sensors = <&tsens1 1>;
4623 cwlan_alert0: trip-point0 {
4629 cwlan_crit: cwlan-crit {
4637 audio-thermal {
4638 polling-delay-passive = <250>;
4640 thermal-sensors = <&tsens1 2>;
4643 audio_alert0: trip-point0 {
4649 audio_crit: audio-crit {
4657 ddr-thermal {
4658 polling-delay-passive = <250>;
4660 thermal-sensors = <&tsens1 3>;
4663 ddr_alert0: trip-point0 {
4669 ddr_crit: ddr-crit {
4677 q6-hvx-thermal {
4678 polling-delay-passive = <250>;
4680 thermal-sensors = <&tsens1 4>;
4683 q6_hvx_alert0: trip-point0 {
4689 q6_hvx_crit: q6-hvx-crit {
4697 camera-thermal {
4698 polling-delay-passive = <250>;
4700 thermal-sensors = <&tsens1 5>;
4703 camera_alert0: trip-point0 {
4709 camera_crit: camera-crit {
4717 mdm-core-thermal {
4718 polling-delay-passive = <250>;
4720 thermal-sensors = <&tsens1 6>;
4723 mdm_alert0: trip-point0 {
4729 mdm_crit: mdm-crit {
4737 mdm-dsp-thermal {
4738 polling-delay-passive = <250>;
4740 thermal-sensors = <&tsens1 7>;
4743 mdm_dsp_alert0: trip-point0 {
4749 mdm_dsp_crit: mdm-dsp-crit {
4757 npu-thermal {
4758 polling-delay-passive = <250>;
4760 thermal-sensors = <&tsens1 8>;
4763 npu_alert0: trip-point0 {
4769 npu_crit: npu-crit {
4777 video-thermal {
4778 polling-delay-passive = <250>;
4780 thermal-sensors = <&tsens1 9>;
4783 video_alert0: trip-point0 {
4789 video_crit: video-crit {
4799 compatible = "arm,armv8-timer";