Lines Matching +full:pdc +full:- +full:intc
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sc7180.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/phy/phy-qcom-qusb2.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
24 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/soc/qcom,apr.h>
27 #include <dt-bindings/sound/qcom,q6afe.h>
28 #include <dt-bindings/thermal/thermal.h>
31 interrupt-parent = <&intc>;
33 #address-cells = <2>;
34 #size-cells = <2>;
64 xo_board: xo-board {
65 compatible = "fixed-clock";
66 clock-frequency = <38400000>;
67 #clock-cells = <0>;
70 sleep_clk: sleep-clk {
71 compatible = "fixed-clock";
72 clock-frequency = <32764>;
73 #clock-cells = <0>;
78 #address-cells = <2>;
79 #size-cells = <0>;
86 enable-method = "psci";
87 power-domains = <&cpu_pd0>;
88 power-domain-names = "psci";
89 capacity-dmips-mhz = <415>;
90 dynamic-power-coefficient = <137>;
91 operating-points-v2 = <&cpu0_opp_table>;
94 next-level-cache = <&l2_0>;
95 #cooling-cells = <2>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 l2_0: l2-cache {
99 cache-level = <2>;
100 cache-unified;
101 next-level-cache = <&l3_0>;
102 l3_0: l3-cache {
104 cache-level = <3>;
105 cache-unified;
115 enable-method = "psci";
116 power-domains = <&cpu_pd1>;
117 power-domain-names = "psci";
118 capacity-dmips-mhz = <415>;
119 dynamic-power-coefficient = <137>;
120 next-level-cache = <&l2_100>;
121 operating-points-v2 = <&cpu0_opp_table>;
124 #cooling-cells = <2>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 l2_100: l2-cache {
128 cache-level = <2>;
129 cache-unified;
130 next-level-cache = <&l3_0>;
139 enable-method = "psci";
140 power-domains = <&cpu_pd2>;
141 power-domain-names = "psci";
142 capacity-dmips-mhz = <415>;
143 dynamic-power-coefficient = <137>;
144 next-level-cache = <&l2_200>;
145 operating-points-v2 = <&cpu0_opp_table>;
148 #cooling-cells = <2>;
149 qcom,freq-domain = <&cpufreq_hw 0>;
150 l2_200: l2-cache {
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_0>;
163 enable-method = "psci";
164 power-domains = <&cpu_pd3>;
165 power-domain-names = "psci";
166 capacity-dmips-mhz = <415>;
167 dynamic-power-coefficient = <137>;
168 next-level-cache = <&l2_300>;
169 operating-points-v2 = <&cpu0_opp_table>;
172 #cooling-cells = <2>;
173 qcom,freq-domain = <&cpufreq_hw 0>;
174 l2_300: l2-cache {
176 cache-level = <2>;
177 cache-unified;
178 next-level-cache = <&l3_0>;
187 enable-method = "psci";
188 power-domains = <&cpu_pd4>;
189 power-domain-names = "psci";
190 capacity-dmips-mhz = <415>;
191 dynamic-power-coefficient = <137>;
192 next-level-cache = <&l2_400>;
193 operating-points-v2 = <&cpu0_opp_table>;
196 #cooling-cells = <2>;
197 qcom,freq-domain = <&cpufreq_hw 0>;
198 l2_400: l2-cache {
200 cache-level = <2>;
201 cache-unified;
202 next-level-cache = <&l3_0>;
211 enable-method = "psci";
212 power-domains = <&cpu_pd5>;
213 power-domain-names = "psci";
214 capacity-dmips-mhz = <415>;
215 dynamic-power-coefficient = <137>;
216 next-level-cache = <&l2_500>;
217 operating-points-v2 = <&cpu0_opp_table>;
220 #cooling-cells = <2>;
221 qcom,freq-domain = <&cpufreq_hw 0>;
222 l2_500: l2-cache {
224 cache-level = <2>;
225 cache-unified;
226 next-level-cache = <&l3_0>;
235 enable-method = "psci";
236 power-domains = <&cpu_pd6>;
237 power-domain-names = "psci";
238 capacity-dmips-mhz = <1024>;
239 dynamic-power-coefficient = <480>;
240 next-level-cache = <&l2_600>;
241 operating-points-v2 = <&cpu6_opp_table>;
244 #cooling-cells = <2>;
245 qcom,freq-domain = <&cpufreq_hw 1>;
246 l2_600: l2-cache {
248 cache-level = <2>;
249 cache-unified;
250 next-level-cache = <&l3_0>;
259 enable-method = "psci";
260 power-domains = <&cpu_pd7>;
261 power-domain-names = "psci";
262 capacity-dmips-mhz = <1024>;
263 dynamic-power-coefficient = <480>;
264 next-level-cache = <&l2_700>;
265 operating-points-v2 = <&cpu6_opp_table>;
268 #cooling-cells = <2>;
269 qcom,freq-domain = <&cpufreq_hw 1>;
270 l2_700: l2-cache {
272 cache-level = <2>;
273 cache-unified;
274 next-level-cache = <&l3_0>;
278 cpu-map {
314 idle_states: idle-states {
315 entry-method = "psci";
317 little_cpu_sleep_0: cpu-sleep-0-0 {
318 compatible = "arm,idle-state";
319 idle-state-name = "little-power-down";
320 arm,psci-suspend-param = <0x40000003>;
321 entry-latency-us = <549>;
322 exit-latency-us = <901>;
323 min-residency-us = <1774>;
324 local-timer-stop;
327 little_cpu_sleep_1: cpu-sleep-0-1 {
328 compatible = "arm,idle-state";
329 idle-state-name = "little-rail-power-down";
330 arm,psci-suspend-param = <0x40000004>;
331 entry-latency-us = <702>;
332 exit-latency-us = <915>;
333 min-residency-us = <4001>;
334 local-timer-stop;
337 big_cpu_sleep_0: cpu-sleep-1-0 {
338 compatible = "arm,idle-state";
339 idle-state-name = "big-power-down";
340 arm,psci-suspend-param = <0x40000003>;
341 entry-latency-us = <523>;
342 exit-latency-us = <1244>;
343 min-residency-us = <2207>;
344 local-timer-stop;
347 big_cpu_sleep_1: cpu-sleep-1-1 {
348 compatible = "arm,idle-state";
349 idle-state-name = "big-rail-power-down";
350 arm,psci-suspend-param = <0x40000004>;
351 entry-latency-us = <526>;
352 exit-latency-us = <1854>;
353 min-residency-us = <5555>;
354 local-timer-stop;
358 domain_idle_states: domain-idle-states {
359 cluster_sleep_pc: cluster-sleep-0 {
360 compatible = "domain-idle-state";
361 arm,psci-suspend-param = <0x41000044>;
362 entry-latency-us = <2752>;
363 exit-latency-us = <3048>;
364 min-residency-us = <6118>;
367 cluster_sleep_cx_ret: cluster-sleep-1 {
368 compatible = "domain-idle-state";
369 arm,psci-suspend-param = <0x41001244>;
370 entry-latency-us = <3638>;
371 exit-latency-us = <4562>;
372 min-residency-us = <8467>;
375 cluster_aoss_sleep: cluster-sleep-2 {
376 compatible = "domain-idle-state";
377 arm,psci-suspend-param = <0x4100b244>;
378 entry-latency-us = <3263>;
379 exit-latency-us = <6562>;
380 min-residency-us = <9826>;
387 compatible = "qcom,scm-sc7180", "qcom,scm";
397 cpu0_opp_table: opp-table-cpu0 {
398 compatible = "operating-points-v2";
399 opp-shared;
401 cpu0_opp1: opp-300000000 {
402 opp-hz = /bits/ 64 <300000000>;
403 opp-peak-kBps = <1200000 4800000>;
406 cpu0_opp2: opp-576000000 {
407 opp-hz = /bits/ 64 <576000000>;
408 opp-peak-kBps = <1200000 4800000>;
411 cpu0_opp3: opp-768000000 {
412 opp-hz = /bits/ 64 <768000000>;
413 opp-peak-kBps = <1200000 4800000>;
416 cpu0_opp4: opp-1017600000 {
417 opp-hz = /bits/ 64 <1017600000>;
418 opp-peak-kBps = <1804000 8908800>;
421 cpu0_opp5: opp-1248000000 {
422 opp-hz = /bits/ 64 <1248000000>;
423 opp-peak-kBps = <2188000 12902400>;
426 cpu0_opp6: opp-1324800000 {
427 opp-hz = /bits/ 64 <1324800000>;
428 opp-peak-kBps = <2188000 12902400>;
431 cpu0_opp7: opp-1516800000 {
432 opp-hz = /bits/ 64 <1516800000>;
433 opp-peak-kBps = <3072000 15052800>;
436 cpu0_opp8: opp-1612800000 {
437 opp-hz = /bits/ 64 <1612800000>;
438 opp-peak-kBps = <3072000 15052800>;
441 cpu0_opp9: opp-1708800000 {
442 opp-hz = /bits/ 64 <1708800000>;
443 opp-peak-kBps = <3072000 15052800>;
446 cpu0_opp10: opp-1804800000 {
447 opp-hz = /bits/ 64 <1804800000>;
448 opp-peak-kBps = <4068000 22425600>;
452 cpu6_opp_table: opp-table-cpu6 {
453 compatible = "operating-points-v2";
454 opp-shared;
456 cpu6_opp1: opp-300000000 {
457 opp-hz = /bits/ 64 <300000000>;
458 opp-peak-kBps = <2188000 8908800>;
461 cpu6_opp2: opp-652800000 {
462 opp-hz = /bits/ 64 <652800000>;
463 opp-peak-kBps = <2188000 8908800>;
466 cpu6_opp3: opp-825600000 {
467 opp-hz = /bits/ 64 <825600000>;
468 opp-peak-kBps = <2188000 8908800>;
471 cpu6_opp4: opp-979200000 {
472 opp-hz = /bits/ 64 <979200000>;
473 opp-peak-kBps = <2188000 8908800>;
476 cpu6_opp5: opp-1113600000 {
477 opp-hz = /bits/ 64 <1113600000>;
478 opp-peak-kBps = <2188000 8908800>;
481 cpu6_opp6: opp-1267200000 {
482 opp-hz = /bits/ 64 <1267200000>;
483 opp-peak-kBps = <4068000 12902400>;
486 cpu6_opp7: opp-1555200000 {
487 opp-hz = /bits/ 64 <1555200000>;
488 opp-peak-kBps = <4068000 15052800>;
491 cpu6_opp8: opp-1708800000 {
492 opp-hz = /bits/ 64 <1708800000>;
493 opp-peak-kBps = <6220000 19353600>;
496 cpu6_opp9: opp-1843200000 {
497 opp-hz = /bits/ 64 <1843200000>;
498 opp-peak-kBps = <6220000 19353600>;
501 cpu6_opp10: opp-1900800000 {
502 opp-hz = /bits/ 64 <1900800000>;
503 opp-peak-kBps = <6220000 22425600>;
506 cpu6_opp11: opp-1996800000 {
507 opp-hz = /bits/ 64 <1996800000>;
508 opp-peak-kBps = <6220000 22425600>;
511 cpu6_opp12: opp-2112000000 {
512 opp-hz = /bits/ 64 <2112000000>;
513 opp-peak-kBps = <6220000 22425600>;
516 cpu6_opp13: opp-2208000000 {
517 opp-hz = /bits/ 64 <2208000000>;
518 opp-peak-kBps = <7216000 22425600>;
521 cpu6_opp14: opp-2323200000 {
522 opp-hz = /bits/ 64 <2323200000>;
523 opp-peak-kBps = <7216000 22425600>;
526 cpu6_opp15: opp-2400000000 {
527 opp-hz = /bits/ 64 <2400000000>;
528 opp-peak-kBps = <8532000 23347200>;
531 cpu6_opp16: opp-2553600000 {
532 opp-hz = /bits/ 64 <2553600000>;
533 opp-peak-kBps = <8532000 23347200>;
537 qspi_opp_table: opp-table-qspi {
538 compatible = "operating-points-v2";
540 opp-75000000 {
541 opp-hz = /bits/ 64 <75000000>;
542 required-opps = <&rpmhpd_opp_low_svs>;
545 opp-150000000 {
546 opp-hz = /bits/ 64 <150000000>;
547 required-opps = <&rpmhpd_opp_svs>;
550 opp-300000000 {
551 opp-hz = /bits/ 64 <300000000>;
552 required-opps = <&rpmhpd_opp_nom>;
556 qup_opp_table: opp-table-qup {
557 compatible = "operating-points-v2";
559 opp-75000000 {
560 opp-hz = /bits/ 64 <75000000>;
561 required-opps = <&rpmhpd_opp_low_svs>;
564 opp-100000000 {
565 opp-hz = /bits/ 64 <100000000>;
566 required-opps = <&rpmhpd_opp_svs>;
569 opp-128000000 {
570 opp-hz = /bits/ 64 <128000000>;
571 required-opps = <&rpmhpd_opp_nom>;
576 compatible = "arm,armv8-pmuv3";
581 compatible = "arm,psci-1.0";
584 cpu_pd0: power-domain-cpu0 {
585 #power-domain-cells = <0>;
586 power-domains = <&cluster_pd>;
587 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
590 cpu_pd1: power-domain-cpu1 {
591 #power-domain-cells = <0>;
592 power-domains = <&cluster_pd>;
593 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
596 cpu_pd2: power-domain-cpu2 {
597 #power-domain-cells = <0>;
598 power-domains = <&cluster_pd>;
599 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
602 cpu_pd3: power-domain-cpu3 {
603 #power-domain-cells = <0>;
604 power-domains = <&cluster_pd>;
605 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
608 cpu_pd4: power-domain-cpu4 {
609 #power-domain-cells = <0>;
610 power-domains = <&cluster_pd>;
611 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
614 cpu_pd5: power-domain-cpu5 {
615 #power-domain-cells = <0>;
616 power-domains = <&cluster_pd>;
617 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
620 cpu_pd6: power-domain-cpu6 {
621 #power-domain-cells = <0>;
622 power-domains = <&cluster_pd>;
623 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
626 cpu_pd7: power-domain-cpu7 {
627 #power-domain-cells = <0>;
628 power-domains = <&cluster_pd>;
629 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
632 cluster_pd: power-domain-cluster {
633 #power-domain-cells = <0>;
634 domain-idle-states = <&cluster_sleep_pc
640 reserved_memory: reserved-memory {
641 #address-cells = <2>;
642 #size-cells = <2>;
647 no-map;
652 no-map;
657 no-map;
662 compatible = "qcom,cmd-db";
663 no-map;
668 no-map;
673 no-map;
678 no-map;
683 no-map;
687 compatible = "qcom,rmtfs-mem";
689 no-map;
691 qcom,client-id = <1>;
698 memory-region = <&smem_mem>;
702 smp2p-cdsp {
710 qcom,local-pid = <0>;
711 qcom,remote-pid = <5>;
713 cdsp_smp2p_out: master-kernel {
714 qcom,entry-name = "master-kernel";
715 #qcom,smem-state-cells = <1>;
718 cdsp_smp2p_in: slave-kernel {
719 qcom,entry-name = "slave-kernel";
721 interrupt-controller;
722 #interrupt-cells = <2>;
726 smp2p-lpass {
734 qcom,local-pid = <0>;
735 qcom,remote-pid = <2>;
737 adsp_smp2p_out: master-kernel {
738 qcom,entry-name = "master-kernel";
739 #qcom,smem-state-cells = <1>;
742 adsp_smp2p_in: slave-kernel {
743 qcom,entry-name = "slave-kernel";
745 interrupt-controller;
746 #interrupt-cells = <2>;
750 smp2p-mpss {
755 qcom,local-pid = <0>;
756 qcom,remote-pid = <1>;
758 modem_smp2p_out: master-kernel {
759 qcom,entry-name = "master-kernel";
760 #qcom,smem-state-cells = <1>;
763 modem_smp2p_in: slave-kernel {
764 qcom,entry-name = "slave-kernel";
765 interrupt-controller;
766 #interrupt-cells = <2>;
769 ipa_smp2p_out: ipa-ap-to-modem {
770 qcom,entry-name = "ipa";
771 #qcom,smem-state-cells = <1>;
774 ipa_smp2p_in: ipa-modem-to-ap {
775 qcom,entry-name = "ipa";
776 interrupt-controller;
777 #interrupt-cells = <2>;
782 #address-cells = <2>;
783 #size-cells = <2>;
785 dma-ranges = <0 0 0 0 0x10 0>;
786 compatible = "simple-bus";
788 gcc: clock-controller@100000 {
789 compatible = "qcom,gcc-sc7180";
794 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
795 #clock-cells = <1>;
796 #reset-cells = <1>;
797 #power-domain-cells = <1>;
798 power-domains = <&rpmhpd SC7180_CX>;
802 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
809 clock-names = "core";
810 #address-cells = <1>;
811 #size-cells = <1>;
813 qusb2p_hstx_trim: hstx-trim-primary@25b {
818 gpu_speed_bin: gpu-speed-bin@1d2 {
825 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg-names = "hc", "cqhci";
833 interrupt-names = "hc_irq", "pwr_irq";
838 clock-names = "iface", "core", "xo";
841 interconnect-names = "sdhc-ddr","cpu-sdhc";
842 power-domains = <&rpmhpd SC7180_CX>;
843 operating-points-v2 = <&sdhc1_opp_table>;
845 bus-width = <8>;
846 non-removable;
847 supports-cqe;
849 mmc-ddr-1_8v;
850 mmc-hs200-1_8v;
851 mmc-hs400-1_8v;
852 mmc-hs400-enhanced-strobe;
856 sdhc1_opp_table: opp-table {
857 compatible = "operating-points-v2";
859 opp-100000000 {
860 opp-hz = /bits/ 64 <100000000>;
861 required-opps = <&rpmhpd_opp_low_svs>;
862 opp-peak-kBps = <1800000 600000>;
863 opp-avg-kBps = <100000 0>;
866 opp-384000000 {
867 opp-hz = /bits/ 64 <384000000>;
868 required-opps = <&rpmhpd_opp_nom>;
869 opp-peak-kBps = <5400000 1600000>;
870 opp-avg-kBps = <390000 0>;
876 compatible = "qcom,geni-se-qup";
878 clock-names = "m-ahb", "s-ahb";
881 #address-cells = <2>;
882 #size-cells = <2>;
888 compatible = "qcom,geni-i2c";
890 clock-names = "se";
892 pinctrl-names = "default";
893 pinctrl-0 = <&qup_i2c0_default>;
895 #address-cells = <1>;
896 #size-cells = <0>;
900 interconnect-names = "qup-core", "qup-config",
901 "qup-memory";
902 power-domains = <&rpmhpd SC7180_CX>;
903 required-opps = <&rpmhpd_opp_low_svs>;
908 compatible = "qcom,geni-spi";
910 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
915 #address-cells = <1>;
916 #size-cells = <0>;
917 power-domains = <&rpmhpd SC7180_CX>;
918 operating-points-v2 = <&qup_opp_table>;
921 interconnect-names = "qup-core", "qup-config";
926 compatible = "qcom,geni-uart";
928 clock-names = "se";
930 pinctrl-names = "default";
931 pinctrl-0 = <&qup_uart0_default>;
933 power-domains = <&rpmhpd SC7180_CX>;
934 operating-points-v2 = <&qup_opp_table>;
937 interconnect-names = "qup-core", "qup-config";
942 compatible = "qcom,geni-i2c";
944 clock-names = "se";
946 pinctrl-names = "default";
947 pinctrl-0 = <&qup_i2c1_default>;
949 #address-cells = <1>;
950 #size-cells = <0>;
954 interconnect-names = "qup-core", "qup-config",
955 "qup-memory";
956 power-domains = <&rpmhpd SC7180_CX>;
957 required-opps = <&rpmhpd_opp_low_svs>;
962 compatible = "qcom,geni-spi";
964 clock-names = "se";
966 pinctrl-names = "default";
967 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
969 #address-cells = <1>;
970 #size-cells = <0>;
971 power-domains = <&rpmhpd SC7180_CX>;
972 operating-points-v2 = <&qup_opp_table>;
975 interconnect-names = "qup-core", "qup-config";
980 compatible = "qcom,geni-uart";
982 clock-names = "se";
984 pinctrl-names = "default";
985 pinctrl-0 = <&qup_uart1_default>;
987 power-domains = <&rpmhpd SC7180_CX>;
988 operating-points-v2 = <&qup_opp_table>;
991 interconnect-names = "qup-core", "qup-config";
996 compatible = "qcom,geni-i2c";
998 clock-names = "se";
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&qup_i2c2_default>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1008 interconnect-names = "qup-core", "qup-config",
1009 "qup-memory";
1010 power-domains = <&rpmhpd SC7180_CX>;
1011 required-opps = <&rpmhpd_opp_low_svs>;
1016 compatible = "qcom,geni-uart";
1018 clock-names = "se";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_uart2_default>;
1023 power-domains = <&rpmhpd SC7180_CX>;
1024 operating-points-v2 = <&qup_opp_table>;
1027 interconnect-names = "qup-core", "qup-config";
1032 compatible = "qcom,geni-i2c";
1034 clock-names = "se";
1036 pinctrl-names = "default";
1037 pinctrl-0 = <&qup_i2c3_default>;
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1044 interconnect-names = "qup-core", "qup-config",
1045 "qup-memory";
1046 power-domains = <&rpmhpd SC7180_CX>;
1047 required-opps = <&rpmhpd_opp_low_svs>;
1052 compatible = "qcom,geni-spi";
1054 clock-names = "se";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 power-domains = <&rpmhpd SC7180_CX>;
1062 operating-points-v2 = <&qup_opp_table>;
1065 interconnect-names = "qup-core", "qup-config";
1070 compatible = "qcom,geni-uart";
1072 clock-names = "se";
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&qup_uart3_default>;
1077 power-domains = <&rpmhpd SC7180_CX>;
1078 operating-points-v2 = <&qup_opp_table>;
1081 interconnect-names = "qup-core", "qup-config";
1086 compatible = "qcom,geni-i2c";
1088 clock-names = "se";
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&qup_i2c4_default>;
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1098 interconnect-names = "qup-core", "qup-config",
1099 "qup-memory";
1100 power-domains = <&rpmhpd SC7180_CX>;
1101 required-opps = <&rpmhpd_opp_low_svs>;
1106 compatible = "qcom,geni-uart";
1108 clock-names = "se";
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&qup_uart4_default>;
1113 power-domains = <&rpmhpd SC7180_CX>;
1114 operating-points-v2 = <&qup_opp_table>;
1117 interconnect-names = "qup-core", "qup-config";
1122 compatible = "qcom,geni-i2c";
1124 clock-names = "se";
1126 pinctrl-names = "default";
1127 pinctrl-0 = <&qup_i2c5_default>;
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1134 interconnect-names = "qup-core", "qup-config",
1135 "qup-memory";
1136 power-domains = <&rpmhpd SC7180_CX>;
1137 required-opps = <&rpmhpd_opp_low_svs>;
1142 compatible = "qcom,geni-spi";
1144 clock-names = "se";
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 power-domains = <&rpmhpd SC7180_CX>;
1152 operating-points-v2 = <&qup_opp_table>;
1155 interconnect-names = "qup-core", "qup-config";
1160 compatible = "qcom,geni-uart";
1162 clock-names = "se";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_uart5_default>;
1167 power-domains = <&rpmhpd SC7180_CX>;
1168 operating-points-v2 = <&qup_opp_table>;
1171 interconnect-names = "qup-core", "qup-config";
1177 compatible = "qcom,geni-se-qup";
1179 clock-names = "m-ahb", "s-ahb";
1182 #address-cells = <2>;
1183 #size-cells = <2>;
1189 compatible = "qcom,geni-i2c";
1191 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_i2c6_default>;
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1201 interconnect-names = "qup-core", "qup-config",
1202 "qup-memory";
1203 power-domains = <&rpmhpd SC7180_CX>;
1204 required-opps = <&rpmhpd_opp_low_svs>;
1209 compatible = "qcom,geni-spi";
1211 clock-names = "se";
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 power-domains = <&rpmhpd SC7180_CX>;
1219 operating-points-v2 = <&qup_opp_table>;
1222 interconnect-names = "qup-core", "qup-config";
1227 compatible = "qcom,geni-uart";
1229 clock-names = "se";
1231 pinctrl-names = "default";
1232 pinctrl-0 = <&qup_uart6_default>;
1234 power-domains = <&rpmhpd SC7180_CX>;
1235 operating-points-v2 = <&qup_opp_table>;
1238 interconnect-names = "qup-core", "qup-config";
1243 compatible = "qcom,geni-i2c";
1245 clock-names = "se";
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&qup_i2c7_default>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1255 interconnect-names = "qup-core", "qup-config",
1256 "qup-memory";
1257 power-domains = <&rpmhpd SC7180_CX>;
1258 required-opps = <&rpmhpd_opp_low_svs>;
1263 compatible = "qcom,geni-uart";
1265 clock-names = "se";
1267 pinctrl-names = "default";
1268 pinctrl-0 = <&qup_uart7_default>;
1270 power-domains = <&rpmhpd SC7180_CX>;
1271 operating-points-v2 = <&qup_opp_table>;
1274 interconnect-names = "qup-core", "qup-config";
1279 compatible = "qcom,geni-i2c";
1281 clock-names = "se";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&qup_i2c8_default>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1291 interconnect-names = "qup-core", "qup-config",
1292 "qup-memory";
1293 power-domains = <&rpmhpd SC7180_CX>;
1294 required-opps = <&rpmhpd_opp_low_svs>;
1299 compatible = "qcom,geni-spi";
1301 clock-names = "se";
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308 power-domains = <&rpmhpd SC7180_CX>;
1309 operating-points-v2 = <&qup_opp_table>;
1312 interconnect-names = "qup-core", "qup-config";
1317 compatible = "qcom,geni-debug-uart";
1319 clock-names = "se";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_uart8_default>;
1324 power-domains = <&rpmhpd SC7180_CX>;
1325 operating-points-v2 = <&qup_opp_table>;
1328 interconnect-names = "qup-core", "qup-config";
1333 compatible = "qcom,geni-i2c";
1335 clock-names = "se";
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&qup_i2c9_default>;
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1345 interconnect-names = "qup-core", "qup-config",
1346 "qup-memory";
1347 power-domains = <&rpmhpd SC7180_CX>;
1348 required-opps = <&rpmhpd_opp_low_svs>;
1353 compatible = "qcom,geni-uart";
1355 clock-names = "se";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_uart9_default>;
1360 power-domains = <&rpmhpd SC7180_CX>;
1361 operating-points-v2 = <&qup_opp_table>;
1364 interconnect-names = "qup-core", "qup-config";
1369 compatible = "qcom,geni-i2c";
1371 clock-names = "se";
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&qup_i2c10_default>;
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1381 interconnect-names = "qup-core", "qup-config",
1382 "qup-memory";
1383 power-domains = <&rpmhpd SC7180_CX>;
1384 required-opps = <&rpmhpd_opp_low_svs>;
1389 compatible = "qcom,geni-spi";
1391 clock-names = "se";
1393 pinctrl-names = "default";
1394 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1398 power-domains = <&rpmhpd SC7180_CX>;
1399 operating-points-v2 = <&qup_opp_table>;
1402 interconnect-names = "qup-core", "qup-config";
1407 compatible = "qcom,geni-uart";
1409 clock-names = "se";
1411 pinctrl-names = "default";
1412 pinctrl-0 = <&qup_uart10_default>;
1414 power-domains = <&rpmhpd SC7180_CX>;
1415 operating-points-v2 = <&qup_opp_table>;
1418 interconnect-names = "qup-core", "qup-config";
1423 compatible = "qcom,geni-i2c";
1425 clock-names = "se";
1427 pinctrl-names = "default";
1428 pinctrl-0 = <&qup_i2c11_default>;
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1435 interconnect-names = "qup-core", "qup-config",
1436 "qup-memory";
1437 power-domains = <&rpmhpd SC7180_CX>;
1438 required-opps = <&rpmhpd_opp_low_svs>;
1443 compatible = "qcom,geni-spi";
1445 clock-names = "se";
1447 pinctrl-names = "default";
1448 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1452 power-domains = <&rpmhpd SC7180_CX>;
1453 operating-points-v2 = <&qup_opp_table>;
1456 interconnect-names = "qup-core", "qup-config";
1461 compatible = "qcom,geni-uart";
1463 clock-names = "se";
1465 pinctrl-names = "default";
1466 pinctrl-0 = <&qup_uart11_default>;
1468 power-domains = <&rpmhpd SC7180_CX>;
1469 operating-points-v2 = <&qup_opp_table>;
1472 interconnect-names = "qup-core", "qup-config";
1478 compatible = "qcom,sc7180-refgen-regulator",
1479 "qcom,sdm845-refgen-regulator";
1484 compatible = "qcom,sc7180-config-noc";
1486 #interconnect-cells = <2>;
1487 qcom,bcm-voters = <&apps_bcm_voter>;
1491 compatible = "qcom,sc7180-system-noc";
1493 #interconnect-cells = <2>;
1494 qcom,bcm-voters = <&apps_bcm_voter>;
1498 compatible = "qcom,sc7180-mc-virt";
1500 #interconnect-cells = <2>;
1501 qcom,bcm-voters = <&apps_bcm_voter>;
1505 compatible = "qcom,sc7180-qup-virt";
1507 #interconnect-cells = <2>;
1508 qcom,bcm-voters = <&apps_bcm_voter>;
1512 compatible = "qcom,sc7180-aggre1-noc";
1514 #interconnect-cells = <2>;
1515 qcom,bcm-voters = <&apps_bcm_voter>;
1519 compatible = "qcom,sc7180-aggre2-noc";
1521 #interconnect-cells = <2>;
1522 qcom,bcm-voters = <&apps_bcm_voter>;
1526 compatible = "qcom,sc7180-compute-noc";
1528 #interconnect-cells = <2>;
1529 qcom,bcm-voters = <&apps_bcm_voter>;
1533 compatible = "qcom,sc7180-mmss-noc";
1535 #interconnect-cells = <2>;
1536 qcom,bcm-voters = <&apps_bcm_voter>;
1540 compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
1541 "jedec,ufs-2.0";
1545 phy-names = "ufsphy";
1546 lanes-per-direction = <1>;
1547 #reset-cells = <1>;
1549 reset-names = "rst";
1551 power-domains = <&gcc UFS_PHY_GDSC>;
1555 clock-names = "core_clk",
1569 freq-table-hz = <50000000 200000000>,
1581 interconnect-names = "ufs-ddr", "cpu-ufs";
1589 compatible = "qcom,sc7180-qmp-ufs-phy";
1594 clock-names = "ref",
1597 power-domains = <&gcc UFS_PHY_GDSC>;
1599 reset-names = "ufsphy";
1600 #phy-cells = <0>;
1605 compatible = "qcom,sc7180-inline-crypto-engine",
1606 "qcom,inline-crypto-engine";
1612 compatible = "qcom,sc7180-ipa";
1619 reg-names = "ipa-reg",
1620 "ipa-shared",
1623 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1624 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1627 interrupt-names = "ipa",
1629 "ipa-clock-query",
1630 "ipa-setup-ready";
1633 clock-names = "core";
1638 interconnect-names = "memory",
1644 qcom,smem-states = <&ipa_smp2p_out 0>,
1646 qcom,smem-state-names = "ipa-clock-enabled-valid",
1647 "ipa-clock-enabled";
1653 compatible = "qcom,tcsr-mutex";
1655 #hwlock-cells = <1>;
1659 compatible = "qcom,sc7180-tcsr", "syscon";
1664 compatible = "qcom,sc7180-tcsr", "syscon";
1669 compatible = "qcom,sc7180-pinctrl";
1673 reg-names = "west", "north", "south";
1675 gpio-controller;
1676 #gpio-cells = <2>;
1677 interrupt-controller;
1678 #interrupt-cells = <2>;
1679 gpio-ranges = <&tlmm 0 0 120>;
1680 wakeup-parent = <&pdc>;
1682 dp_hot_plug_det: dp-hot-plug-det-state {
1687 qspi_clk: qspi-clk-state {
1692 qspi_cs0: qspi-cs0-state {
1697 qspi_cs1: qspi-cs1-state {
1702 qspi_data0: qspi-data0-state {
1707 qspi_data1: qspi-data1-state {
1712 qspi_data23: qspi-data23-state {
1717 qup_i2c0_default: qup-i2c0-default-state {
1722 qup_i2c1_default: qup-i2c1-default-state {
1727 qup_i2c2_default: qup-i2c2-default-state {
1732 qup_i2c3_default: qup-i2c3-default-state {
1737 qup_i2c4_default: qup-i2c4-default-state {
1742 qup_i2c5_default: qup-i2c5-default-state {
1747 qup_i2c6_default: qup-i2c6-default-state {
1752 qup_i2c7_default: qup-i2c7-default-state {
1757 qup_i2c8_default: qup-i2c8-default-state {
1762 qup_i2c9_default: qup-i2c9-default-state {
1767 qup_i2c10_default: qup-i2c10-default-state {
1772 qup_i2c11_default: qup-i2c11-default-state {
1777 qup_spi0_spi: qup-spi0-spi-state {
1782 qup_spi0_cs: qup-spi0-cs-state {
1787 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1792 qup_spi1_spi: qup-spi1-spi-state {
1797 qup_spi1_cs: qup-spi1-cs-state {
1802 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1807 qup_spi3_spi: qup-spi3-spi-state {
1812 qup_spi3_cs: qup-spi3-cs-state {
1817 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1822 qup_spi5_spi: qup-spi5-spi-state {
1827 qup_spi5_cs: qup-spi5-cs-state {
1832 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1837 qup_spi6_spi: qup-spi6-spi-state {
1842 qup_spi6_cs: qup-spi6-cs-state {
1847 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1852 qup_spi8_spi: qup-spi8-spi-state {
1857 qup_spi8_cs: qup-spi8-cs-state {
1862 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1867 qup_spi10_spi: qup-spi10-spi-state {
1872 qup_spi10_cs: qup-spi10-cs-state {
1877 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1882 qup_spi11_spi: qup-spi11-spi-state {
1887 qup_spi11_cs: qup-spi11-cs-state {
1892 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1897 qup_uart0_default: qup-uart0-default-state {
1898 qup_uart0_cts: cts-pins {
1903 qup_uart0_rts: rts-pins {
1908 qup_uart0_tx: tx-pins {
1913 qup_uart0_rx: rx-pins {
1919 qup_uart1_default: qup-uart1-default-state {
1920 qup_uart1_cts: cts-pins {
1925 qup_uart1_rts: rts-pins {
1930 qup_uart1_tx: tx-pins {
1935 qup_uart1_rx: rx-pins {
1941 qup_uart2_default: qup-uart2-default-state {
1942 qup_uart2_tx: tx-pins {
1947 qup_uart2_rx: rx-pins {
1953 qup_uart3_default: qup-uart3-default-state {
1954 qup_uart3_cts: cts-pins {
1959 qup_uart3_rts: rts-pins {
1964 qup_uart3_tx: tx-pins {
1969 qup_uart3_rx: rx-pins {
1975 qup_uart4_default: qup-uart4-default-state {
1976 qup_uart4_tx: tx-pins {
1981 qup_uart4_rx: rx-pins {
1987 qup_uart5_default: qup-uart5-default-state {
1988 qup_uart5_cts: cts-pins {
1993 qup_uart5_rts: rts-pins {
1998 qup_uart5_tx: tx-pins {
2003 qup_uart5_rx: rx-pins {
2009 qup_uart6_default: qup-uart6-default-state {
2010 qup_uart6_cts: cts-pins {
2015 qup_uart6_rts: rts-pins {
2020 qup_uart6_tx: tx-pins {
2025 qup_uart6_rx: rx-pins {
2031 qup_uart7_default: qup-uart7-default-state {
2032 qup_uart7_tx: tx-pins {
2037 qup_uart7_rx: rx-pins {
2043 qup_uart8_default: qup-uart8-default-state {
2044 qup_uart8_tx: tx-pins {
2049 qup_uart8_rx: rx-pins {
2055 qup_uart9_default: qup-uart9-default-state {
2056 qup_uart9_tx: tx-pins {
2061 qup_uart9_rx: rx-pins {
2067 qup_uart10_default: qup-uart10-default-state {
2068 qup_uart10_cts: cts-pins {
2073 qup_uart10_rts: rts-pins {
2078 qup_uart10_tx: tx-pins {
2083 qup_uart10_rx: rx-pins {
2089 qup_uart11_default: qup-uart11-default-state {
2090 qup_uart11_cts: cts-pins {
2095 qup_uart11_rts: rts-pins {
2100 qup_uart11_tx: tx-pins {
2105 qup_uart11_rx: rx-pins {
2111 sec_mi2s_active: sec-mi2s-active-state {
2116 pri_mi2s_active: pri-mi2s-active-state {
2121 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2126 ter_mi2s_active: ter-mi2s-active-state {
2133 compatible = "qcom,sc7180-mpss-pas";
2136 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2142 interrupt-names = "wdog", "fatal", "ready", "handover",
2143 "stop-ack", "shutdown-ack";
2146 clock-names = "xo";
2148 power-domains = <&rpmhpd SC7180_CX>,
2151 power-domain-names = "cx", "mx", "mss";
2153 memory-region = <&mpss_mem>;
2157 qcom,smem-states = <&modem_smp2p_out 0>;
2158 qcom,smem-state-names = "stop";
2162 glink-edge {
2165 qcom,remote-pid = <1>;
2171 compatible = "qcom,adreno-618.0", "qcom,adreno";
2174 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2177 operating-points-v2 = <&gpu_opp_table>;
2180 #cooling-cells = <2>;
2182 nvmem-cells = <&gpu_speed_bin>;
2183 nvmem-cell-names = "speed_bin";
2186 interconnect-names = "gfx-mem";
2188 gpu_zap_shader: zap-shader {
2189 memory-region = <&gpu_mem>;
2192 gpu_opp_table: opp-table {
2193 compatible = "operating-points-v2";
2195 opp-825000000 {
2196 opp-hz = /bits/ 64 <825000000>;
2197 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2198 opp-peak-kBps = <8532000>;
2199 opp-supported-hw = <0x04>;
2202 opp-800000000 {
2203 opp-hz = /bits/ 64 <800000000>;
2204 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2205 opp-peak-kBps = <8532000>;
2206 opp-supported-hw = <0x07>;
2209 opp-650000000 {
2210 opp-hz = /bits/ 64 <650000000>;
2211 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2212 opp-peak-kBps = <7216000>;
2213 opp-supported-hw = <0x07>;
2216 opp-565000000 {
2217 opp-hz = /bits/ 64 <565000000>;
2218 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2219 opp-peak-kBps = <5412000>;
2220 opp-supported-hw = <0x07>;
2223 opp-430000000 {
2224 opp-hz = /bits/ 64 <430000000>;
2225 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2226 opp-peak-kBps = <5412000>;
2227 opp-supported-hw = <0x07>;
2230 opp-355000000 {
2231 opp-hz = /bits/ 64 <355000000>;
2232 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2233 opp-peak-kBps = <3072000>;
2234 opp-supported-hw = <0x07>;
2237 opp-267000000 {
2238 opp-hz = /bits/ 64 <267000000>;
2239 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2240 opp-peak-kBps = <3072000>;
2241 opp-supported-hw = <0x07>;
2244 opp-180000000 {
2245 opp-hz = /bits/ 64 <180000000>;
2246 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2247 opp-peak-kBps = <1804000>;
2248 opp-supported-hw = <0x07>;
2254 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2256 #iommu-cells = <1>;
2257 #global-interrupts = <2>;
2271 clock-names = "bus", "iface";
2273 power-domains = <&gpucc CX_GDSC>;
2277 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2280 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2283 interrupt-names = "hfi", "gmu";
2288 clock-names = "gmu", "cxo", "axi", "memnoc";
2289 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2290 power-domain-names = "cx", "gx";
2292 operating-points-v2 = <&gmu_opp_table>;
2294 gmu_opp_table: opp-table {
2295 compatible = "operating-points-v2";
2297 opp-200000000 {
2298 opp-hz = /bits/ 64 <200000000>;
2299 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2304 gpucc: clock-controller@5090000 {
2305 compatible = "qcom,sc7180-gpucc";
2310 clock-names = "bi_tcxo",
2313 #clock-cells = <1>;
2314 #reset-cells = <1>;
2315 #power-domain-cells = <1>;
2319 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2326 compatible = "arm,coresight-stm", "arm,primecell";
2329 reg-names = "stm-base", "stm-stimulus-base";
2332 clock-names = "apb_pclk";
2334 out-ports {
2337 remote-endpoint = <&funnel0_in7>;
2344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2348 clock-names = "apb_pclk";
2350 out-ports {
2353 remote-endpoint = <&merge_funnel_in0>;
2358 in-ports {
2359 #address-cells = <1>;
2360 #size-cells = <0>;
2365 remote-endpoint = <&stm_out>;
2372 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2376 clock-names = "apb_pclk";
2378 out-ports {
2381 remote-endpoint = <&merge_funnel_in1>;
2386 in-ports {
2387 #address-cells = <1>;
2388 #size-cells = <0>;
2393 remote-endpoint = <&apss_merge_funnel_out>;
2400 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2404 clock-names = "apb_pclk";
2406 out-ports {
2409 remote-endpoint = <&swao_funnel_in>;
2414 in-ports {
2415 #address-cells = <1>;
2416 #size-cells = <0>;
2421 remote-endpoint = <&funnel0_out>;
2428 remote-endpoint = <&funnel1_out>;
2435 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2439 clock-names = "apb_pclk";
2441 out-ports {
2444 remote-endpoint = <&etr_in>;
2449 in-ports {
2452 remote-endpoint = <&swao_replicator_out>;
2459 compatible = "arm,coresight-tmc", "arm,primecell";
2464 clock-names = "apb_pclk";
2465 arm,scatter-gather;
2467 in-ports {
2470 remote-endpoint = <&replicator_out>;
2477 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2481 clock-names = "apb_pclk";
2483 out-ports {
2486 remote-endpoint = <&etf_in>;
2491 in-ports {
2492 #address-cells = <1>;
2493 #size-cells = <0>;
2498 remote-endpoint = <&merge_funnel_out>;
2505 compatible = "arm,coresight-tmc", "arm,primecell";
2509 clock-names = "apb_pclk";
2511 out-ports {
2514 remote-endpoint = <&swao_replicator_in>;
2519 in-ports {
2522 remote-endpoint = <&swao_funnel_out>;
2529 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2533 clock-names = "apb_pclk";
2534 qcom,replicator-loses-context;
2536 out-ports {
2539 remote-endpoint = <&replicator_in>;
2544 in-ports {
2547 remote-endpoint = <&etf_out>;
2554 compatible = "arm,coresight-etm4x", "arm,primecell";
2560 clock-names = "apb_pclk";
2561 arm,coresight-loses-context-with-cpu;
2562 qcom,skip-power-up;
2564 out-ports {
2567 remote-endpoint = <&apss_funnel_in0>;
2574 compatible = "arm,coresight-etm4x", "arm,primecell";
2580 clock-names = "apb_pclk";
2581 arm,coresight-loses-context-with-cpu;
2582 qcom,skip-power-up;
2584 out-ports {
2587 remote-endpoint = <&apss_funnel_in1>;
2594 compatible = "arm,coresight-etm4x", "arm,primecell";
2600 clock-names = "apb_pclk";
2601 arm,coresight-loses-context-with-cpu;
2602 qcom,skip-power-up;
2604 out-ports {
2607 remote-endpoint = <&apss_funnel_in2>;
2614 compatible = "arm,coresight-etm4x", "arm,primecell";
2620 clock-names = "apb_pclk";
2621 arm,coresight-loses-context-with-cpu;
2622 qcom,skip-power-up;
2624 out-ports {
2627 remote-endpoint = <&apss_funnel_in3>;
2634 compatible = "arm,coresight-etm4x", "arm,primecell";
2640 clock-names = "apb_pclk";
2641 arm,coresight-loses-context-with-cpu;
2642 qcom,skip-power-up;
2644 out-ports {
2647 remote-endpoint = <&apss_funnel_in4>;
2654 compatible = "arm,coresight-etm4x", "arm,primecell";
2660 clock-names = "apb_pclk";
2661 arm,coresight-loses-context-with-cpu;
2662 qcom,skip-power-up;
2664 out-ports {
2667 remote-endpoint = <&apss_funnel_in5>;
2674 compatible = "arm,coresight-etm4x", "arm,primecell";
2680 clock-names = "apb_pclk";
2681 arm,coresight-loses-context-with-cpu;
2682 qcom,skip-power-up;
2684 out-ports {
2687 remote-endpoint = <&apss_funnel_in6>;
2694 compatible = "arm,coresight-etm4x", "arm,primecell";
2700 clock-names = "apb_pclk";
2701 arm,coresight-loses-context-with-cpu;
2702 qcom,skip-power-up;
2704 out-ports {
2707 remote-endpoint = <&apss_funnel_in7>;
2714 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2718 clock-names = "apb_pclk";
2720 out-ports {
2723 remote-endpoint = <&apss_merge_funnel_in>;
2728 in-ports {
2729 #address-cells = <1>;
2730 #size-cells = <0>;
2735 remote-endpoint = <&etm0_out>;
2742 remote-endpoint = <&etm1_out>;
2749 remote-endpoint = <&etm2_out>;
2756 remote-endpoint = <&etm3_out>;
2763 remote-endpoint = <&etm4_out>;
2770 remote-endpoint = <&etm5_out>;
2777 remote-endpoint = <&etm6_out>;
2784 remote-endpoint = <&etm7_out>;
2791 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2795 clock-names = "apb_pclk";
2797 out-ports {
2800 remote-endpoint = <&funnel1_in4>;
2805 in-ports {
2808 remote-endpoint = <&apss_funnel_out>;
2815 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2821 interrupt-names = "hc_irq", "pwr_irq";
2826 clock-names = "iface", "core", "xo";
2830 interconnect-names = "sdhc-ddr","cpu-sdhc";
2831 power-domains = <&rpmhpd SC7180_CX>;
2832 operating-points-v2 = <&sdhc2_opp_table>;
2834 bus-width = <4>;
2838 sdhc2_opp_table: opp-table {
2839 compatible = "operating-points-v2";
2841 opp-100000000 {
2842 opp-hz = /bits/ 64 <100000000>;
2843 required-opps = <&rpmhpd_opp_low_svs>;
2844 opp-peak-kBps = <1800000 600000>;
2845 opp-avg-kBps = <100000 0>;
2848 opp-202000000 {
2849 opp-hz = /bits/ 64 <202000000>;
2850 required-opps = <&rpmhpd_opp_nom>;
2851 opp-peak-kBps = <5400000 1600000>;
2852 opp-avg-kBps = <200000 0>;
2858 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2861 #address-cells = <1>;
2862 #size-cells = <0>;
2866 clock-names = "iface", "core";
2869 interconnect-names = "qspi-config";
2870 power-domains = <&rpmhpd SC7180_CX>;
2871 operating-points-v2 = <&qspi_opp_table>;
2876 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2879 #phy-cells = <0>;
2882 clock-names = "cfg_ahb", "ref";
2885 nvmem-cells = <&qusb2p_hstx_trim>;
2889 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2898 clock-names = "aux",
2906 reset-names = "phy", "common";
2908 #clock-cells = <1>;
2909 #phy-cells = <1>;
2912 #address-cells = <1>;
2913 #size-cells = <0>;
2925 remote-endpoint = <&usb_1_dwc3_ss>;
2938 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2944 operating-points-v2 = <&cpu_bwmon_opp_table>;
2946 cpu_bwmon_opp_table: opp-table {
2947 compatible = "operating-points-v2";
2949 opp-0 {
2950 opp-peak-kBps = <2288000>;
2953 opp-1 {
2954 opp-peak-kBps = <4577000>;
2957 opp-2 {
2958 opp-peak-kBps = <7110000>;
2961 opp-3 {
2962 opp-peak-kBps = <9155000>;
2965 opp-4 {
2966 opp-peak-kBps = <12298000>;
2969 opp-5 {
2970 opp-peak-kBps = <14236000>;
2976 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2982 operating-points-v2 = <&llcc_bwmon_opp_table>;
2984 llcc_bwmon_opp_table: opp-table {
2985 compatible = "operating-points-v2";
2987 opp-0 {
2988 opp-peak-kBps = <1144000>;
2991 opp-1 {
2992 opp-peak-kBps = <1720000>;
2995 opp-2 {
2996 opp-peak-kBps = <2086000>;
2999 opp-3 {
3000 opp-peak-kBps = <2929000>;
3003 opp-4 {
3004 opp-peak-kBps = <3879000>;
3007 opp-5 {
3008 opp-peak-kBps = <5931000>;
3011 opp-6 {
3012 opp-peak-kBps = <6881000>;
3015 opp-7 {
3016 opp-peak-kBps = <8137000>;
3022 compatible = "qcom,sc7180-dc-noc";
3024 #interconnect-cells = <2>;
3025 qcom,bcm-voters = <&apps_bcm_voter>;
3028 system-cache-controller@9200000 {
3029 compatible = "qcom,sc7180-llcc";
3031 reg-names = "llcc0_base", "llcc_broadcast_base";
3036 compatible = "qcom,sc7180-gem-noc";
3038 #interconnect-cells = <2>;
3039 qcom,bcm-voters = <&apps_bcm_voter>;
3043 compatible = "qcom,sc7180-npu-noc";
3045 #interconnect-cells = <2>;
3046 qcom,bcm-voters = <&apps_bcm_voter>;
3050 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3053 #address-cells = <2>;
3054 #size-cells = <2>;
3056 dma-ranges;
3063 clock-names = "cfg_noc",
3069 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3071 assigned-clock-rates = <19200000>, <150000000>;
3073 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3074 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3075 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
3076 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3077 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
3078 interrupt-names = "pwr_event",
3084 power-domains = <&gcc USB30_PRIM_GDSC>;
3085 required-opps = <&rpmhpd_opp_nom>;
3091 interconnect-names = "usb-ddr", "apps-usb";
3093 wakeup-source;
3102 snps,parkmode-disable-ss-quirk;
3103 snps,dis-u1-entry-quirk;
3104 snps,dis-u2-entry-quirk;
3106 phy-names = "usb2-phy", "usb3-phy";
3107 maximum-speed = "super-speed";
3110 #address-cells = <1>;
3111 #size-cells = <0>;
3124 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3131 venus: video-codec@aa00000 {
3132 compatible = "qcom,sc7180-venus";
3135 power-domains = <&videocc VENUS_GDSC>,
3138 power-domain-names = "venus", "vcodec0", "cx";
3139 operating-points-v2 = <&venus_opp_table>;
3145 clock-names = "core", "iface", "bus",
3148 memory-region = <&venus_mem>;
3151 interconnect-names = "video-mem", "cpu-cfg";
3153 venus_opp_table: opp-table {
3154 compatible = "operating-points-v2";
3156 opp-150000000 {
3157 opp-hz = /bits/ 64 <150000000>;
3158 required-opps = <&rpmhpd_opp_low_svs>;
3161 opp-270000000 {
3162 opp-hz = /bits/ 64 <270000000>;
3163 required-opps = <&rpmhpd_opp_svs>;
3166 opp-340000000 {
3167 opp-hz = /bits/ 64 <340000000>;
3168 required-opps = <&rpmhpd_opp_svs_l1>;
3171 opp-434000000 {
3172 opp-hz = /bits/ 64 <434000000>;
3173 required-opps = <&rpmhpd_opp_nom>;
3176 opp-500000097 {
3177 opp-hz = /bits/ 64 <500000097>;
3178 required-opps = <&rpmhpd_opp_turbo>;
3183 videocc: clock-controller@ab00000 {
3184 compatible = "qcom,sc7180-videocc";
3187 clock-names = "bi_tcxo";
3188 #clock-cells = <1>;
3189 #reset-cells = <1>;
3190 #power-domain-cells = <1>;
3194 compatible = "qcom,sc7180-camnoc-virt";
3196 #interconnect-cells = <2>;
3197 qcom,bcm-voters = <&apps_bcm_voter>;
3200 camcc: clock-controller@ad00000 {
3201 compatible = "qcom,sc7180-camcc";
3206 clock-names = "bi_tcxo", "iface", "xo";
3207 #clock-cells = <1>;
3208 #reset-cells = <1>;
3209 #power-domain-cells = <1>;
3212 mdss: display-subsystem@ae00000 {
3213 compatible = "qcom,sc7180-mdss";
3215 reg-names = "mdss";
3217 power-domains = <&dispcc MDSS_GDSC>;
3222 clock-names = "iface", "ahb", "core";
3225 interrupt-controller;
3226 #interrupt-cells = <1>;
3232 interconnect-names = "mdp0-mem",
3233 "cpu-cfg";
3237 #address-cells = <2>;
3238 #size-cells = <2>;
3243 mdp: display-controller@ae01000 {
3244 compatible = "qcom,sc7180-dpu";
3247 reg-names = "mdp", "vbif";
3255 clock-names = "bus", "iface", "rot", "lut", "core",
3257 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3260 assigned-clock-rates = <19200000>,
3263 operating-points-v2 = <&mdp_opp_table>;
3264 power-domains = <&rpmhpd SC7180_CX>;
3266 interrupt-parent = <&mdss>;
3270 #address-cells = <1>;
3271 #size-cells = <0>;
3276 remote-endpoint = <&mdss_dsi0_in>;
3283 remote-endpoint = <&dp_in>;
3288 mdp_opp_table: opp-table {
3289 compatible = "operating-points-v2";
3291 opp-200000000 {
3292 opp-hz = /bits/ 64 <200000000>;
3293 required-opps = <&rpmhpd_opp_low_svs>;
3296 opp-300000000 {
3297 opp-hz = /bits/ 64 <300000000>;
3298 required-opps = <&rpmhpd_opp_svs>;
3301 opp-345000000 {
3302 opp-hz = /bits/ 64 <345000000>;
3303 required-opps = <&rpmhpd_opp_svs_l1>;
3306 opp-460000000 {
3307 opp-hz = /bits/ 64 <460000000>;
3308 required-opps = <&rpmhpd_opp_nom>;
3314 compatible = "qcom,sc7180-dsi-ctrl",
3315 "qcom,mdss-dsi-ctrl";
3317 reg-names = "dsi_ctrl";
3319 interrupt-parent = <&mdss>;
3328 clock-names = "byte",
3335 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3337 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3340 operating-points-v2 = <&dsi_opp_table>;
3341 power-domains = <&rpmhpd SC7180_CX>;
3345 refgen-supply = <&refgen>;
3347 #address-cells = <1>;
3348 #size-cells = <0>;
3353 #address-cells = <1>;
3354 #size-cells = <0>;
3359 remote-endpoint = <&dpu_intf1_out>;
3370 dsi_opp_table: opp-table {
3371 compatible = "operating-points-v2";
3373 opp-187500000 {
3374 opp-hz = /bits/ 64 <187500000>;
3375 required-opps = <&rpmhpd_opp_low_svs>;
3378 opp-300000000 {
3379 opp-hz = /bits/ 64 <300000000>;
3380 required-opps = <&rpmhpd_opp_svs>;
3383 opp-358000000 {
3384 opp-hz = /bits/ 64 <358000000>;
3385 required-opps = <&rpmhpd_opp_svs_l1>;
3391 compatible = "qcom,dsi-phy-10nm";
3395 reg-names = "dsi_phy",
3399 #clock-cells = <1>;
3400 #phy-cells = <0>;
3404 clock-names = "iface", "ref";
3409 mdss_dp: displayport-controller@ae90000 {
3410 compatible = "qcom,sc7180-dp";
3419 interrupt-parent = <&mdss>;
3427 clock-names = "core_iface", "core_aux", "ctrl_link",
3429 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3431 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3434 phy-names = "dp";
3436 operating-points-v2 = <&dp_opp_table>;
3437 power-domains = <&rpmhpd SC7180_CX>;
3439 #sound-dai-cells = <0>;
3442 #address-cells = <1>;
3443 #size-cells = <0>;
3449 remote-endpoint = <&dpu_intf0_out>;
3460 dp_opp_table: opp-table {
3461 compatible = "operating-points-v2";
3463 opp-160000000 {
3464 opp-hz = /bits/ 64 <160000000>;
3465 required-opps = <&rpmhpd_opp_low_svs>;
3468 opp-270000000 {
3469 opp-hz = /bits/ 64 <270000000>;
3470 required-opps = <&rpmhpd_opp_svs>;
3473 opp-540000000 {
3474 opp-hz = /bits/ 64 <540000000>;
3475 required-opps = <&rpmhpd_opp_svs_l1>;
3478 opp-810000000 {
3479 opp-hz = /bits/ 64 <810000000>;
3480 required-opps = <&rpmhpd_opp_nom>;
3486 dispcc: clock-controller@af00000 {
3487 compatible = "qcom,sc7180-dispcc";
3495 clock-names = "bi_tcxo",
3501 #clock-cells = <1>;
3502 #reset-cells = <1>;
3503 #power-domain-cells = <1>;
3506 pdc: interrupt-controller@b220000 { label
3507 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3509 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3510 #interrupt-cells = <2>;
3511 interrupt-parent = <&intc>;
3512 interrupt-controller;
3515 pdc_reset: reset-controller@b2e0000 {
3516 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3518 #reset-cells = <1>;
3521 tsens0: thermal-sensor@c263000 {
3522 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3528 interrupt-names = "uplow","critical";
3529 #thermal-sensor-cells = <1>;
3532 tsens1: thermal-sensor@c265000 {
3533 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3539 interrupt-names = "uplow","critical";
3540 #thermal-sensor-cells = <1>;
3543 aoss_reset: reset-controller@c2a0000 {
3544 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3546 #reset-cells = <1>;
3549 aoss_qmp: power-management@c300000 {
3550 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3555 #clock-cells = <0>;
3559 compatible = "qcom,rpmh-stats";
3564 compatible = "qcom,spmi-pmic-arb";
3570 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3571 interrupt-names = "periph_irq";
3572 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3575 #address-cells = <2>;
3576 #size-cells = <0>;
3577 interrupt-controller;
3578 #interrupt-cells = <4>;
3582 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3585 #address-cells = <1>;
3586 #size-cells = <1>;
3590 pil-reloc@2a94c {
3591 compatible = "qcom,pil-reloc-info";
3597 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3599 #iommu-cells = <2>;
3600 #global-interrupts = <1>;
3682 dma-coherent;
3685 intc: interrupt-controller@17a00000 { label
3686 compatible = "arm,gic-v3";
3687 #address-cells = <2>;
3688 #size-cells = <2>;
3690 #interrupt-cells = <3>;
3691 interrupt-controller;
3696 msi-controller@17a40000 {
3697 compatible = "arm,gic-v3-its";
3698 msi-controller;
3699 #msi-cells = <1>;
3706 compatible = "qcom,sc7180-apss-shared",
3707 "qcom,sdm845-apss-shared";
3709 #mbox-cells = <1>;
3713 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3720 #address-cells = <1>;
3721 #size-cells = <1>;
3723 compatible = "arm,armv7-timer-mem";
3727 frame-number = <0>;
3735 frame-number = <1>;
3742 frame-number = <2>;
3749 frame-number = <3>;
3756 frame-number = <4>;
3763 frame-number = <5>;
3770 frame-number = <6>;
3778 compatible = "qcom,sc7180-rpmh-apps-rsc", "qcom,rpmh-rsc";
3782 reg-names = "drv-0", "drv-1", "drv-2";
3786 qcom,tcs-offset = <0xd00>;
3787 qcom,drv-id = <2>;
3788 qcom,tcs-config = <ACTIVE_TCS 2>,
3792 power-domains = <&cluster_pd>;
3794 rpmhcc: clock-controller {
3795 compatible = "qcom,sc7180-rpmh-clk";
3797 clock-names = "xo";
3798 #clock-cells = <1>;
3801 rpmhpd: power-controller {
3802 compatible = "qcom,sc7180-rpmhpd";
3803 #power-domain-cells = <1>;
3804 operating-points-v2 = <&rpmhpd_opp_table>;
3806 rpmhpd_opp_table: opp-table {
3807 compatible = "operating-points-v2";
3810 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3814 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3818 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3822 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3826 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3830 opp-level = <224>;
3834 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3838 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3842 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3846 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3850 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3855 apps_bcm_voter: bcm-voter {
3856 compatible = "qcom,bcm-voter";
3861 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3865 clock-names = "xo", "alternate";
3867 #interconnect-cells = <1>;
3871 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3873 reg-names = "freq-domain0", "freq-domain1";
3876 clock-names = "xo", "alternate";
3878 #freq-domain-cells = <1>;
3879 #clock-cells = <1>;
3883 compatible = "qcom,wcn3990-wifi";
3885 reg-names = "membase";
3900 memory-region = <&wlan_mem>;
3901 qcom,msa-fixed-perm;
3906 compatible = "qcom,sc7180-adsp-pas";
3909 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3914 interrupt-names = "wdog",
3918 "stop-ack";
3921 clock-names = "xo";
3923 power-domains = <&rpmhpd SC7180_LCX>,
3925 power-domain-names = "lcx", "lmx";
3928 qcom,smem-states = <&adsp_smp2p_out 0>;
3929 qcom,smem-state-names = "stop";
3933 glink-edge {
3936 qcom,remote-pid = <2>;
3940 compatible = "qcom,apr-v2";
3941 qcom,glink-channels = "apr_audio_svc";
3943 #address-cells = <1>;
3944 #size-cells = <0>;
3949 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3955 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3958 compatible = "qcom,q6afe-dais";
3959 #address-cells = <1>;
3960 #size-cells = <0>;
3961 #sound-dai-cells = <1>;
3964 q6afecc: clock-controller {
3965 compatible = "qcom,q6afe-clocks";
3966 #clock-cells = <2>;
3973 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3976 compatible = "qcom,q6asm-dais";
3977 #address-cells = <1>;
3978 #size-cells = <0>;
3979 #sound-dai-cells = <1>;
3987 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3990 compatible = "qcom,q6adm-routing";
3991 #sound-dai-cells = <0>;
3998 qcom,glink-channels = "fastrpcglink-apps-dsp";
4000 #address-cells = <1>;
4001 #size-cells = <0>;
4003 compute-cb@3 {
4004 compatible = "qcom,fastrpc-compute-cb";
4009 compute-cb@4 {
4010 compatible = "qcom,fastrpc-compute-cb";
4015 compute-cb@5 {
4016 compatible = "qcom,fastrpc-compute-cb";
4025 lpasscc: clock-controller@62d00000 {
4026 compatible = "qcom,sc7180-lpasscorecc";
4029 reg-names = "lpass_core_cc", "lpass_audio_cc";
4032 clock-names = "iface", "bi_tcxo";
4033 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
4034 #clock-cells = <1>;
4035 #power-domain-cells = <1>;
4041 compatible = "qcom,sc7180-lpass-cpu";
4044 reg-names = "lpass-hdmiif", "lpass-lpaif";
4050 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
4051 required-opps = <&rpmhpd_opp_nom>;
4062 clock-names = "pcnoc-sway-clk", "audio-core",
4063 "mclk0", "pcnoc-mport-clk",
4064 "mi2s-bit-clk0", "mi2s-bit-clk1";
4067 #sound-dai-cells = <1>;
4068 #address-cells = <1>;
4069 #size-cells = <0>;
4073 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4076 lpass_hm: clock-controller@63000000 {
4077 compatible = "qcom,sc7180-lpasshm";
4081 clock-names = "iface", "bi_tcxo";
4082 power-domains = <&rpmhpd SC7180_CX>;
4084 #clock-cells = <1>;
4085 #power-domain-cells = <1>;
4091 thermal-zones {
4092 cpu0_thermal: cpu0-thermal {
4093 polling-delay-passive = <250>;
4095 thermal-sensors = <&tsens0 1>;
4096 sustainable-power = <1052>;
4099 cpu0_alert0: trip-point0 {
4105 cpu0_alert1: trip-point1 {
4111 cpu0_crit: cpu-crit {
4118 cooling-maps {
4121 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4130 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4140 cpu1_thermal: cpu1-thermal {
4141 polling-delay-passive = <250>;
4143 thermal-sensors = <&tsens0 2>;
4144 sustainable-power = <1052>;
4147 cpu1_alert0: trip-point0 {
4153 cpu1_alert1: trip-point1 {
4159 cpu1_crit: cpu-crit {
4166 cooling-maps {
4169 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4178 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4188 cpu2_thermal: cpu2-thermal {
4189 polling-delay-passive = <250>;
4191 thermal-sensors = <&tsens0 3>;
4192 sustainable-power = <1052>;
4195 cpu2_alert0: trip-point0 {
4201 cpu2_alert1: trip-point1 {
4207 cpu2_crit: cpu-crit {
4214 cooling-maps {
4217 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4226 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4236 cpu3_thermal: cpu3-thermal {
4237 polling-delay-passive = <250>;
4239 thermal-sensors = <&tsens0 4>;
4240 sustainable-power = <1052>;
4243 cpu3_alert0: trip-point0 {
4249 cpu3_alert1: trip-point1 {
4255 cpu3_crit: cpu-crit {
4262 cooling-maps {
4265 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4274 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4284 cpu4_thermal: cpu4-thermal {
4285 polling-delay-passive = <250>;
4287 thermal-sensors = <&tsens0 5>;
4288 sustainable-power = <1052>;
4291 cpu4_alert0: trip-point0 {
4297 cpu4_alert1: trip-point1 {
4303 cpu4_crit: cpu-crit {
4310 cooling-maps {
4313 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4322 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4332 cpu5_thermal: cpu5-thermal {
4333 polling-delay-passive = <250>;
4335 thermal-sensors = <&tsens0 6>;
4336 sustainable-power = <1052>;
4339 cpu5_alert0: trip-point0 {
4345 cpu5_alert1: trip-point1 {
4351 cpu5_crit: cpu-crit {
4358 cooling-maps {
4361 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4370 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4380 cpu6_thermal: cpu6-thermal {
4381 polling-delay-passive = <250>;
4383 thermal-sensors = <&tsens0 9>;
4384 sustainable-power = <1425>;
4387 cpu6_alert0: trip-point0 {
4393 cpu6_alert1: trip-point1 {
4399 cpu6_crit: cpu-crit {
4406 cooling-maps {
4409 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4414 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4420 cpu7_thermal: cpu7-thermal {
4421 polling-delay-passive = <250>;
4423 thermal-sensors = <&tsens0 10>;
4424 sustainable-power = <1425>;
4427 cpu7_alert0: trip-point0 {
4433 cpu7_alert1: trip-point1 {
4439 cpu7_crit: cpu-crit {
4446 cooling-maps {
4449 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4454 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4460 cpu8_thermal: cpu8-thermal {
4461 polling-delay-passive = <250>;
4463 thermal-sensors = <&tsens0 11>;
4464 sustainable-power = <1425>;
4467 cpu8_alert0: trip-point0 {
4473 cpu8_alert1: trip-point1 {
4479 cpu8_crit: cpu-crit {
4486 cooling-maps {
4489 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4494 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4500 cpu9_thermal: cpu9-thermal {
4501 polling-delay-passive = <250>;
4503 thermal-sensors = <&tsens0 12>;
4504 sustainable-power = <1425>;
4507 cpu9_alert0: trip-point0 {
4513 cpu9_alert1: trip-point1 {
4519 cpu9_crit: cpu-crit {
4526 cooling-maps {
4529 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4534 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4540 aoss0-thermal {
4541 polling-delay-passive = <250>;
4543 thermal-sensors = <&tsens0 0>;
4546 aoss0_alert0: trip-point0 {
4552 aoss0_crit: aoss0-crit {
4560 cpuss0-thermal {
4561 polling-delay-passive = <250>;
4563 thermal-sensors = <&tsens0 7>;
4566 cpuss0_alert0: trip-point0 {
4571 cpuss0_crit: cluster0-crit {
4579 cpuss1-thermal {
4580 polling-delay-passive = <250>;
4582 thermal-sensors = <&tsens0 8>;
4585 cpuss1_alert0: trip-point0 {
4590 cpuss1_crit: cluster0-crit {
4598 gpuss0-thermal {
4599 polling-delay-passive = <250>;
4601 thermal-sensors = <&tsens0 13>;
4604 gpuss0_alert0: trip-point0 {
4610 gpuss0_crit: gpuss0-crit {
4617 cooling-maps {
4620 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4625 gpuss1-thermal {
4626 polling-delay-passive = <250>;
4628 thermal-sensors = <&tsens0 14>;
4631 gpuss1_alert0: trip-point0 {
4637 gpuss1_crit: gpuss1-crit {
4644 cooling-maps {
4647 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4652 aoss1-thermal {
4653 polling-delay-passive = <250>;
4655 thermal-sensors = <&tsens1 0>;
4658 aoss1_alert0: trip-point0 {
4664 aoss1_crit: aoss1-crit {
4672 cwlan-thermal {
4673 polling-delay-passive = <250>;
4675 thermal-sensors = <&tsens1 1>;
4678 cwlan_alert0: trip-point0 {
4684 cwlan_crit: cwlan-crit {
4692 audio-thermal {
4693 polling-delay-passive = <250>;
4695 thermal-sensors = <&tsens1 2>;
4698 audio_alert0: trip-point0 {
4704 audio_crit: audio-crit {
4712 ddr-thermal {
4713 polling-delay-passive = <250>;
4715 thermal-sensors = <&tsens1 3>;
4718 ddr_alert0: trip-point0 {
4724 ddr_crit: ddr-crit {
4732 q6-hvx-thermal {
4733 polling-delay-passive = <250>;
4735 thermal-sensors = <&tsens1 4>;
4738 q6_hvx_alert0: trip-point0 {
4744 q6_hvx_crit: q6-hvx-crit {
4752 camera-thermal {
4753 polling-delay-passive = <250>;
4755 thermal-sensors = <&tsens1 5>;
4758 camera_alert0: trip-point0 {
4764 camera_crit: camera-crit {
4772 mdm-core-thermal {
4773 polling-delay-passive = <250>;
4775 thermal-sensors = <&tsens1 6>;
4778 mdm_alert0: trip-point0 {
4784 mdm_crit: mdm-crit {
4792 mdm-dsp-thermal {
4793 polling-delay-passive = <250>;
4795 thermal-sensors = <&tsens1 7>;
4798 mdm_dsp_alert0: trip-point0 {
4804 mdm_dsp_crit: mdm-dsp-crit {
4812 npu-thermal {
4813 polling-delay-passive = <250>;
4815 thermal-sensors = <&tsens1 8>;
4818 npu_alert0: trip-point0 {
4824 npu_crit: npu-crit {
4832 video-thermal {
4833 polling-delay-passive = <250>;
4835 thermal-sensors = <&tsens1 9>;
4838 video_alert0: trip-point0 {
4844 video_crit: video-crit {
4854 compatible = "arm,armv8-timer";