Lines Matching +full:ipa +full:- +full:clock +full:- +full:enabled
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sc7180.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/phy/phy-qcom-qusb2.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
24 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/soc/qcom,apr.h>
27 #include <dt-bindings/sound/qcom,q6afe.h>
28 #include <dt-bindings/thermal/thermal.h>
31 interrupt-parent = <&intc>;
33 #address-cells = <2>;
34 #size-cells = <2>;
64 xo_board: xo-board {
65 compatible = "fixed-clock";
66 clock-frequency = <38400000>;
67 #clock-cells = <0>;
70 sleep_clk: sleep-clk {
71 compatible = "fixed-clock";
72 clock-frequency = <32764>;
73 #clock-cells = <0>;
78 #address-cells = <2>;
79 #size-cells = <0>;
86 enable-method = "psci";
87 power-domains = <&cpu_pd0>;
88 power-domain-names = "psci";
89 capacity-dmips-mhz = <415>;
90 dynamic-power-coefficient = <137>;
91 operating-points-v2 = <&cpu0_opp_table>;
94 next-level-cache = <&l2_0>;
95 #cooling-cells = <2>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 l2_0: l2-cache {
99 cache-level = <2>;
100 cache-unified;
101 next-level-cache = <&l3_0>;
102 l3_0: l3-cache {
104 cache-level = <3>;
105 cache-unified;
115 enable-method = "psci";
116 power-domains = <&cpu_pd1>;
117 power-domain-names = "psci";
118 capacity-dmips-mhz = <415>;
119 dynamic-power-coefficient = <137>;
120 next-level-cache = <&l2_100>;
121 operating-points-v2 = <&cpu0_opp_table>;
124 #cooling-cells = <2>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 l2_100: l2-cache {
128 cache-level = <2>;
129 cache-unified;
130 next-level-cache = <&l3_0>;
139 enable-method = "psci";
140 power-domains = <&cpu_pd2>;
141 power-domain-names = "psci";
142 capacity-dmips-mhz = <415>;
143 dynamic-power-coefficient = <137>;
144 next-level-cache = <&l2_200>;
145 operating-points-v2 = <&cpu0_opp_table>;
148 #cooling-cells = <2>;
149 qcom,freq-domain = <&cpufreq_hw 0>;
150 l2_200: l2-cache {
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_0>;
163 enable-method = "psci";
164 power-domains = <&cpu_pd3>;
165 power-domain-names = "psci";
166 capacity-dmips-mhz = <415>;
167 dynamic-power-coefficient = <137>;
168 next-level-cache = <&l2_300>;
169 operating-points-v2 = <&cpu0_opp_table>;
172 #cooling-cells = <2>;
173 qcom,freq-domain = <&cpufreq_hw 0>;
174 l2_300: l2-cache {
176 cache-level = <2>;
177 cache-unified;
178 next-level-cache = <&l3_0>;
187 enable-method = "psci";
188 power-domains = <&cpu_pd4>;
189 power-domain-names = "psci";
190 capacity-dmips-mhz = <415>;
191 dynamic-power-coefficient = <137>;
192 next-level-cache = <&l2_400>;
193 operating-points-v2 = <&cpu0_opp_table>;
196 #cooling-cells = <2>;
197 qcom,freq-domain = <&cpufreq_hw 0>;
198 l2_400: l2-cache {
200 cache-level = <2>;
201 cache-unified;
202 next-level-cache = <&l3_0>;
211 enable-method = "psci";
212 power-domains = <&cpu_pd5>;
213 power-domain-names = "psci";
214 capacity-dmips-mhz = <415>;
215 dynamic-power-coefficient = <137>;
216 next-level-cache = <&l2_500>;
217 operating-points-v2 = <&cpu0_opp_table>;
220 #cooling-cells = <2>;
221 qcom,freq-domain = <&cpufreq_hw 0>;
222 l2_500: l2-cache {
224 cache-level = <2>;
225 cache-unified;
226 next-level-cache = <&l3_0>;
235 enable-method = "psci";
236 power-domains = <&cpu_pd6>;
237 power-domain-names = "psci";
238 capacity-dmips-mhz = <1024>;
239 dynamic-power-coefficient = <480>;
240 next-level-cache = <&l2_600>;
241 operating-points-v2 = <&cpu6_opp_table>;
244 #cooling-cells = <2>;
245 qcom,freq-domain = <&cpufreq_hw 1>;
246 l2_600: l2-cache {
248 cache-level = <2>;
249 cache-unified;
250 next-level-cache = <&l3_0>;
259 enable-method = "psci";
260 power-domains = <&cpu_pd7>;
261 power-domain-names = "psci";
262 capacity-dmips-mhz = <1024>;
263 dynamic-power-coefficient = <480>;
264 next-level-cache = <&l2_700>;
265 operating-points-v2 = <&cpu6_opp_table>;
268 #cooling-cells = <2>;
269 qcom,freq-domain = <&cpufreq_hw 1>;
270 l2_700: l2-cache {
272 cache-level = <2>;
273 cache-unified;
274 next-level-cache = <&l3_0>;
278 cpu-map {
314 idle_states: idle-states {
315 entry-method = "psci";
317 little_cpu_sleep_0: cpu-sleep-0-0 {
318 compatible = "arm,idle-state";
319 idle-state-name = "little-power-down";
320 arm,psci-suspend-param = <0x40000003>;
321 entry-latency-us = <549>;
322 exit-latency-us = <901>;
323 min-residency-us = <1774>;
324 local-timer-stop;
327 little_cpu_sleep_1: cpu-sleep-0-1 {
328 compatible = "arm,idle-state";
329 idle-state-name = "little-rail-power-down";
330 arm,psci-suspend-param = <0x40000004>;
331 entry-latency-us = <702>;
332 exit-latency-us = <915>;
333 min-residency-us = <4001>;
334 local-timer-stop;
337 big_cpu_sleep_0: cpu-sleep-1-0 {
338 compatible = "arm,idle-state";
339 idle-state-name = "big-power-down";
340 arm,psci-suspend-param = <0x40000003>;
341 entry-latency-us = <523>;
342 exit-latency-us = <1244>;
343 min-residency-us = <2207>;
344 local-timer-stop;
347 big_cpu_sleep_1: cpu-sleep-1-1 {
348 compatible = "arm,idle-state";
349 idle-state-name = "big-rail-power-down";
350 arm,psci-suspend-param = <0x40000004>;
351 entry-latency-us = <526>;
352 exit-latency-us = <1854>;
353 min-residency-us = <5555>;
354 local-timer-stop;
358 domain_idle_states: domain-idle-states {
359 cluster_sleep_pc: cluster-sleep-0 {
360 compatible = "domain-idle-state";
361 arm,psci-suspend-param = <0x41000044>;
362 entry-latency-us = <2752>;
363 exit-latency-us = <3048>;
364 min-residency-us = <6118>;
367 cluster_sleep_cx_ret: cluster-sleep-1 {
368 compatible = "domain-idle-state";
369 arm,psci-suspend-param = <0x41001244>;
370 entry-latency-us = <3638>;
371 exit-latency-us = <4562>;
372 min-residency-us = <8467>;
375 cluster_aoss_sleep: cluster-sleep-2 {
376 compatible = "domain-idle-state";
377 arm,psci-suspend-param = <0x4100b244>;
378 entry-latency-us = <3263>;
379 exit-latency-us = <6562>;
380 min-residency-us = <9826>;
387 compatible = "qcom,scm-sc7180", "qcom,scm";
397 cpu0_opp_table: opp-table-cpu0 {
398 compatible = "operating-points-v2";
399 opp-shared;
401 cpu0_opp1: opp-300000000 {
402 opp-hz = /bits/ 64 <300000000>;
403 opp-peak-kBps = <1200000 4800000>;
406 cpu0_opp2: opp-576000000 {
407 opp-hz = /bits/ 64 <576000000>;
408 opp-peak-kBps = <1200000 4800000>;
411 cpu0_opp3: opp-768000000 {
412 opp-hz = /bits/ 64 <768000000>;
413 opp-peak-kBps = <1200000 4800000>;
416 cpu0_opp4: opp-1017600000 {
417 opp-hz = /bits/ 64 <1017600000>;
418 opp-peak-kBps = <1804000 8908800>;
421 cpu0_opp5: opp-1248000000 {
422 opp-hz = /bits/ 64 <1248000000>;
423 opp-peak-kBps = <2188000 12902400>;
426 cpu0_opp6: opp-1324800000 {
427 opp-hz = /bits/ 64 <1324800000>;
428 opp-peak-kBps = <2188000 12902400>;
431 cpu0_opp7: opp-1516800000 {
432 opp-hz = /bits/ 64 <1516800000>;
433 opp-peak-kBps = <3072000 15052800>;
436 cpu0_opp8: opp-1612800000 {
437 opp-hz = /bits/ 64 <1612800000>;
438 opp-peak-kBps = <3072000 15052800>;
441 cpu0_opp9: opp-1708800000 {
442 opp-hz = /bits/ 64 <1708800000>;
443 opp-peak-kBps = <3072000 15052800>;
446 cpu0_opp10: opp-1804800000 {
447 opp-hz = /bits/ 64 <1804800000>;
448 opp-peak-kBps = <4068000 22425600>;
452 cpu6_opp_table: opp-table-cpu6 {
453 compatible = "operating-points-v2";
454 opp-shared;
456 cpu6_opp1: opp-300000000 {
457 opp-hz = /bits/ 64 <300000000>;
458 opp-peak-kBps = <2188000 8908800>;
461 cpu6_opp2: opp-652800000 {
462 opp-hz = /bits/ 64 <652800000>;
463 opp-peak-kBps = <2188000 8908800>;
466 cpu6_opp3: opp-825600000 {
467 opp-hz = /bits/ 64 <825600000>;
468 opp-peak-kBps = <2188000 8908800>;
471 cpu6_opp4: opp-979200000 {
472 opp-hz = /bits/ 64 <979200000>;
473 opp-peak-kBps = <2188000 8908800>;
476 cpu6_opp5: opp-1113600000 {
477 opp-hz = /bits/ 64 <1113600000>;
478 opp-peak-kBps = <2188000 8908800>;
481 cpu6_opp6: opp-1267200000 {
482 opp-hz = /bits/ 64 <1267200000>;
483 opp-peak-kBps = <4068000 12902400>;
486 cpu6_opp7: opp-1555200000 {
487 opp-hz = /bits/ 64 <1555200000>;
488 opp-peak-kBps = <4068000 15052800>;
491 cpu6_opp8: opp-1708800000 {
492 opp-hz = /bits/ 64 <1708800000>;
493 opp-peak-kBps = <6220000 19353600>;
496 cpu6_opp9: opp-1843200000 {
497 opp-hz = /bits/ 64 <1843200000>;
498 opp-peak-kBps = <6220000 19353600>;
501 cpu6_opp10: opp-1900800000 {
502 opp-hz = /bits/ 64 <1900800000>;
503 opp-peak-kBps = <6220000 22425600>;
506 cpu6_opp11: opp-1996800000 {
507 opp-hz = /bits/ 64 <1996800000>;
508 opp-peak-kBps = <6220000 22425600>;
511 cpu6_opp12: opp-2112000000 {
512 opp-hz = /bits/ 64 <2112000000>;
513 opp-peak-kBps = <6220000 22425600>;
516 cpu6_opp13: opp-2208000000 {
517 opp-hz = /bits/ 64 <2208000000>;
518 opp-peak-kBps = <7216000 22425600>;
521 cpu6_opp14: opp-2323200000 {
522 opp-hz = /bits/ 64 <2323200000>;
523 opp-peak-kBps = <7216000 22425600>;
526 cpu6_opp15: opp-2400000000 {
527 opp-hz = /bits/ 64 <2400000000>;
528 opp-peak-kBps = <8532000 23347200>;
531 cpu6_opp16: opp-2553600000 {
532 opp-hz = /bits/ 64 <2553600000>;
533 opp-peak-kBps = <8532000 23347200>;
537 qspi_opp_table: opp-table-qspi {
538 compatible = "operating-points-v2";
540 opp-75000000 {
541 opp-hz = /bits/ 64 <75000000>;
542 required-opps = <&rpmhpd_opp_low_svs>;
545 opp-150000000 {
546 opp-hz = /bits/ 64 <150000000>;
547 required-opps = <&rpmhpd_opp_svs>;
550 opp-300000000 {
551 opp-hz = /bits/ 64 <300000000>;
552 required-opps = <&rpmhpd_opp_nom>;
556 qup_opp_table: opp-table-qup {
557 compatible = "operating-points-v2";
559 opp-75000000 {
560 opp-hz = /bits/ 64 <75000000>;
561 required-opps = <&rpmhpd_opp_low_svs>;
564 opp-100000000 {
565 opp-hz = /bits/ 64 <100000000>;
566 required-opps = <&rpmhpd_opp_svs>;
569 opp-128000000 {
570 opp-hz = /bits/ 64 <128000000>;
571 required-opps = <&rpmhpd_opp_nom>;
576 compatible = "arm,armv8-pmuv3";
581 compatible = "arm,psci-1.0";
584 cpu_pd0: power-domain-cpu0 {
585 #power-domain-cells = <0>;
586 power-domains = <&cluster_pd>;
587 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
590 cpu_pd1: power-domain-cpu1 {
591 #power-domain-cells = <0>;
592 power-domains = <&cluster_pd>;
593 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
596 cpu_pd2: power-domain-cpu2 {
597 #power-domain-cells = <0>;
598 power-domains = <&cluster_pd>;
599 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
602 cpu_pd3: power-domain-cpu3 {
603 #power-domain-cells = <0>;
604 power-domains = <&cluster_pd>;
605 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
608 cpu_pd4: power-domain-cpu4 {
609 #power-domain-cells = <0>;
610 power-domains = <&cluster_pd>;
611 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
614 cpu_pd5: power-domain-cpu5 {
615 #power-domain-cells = <0>;
616 power-domains = <&cluster_pd>;
617 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
620 cpu_pd6: power-domain-cpu6 {
621 #power-domain-cells = <0>;
622 power-domains = <&cluster_pd>;
623 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
626 cpu_pd7: power-domain-cpu7 {
627 #power-domain-cells = <0>;
628 power-domains = <&cluster_pd>;
629 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
632 cluster_pd: power-domain-cluster {
633 #power-domain-cells = <0>;
634 domain-idle-states = <&cluster_sleep_pc
640 reserved_memory: reserved-memory {
641 #address-cells = <2>;
642 #size-cells = <2>;
647 no-map;
652 no-map;
657 no-map;
662 compatible = "qcom,cmd-db";
663 no-map;
668 no-map;
673 no-map;
678 no-map;
683 no-map;
687 compatible = "qcom,rmtfs-mem";
689 no-map;
691 qcom,client-id = <1>;
698 memory-region = <&smem_mem>;
702 smp2p-cdsp {
710 qcom,local-pid = <0>;
711 qcom,remote-pid = <5>;
713 cdsp_smp2p_out: master-kernel {
714 qcom,entry-name = "master-kernel";
715 #qcom,smem-state-cells = <1>;
718 cdsp_smp2p_in: slave-kernel {
719 qcom,entry-name = "slave-kernel";
721 interrupt-controller;
722 #interrupt-cells = <2>;
726 smp2p-lpass {
734 qcom,local-pid = <0>;
735 qcom,remote-pid = <2>;
737 adsp_smp2p_out: master-kernel {
738 qcom,entry-name = "master-kernel";
739 #qcom,smem-state-cells = <1>;
742 adsp_smp2p_in: slave-kernel {
743 qcom,entry-name = "slave-kernel";
745 interrupt-controller;
746 #interrupt-cells = <2>;
750 smp2p-mpss {
755 qcom,local-pid = <0>;
756 qcom,remote-pid = <1>;
758 modem_smp2p_out: master-kernel {
759 qcom,entry-name = "master-kernel";
760 #qcom,smem-state-cells = <1>;
763 modem_smp2p_in: slave-kernel {
764 qcom,entry-name = "slave-kernel";
765 interrupt-controller;
766 #interrupt-cells = <2>;
769 ipa_smp2p_out: ipa-ap-to-modem {
770 qcom,entry-name = "ipa";
771 #qcom,smem-state-cells = <1>;
774 ipa_smp2p_in: ipa-modem-to-ap {
775 qcom,entry-name = "ipa";
776 interrupt-controller;
777 #interrupt-cells = <2>;
782 #address-cells = <2>;
783 #size-cells = <2>;
785 dma-ranges = <0 0 0 0 0x10 0>;
786 compatible = "simple-bus";
788 gcc: clock-controller@100000 {
789 compatible = "qcom,gcc-sc7180";
794 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
795 #clock-cells = <1>;
796 #reset-cells = <1>;
797 #power-domain-cells = <1>;
798 power-domains = <&rpmhpd SC7180_CX>;
802 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
809 clock-names = "core";
810 #address-cells = <1>;
811 #size-cells = <1>;
813 qusb2p_hstx_trim: hstx-trim-primary@25b {
818 gpu_speed_bin: gpu-speed-bin@1d2 {
825 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg-names = "hc", "cqhci";
833 interrupt-names = "hc_irq", "pwr_irq";
838 clock-names = "iface", "core", "xo";
841 interconnect-names = "sdhc-ddr","cpu-sdhc";
842 power-domains = <&rpmhpd SC7180_CX>;
843 operating-points-v2 = <&sdhc1_opp_table>;
845 bus-width = <8>;
846 non-removable;
847 supports-cqe;
849 mmc-ddr-1_8v;
850 mmc-hs200-1_8v;
851 mmc-hs400-1_8v;
852 mmc-hs400-enhanced-strobe;
856 sdhc1_opp_table: opp-table {
857 compatible = "operating-points-v2";
859 opp-100000000 {
860 opp-hz = /bits/ 64 <100000000>;
861 required-opps = <&rpmhpd_opp_low_svs>;
862 opp-peak-kBps = <1800000 600000>;
863 opp-avg-kBps = <100000 0>;
866 opp-384000000 {
867 opp-hz = /bits/ 64 <384000000>;
868 required-opps = <&rpmhpd_opp_nom>;
869 opp-peak-kBps = <5400000 1600000>;
870 opp-avg-kBps = <390000 0>;
876 compatible = "qcom,geni-se-qup";
878 clock-names = "m-ahb", "s-ahb";
881 #address-cells = <2>;
882 #size-cells = <2>;
888 compatible = "qcom,geni-i2c";
890 clock-names = "se";
892 pinctrl-names = "default";
893 pinctrl-0 = <&qup_i2c0_default>;
895 #address-cells = <1>;
896 #size-cells = <0>;
900 interconnect-names = "qup-core", "qup-config",
901 "qup-memory";
902 power-domains = <&rpmhpd SC7180_CX>;
903 required-opps = <&rpmhpd_opp_low_svs>;
908 compatible = "qcom,geni-spi";
910 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
915 #address-cells = <1>;
916 #size-cells = <0>;
917 power-domains = <&rpmhpd SC7180_CX>;
918 operating-points-v2 = <&qup_opp_table>;
921 interconnect-names = "qup-core", "qup-config";
926 compatible = "qcom,geni-uart";
928 clock-names = "se";
930 pinctrl-names = "default";
931 pinctrl-0 = <&qup_uart0_default>;
933 power-domains = <&rpmhpd SC7180_CX>;
934 operating-points-v2 = <&qup_opp_table>;
937 interconnect-names = "qup-core", "qup-config";
942 compatible = "qcom,geni-i2c";
944 clock-names = "se";
946 pinctrl-names = "default";
947 pinctrl-0 = <&qup_i2c1_default>;
949 #address-cells = <1>;
950 #size-cells = <0>;
954 interconnect-names = "qup-core", "qup-config",
955 "qup-memory";
956 power-domains = <&rpmhpd SC7180_CX>;
957 required-opps = <&rpmhpd_opp_low_svs>;
962 compatible = "qcom,geni-spi";
964 clock-names = "se";
966 pinctrl-names = "default";
967 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
969 #address-cells = <1>;
970 #size-cells = <0>;
971 power-domains = <&rpmhpd SC7180_CX>;
972 operating-points-v2 = <&qup_opp_table>;
975 interconnect-names = "qup-core", "qup-config";
980 compatible = "qcom,geni-uart";
982 clock-names = "se";
984 pinctrl-names = "default";
985 pinctrl-0 = <&qup_uart1_default>;
987 power-domains = <&rpmhpd SC7180_CX>;
988 operating-points-v2 = <&qup_opp_table>;
991 interconnect-names = "qup-core", "qup-config";
996 compatible = "qcom,geni-i2c";
998 clock-names = "se";
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&qup_i2c2_default>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1008 interconnect-names = "qup-core", "qup-config",
1009 "qup-memory";
1010 power-domains = <&rpmhpd SC7180_CX>;
1011 required-opps = <&rpmhpd_opp_low_svs>;
1016 compatible = "qcom,geni-uart";
1018 clock-names = "se";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_uart2_default>;
1023 power-domains = <&rpmhpd SC7180_CX>;
1024 operating-points-v2 = <&qup_opp_table>;
1027 interconnect-names = "qup-core", "qup-config";
1032 compatible = "qcom,geni-i2c";
1034 clock-names = "se";
1036 pinctrl-names = "default";
1037 pinctrl-0 = <&qup_i2c3_default>;
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1044 interconnect-names = "qup-core", "qup-config",
1045 "qup-memory";
1046 power-domains = <&rpmhpd SC7180_CX>;
1047 required-opps = <&rpmhpd_opp_low_svs>;
1052 compatible = "qcom,geni-spi";
1054 clock-names = "se";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 power-domains = <&rpmhpd SC7180_CX>;
1062 operating-points-v2 = <&qup_opp_table>;
1065 interconnect-names = "qup-core", "qup-config";
1070 compatible = "qcom,geni-uart";
1072 clock-names = "se";
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&qup_uart3_default>;
1077 power-domains = <&rpmhpd SC7180_CX>;
1078 operating-points-v2 = <&qup_opp_table>;
1081 interconnect-names = "qup-core", "qup-config";
1086 compatible = "qcom,geni-i2c";
1088 clock-names = "se";
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&qup_i2c4_default>;
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1098 interconnect-names = "qup-core", "qup-config",
1099 "qup-memory";
1100 power-domains = <&rpmhpd SC7180_CX>;
1101 required-opps = <&rpmhpd_opp_low_svs>;
1106 compatible = "qcom,geni-uart";
1108 clock-names = "se";
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&qup_uart4_default>;
1113 power-domains = <&rpmhpd SC7180_CX>;
1114 operating-points-v2 = <&qup_opp_table>;
1117 interconnect-names = "qup-core", "qup-config";
1122 compatible = "qcom,geni-i2c";
1124 clock-names = "se";
1126 pinctrl-names = "default";
1127 pinctrl-0 = <&qup_i2c5_default>;
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1134 interconnect-names = "qup-core", "qup-config",
1135 "qup-memory";
1136 power-domains = <&rpmhpd SC7180_CX>;
1137 required-opps = <&rpmhpd_opp_low_svs>;
1142 compatible = "qcom,geni-spi";
1144 clock-names = "se";
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 power-domains = <&rpmhpd SC7180_CX>;
1152 operating-points-v2 = <&qup_opp_table>;
1155 interconnect-names = "qup-core", "qup-config";
1160 compatible = "qcom,geni-uart";
1162 clock-names = "se";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_uart5_default>;
1167 power-domains = <&rpmhpd SC7180_CX>;
1168 operating-points-v2 = <&qup_opp_table>;
1171 interconnect-names = "qup-core", "qup-config";
1177 compatible = "qcom,geni-se-qup";
1179 clock-names = "m-ahb", "s-ahb";
1182 #address-cells = <2>;
1183 #size-cells = <2>;
1189 compatible = "qcom,geni-i2c";
1191 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_i2c6_default>;
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1201 interconnect-names = "qup-core", "qup-config",
1202 "qup-memory";
1203 power-domains = <&rpmhpd SC7180_CX>;
1204 required-opps = <&rpmhpd_opp_low_svs>;
1209 compatible = "qcom,geni-spi";
1211 clock-names = "se";
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 power-domains = <&rpmhpd SC7180_CX>;
1219 operating-points-v2 = <&qup_opp_table>;
1222 interconnect-names = "qup-core", "qup-config";
1227 compatible = "qcom,geni-uart";
1229 clock-names = "se";
1231 pinctrl-names = "default";
1232 pinctrl-0 = <&qup_uart6_default>;
1234 power-domains = <&rpmhpd SC7180_CX>;
1235 operating-points-v2 = <&qup_opp_table>;
1238 interconnect-names = "qup-core", "qup-config";
1243 compatible = "qcom,geni-i2c";
1245 clock-names = "se";
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&qup_i2c7_default>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1255 interconnect-names = "qup-core", "qup-config",
1256 "qup-memory";
1257 power-domains = <&rpmhpd SC7180_CX>;
1258 required-opps = <&rpmhpd_opp_low_svs>;
1263 compatible = "qcom,geni-uart";
1265 clock-names = "se";
1267 pinctrl-names = "default";
1268 pinctrl-0 = <&qup_uart7_default>;
1270 power-domains = <&rpmhpd SC7180_CX>;
1271 operating-points-v2 = <&qup_opp_table>;
1274 interconnect-names = "qup-core", "qup-config";
1279 compatible = "qcom,geni-i2c";
1281 clock-names = "se";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&qup_i2c8_default>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1291 interconnect-names = "qup-core", "qup-config",
1292 "qup-memory";
1293 power-domains = <&rpmhpd SC7180_CX>;
1294 required-opps = <&rpmhpd_opp_low_svs>;
1299 compatible = "qcom,geni-spi";
1301 clock-names = "se";
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308 power-domains = <&rpmhpd SC7180_CX>;
1309 operating-points-v2 = <&qup_opp_table>;
1312 interconnect-names = "qup-core", "qup-config";
1317 compatible = "qcom,geni-debug-uart";
1319 clock-names = "se";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_uart8_default>;
1324 power-domains = <&rpmhpd SC7180_CX>;
1325 operating-points-v2 = <&qup_opp_table>;
1328 interconnect-names = "qup-core", "qup-config";
1333 compatible = "qcom,geni-i2c";
1335 clock-names = "se";
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&qup_i2c9_default>;
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1345 interconnect-names = "qup-core", "qup-config",
1346 "qup-memory";
1347 power-domains = <&rpmhpd SC7180_CX>;
1348 required-opps = <&rpmhpd_opp_low_svs>;
1353 compatible = "qcom,geni-uart";
1355 clock-names = "se";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_uart9_default>;
1360 power-domains = <&rpmhpd SC7180_CX>;
1361 operating-points-v2 = <&qup_opp_table>;
1364 interconnect-names = "qup-core", "qup-config";
1369 compatible = "qcom,geni-i2c";
1371 clock-names = "se";
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&qup_i2c10_default>;
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1381 interconnect-names = "qup-core", "qup-config",
1382 "qup-memory";
1383 power-domains = <&rpmhpd SC7180_CX>;
1384 required-opps = <&rpmhpd_opp_low_svs>;
1389 compatible = "qcom,geni-spi";
1391 clock-names = "se";
1393 pinctrl-names = "default";
1394 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1398 power-domains = <&rpmhpd SC7180_CX>;
1399 operating-points-v2 = <&qup_opp_table>;
1402 interconnect-names = "qup-core", "qup-config";
1407 compatible = "qcom,geni-uart";
1409 clock-names = "se";
1411 pinctrl-names = "default";
1412 pinctrl-0 = <&qup_uart10_default>;
1414 power-domains = <&rpmhpd SC7180_CX>;
1415 operating-points-v2 = <&qup_opp_table>;
1418 interconnect-names = "qup-core", "qup-config";
1423 compatible = "qcom,geni-i2c";
1425 clock-names = "se";
1427 pinctrl-names = "default";
1428 pinctrl-0 = <&qup_i2c11_default>;
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1435 interconnect-names = "qup-core", "qup-config",
1436 "qup-memory";
1437 power-domains = <&rpmhpd SC7180_CX>;
1438 required-opps = <&rpmhpd_opp_low_svs>;
1443 compatible = "qcom,geni-spi";
1445 clock-names = "se";
1447 pinctrl-names = "default";
1448 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1452 power-domains = <&rpmhpd SC7180_CX>;
1453 operating-points-v2 = <&qup_opp_table>;
1456 interconnect-names = "qup-core", "qup-config";
1461 compatible = "qcom,geni-uart";
1463 clock-names = "se";
1465 pinctrl-names = "default";
1466 pinctrl-0 = <&qup_uart11_default>;
1468 power-domains = <&rpmhpd SC7180_CX>;
1469 operating-points-v2 = <&qup_opp_table>;
1472 interconnect-names = "qup-core", "qup-config";
1478 compatible = "qcom,sc7180-config-noc";
1480 #interconnect-cells = <2>;
1481 qcom,bcm-voters = <&apps_bcm_voter>;
1485 compatible = "qcom,sc7180-system-noc";
1487 #interconnect-cells = <2>;
1488 qcom,bcm-voters = <&apps_bcm_voter>;
1492 compatible = "qcom,sc7180-mc-virt";
1494 #interconnect-cells = <2>;
1495 qcom,bcm-voters = <&apps_bcm_voter>;
1499 compatible = "qcom,sc7180-qup-virt";
1501 #interconnect-cells = <2>;
1502 qcom,bcm-voters = <&apps_bcm_voter>;
1506 compatible = "qcom,sc7180-aggre1-noc";
1508 #interconnect-cells = <2>;
1509 qcom,bcm-voters = <&apps_bcm_voter>;
1513 compatible = "qcom,sc7180-aggre2-noc";
1515 #interconnect-cells = <2>;
1516 qcom,bcm-voters = <&apps_bcm_voter>;
1520 compatible = "qcom,sc7180-compute-noc";
1522 #interconnect-cells = <2>;
1523 qcom,bcm-voters = <&apps_bcm_voter>;
1527 compatible = "qcom,sc7180-mmss-noc";
1529 #interconnect-cells = <2>;
1530 qcom,bcm-voters = <&apps_bcm_voter>;
1534 compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
1535 "jedec,ufs-2.0";
1539 phy-names = "ufsphy";
1540 lanes-per-direction = <1>;
1541 #reset-cells = <1>;
1543 reset-names = "rst";
1545 power-domains = <&gcc UFS_PHY_GDSC>;
1549 clock-names = "core_clk",
1563 freq-table-hz = <50000000 200000000>,
1575 interconnect-names = "ufs-ddr", "cpu-ufs";
1583 compatible = "qcom,sc7180-qmp-ufs-phy";
1588 clock-names = "ref",
1591 power-domains = <&gcc UFS_PHY_GDSC>;
1593 reset-names = "ufsphy";
1594 #phy-cells = <0>;
1599 compatible = "qcom,sc7180-inline-crypto-engine",
1600 "qcom,inline-crypto-engine";
1605 ipa: ipa@1e40000 { label
1606 compatible = "qcom,sc7180-ipa";
1613 reg-names = "ipa-reg",
1614 "ipa-shared",
1617 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1621 interrupt-names = "ipa",
1623 "ipa-clock-query",
1624 "ipa-setup-ready";
1627 clock-names = "core";
1632 interconnect-names = "memory",
1638 qcom,smem-states = <&ipa_smp2p_out 0>,
1640 qcom,smem-state-names = "ipa-clock-enabled-valid",
1641 "ipa-clock-enabled";
1647 compatible = "qcom,tcsr-mutex";
1649 #hwlock-cells = <1>;
1653 compatible = "qcom,sc7180-tcsr", "syscon";
1658 compatible = "qcom,sc7180-tcsr", "syscon";
1663 compatible = "qcom,sc7180-pinctrl";
1667 reg-names = "west", "north", "south";
1669 gpio-controller;
1670 #gpio-cells = <2>;
1671 interrupt-controller;
1672 #interrupt-cells = <2>;
1673 gpio-ranges = <&tlmm 0 0 120>;
1674 wakeup-parent = <&pdc>;
1676 dp_hot_plug_det: dp-hot-plug-det-state {
1681 qspi_clk: qspi-clk-state {
1686 qspi_cs0: qspi-cs0-state {
1691 qspi_cs1: qspi-cs1-state {
1696 qspi_data0: qspi-data0-state {
1701 qspi_data1: qspi-data1-state {
1706 qspi_data23: qspi-data23-state {
1711 qup_i2c0_default: qup-i2c0-default-state {
1716 qup_i2c1_default: qup-i2c1-default-state {
1721 qup_i2c2_default: qup-i2c2-default-state {
1726 qup_i2c3_default: qup-i2c3-default-state {
1731 qup_i2c4_default: qup-i2c4-default-state {
1736 qup_i2c5_default: qup-i2c5-default-state {
1741 qup_i2c6_default: qup-i2c6-default-state {
1746 qup_i2c7_default: qup-i2c7-default-state {
1751 qup_i2c8_default: qup-i2c8-default-state {
1756 qup_i2c9_default: qup-i2c9-default-state {
1761 qup_i2c10_default: qup-i2c10-default-state {
1766 qup_i2c11_default: qup-i2c11-default-state {
1771 qup_spi0_spi: qup-spi0-spi-state {
1776 qup_spi0_cs: qup-spi0-cs-state {
1781 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1786 qup_spi1_spi: qup-spi1-spi-state {
1791 qup_spi1_cs: qup-spi1-cs-state {
1796 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1801 qup_spi3_spi: qup-spi3-spi-state {
1806 qup_spi3_cs: qup-spi3-cs-state {
1811 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1816 qup_spi5_spi: qup-spi5-spi-state {
1821 qup_spi5_cs: qup-spi5-cs-state {
1826 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1831 qup_spi6_spi: qup-spi6-spi-state {
1836 qup_spi6_cs: qup-spi6-cs-state {
1841 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1846 qup_spi8_spi: qup-spi8-spi-state {
1851 qup_spi8_cs: qup-spi8-cs-state {
1856 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1861 qup_spi10_spi: qup-spi10-spi-state {
1866 qup_spi10_cs: qup-spi10-cs-state {
1871 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1876 qup_spi11_spi: qup-spi11-spi-state {
1881 qup_spi11_cs: qup-spi11-cs-state {
1886 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1891 qup_uart0_default: qup-uart0-default-state {
1892 qup_uart0_cts: cts-pins {
1897 qup_uart0_rts: rts-pins {
1902 qup_uart0_tx: tx-pins {
1907 qup_uart0_rx: rx-pins {
1913 qup_uart1_default: qup-uart1-default-state {
1914 qup_uart1_cts: cts-pins {
1919 qup_uart1_rts: rts-pins {
1924 qup_uart1_tx: tx-pins {
1929 qup_uart1_rx: rx-pins {
1935 qup_uart2_default: qup-uart2-default-state {
1936 qup_uart2_tx: tx-pins {
1941 qup_uart2_rx: rx-pins {
1947 qup_uart3_default: qup-uart3-default-state {
1948 qup_uart3_cts: cts-pins {
1953 qup_uart3_rts: rts-pins {
1958 qup_uart3_tx: tx-pins {
1963 qup_uart3_rx: rx-pins {
1969 qup_uart4_default: qup-uart4-default-state {
1970 qup_uart4_tx: tx-pins {
1975 qup_uart4_rx: rx-pins {
1981 qup_uart5_default: qup-uart5-default-state {
1982 qup_uart5_cts: cts-pins {
1987 qup_uart5_rts: rts-pins {
1992 qup_uart5_tx: tx-pins {
1997 qup_uart5_rx: rx-pins {
2003 qup_uart6_default: qup-uart6-default-state {
2004 qup_uart6_cts: cts-pins {
2009 qup_uart6_rts: rts-pins {
2014 qup_uart6_tx: tx-pins {
2019 qup_uart6_rx: rx-pins {
2025 qup_uart7_default: qup-uart7-default-state {
2026 qup_uart7_tx: tx-pins {
2031 qup_uart7_rx: rx-pins {
2037 qup_uart8_default: qup-uart8-default-state {
2038 qup_uart8_tx: tx-pins {
2043 qup_uart8_rx: rx-pins {
2049 qup_uart9_default: qup-uart9-default-state {
2050 qup_uart9_tx: tx-pins {
2055 qup_uart9_rx: rx-pins {
2061 qup_uart10_default: qup-uart10-default-state {
2062 qup_uart10_cts: cts-pins {
2067 qup_uart10_rts: rts-pins {
2072 qup_uart10_tx: tx-pins {
2077 qup_uart10_rx: rx-pins {
2083 qup_uart11_default: qup-uart11-default-state {
2084 qup_uart11_cts: cts-pins {
2089 qup_uart11_rts: rts-pins {
2094 qup_uart11_tx: tx-pins {
2099 qup_uart11_rx: rx-pins {
2105 sec_mi2s_active: sec-mi2s-active-state {
2110 pri_mi2s_active: pri-mi2s-active-state {
2115 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2120 ter_mi2s_active: ter-mi2s-active-state {
2127 compatible = "qcom,sc7180-mpss-pas";
2130 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2136 interrupt-names = "wdog", "fatal", "ready", "handover",
2137 "stop-ack", "shutdown-ack";
2140 clock-names = "xo";
2142 power-domains = <&rpmhpd SC7180_CX>,
2145 power-domain-names = "cx", "mx", "mss";
2147 memory-region = <&mpss_mem>;
2151 qcom,smem-states = <&modem_smp2p_out 0>;
2152 qcom,smem-state-names = "stop";
2156 glink-edge {
2159 qcom,remote-pid = <1>;
2165 compatible = "qcom,adreno-618.0", "qcom,adreno";
2168 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 operating-points-v2 = <&gpu_opp_table>;
2174 #cooling-cells = <2>;
2176 nvmem-cells = <&gpu_speed_bin>;
2177 nvmem-cell-names = "speed_bin";
2180 interconnect-names = "gfx-mem";
2182 gpu_opp_table: opp-table {
2183 compatible = "operating-points-v2";
2185 opp-825000000 {
2186 opp-hz = /bits/ 64 <825000000>;
2187 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2188 opp-peak-kBps = <8532000>;
2189 opp-supported-hw = <0x04>;
2192 opp-800000000 {
2193 opp-hz = /bits/ 64 <800000000>;
2194 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2195 opp-peak-kBps = <8532000>;
2196 opp-supported-hw = <0x07>;
2199 opp-650000000 {
2200 opp-hz = /bits/ 64 <650000000>;
2201 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2202 opp-peak-kBps = <7216000>;
2203 opp-supported-hw = <0x07>;
2206 opp-565000000 {
2207 opp-hz = /bits/ 64 <565000000>;
2208 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2209 opp-peak-kBps = <5412000>;
2210 opp-supported-hw = <0x07>;
2213 opp-430000000 {
2214 opp-hz = /bits/ 64 <430000000>;
2215 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2216 opp-peak-kBps = <5412000>;
2217 opp-supported-hw = <0x07>;
2220 opp-355000000 {
2221 opp-hz = /bits/ 64 <355000000>;
2222 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2223 opp-peak-kBps = <3072000>;
2224 opp-supported-hw = <0x07>;
2227 opp-267000000 {
2228 opp-hz = /bits/ 64 <267000000>;
2229 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2230 opp-peak-kBps = <3072000>;
2231 opp-supported-hw = <0x07>;
2234 opp-180000000 {
2235 opp-hz = /bits/ 64 <180000000>;
2236 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2237 opp-peak-kBps = <1804000>;
2238 opp-supported-hw = <0x07>;
2244 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2246 #iommu-cells = <1>;
2247 #global-interrupts = <2>;
2261 clock-names = "bus", "iface";
2263 power-domains = <&gpucc CX_GDSC>;
2267 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupt-names = "hfi", "gmu";
2278 clock-names = "gmu", "cxo", "axi", "memnoc";
2279 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2280 power-domain-names = "cx", "gx";
2282 operating-points-v2 = <&gmu_opp_table>;
2284 gmu_opp_table: opp-table {
2285 compatible = "operating-points-v2";
2287 opp-200000000 {
2288 opp-hz = /bits/ 64 <200000000>;
2289 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2294 gpucc: clock-controller@5090000 {
2295 compatible = "qcom,sc7180-gpucc";
2300 clock-names = "bi_tcxo",
2303 #clock-cells = <1>;
2304 #reset-cells = <1>;
2305 #power-domain-cells = <1>;
2309 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2316 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg-names = "stm-base", "stm-stimulus-base";
2322 clock-names = "apb_pclk";
2324 out-ports {
2327 remote-endpoint = <&funnel0_in7>;
2334 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2338 clock-names = "apb_pclk";
2340 out-ports {
2343 remote-endpoint = <&merge_funnel_in0>;
2348 in-ports {
2349 #address-cells = <1>;
2350 #size-cells = <0>;
2355 remote-endpoint = <&stm_out>;
2362 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2366 clock-names = "apb_pclk";
2368 out-ports {
2371 remote-endpoint = <&merge_funnel_in1>;
2376 in-ports {
2377 #address-cells = <1>;
2378 #size-cells = <0>;
2383 remote-endpoint = <&apss_merge_funnel_out>;
2390 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2394 clock-names = "apb_pclk";
2396 out-ports {
2399 remote-endpoint = <&swao_funnel_in>;
2404 in-ports {
2405 #address-cells = <1>;
2406 #size-cells = <0>;
2411 remote-endpoint = <&funnel0_out>;
2418 remote-endpoint = <&funnel1_out>;
2425 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2429 clock-names = "apb_pclk";
2431 out-ports {
2434 remote-endpoint = <&etr_in>;
2439 in-ports {
2442 remote-endpoint = <&swao_replicator_out>;
2449 compatible = "arm,coresight-tmc", "arm,primecell";
2454 clock-names = "apb_pclk";
2455 arm,scatter-gather;
2457 in-ports {
2460 remote-endpoint = <&replicator_out>;
2467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2471 clock-names = "apb_pclk";
2473 out-ports {
2476 remote-endpoint = <&etf_in>;
2481 in-ports {
2482 #address-cells = <1>;
2483 #size-cells = <0>;
2488 remote-endpoint = <&merge_funnel_out>;
2495 compatible = "arm,coresight-tmc", "arm,primecell";
2499 clock-names = "apb_pclk";
2501 out-ports {
2504 remote-endpoint = <&swao_replicator_in>;
2509 in-ports {
2512 remote-endpoint = <&swao_funnel_out>;
2519 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2523 clock-names = "apb_pclk";
2524 qcom,replicator-loses-context;
2526 out-ports {
2529 remote-endpoint = <&replicator_in>;
2534 in-ports {
2537 remote-endpoint = <&etf_out>;
2544 compatible = "arm,coresight-etm4x", "arm,primecell";
2550 clock-names = "apb_pclk";
2551 arm,coresight-loses-context-with-cpu;
2552 qcom,skip-power-up;
2554 out-ports {
2557 remote-endpoint = <&apss_funnel_in0>;
2564 compatible = "arm,coresight-etm4x", "arm,primecell";
2570 clock-names = "apb_pclk";
2571 arm,coresight-loses-context-with-cpu;
2572 qcom,skip-power-up;
2574 out-ports {
2577 remote-endpoint = <&apss_funnel_in1>;
2584 compatible = "arm,coresight-etm4x", "arm,primecell";
2590 clock-names = "apb_pclk";
2591 arm,coresight-loses-context-with-cpu;
2592 qcom,skip-power-up;
2594 out-ports {
2597 remote-endpoint = <&apss_funnel_in2>;
2604 compatible = "arm,coresight-etm4x", "arm,primecell";
2610 clock-names = "apb_pclk";
2611 arm,coresight-loses-context-with-cpu;
2612 qcom,skip-power-up;
2614 out-ports {
2617 remote-endpoint = <&apss_funnel_in3>;
2624 compatible = "arm,coresight-etm4x", "arm,primecell";
2630 clock-names = "apb_pclk";
2631 arm,coresight-loses-context-with-cpu;
2632 qcom,skip-power-up;
2634 out-ports {
2637 remote-endpoint = <&apss_funnel_in4>;
2644 compatible = "arm,coresight-etm4x", "arm,primecell";
2650 clock-names = "apb_pclk";
2651 arm,coresight-loses-context-with-cpu;
2652 qcom,skip-power-up;
2654 out-ports {
2657 remote-endpoint = <&apss_funnel_in5>;
2664 compatible = "arm,coresight-etm4x", "arm,primecell";
2670 clock-names = "apb_pclk";
2671 arm,coresight-loses-context-with-cpu;
2672 qcom,skip-power-up;
2674 out-ports {
2677 remote-endpoint = <&apss_funnel_in6>;
2684 compatible = "arm,coresight-etm4x", "arm,primecell";
2690 clock-names = "apb_pclk";
2691 arm,coresight-loses-context-with-cpu;
2692 qcom,skip-power-up;
2694 out-ports {
2697 remote-endpoint = <&apss_funnel_in7>;
2704 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2708 clock-names = "apb_pclk";
2710 out-ports {
2713 remote-endpoint = <&apss_merge_funnel_in>;
2718 in-ports {
2719 #address-cells = <1>;
2720 #size-cells = <0>;
2725 remote-endpoint = <&etm0_out>;
2732 remote-endpoint = <&etm1_out>;
2739 remote-endpoint = <&etm2_out>;
2746 remote-endpoint = <&etm3_out>;
2753 remote-endpoint = <&etm4_out>;
2760 remote-endpoint = <&etm5_out>;
2767 remote-endpoint = <&etm6_out>;
2774 remote-endpoint = <&etm7_out>;
2781 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2785 clock-names = "apb_pclk";
2787 out-ports {
2790 remote-endpoint = <&funnel1_in4>;
2795 in-ports {
2798 remote-endpoint = <&apss_funnel_out>;
2805 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2811 interrupt-names = "hc_irq", "pwr_irq";
2816 clock-names = "iface", "core", "xo";
2820 interconnect-names = "sdhc-ddr","cpu-sdhc";
2821 power-domains = <&rpmhpd SC7180_CX>;
2822 operating-points-v2 = <&sdhc2_opp_table>;
2824 bus-width = <4>;
2828 sdhc2_opp_table: opp-table {
2829 compatible = "operating-points-v2";
2831 opp-100000000 {
2832 opp-hz = /bits/ 64 <100000000>;
2833 required-opps = <&rpmhpd_opp_low_svs>;
2834 opp-peak-kBps = <1800000 600000>;
2835 opp-avg-kBps = <100000 0>;
2838 opp-202000000 {
2839 opp-hz = /bits/ 64 <202000000>;
2840 required-opps = <&rpmhpd_opp_nom>;
2841 opp-peak-kBps = <5400000 1600000>;
2842 opp-avg-kBps = <200000 0>;
2848 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2851 #address-cells = <1>;
2852 #size-cells = <0>;
2856 clock-names = "iface", "core";
2859 interconnect-names = "qspi-config";
2860 power-domains = <&rpmhpd SC7180_CX>;
2861 operating-points-v2 = <&qspi_opp_table>;
2866 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 #phy-cells = <0>;
2872 clock-names = "cfg_ahb", "ref";
2875 nvmem-cells = <&qusb2p_hstx_trim>;
2879 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2888 clock-names = "aux",
2896 reset-names = "phy", "common";
2898 #clock-cells = <1>;
2899 #phy-cells = <1>;
2903 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2909 operating-points-v2 = <&cpu_bwmon_opp_table>;
2911 cpu_bwmon_opp_table: opp-table {
2912 compatible = "operating-points-v2";
2914 opp-0 {
2915 opp-peak-kBps = <2288000>;
2918 opp-1 {
2919 opp-peak-kBps = <4577000>;
2922 opp-2 {
2923 opp-peak-kBps = <7110000>;
2926 opp-3 {
2927 opp-peak-kBps = <9155000>;
2930 opp-4 {
2931 opp-peak-kBps = <12298000>;
2934 opp-5 {
2935 opp-peak-kBps = <14236000>;
2941 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2947 operating-points-v2 = <&llcc_bwmon_opp_table>;
2949 llcc_bwmon_opp_table: opp-table {
2950 compatible = "operating-points-v2";
2952 opp-0 {
2953 opp-peak-kBps = <1144000>;
2956 opp-1 {
2957 opp-peak-kBps = <1720000>;
2960 opp-2 {
2961 opp-peak-kBps = <2086000>;
2964 opp-3 {
2965 opp-peak-kBps = <2929000>;
2968 opp-4 {
2969 opp-peak-kBps = <3879000>;
2972 opp-5 {
2973 opp-peak-kBps = <5931000>;
2976 opp-6 {
2977 opp-peak-kBps = <6881000>;
2980 opp-7 {
2981 opp-peak-kBps = <8137000>;
2987 compatible = "qcom,sc7180-dc-noc";
2989 #interconnect-cells = <2>;
2990 qcom,bcm-voters = <&apps_bcm_voter>;
2993 system-cache-controller@9200000 {
2994 compatible = "qcom,sc7180-llcc";
2996 reg-names = "llcc0_base", "llcc_broadcast_base";
3001 compatible = "qcom,sc7180-gem-noc";
3003 #interconnect-cells = <2>;
3004 qcom,bcm-voters = <&apps_bcm_voter>;
3008 compatible = "qcom,sc7180-npu-noc";
3010 #interconnect-cells = <2>;
3011 qcom,bcm-voters = <&apps_bcm_voter>;
3015 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 #address-cells = <2>;
3019 #size-cells = <2>;
3021 dma-ranges;
3028 clock-names = "cfg_noc",
3034 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3036 assigned-clock-rates = <19200000>, <150000000>;
3038 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3043 interrupt-names = "pwr_event",
3049 power-domains = <&gcc USB30_PRIM_GDSC>;
3050 required-opps = <&rpmhpd_opp_nom>;
3056 interconnect-names = "usb-ddr", "apps-usb";
3058 wakeup-source;
3067 snps,parkmode-disable-ss-quirk;
3068 snps,dis-u1-entry-quirk;
3069 snps,dis-u2-entry-quirk;
3071 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed = "super-speed";
3076 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc7180-venus";
3080 power-domains = <&videocc VENUS_GDSC>,
3083 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = <&venus_opp_table>;
3090 clock-names = "core", "iface", "bus",
3093 memory-region = <&venus_mem>;
3096 interconnect-names = "video-mem", "cpu-cfg";
3098 video-decoder {
3099 compatible = "venus-decoder";
3102 video-encoder {
3103 compatible = "venus-encoder";
3106 venus_opp_table: opp-table {
3107 compatible = "operating-points-v2";
3109 opp-150000000 {
3110 opp-hz = /bits/ 64 <150000000>;
3111 required-opps = <&rpmhpd_opp_low_svs>;
3114 opp-270000000 {
3115 opp-hz = /bits/ 64 <270000000>;
3116 required-opps = <&rpmhpd_opp_svs>;
3119 opp-340000000 {
3120 opp-hz = /bits/ 64 <340000000>;
3121 required-opps = <&rpmhpd_opp_svs_l1>;
3124 opp-434000000 {
3125 opp-hz = /bits/ 64 <434000000>;
3126 required-opps = <&rpmhpd_opp_nom>;
3129 opp-500000097 {
3130 opp-hz = /bits/ 64 <500000097>;
3131 required-opps = <&rpmhpd_opp_turbo>;
3136 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc7180-videocc";
3140 clock-names = "bi_tcxo";
3141 #clock-cells = <1>;
3142 #reset-cells = <1>;
3143 #power-domain-cells = <1>;
3147 compatible = "qcom,sc7180-camnoc-virt";
3149 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&apps_bcm_voter>;
3153 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc7180-camcc";
3159 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>;
3161 #reset-cells = <1>;
3162 #power-domain-cells = <1>;
3165 mdss: display-subsystem@ae00000 {
3166 compatible = "qcom,sc7180-mdss";
3168 reg-names = "mdss";
3170 power-domains = <&dispcc MDSS_GDSC>;
3175 clock-names = "iface", "ahb", "core";
3178 interrupt-controller;
3179 #interrupt-cells = <1>;
3185 interconnect-names = "mdp0-mem",
3186 "cpu-cfg";
3190 #address-cells = <2>;
3191 #size-cells = <2>;
3196 mdp: display-controller@ae01000 {
3197 compatible = "qcom,sc7180-dpu";
3200 reg-names = "mdp", "vbif";
3208 clock-names = "bus", "iface", "rot", "lut", "core",
3210 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3213 assigned-clock-rates = <19200000>,
3216 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains = <&rpmhpd SC7180_CX>;
3219 interrupt-parent = <&mdss>;
3223 #address-cells = <1>;
3224 #size-cells = <0>;
3229 remote-endpoint = <&mdss_dsi0_in>;
3236 remote-endpoint = <&dp_in>;
3241 mdp_opp_table: opp-table {
3242 compatible = "operating-points-v2";
3244 opp-200000000 {
3245 opp-hz = /bits/ 64 <200000000>;
3246 required-opps = <&rpmhpd_opp_low_svs>;
3249 opp-300000000 {
3250 opp-hz = /bits/ 64 <300000000>;
3251 required-opps = <&rpmhpd_opp_svs>;
3254 opp-345000000 {
3255 opp-hz = /bits/ 64 <345000000>;
3256 required-opps = <&rpmhpd_opp_svs_l1>;
3259 opp-460000000 {
3260 opp-hz = /bits/ 64 <460000000>;
3261 required-opps = <&rpmhpd_opp_nom>;
3267 compatible = "qcom,sc7180-dsi-ctrl",
3268 "qcom,mdss-dsi-ctrl";
3270 reg-names = "dsi_ctrl";
3272 interrupt-parent = <&mdss>;
3281 clock-names = "byte",
3288 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3290 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3293 operating-points-v2 = <&dsi_opp_table>;
3294 power-domains = <&rpmhpd SC7180_CX>;
3298 #address-cells = <1>;
3299 #size-cells = <0>;
3304 #address-cells = <1>;
3305 #size-cells = <0>;
3310 remote-endpoint = <&dpu_intf1_out>;
3321 dsi_opp_table: opp-table {
3322 compatible = "operating-points-v2";
3324 opp-187500000 {
3325 opp-hz = /bits/ 64 <187500000>;
3326 required-opps = <&rpmhpd_opp_low_svs>;
3329 opp-300000000 {
3330 opp-hz = /bits/ 64 <300000000>;
3331 required-opps = <&rpmhpd_opp_svs>;
3334 opp-358000000 {
3335 opp-hz = /bits/ 64 <358000000>;
3336 required-opps = <&rpmhpd_opp_svs_l1>;
3342 compatible = "qcom,dsi-phy-10nm";
3346 reg-names = "dsi_phy",
3350 #clock-cells = <1>;
3351 #phy-cells = <0>;
3355 clock-names = "iface", "ref";
3360 mdss_dp: displayport-controller@ae90000 {
3361 compatible = "qcom,sc7180-dp";
3370 interrupt-parent = <&mdss>;
3378 clock-names = "core_iface", "core_aux", "ctrl_link",
3380 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3382 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3385 phy-names = "dp";
3387 operating-points-v2 = <&dp_opp_table>;
3388 power-domains = <&rpmhpd SC7180_CX>;
3390 #sound-dai-cells = <0>;
3393 #address-cells = <1>;
3394 #size-cells = <0>;
3398 remote-endpoint = <&dpu_intf0_out>;
3408 dp_opp_table: opp-table {
3409 compatible = "operating-points-v2";
3411 opp-160000000 {
3412 opp-hz = /bits/ 64 <160000000>;
3413 required-opps = <&rpmhpd_opp_low_svs>;
3416 opp-270000000 {
3417 opp-hz = /bits/ 64 <270000000>;
3418 required-opps = <&rpmhpd_opp_svs>;
3421 opp-540000000 {
3422 opp-hz = /bits/ 64 <540000000>;
3423 required-opps = <&rpmhpd_opp_svs_l1>;
3426 opp-810000000 {
3427 opp-hz = /bits/ 64 <810000000>;
3428 required-opps = <&rpmhpd_opp_nom>;
3434 dispcc: clock-controller@af00000 {
3435 compatible = "qcom,sc7180-dispcc";
3443 clock-names = "bi_tcxo",
3449 #clock-cells = <1>;
3450 #reset-cells = <1>;
3451 #power-domain-cells = <1>;
3454 pdc: interrupt-controller@b220000 {
3455 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3457 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3458 #interrupt-cells = <2>;
3459 interrupt-parent = <&intc>;
3460 interrupt-controller;
3463 pdc_reset: reset-controller@b2e0000 {
3464 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3466 #reset-cells = <1>;
3469 tsens0: thermal-sensor@c263000 {
3470 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3476 interrupt-names = "uplow","critical";
3477 #thermal-sensor-cells = <1>;
3480 tsens1: thermal-sensor@c265000 {
3481 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3487 interrupt-names = "uplow","critical";
3488 #thermal-sensor-cells = <1>;
3491 aoss_reset: reset-controller@c2a0000 {
3492 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3494 #reset-cells = <1>;
3497 aoss_qmp: power-management@c300000 {
3498 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3503 #clock-cells = <0>;
3507 compatible = "qcom,rpmh-stats";
3512 compatible = "qcom,spmi-pmic-arb";
3518 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3519 interrupt-names = "periph_irq";
3520 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3523 #address-cells = <2>;
3524 #size-cells = <0>;
3525 interrupt-controller;
3526 #interrupt-cells = <4>;
3530 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3533 #address-cells = <1>;
3534 #size-cells = <1>;
3538 pil-reloc@94c {
3539 compatible = "qcom,pil-reloc-info";
3545 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3547 #iommu-cells = <2>;
3548 #global-interrupts = <1>;
3630 dma-coherent;
3633 intc: interrupt-controller@17a00000 {
3634 compatible = "arm,gic-v3";
3635 #address-cells = <2>;
3636 #size-cells = <2>;
3638 #interrupt-cells = <3>;
3639 interrupt-controller;
3644 msi-controller@17a40000 {
3645 compatible = "arm,gic-v3-its";
3646 msi-controller;
3647 #msi-cells = <1>;
3654 compatible = "qcom,sc7180-apss-shared",
3655 "qcom,sdm845-apss-shared";
3657 #mbox-cells = <1>;
3661 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3668 #address-cells = <1>;
3669 #size-cells = <1>;
3671 compatible = "arm,armv7-timer-mem";
3675 frame-number = <0>;
3683 frame-number = <1>;
3690 frame-number = <2>;
3697 frame-number = <3>;
3704 frame-number = <4>;
3711 frame-number = <5>;
3718 frame-number = <6>;
3726 compatible = "qcom,sc7180-rpmh-apps-rsc", "qcom,rpmh-rsc";
3730 reg-names = "drv-0", "drv-1", "drv-2";
3734 qcom,tcs-offset = <0xd00>;
3735 qcom,drv-id = <2>;
3736 qcom,tcs-config = <ACTIVE_TCS 2>,
3740 power-domains = <&cluster_pd>;
3742 rpmhcc: clock-controller {
3743 compatible = "qcom,sc7180-rpmh-clk";
3745 clock-names = "xo";
3746 #clock-cells = <1>;
3749 rpmhpd: power-controller {
3750 compatible = "qcom,sc7180-rpmhpd";
3751 #power-domain-cells = <1>;
3752 operating-points-v2 = <&rpmhpd_opp_table>;
3754 rpmhpd_opp_table: opp-table {
3755 compatible = "operating-points-v2";
3758 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3762 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3766 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3770 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3774 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3778 opp-level = <224>;
3782 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3786 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3790 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3794 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3798 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3803 apps_bcm_voter: bcm-voter {
3804 compatible = "qcom,bcm-voter";
3809 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3813 clock-names = "xo", "alternate";
3815 #interconnect-cells = <1>;
3819 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3821 reg-names = "freq-domain0", "freq-domain1";
3824 clock-names = "xo", "alternate";
3826 #freq-domain-cells = <1>;
3827 #clock-cells = <1>;
3831 compatible = "qcom,wcn3990-wifi";
3833 reg-names = "membase";
3848 memory-region = <&wlan_mem>;
3849 qcom,msa-fixed-perm;
3854 compatible = "qcom,sc7180-adsp-pas";
3857 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3862 interrupt-names = "wdog",
3866 "stop-ack";
3869 clock-names = "xo";
3871 power-domains = <&rpmhpd SC7180_LCX>,
3873 power-domain-names = "lcx", "lmx";
3876 qcom,smem-states = <&adsp_smp2p_out 0>;
3877 qcom,smem-state-names = "stop";
3881 glink-edge {
3884 qcom,remote-pid = <2>;
3888 compatible = "qcom,apr-v2";
3889 qcom,glink-channels = "apr_audio_svc";
3891 #address-cells = <1>;
3892 #size-cells = <0>;
3897 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3903 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3906 compatible = "qcom,q6afe-dais";
3907 #address-cells = <1>;
3908 #size-cells = <0>;
3909 #sound-dai-cells = <1>;
3912 q6afecc: clock-controller {
3913 compatible = "qcom,q6afe-clocks";
3914 #clock-cells = <2>;
3921 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3924 compatible = "qcom,q6asm-dais";
3925 #address-cells = <1>;
3926 #size-cells = <0>;
3927 #sound-dai-cells = <1>;
3935 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3938 compatible = "qcom,q6adm-routing";
3939 #sound-dai-cells = <0>;
3946 qcom,glink-channels = "fastrpcglink-apps-dsp";
3948 #address-cells = <1>;
3949 #size-cells = <0>;
3951 compute-cb@3 {
3952 compatible = "qcom,fastrpc-compute-cb";
3957 compute-cb@4 {
3958 compatible = "qcom,fastrpc-compute-cb";
3963 compute-cb@5 {
3964 compatible = "qcom,fastrpc-compute-cb";
3973 lpasscc: clock-controller@62d00000 {
3974 compatible = "qcom,sc7180-lpasscorecc";
3977 reg-names = "lpass_core_cc", "lpass_audio_cc";
3980 clock-names = "iface", "bi_tcxo";
3981 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3982 #clock-cells = <1>;
3983 #power-domain-cells = <1>;
3989 compatible = "qcom,sc7180-lpass-cpu";
3992 reg-names = "lpass-hdmiif", "lpass-lpaif";
3998 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3999 required-opps = <&rpmhpd_opp_nom>;
4010 clock-names = "pcnoc-sway-clk", "audio-core",
4011 "mclk0", "pcnoc-mport-clk",
4012 "mi2s-bit-clk0", "mi2s-bit-clk1";
4015 #sound-dai-cells = <1>;
4016 #address-cells = <1>;
4017 #size-cells = <0>;
4021 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4024 lpass_hm: clock-controller@63000000 {
4025 compatible = "qcom,sc7180-lpasshm";
4029 clock-names = "iface", "bi_tcxo";
4030 power-domains = <&rpmhpd SC7180_CX>;
4032 #clock-cells = <1>;
4033 #power-domain-cells = <1>;
4039 thermal-zones {
4040 cpu0_thermal: cpu0-thermal {
4041 polling-delay-passive = <250>;
4043 thermal-sensors = <&tsens0 1>;
4044 sustainable-power = <1052>;
4047 cpu0_alert0: trip-point0 {
4053 cpu0_alert1: trip-point1 {
4059 cpu0_crit: cpu-crit {
4066 cooling-maps {
4069 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4088 cpu1_thermal: cpu1-thermal {
4089 polling-delay-passive = <250>;
4091 thermal-sensors = <&tsens0 2>;
4092 sustainable-power = <1052>;
4095 cpu1_alert0: trip-point0 {
4101 cpu1_alert1: trip-point1 {
4107 cpu1_crit: cpu-crit {
4114 cooling-maps {
4117 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4136 cpu2_thermal: cpu2-thermal {
4137 polling-delay-passive = <250>;
4139 thermal-sensors = <&tsens0 3>;
4140 sustainable-power = <1052>;
4143 cpu2_alert0: trip-point0 {
4149 cpu2_alert1: trip-point1 {
4155 cpu2_crit: cpu-crit {
4162 cooling-maps {
4165 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4184 cpu3_thermal: cpu3-thermal {
4185 polling-delay-passive = <250>;
4187 thermal-sensors = <&tsens0 4>;
4188 sustainable-power = <1052>;
4191 cpu3_alert0: trip-point0 {
4197 cpu3_alert1: trip-point1 {
4203 cpu3_crit: cpu-crit {
4210 cooling-maps {
4213 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4232 cpu4_thermal: cpu4-thermal {
4233 polling-delay-passive = <250>;
4235 thermal-sensors = <&tsens0 5>;
4236 sustainable-power = <1052>;
4239 cpu4_alert0: trip-point0 {
4245 cpu4_alert1: trip-point1 {
4251 cpu4_crit: cpu-crit {
4258 cooling-maps {
4261 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4280 cpu5_thermal: cpu5-thermal {
4281 polling-delay-passive = <250>;
4283 thermal-sensors = <&tsens0 6>;
4284 sustainable-power = <1052>;
4287 cpu5_alert0: trip-point0 {
4293 cpu5_alert1: trip-point1 {
4299 cpu5_crit: cpu-crit {
4306 cooling-maps {
4309 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4328 cpu6_thermal: cpu6-thermal {
4329 polling-delay-passive = <250>;
4331 thermal-sensors = <&tsens0 9>;
4332 sustainable-power = <1425>;
4335 cpu6_alert0: trip-point0 {
4341 cpu6_alert1: trip-point1 {
4347 cpu6_crit: cpu-crit {
4354 cooling-maps {
4357 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4362 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4368 cpu7_thermal: cpu7-thermal {
4369 polling-delay-passive = <250>;
4371 thermal-sensors = <&tsens0 10>;
4372 sustainable-power = <1425>;
4375 cpu7_alert0: trip-point0 {
4381 cpu7_alert1: trip-point1 {
4387 cpu7_crit: cpu-crit {
4394 cooling-maps {
4397 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4402 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4408 cpu8_thermal: cpu8-thermal {
4409 polling-delay-passive = <250>;
4411 thermal-sensors = <&tsens0 11>;
4412 sustainable-power = <1425>;
4415 cpu8_alert0: trip-point0 {
4421 cpu8_alert1: trip-point1 {
4427 cpu8_crit: cpu-crit {
4434 cooling-maps {
4437 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4442 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4448 cpu9_thermal: cpu9-thermal {
4449 polling-delay-passive = <250>;
4451 thermal-sensors = <&tsens0 12>;
4452 sustainable-power = <1425>;
4455 cpu9_alert0: trip-point0 {
4461 cpu9_alert1: trip-point1 {
4467 cpu9_crit: cpu-crit {
4474 cooling-maps {
4477 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4482 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4488 aoss0-thermal {
4489 polling-delay-passive = <250>;
4491 thermal-sensors = <&tsens0 0>;
4494 aoss0_alert0: trip-point0 {
4500 aoss0_crit: aoss0-crit {
4508 cpuss0-thermal {
4509 polling-delay-passive = <250>;
4511 thermal-sensors = <&tsens0 7>;
4514 cpuss0_alert0: trip-point0 {
4519 cpuss0_crit: cluster0-crit {
4527 cpuss1-thermal {
4528 polling-delay-passive = <250>;
4530 thermal-sensors = <&tsens0 8>;
4533 cpuss1_alert0: trip-point0 {
4538 cpuss1_crit: cluster0-crit {
4546 gpuss0-thermal {
4547 polling-delay-passive = <250>;
4549 thermal-sensors = <&tsens0 13>;
4552 gpuss0_alert0: trip-point0 {
4558 gpuss0_crit: gpuss0-crit {
4565 cooling-maps {
4568 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4573 gpuss1-thermal {
4574 polling-delay-passive = <250>;
4576 thermal-sensors = <&tsens0 14>;
4579 gpuss1_alert0: trip-point0 {
4585 gpuss1_crit: gpuss1-crit {
4592 cooling-maps {
4595 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4600 aoss1-thermal {
4601 polling-delay-passive = <250>;
4603 thermal-sensors = <&tsens1 0>;
4606 aoss1_alert0: trip-point0 {
4612 aoss1_crit: aoss1-crit {
4620 cwlan-thermal {
4621 polling-delay-passive = <250>;
4623 thermal-sensors = <&tsens1 1>;
4626 cwlan_alert0: trip-point0 {
4632 cwlan_crit: cwlan-crit {
4640 audio-thermal {
4641 polling-delay-passive = <250>;
4643 thermal-sensors = <&tsens1 2>;
4646 audio_alert0: trip-point0 {
4652 audio_crit: audio-crit {
4660 ddr-thermal {
4661 polling-delay-passive = <250>;
4663 thermal-sensors = <&tsens1 3>;
4666 ddr_alert0: trip-point0 {
4672 ddr_crit: ddr-crit {
4680 q6-hvx-thermal {
4681 polling-delay-passive = <250>;
4683 thermal-sensors = <&tsens1 4>;
4686 q6_hvx_alert0: trip-point0 {
4692 q6_hvx_crit: q6-hvx-crit {
4700 camera-thermal {
4701 polling-delay-passive = <250>;
4703 thermal-sensors = <&tsens1 5>;
4706 camera_alert0: trip-point0 {
4712 camera_crit: camera-crit {
4720 mdm-core-thermal {
4721 polling-delay-passive = <250>;
4723 thermal-sensors = <&tsens1 6>;
4726 mdm_alert0: trip-point0 {
4732 mdm_crit: mdm-crit {
4740 mdm-dsp-thermal {
4741 polling-delay-passive = <250>;
4743 thermal-sensors = <&tsens1 7>;
4746 mdm_dsp_alert0: trip-point0 {
4752 mdm_dsp_crit: mdm-dsp-crit {
4760 npu-thermal {
4761 polling-delay-passive = <250>;
4763 thermal-sensors = <&tsens1 8>;
4766 npu_alert0: trip-point0 {
4772 npu_crit: npu-crit {
4780 video-thermal {
4781 polling-delay-passive = <250>;
4783 thermal-sensors = <&tsens1 9>;
4786 video_alert0: trip-point0 {
4792 video_crit: video-crit {
4802 compatible = "arm,armv8-timer";