Lines Matching +full:opp +full:- +full:810000000
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sar2130p-gcc.h>
8 #include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
9 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/interconnect/qcom,icc.h>
13 #include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/thermal/thermal.h>
24 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
32 xo_board: xo-board {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <19200000>;
38 sleep_clk: sleep-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <32764>;
46 #address-cells = <2>;
47 #size-cells = <0>;
51 compatible = "arm,cortex-a55";
54 enable-method = "psci";
55 next-level-cache = <&l2_0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 power-domains = <&cpu_pd0>;
58 power-domain-names = "psci";
59 #cooling-cells = <2>;
61 l2_0: l2-cache {
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&l3_0>;
67 l3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
77 compatible = "arm,cortex-a55";
80 enable-method = "psci";
81 next-level-cache = <&l2_100>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
83 power-domains = <&cpu_pd1>;
84 power-domain-names = "psci";
85 #cooling-cells = <2>;
87 l2_100: l2-cache {
89 cache-level = <2>;
90 cache-unified;
91 next-level-cache = <&l3_0>;
97 compatible = "arm,cortex-a55";
100 enable-method = "psci";
101 next-level-cache = <&l2_200>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 power-domains = <&cpu_pd2>;
104 power-domain-names = "psci";
105 #cooling-cells = <2>;
107 l2_200: l2-cache {
109 cache-level = <2>;
110 cache-unified;
111 next-level-cache = <&l3_0>;
117 compatible = "arm,cortex-a55";
120 enable-method = "psci";
121 next-level-cache = <&l2_300>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 power-domains = <&cpu_pd3>;
124 power-domain-names = "psci";
125 #cooling-cells = <2>;
127 l2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&l3_0>;
135 cpu-map {
155 idle-states {
156 entry-method = "psci";
158 cpu_sleep_0: cpu-sleep-0-0 {
159 compatible = "arm,idle-state";
160 idle-state-name = "silver-power-collapse";
161 arm,psci-suspend-param = <0x40000003>;
162 entry-latency-us = <549>;
163 exit-latency-us = <901>;
164 min-residency-us = <1774>;
165 local-timer-stop;
168 cpu_sleep_1: cpu-sleep-0-1 {
169 compatible = "arm,idle-state";
170 idle-state-name = "silver-rail-power-collapse";
171 arm,psci-suspend-param = <0x40000004>;
172 entry-latency-us = <702>;
173 exit-latency-us = <915>;
174 min-residency-us = <4001>;
175 local-timer-stop;
179 domain-idle-states {
180 cluster_sleep_0: cluster-sleep-0 {
181 compatible = "domain-idle-state";
182 arm,psci-suspend-param = <0x41000044>;
183 entry-latency-us = <2752>;
184 exit-latency-us = <3048>;
185 min-residency-us = <6118>;
188 cluster_sleep_1: cluster-sleep-1 {
189 compatible = "domain-idle-state";
190 arm,psci-suspend-param = <0x41002344>;
191 entry-latency-us = <3263>;
192 exit-latency-us = <4562>;
193 min-residency-us = <8467>;
196 cluster_sleep_2: cluster-sleep-2 {
197 compatible = "domain-idle-state";
198 arm,psci-suspend-param = <0x4100c344>;
199 entry-latency-us = <3638>;
200 exit-latency-us = <6562>;
201 min-residency-us = <9862>;
208 compatible = "qcom,scm-sar2130p", "qcom,scm";
209 qcom,dload-mode = <&tcsr_mutex 0x13000>;
215 clk_virt: interconnect-0 {
216 compatible = "qcom,sar2130p-clk-virt";
217 #interconnect-cells = <2>;
218 qcom,bcm-voters = <&apps_bcm_voter>;
221 mc_virt: interconnect-1 {
222 compatible = "qcom,sar2130p-mc-virt";
223 #interconnect-cells = <2>;
224 qcom,bcm-voters = <&apps_bcm_voter>;
234 compatible = "arm,armv8-pmuv3";
239 compatible = "arm,psci-1.0";
242 cpu_pd0: power-domain-cpu0 {
243 #power-domain-cells = <0>;
244 power-domains = <&cluster_pd>;
245 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
248 cpu_pd1: power-domain-cpu1 {
249 #power-domain-cells = <0>;
250 power-domains = <&cluster_pd>;
251 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
254 cpu_pd2: power-domain-cpu2 {
255 #power-domain-cells = <0>;
256 power-domains = <&cluster_pd>;
257 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
260 cpu_pd3: power-domain-cpu3 {
261 #power-domain-cells = <0>;
262 power-domains = <&cluster_pd>;
263 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
266 cluster_pd: power-domain-cpu-cluster0 {
267 #power-domain-cells = <0>;
268 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>;
272 reserved_memory: reserved-memory {
273 #address-cells = <2>;
274 #size-cells = <2>;
279 no-map;
282 xbl_dt_log_mem: xbl-dt-log@80600000 {
284 no-map;
287 xbl_ramdump_mem: xbl-ramdump@80640000 {
289 no-map;
292 aop_image_mem: aop-image@80800000 {
294 no-map;
297 aop_cmd_db_mem: aop-cmd-db@80860000 {
298 compatible = "qcom,cmd-db";
300 no-map;
303 aop_config_mem: aop-config@80880000 {
305 no-map;
308 tme_crash_dump_mem: tme-crash-dump@808a0000 {
310 no-map;
313 tme_log_mem: tme-log@808e0000 {
315 no-map;
318 uefi_log_mem: uefi-log@808e4000 {
320 no-map;
323 secdata_apss_mem: secdata-apss@808ff000 {
325 no-map;
332 no-map;
335 cpucp_fw_mem: cpucp-fw@80b00000 {
337 no-map;
340 helios_ram_dump_mem: helios-ram-dump@80c00000 {
342 no-map;
347 no-map;
352 no-map;
357 no-map;
362 no-map;
365 ipa_fw_mem: ipa-fw@8a300000 {
367 no-map;
370 ipa_gsi_mem: ipa-gsi@8a3a0000 {
372 no-map;
375 gpu_micro_code_mem: gpu-micro-code@8a31a000 {
377 no-map;
382 no-map;
385 xbl_sc_mem: xbl-sc@a6e00000 {
386 no-map;
390 global_sync_mem: global-sync@a6f00000 {
391 no-map;
395 tz_stat_mem: tz-stat@e8800000 {
396 no-map;
401 no-map;
406 no-map;
410 trusted_apps_mem: trusted-apps@e9300000 {
411 no-map;
416 smp2p-adsp {
419 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
425 qcom,local-pid = <0>;
426 qcom,remote-pid = <2>;
428 smp2p_adsp_out: master-kernel {
429 qcom,entry-name = "master-kernel";
430 #qcom,smem-state-cells = <1>;
433 smp2p_adsp_in: slave-kernel {
434 qcom,entry-name = "slave-kernel";
435 interrupt-controller;
436 #interrupt-cells = <2>;
440 smp2p-cdsp {
443 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
449 qcom,local-pid = <0>;
450 qcom,remote-pid = <5>;
452 smp2p_cdsp_out: master-kernel {
453 qcom,entry-name = "master-kernel";
454 #qcom,smem-state-cells = <1>;
457 smp2p_cdsp_in: slave-kernel {
458 qcom,entry-name = "slave-kernel";
459 interrupt-controller;
460 #interrupt-cells = <2>;
465 compatible = "simple-bus";
466 #address-cells = <2>;
467 #size-cells = <2>;
469 dma-ranges = <0 0 0 0 0x10 0>;
471 gcc: clock-controller@100000 {
472 compatible = "qcom,sar2130p-gcc";
474 #clock-cells = <1>;
475 #reset-cells = <1>;
476 #power-domain-cells = <1>;
485 compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5";
488 reg-names = "hc", "cqhci";
493 interrupt-names = "hc_irq", "pwr_irq";
498 clock-names = "iface", "core", "xo";
503 interconnect-names = "sdhc-ddr","cpu-sdhc";
504 power-domains = <&rpmhpd RPMHPD_CX>;
505 operating-points-v2 = <&sdhc1_opp_table>;
507 pinctrl-0 = <&sdc1_default>;
508 pinctrl-1 = <&sdc1_sleep>;
509 pinctrl-names = "default", "sleep";
511 bus-width = <8>;
512 non-removable;
513 supports-cqe;
515 mmc-ddr-1_8v;
516 mmc-hs200-1_8v;
517 mmc-hs400-1_8v;
518 mmc-hs400-enhanced-strobe;
522 sdhc1_opp_table: opp-table {
523 compatible = "operating-points-v2";
525 opp-100000000 {
526 opp-hz = /bits/ 64 <100000000>;
527 required-opps = <&rpmhpd_opp_low_svs>;
528 opp-peak-kBps = <500000 200000>;
529 opp-avg-kBps = <104000 0>;
532 opp-384000000 {
533 opp-hz = /bits/ 64 <384000000>;
534 required-opps = <&rpmhpd_opp_nom>;
535 opp-peak-kBps = <2500000 1000000>;
536 opp-avg-kBps = <400000 0>;
541 gpi_dma0: dma-controller@900000 {
542 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
556 #dma-cells = <3>;
557 dma-channels = <12>;
558 dma-channel-mask = <0x7e>;
565 compatible = "qcom,geni-se-qup";
567 clock-names = "m-ahb", "s-ahb";
573 interconnect-names = "qup-core";
574 #address-cells = <2>;
575 #size-cells = <2>;
581 compatible = "qcom,geni-i2c";
583 clock-names = "se";
585 pinctrl-0 = <&qup_i2c0_data_clk>;
586 pinctrl-names = "default";
588 #address-cells = <1>;
589 #size-cells = <0>;
596 interconnect-names = "qup-core", "qup-config", "qup-memory";
599 dma-names = "tx", "rx";
605 compatible = "qcom,geni-spi";
607 clock-names = "se";
610 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>;
611 pinctrl-names = "default";
618 interconnect-names = "qup-core", "qup-config", "qup-memory";
621 dma-names = "tx", "rx";
622 #address-cells = <1>;
623 #size-cells = <0>;
629 compatible = "qcom,geni-i2c";
631 clock-names = "se";
633 pinctrl-0 = <&qup_i2c1_data_clk>;
634 pinctrl-names = "default";
636 #address-cells = <1>;
637 #size-cells = <0>;
644 interconnect-names = "qup-core", "qup-config", "qup-memory";
647 dma-names = "tx", "rx";
653 compatible = "qcom,geni-spi";
655 clock-names = "se";
658 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
659 pinctrl-names = "default";
666 interconnect-names = "qup-core", "qup-config", "qup-memory";
669 dma-names = "tx", "rx";
670 #address-cells = <1>;
671 #size-cells = <0>;
677 compatible = "qcom,geni-i2c";
679 clock-names = "se";
681 pinctrl-0 = <&qup_i2c2_data_clk>;
682 pinctrl-names = "default";
684 #address-cells = <1>;
685 #size-cells = <0>;
692 interconnect-names = "qup-core", "qup-config", "qup-memory";
695 dma-names = "tx", "rx";
701 compatible = "qcom,geni-spi";
703 clock-names = "se";
706 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
707 pinctrl-names = "default";
714 interconnect-names = "qup-core", "qup-config", "qup-memory";
717 dma-names = "tx", "rx";
718 #address-cells = <1>;
719 #size-cells = <0>;
726 compatible = "qcom,geni-i2c";
728 clock-names = "se";
730 pinctrl-0 = <&qup_i2c3_data_clk>;
731 pinctrl-names = "default";
733 #address-cells = <1>;
734 #size-cells = <0>;
741 interconnect-names = "qup-core", "qup-config", "qup-memory";
744 dma-names = "tx", "rx";
750 compatible = "qcom,geni-spi";
752 clock-names = "se";
755 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>;
756 pinctrl-names = "default";
763 interconnect-names = "qup-core", "qup-config", "qup-memory";
766 dma-names = "tx", "rx";
767 #address-cells = <1>;
768 #size-cells = <0>;
774 compatible = "qcom,geni-i2c";
776 clock-names = "se";
778 pinctrl-0 = <&qup_i2c4_data_clk>;
779 pinctrl-names = "default";
781 #address-cells = <1>;
782 #size-cells = <0>;
789 interconnect-names = "qup-core", "qup-config", "qup-memory";
792 dma-names = "tx", "rx";
798 compatible = "qcom,geni-spi";
800 clock-names = "se";
803 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>;
804 pinctrl-names = "default";
811 interconnect-names = "qup-core", "qup-config", "qup-memory";
814 dma-names = "tx", "rx";
815 #address-cells = <1>;
816 #size-cells = <0>;
822 compatible = "qcom,geni-i2c";
824 clock-names = "se";
826 pinctrl-0 = <&qup_i2c5_data_clk>;
827 pinctrl-names = "default";
829 #address-cells = <1>;
830 #size-cells = <0>;
837 interconnect-names = "qup-core", "qup-config", "qup-memory";
840 dma-names = "tx", "rx";
846 compatible = "qcom,geni-spi";
848 clock-names = "se";
851 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
852 pinctrl-names = "default";
859 interconnect-names = "qup-core", "qup-config", "qup-memory";
862 dma-names = "tx", "rx";
863 #address-cells = <1>;
864 #size-cells = <0>;
870 gpi_dma1: dma-controller@a00000 {
871 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
872 #dma-cells = <3>;
886 dma-channels = <12>;
887 dma-channel-mask = <0x7e>;
894 compatible = "qcom,geni-se-qup";
896 clock-names = "m-ahb", "s-ahb";
902 interconnect-names = "qup-core";
903 #address-cells = <2>;
904 #size-cells = <2>;
910 compatible = "qcom,geni-i2c";
912 clock-names = "se";
914 pinctrl-0 = <&qup_i2c6_data_clk>;
915 pinctrl-names = "default";
917 #address-cells = <1>;
918 #size-cells = <0>;
925 interconnect-names = "qup-core", "qup-config", "qup-memory";
928 dma-names = "tx", "rx";
934 compatible = "qcom,geni-spi";
936 clock-names = "se";
939 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
940 pinctrl-names = "default";
947 interconnect-names = "qup-core", "qup-config", "qup-memory";
950 dma-names = "tx", "rx";
951 #address-cells = <1>;
952 #size-cells = <0>;
958 compatible = "qcom,geni-i2c";
960 clock-names = "se";
962 pinctrl-0 = <&qup_i2c7_data_clk>;
963 pinctrl-names = "default";
965 #address-cells = <1>;
966 #size-cells = <0>;
973 interconnect-names = "qup-core", "qup-config", "qup-memory";
976 dma-names = "tx", "rx";
982 compatible = "qcom,geni-spi";
984 clock-names = "se";
987 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
988 pinctrl-names = "default";
995 interconnect-names = "qup-core", "qup-config", "qup-memory";
998 dma-names = "tx", "rx";
999 #address-cells = <1>;
1000 #size-cells = <0>;
1006 compatible = "qcom,geni-uart";
1008 clock-names = "se";
1010 pinctrl-0 = <&qup_uart7_default>;
1011 pinctrl-names = "default";
1017 interconnect-names = "qup-core", "qup-config";
1023 compatible = "qcom,geni-i2c";
1025 clock-names = "se";
1027 pinctrl-0 = <&qup_i2c8_data_clk>;
1028 pinctrl-names = "default";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1038 interconnect-names = "qup-core", "qup-config", "qup-memory";
1041 dma-names = "tx", "rx";
1047 compatible = "qcom,geni-spi";
1049 clock-names = "se";
1052 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1053 pinctrl-names = "default";
1060 interconnect-names = "qup-core", "qup-config", "qup-memory";
1063 dma-names = "tx", "rx";
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1071 compatible = "qcom,geni-i2c";
1073 clock-names = "se";
1075 pinctrl-0 = <&qup_i2c9_data_clk>;
1076 pinctrl-names = "default";
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1086 interconnect-names = "qup-core", "qup-config", "qup-memory";
1089 dma-names = "tx", "rx";
1095 compatible = "qcom,geni-spi";
1097 clock-names = "se";
1100 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1101 pinctrl-names = "default";
1108 interconnect-names = "qup-core", "qup-config", "qup-memory";
1111 dma-names = "tx", "rx";
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1119 compatible = "qcom,geni-i2c";
1121 clock-names = "se";
1123 pinctrl-0 = <&qup_i2c10_data_clk>;
1124 pinctrl-names = "default";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1134 interconnect-names = "qup-core", "qup-config", "qup-memory";
1137 dma-names = "tx", "rx";
1143 compatible = "qcom,geni-spi";
1145 clock-names = "se";
1148 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1149 pinctrl-names = "default";
1156 interconnect-names = "qup-core", "qup-config", "qup-memory";
1159 dma-names = "tx", "rx";
1160 #address-cells = <1>;
1161 #size-cells = <0>;
1167 compatible = "qcom,geni-i2c";
1169 clock-names = "se";
1171 pinctrl-0 = <&qup_i2c11_data_clk>;
1172 pinctrl-names = "default";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1182 interconnect-names = "qup-core", "qup-config", "qup-memory";
1185 dma-names = "tx", "rx";
1191 compatible = "qcom,geni-spi";
1193 clock-names = "se";
1196 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1197 pinctrl-names = "default";
1204 interconnect-names = "qup-core", "qup-config", "qup-memory";
1207 dma-names = "tx", "rx";
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1215 compatible = "qcom,geni-debug-uart";
1217 clock-names = "se";
1219 pinctrl-0 = <&qup_uart11_default>;
1220 pinctrl-names = "default";
1226 interconnect-names = "qup-core",
1227 "qup-config";
1234 compatible = "qcom,sar2130p-config-noc";
1236 #interconnect-cells = <2>;
1237 qcom,bcm-voters = <&apps_bcm_voter>;
1241 compatible = "qcom,sar2130p-system-noc";
1244 #interconnect-cells = <2>;
1245 qcom,bcm-voters = <&apps_bcm_voter>;
1249 compatible = "qcom,sar2130p-pcie-anoc";
1253 #interconnect-cells = <2>;
1254 qcom,bcm-voters = <&apps_bcm_voter>;
1258 compatible = "qcom,sar2130p-mmss-noc";
1260 #interconnect-cells = <2>;
1261 qcom,bcm-voters = <&apps_bcm_voter>;
1266 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
1273 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1274 #address-cells = <3>;
1275 #size-cells = <2>;
1278 bus-range = <0x00 0xff>;
1280 dma-coherent;
1282 linux,pci-domain = <0>;
1283 num-lanes = <2>;
1294 interrupt-names = "msi0",
1303 #interrupt-cells = <1>;
1304 interrupt-map-mask = <0 0 0 0x7>;
1305 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1317 clock-names = "aux",
1329 interconnect-names = "pcie-mem", "cpu-pcie";
1331 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1335 reset-names = "pci";
1337 power-domains = <&gcc PCIE_0_GDSC>;
1340 phy-names = "pciephy";
1347 bus-range = <0x01 0xff>;
1349 #address-cells = <3>;
1350 #size-cells = <2>;
1356 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
1364 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1368 reset-names = "phy";
1370 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1371 assigned-clock-rates = <100000000>;
1373 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1375 #clock-cells = <0>;
1376 clock-output-names = "pcie0_pipe_clk";
1378 #phy-cells = <0>;
1385 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
1392 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1393 #address-cells = <3>;
1394 #size-cells = <2>;
1397 bus-range = <0x00 0xff>;
1399 dma-coherent;
1401 linux,pci-domain = <1>;
1402 num-lanes = <2>;
1413 interrupt-names = "msi0",
1422 #interrupt-cells = <1>;
1423 interrupt-map-mask = <0 0 0 0x7>;
1424 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1438 clock-names = "aux",
1448 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1449 assigned-clock-rates = <19200000>;
1455 interconnect-names = "pcie-mem", "cpu-pcie";
1457 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1462 reset-names = "pci", "link_down";
1464 power-domains = <&gcc PCIE_1_GDSC>;
1467 phy-names = "pciephy";
1474 bus-range = <0x01 0xff>;
1476 #address-cells = <3>;
1477 #size-cells = <2>;
1482 pcie1_ep: pcie-ep@1c08000 {
1483 compatible = "qcom,sar2130p-pcie-ep";
1491 reg-names = "parf",
1508 clock-names = "aux",
1521 interrupt-names = "global",
1529 interconnect-names = "pcie-mem",
1530 "cpu-pcie";
1533 reset-names = "core";
1534 power-domains = <&gcc PCIE_1_GDSC>;
1536 phy-names = "pciephy";
1538 num-lanes = <2>;
1544 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
1552 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1556 reset-names = "phy";
1558 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1559 assigned-clock-rates = <100000000>;
1561 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1563 #clock-cells = <0>;
1564 clock-output-names = "pcie1_pipe_clk";
1566 #phy-cells = <0>;
1572 compatible = "qcom,tcsr-mutex";
1575 #hwlock-cells = <1>;
1578 tcsr: clock-controller@1fc0000 {
1579 compatible = "qcom,sar2130p-tcsr", "syscon";
1582 #clock-cells = <1>;
1583 #reset-cells = <1>;
1587 compatible = "qcom,sar2130p-adsp-pas";
1590 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1595 interrupt-names = "wdog", "fatal", "ready",
1596 "handover", "stop-ack";
1599 clock-names = "xo";
1601 power-domains = <&rpmhpd RPMHPD_LCX>,
1603 power-domain-names = "lcx", "lmx";
1605 memory-region = <&adsp_mem>;
1609 qcom,smem-states = <&smp2p_adsp_out 0>;
1610 qcom,smem-state-names = "stop";
1614 remoteproc_adsp_glink: glink-edge {
1615 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1622 qcom,remote-pid = <2>;
1626 qcom,glink-channels = "adsp_apps";
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1635 #sound-dai-cells = <0>;
1636 qcom,protection-domain = "avs/audio",
1640 compatible = "qcom,q6apm-dais";
1645 compatible = "qcom,q6apm-lpass-dais";
1646 #sound-dai-cells = <1>;
1653 qcom,protection-domain = "avs/audio",
1656 q6prmcc: clock-controller {
1657 compatible = "qcom,q6prm-lpass-clocks";
1658 #clock-cells = <2>;
1665 qcom,glink-channels = "fastrpcglink-apps-dsp";
1667 qcom,non-secure-domain;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1671 compute-cb@3 {
1672 compatible = "qcom,fastrpc-compute-cb";
1677 compute-cb@4 {
1678 compatible = "qcom,fastrpc-compute-cb";
1683 compute-cb@5 {
1684 compatible = "qcom,fastrpc-compute-cb";
1689 compute-cb@6 {
1690 compatible = "qcom,fastrpc-compute-cb";
1699 compatible = "qcom,adreno-621.0", "qcom,adreno";
1703 reg-names = "kgsl_3d0_reg_memory",
1711 operating-points-v2 = <&gpu_opp_table>;
1715 nvmem-cells = <&gpu_speed_bin>;
1716 nvmem-cell-names = "speed_bin";
1717 #cooling-cells = <2>;
1721 gpu_zap_shader: zap-shader {
1722 memory-region = <&gpu_micro_code_mem>;
1725 gpu_opp_table: opp-table {
1726 compatible = "operating-points-v2";
1728 opp-843000000 {
1729 opp-hz = /bits/ 64 <843000000>;
1730 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1731 opp-supported-hw = <0x1>;
1734 opp-780000000 {
1735 opp-hz = /bits/ 64 <780000000>;
1736 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1737 opp-supported-hw = <0x1>;
1740 opp-644000000 {
1741 opp-hz = /bits/ 64 <644000000>;
1742 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1743 opp-supported-hw = <0x3>;
1746 opp-570000000 {
1747 opp-hz = /bits/ 64 <570000000>;
1748 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1749 opp-supported-hw = <0x3>;
1752 opp-450000000 {
1753 opp-hz = /bits/ 64 <450000000>;
1754 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1755 opp-supported-hw = <0x3>;
1758 opp-320000000 {
1759 opp-hz = /bits/ 64 <320000000>;
1760 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1761 opp-supported-hw = <0x3>;
1764 opp-235000000 {
1765 opp-hz = /bits/ 64 <235000000>;
1766 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
1767 opp-supported-hw = <0x3>;
1773 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu";
1777 reg-names = "gmu", "rscc", "gmu_pdc";
1781 interrupt-names = "hfi", "gmu";
1789 clock-names = "ahb",
1796 power-domains = <&gpucc GPU_CX_GDSC>,
1798 power-domain-names = "cx",
1805 operating-points-v2 = <&gmu_opp_table>;
1807 gmu_opp_table: opp-table {
1808 compatible = "operating-points-v2";
1810 opp-220000000 {
1811 opp-hz = /bits/ 64 <220000000>;
1812 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1815 opp-550000000 {
1816 opp-hz = /bits/ 64 <550000000>;
1817 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1822 gpucc: clock-controller@3d90000 {
1823 compatible = "qcom,sar2130p-gpucc";
1830 #clock-cells = <1>;
1831 #reset-cells = <1>;
1832 #power-domain-cells = <1>;
1836 compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu",
1837 "qcom,smmu-500", "arm,mmu-500";
1839 #iommu-cells = <2>;
1840 #global-interrupts = <1>;
1855 clock-names = "hlos",
1859 power-domains = <&gpucc GPU_CX_GDSC>;
1860 dma-coherent;
1864 compatible = "qcom,sar2130p-snps-eusb2-phy",
1865 "qcom,sm8550-snps-eusb2-phy";
1867 #phy-cells = <0>;
1870 clock-names = "ref";
1878 compatible = "qcom,sar2130p-qmp-usb3-dp-phy";
1885 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1887 power-domains = <&gcc USB3_PHY_GDSC>;
1891 reset-names = "phy", "common";
1893 #clock-cells = <1>;
1894 #phy-cells = <1>;
1896 orientation-switch;
1901 #address-cells = <1>;
1902 #size-cells = <0>;
1915 remote-endpoint = <&usb_1_dwc3_ss>;
1923 remote-endpoint = <&mdss_dp0_out>;
1930 compatible = "qcom,sar2130p-dwc3", "qcom,dwc3";
1932 #address-cells = <2>;
1933 #size-cells = <2>;
1942 clock-names = "cfg_noc",
1949 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1951 assigned-clock-rates = <19200000>, <200000000>;
1953 interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1958 interrupt-names = "pwr_event",
1964 power-domains = <&gcc USB30_PRIM_GDSC>;
1965 required-opps = <&rpmhpd_opp_nom>;
1973 interconnect-names = "usb-ddr", "apps-usb";
1984 phy-names = "usb2-phy", "usb3-phy";
1986 snps,has-lpm-erratum;
1987 snps,hird-threshold = /bits/ 8 <0x0>;
1988 snps,is-utmi-l1-suspend;
1989 snps,dis-u1-entry-quirk;
1990 snps,dis-u2-entry-quirk;
1993 snps,parkmode-disable-ss-quirk;
1995 tx-fifo-resize;
1996 dma-coherent;
1997 usb-role-switch;
2000 #address-cells = <1>;
2001 #size-cells = <0>;
2014 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
2021 mdss: display-subsystem@ae00000 {
2022 compatible = "qcom,sar2130p-mdss";
2024 reg-names = "mdss";
2027 interrupt-controller;
2028 #interrupt-cells = <1>;
2037 power-domains = <&dispcc MDSS_GDSC>;
2043 interconnect-names = "mdp0-mem", "cpu-cfg";
2047 #address-cells = <2>;
2048 #size-cells = <2>;
2053 mdss_mdp: display-controller@ae01000 {
2054 compatible = "qcom,sar2130p-dpu";
2057 reg-names = "mdp",
2060 interrupt-parent = <&mdss>;
2069 clock-names = "bus",
2076 power-domains = <&rpmhpd RPMHPD_MMCX>;
2078 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2079 assigned-clock-rates = <19200000>;
2081 operating-points-v2 = <&mdp_opp_table>;
2084 #address-cells = <1>;
2085 #size-cells = <0>;
2091 remote-endpoint = <&mdss_dsi0_in>;
2099 remote-endpoint = <&mdss_dsi1_in>;
2107 remote-endpoint = <&mdss_dp0_in>;
2112 mdp_opp_table: opp-table {
2113 compatible = "operating-points-v2";
2115 opp-200000000 {
2116 opp-hz = /bits/ 64 <200000000>;
2117 required-opps = <&rpmhpd_opp_low_svs>;
2120 opp-325000000 {
2121 opp-hz = /bits/ 64 <325000000>;
2122 required-opps = <&rpmhpd_opp_svs>;
2125 opp-514000000 {
2126 opp-hz = /bits/ 64 <514000000>;
2127 required-opps = <&rpmhpd_opp_turbo>;
2132 mdss_dp0: displayport-controller@ae90000 {
2133 compatible = "qcom,sar2130p-dp",
2134 "qcom,sm8350-dp";
2140 interrupt-parent = <&mdss>;
2147 clock-names = "core_iface",
2153 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2155 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2159 phy-names = "dp";
2161 #sound-dai-cells = <0>;
2163 operating-points-v2 = <&dp_opp_table>;
2164 power-domains = <&rpmhpd RPMHPD_MMCX>;
2169 #address-cells = <1>;
2170 #size-cells = <0>;
2176 remote-endpoint = <&dpu_intf0_out>;
2184 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
2189 dp_opp_table: opp-table {
2190 compatible = "operating-points-v2";
2192 opp-162000000 {
2193 opp-hz = /bits/ 64 <162000000>;
2194 required-opps = <&rpmhpd_opp_low_svs_d1>;
2197 opp-270000000 {
2198 opp-hz = /bits/ 64 <270000000>;
2199 required-opps = <&rpmhpd_opp_low_svs>;
2202 opp-540000000 {
2203 opp-hz = /bits/ 64 <540000000>;
2204 required-opps = <&rpmhpd_opp_svs_l1>;
2207 opp-810000000 {
2208 opp-hz = /bits/ 64 <810000000>;
2209 required-opps = <&rpmhpd_opp_nom>;
2215 compatible = "qcom,sar2130p-dsi-ctrl",
2216 "qcom,mdss-dsi-ctrl";
2218 reg-names = "dsi_ctrl";
2220 interrupt-parent = <&mdss>;
2229 clock-names = "byte",
2236 power-domains = <&rpmhpd RPMHPD_MMCX>;
2238 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2240 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2243 operating-points-v2 = <&mdss_dsi_opp_table>;
2246 phy-names = "dsi";
2248 #address-cells = <1>;
2249 #size-cells = <0>;
2254 #address-cells = <1>;
2255 #size-cells = <0>;
2260 remote-endpoint = <&dpu_intf1_out>;
2271 mdss_dsi_opp_table: opp-table {
2272 compatible = "operating-points-v2";
2274 opp-187500000 {
2275 opp-hz = /bits/ 64 <187500000>;
2276 required-opps = <&rpmhpd_opp_low_svs>;
2279 opp-300000000 {
2280 opp-hz = /bits/ 64 <300000000>;
2281 required-opps = <&rpmhpd_opp_svs>;
2284 opp-358000000 {
2285 opp-hz = /bits/ 64 <358000000>;
2286 required-opps = <&rpmhpd_opp_nom>;
2292 compatible = "qcom,sar2130p-dsi-phy-5nm";
2296 reg-names = "dsi_phy",
2302 clock-names = "iface", "ref";
2304 #clock-cells = <1>;
2305 #phy-cells = <0>;
2311 compatible = "qcom,sar2130p-dsi-ctrl",
2312 "qcom,mdss-dsi-ctrl";
2314 reg-names = "dsi_ctrl";
2316 interrupt-parent = <&mdss>;
2325 clock-names = "byte",
2332 power-domains = <&rpmhpd RPMHPD_MMCX>;
2334 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2336 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2339 operating-points-v2 = <&mdss_dsi_opp_table>;
2342 phy-names = "dsi";
2344 #address-cells = <1>;
2345 #size-cells = <0>;
2350 #address-cells = <1>;
2351 #size-cells = <0>;
2356 remote-endpoint = <&dpu_intf2_out>;
2369 compatible = "qcom,sar2130p-dsi-phy-5nm";
2373 reg-names = "dsi_phy",
2379 clock-names = "iface", "ref";
2381 #clock-cells = <1>;
2382 #phy-cells = <0>;
2388 dispcc: clock-controller@af00000 {
2389 compatible = "qcom,sar2130p-dispcc";
2407 power-domains = <&rpmhpd RPMHPD_MMCX>;
2408 #clock-cells = <1>;
2409 #reset-cells = <1>;
2410 #power-domain-cells = <1>;
2413 pdc: interrupt-controller@b220000 {
2414 compatible = "qcom,sar2130p-pdc", "qcom,pdc";
2416 qcom,pdc-ranges = <0 480 94>,
2420 #interrupt-cells = <2>;
2421 interrupt-parent = <&intc>;
2422 interrupt-controller;
2425 aoss_qmp: power-management@c300000 {
2426 compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp";
2428 interrupt-parent = <&ipcc>;
2429 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2433 #clock-cells = <0>;
2436 tsens0: thermal-sensor@c263000 {
2437 compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2";
2443 interrupt-names = "uplow", "critical";
2444 #thermal-sensor-cells = <1>;
2448 compatible = "qcom,rpmh-stats";
2453 compatible = "qcom,sar2130p-spmi-pmic-arb",
2454 "qcom,x1e80100-spmi-pmic-arb";
2458 reg-names = "core", "chnls", "obsrvr";
2463 #address-cells = <2>;
2464 #size-cells = <2>;
2470 reg-names = "cnfg", "intr";
2472 interrupt-names = "periph_irq";
2473 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2474 interrupt-controller;
2475 #interrupt-cells = <4>;
2477 #address-cells = <2>;
2478 #size-cells = <0>;
2483 compatible = "qcom,sar2130p-ipcc", "qcom,ipcc";
2487 interrupt-controller;
2488 #interrupt-cells = <3>;
2490 #mbox-cells = <2>;
2494 compatible = "qcom,sar2130p-tlmm";
2497 gpio-controller;
2498 #gpio-cells = <2>;
2499 interrupt-controller;
2500 #interrupt-cells = <2>;
2501 gpio-ranges = <&tlmm 0 0 156>;
2502 wakeup-parent = <&pdc>;
2504 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2508 drive-strength = <2>;
2509 bias-pull-up;
2512 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2516 drive-strength = <2>;
2517 bias-pull-up;
2520 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2524 drive-strength = <2>;
2525 bias-pull-up;
2528 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2532 drive-strength = <2>;
2533 bias-pull-up;
2536 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2540 drive-strength = <2>;
2541 bias-pull-up;
2544 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2548 drive-strength = <2>;
2549 bias-pull-up;
2552 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2556 drive-strength = <2>;
2557 bias-pull-up;
2560 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
2564 drive-strength = <2>;
2565 bias-pull-up;
2568 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2572 drive-strength = <2>;
2573 bias-pull-up;
2576 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2580 drive-strength = <2>;
2581 bias-pull-up;
2584 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2588 drive-strength = <2>;
2589 bias-pull-up;
2592 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
2596 drive-strength = <2>;
2597 bias-pull-up;
2600 qup_spi0_cs0: qup-spi0-cs0-state {
2603 drive-strength = <2>;
2604 bias-disable;
2607 qup_spi0_cs1: qup-spi0-cs1-state {
2610 drive-strength = <2>;
2611 bias-disable;
2614 qup_spi0_data_clk: qup-spi0-data-clk-state {
2618 drive-strength = <2>;
2619 bias-disable;
2622 qup_spi1_cs: qup-spi1-cs-state {
2625 drive-strength = <2>;
2626 bias-disable;
2629 qup_spi1_data_clk: qup-spi1-data-clk-state {
2633 drive-strength = <2>;
2634 bias-disable;
2637 qup_spi2_cs: qup-spi2-cs-state {
2640 drive-strength = <2>;
2641 bias-disable;
2644 qup_spi2_data_clk: qup-spi2-data-clk-state {
2648 drive-strength = <2>;
2649 bias-disable;
2652 qup_spi3_cs0: qup-spi3-cs0-state {
2655 drive-strength = <2>;
2656 bias-disable;
2659 qup_spi3_cs1: qup-spi3-cs1-state {
2662 drive-strength = <2>;
2663 bias-disable;
2666 qup_spi3_data_clk: qup-spi3-data-clk-state {
2670 drive-strength = <2>;
2671 bias-disable;
2674 qup_spi4_cs0: qup-spi4-cs0-state {
2677 drive-strength = <2>;
2678 bias-disable;
2681 qup_spi4_cs1: qup-spi4-cs1-state {
2684 drive-strength = <2>;
2685 bias-disable;
2688 qup_spi4_data_clk: qup-spi4-data-clk-state {
2692 drive-strength = <2>;
2693 bias-disable;
2696 qup_spi5_cs: qup-spi5-cs-state {
2699 drive-strength = <2>;
2700 bias-disable;
2703 qup_spi5_data_clk: qup-spi5-data-clk-state {
2707 drive-strength = <2>;
2708 bias-disable;
2711 qup_spi6_cs: qup-spi6-cs-state {
2714 drive-strength = <2>;
2715 bias-disable;
2718 qup_spi6_data_clk: qup-spi6-data-clk-state {
2722 drive-strength = <2>;
2723 bias-disable;
2726 qup_spi7_cs: qup-spi7-cs-state {
2729 drive-strength = <2>;
2730 bias-disable;
2733 qup_spi7_data_clk: qup-spi7-data-clk-state {
2737 drive-strength = <2>;
2738 bias-disable;
2741 qup_spi8_cs: qup-spi8-cs-state {
2744 drive-strength = <2>;
2745 bias-disable;
2748 qup_spi8_data_clk: qup-spi8-data-clk-state {
2752 drive-strength = <2>;
2753 bias-disable;
2756 qup_spi9_cs: qup-spi9-cs-state {
2759 drive-strength = <2>;
2760 bias-disable;
2763 qup_spi9_data_clk: qup-spi9-data-clk-state {
2767 drive-strength = <2>;
2768 bias-disable;
2771 qup_spi10_cs: qup-spi10-cs-state {
2774 drive-strength = <2>;
2775 bias-disable;
2778 qup_spi10_data_clk: qup-spi10-data-clk-state {
2782 drive-strength = <2>;
2783 bias-disable;
2786 qup_spi11_cs: qup-spi11-cs-state {
2789 drive-strength = <2>;
2790 bias-disable;
2793 qup_spi11_data_clk: qup-spi11-data-clk-state {
2797 drive-strength = <2>;
2798 bias-disable;
2801 qup_uart7_default: qup-uart7-default-state {
2802 cts-pins {
2805 drive-strength = <2>;
2806 bias-disable;
2809 rts-pins {
2812 drive-strength = <2>;
2813 bias-pull-down;
2816 rx-pins {
2819 drive-strength = <2>;
2820 bias-pull-down;
2823 tx-pins {
2826 drive-strength = <2>;
2827 bias-pull-up;
2831 qup_uart11_default: qup-uart11-default-state {
2834 drive-strength = <2>;
2835 bias-disable;
2838 sdc1_default: sdc1-default-state {
2839 clk-pins {
2841 drive-strength = <16>;
2842 bias-disable;
2845 cmd-pins {
2847 drive-strength = <10>;
2848 bias-pull-up;
2851 data-pins {
2853 drive-strength = <10>;
2854 bias-pull-up;
2857 rclk-pins {
2859 bias-pull-down;
2863 sdc1_sleep: sdc1-sleep-state {
2864 clk-pins {
2866 drive-strength = <2>;
2867 bias-disable;
2870 cmd-pins {
2872 drive-strength = <2>;
2873 bias-pull-up;
2876 data-pins {
2878 drive-strength = <2>;
2879 bias-pull-up;
2882 rclk-pins {
2884 bias-pull-down;
2890 compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2892 #iommu-cells = <2>;
2893 #global-interrupts = <1>;
2991 dma-coherent;
2994 intc: interrupt-controller@17200000 {
2995 compatible = "arm,gic-v3";
2996 #interrupt-cells = <3>;
2997 interrupt-controller;
2998 #redistributor-regions = <1>;
2999 redistributor-stride = <0x0 0x20000>;
3003 #address-cells = <2>;
3004 #size-cells = <2>;
3007 gic_its: msi-controller@17240000 {
3008 compatible = "arm,gic-v3-its";
3010 msi-controller;
3011 #msi-cells = <1>;
3017 compatible = "qcom,rpmh-rsc";
3021 reg-names = "drv-0", "drv-1", "drv-2";
3025 qcom,tcs-offset = <0xd00>;
3026 qcom,drv-id = <2>;
3027 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3029 power-domains = <&cluster_pd>;
3031 apps_bcm_voter: bcm-voter {
3032 compatible = "qcom,bcm-voter";
3035 rpmhcc: clock-controller {
3036 compatible = "qcom,sar2130p-rpmh-clk";
3037 #clock-cells = <1>;
3038 clock-names = "xo";
3042 rpmhpd: power-controller {
3043 compatible = "qcom,sar2130p-rpmhpd";
3044 #power-domain-cells = <1>;
3045 operating-points-v2 = <&rpmhpd_opp_table>;
3047 rpmhpd_opp_table: opp-table {
3048 compatible = "operating-points-v2";
3051 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3055 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3059 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3063 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3067 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3071 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3075 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3079 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3083 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3090 compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss";
3092 reg-names = "freq-domain0";
3094 clock-names = "xo", "alternate";
3096 interrupt-names = "dcvsh-irq-0";
3097 #freq-domain-cells = <1>;
3098 #clock-cells = <1>;
3102 compatible = "qcom,sar2130p-gem-noc";
3104 #interconnect-cells = <2>;
3105 qcom,bcm-voters = <&apps_bcm_voter>;
3109 * Bootloader expects just cache-controller node instead of
3110 * the typical system-cache-controller
3112 llcc: cache-controller@19200000 {
3113 compatible = "qcom,sar2130p-llcc";
3120 reg-names = "llcc0_base",
3130 compatible = "qcom,sar2130p-qfprom", "qcom,qfprom";
3132 #address-cells = <1>;
3133 #size-cells = <1>;
3134 read-only;
3136 gpu_speed_bin: gpu-speed-bin@119 {
3143 compatible = "qcom,sar2130p-nsp-noc";
3145 #interconnect-cells = <2>;
3146 qcom,bcm-voters = <&apps_bcm_voter>;
3150 compatible = "qcom,sar2130p-lpass-ag-noc";
3152 #interconnect-cells = <1>;
3153 qcom,bcm-voters = <&apps_bcm_voter>;
3158 compatible = "arm,armv8-timer";
3166 thermal-zones {
3167 aoss0-thermal {
3168 thermal-sensors = <&tsens0 0>;
3171 trip-point0 {
3177 aoss0-critical {
3186 cpu0-thermal {
3187 thermal-sensors = <&tsens0 1>;
3190 cpu0_alert0: trip-point0 {
3196 cpu0_alert1: trip-point1 {
3202 cpu0-critical {
3209 cooling-maps {
3212 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3220 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3228 cpu1-thermal {
3229 thermal-sensors = <&tsens0 2>;
3232 cpu1_alert0: trip-point0 {
3238 cpu1_alert1: trip-point1 {
3244 cpu1-critical {
3251 cooling-maps {
3254 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3262 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3270 cpu2-thermal {
3271 thermal-sensors = <&tsens0 3>;
3274 cpu2_alert0: trip-point0 {
3280 cpu2_alert1: trip-point1 {
3286 cpu2-critical {
3293 cooling-maps {
3296 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3304 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3312 cpu3-thermal {
3313 thermal-sensors = <&tsens0 4>;
3316 cpu3_alert0: trip-point0 {
3322 cpu3_alert1: rip-point1 {
3328 cpu3-critical {
3335 cooling-maps {
3338 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3346 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3354 gpuss0-thermal {
3355 polling-delay-passive = <250>;
3357 thermal-sensors = <&tsens0 5>;
3359 cooling-maps {
3362 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3367 gpu0_alert0: trip-point0 {
3373 trip-point1 {
3379 trip-point2 {
3387 gpuss1-thermal {
3388 polling-delay-passive = <250>;
3390 thermal-sensors = <&tsens0 6>;
3392 cooling-maps {
3395 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3400 gpu1_alert0: trip-point0 {
3406 trip-point1 {
3412 trip-point2 {
3420 nspss0-thermal {
3421 thermal-sensors = <&tsens0 7>;
3424 trip-point0 {
3430 trip-point1 {
3436 nspss1-critical {
3444 nspss1-thermal {
3445 thermal-sensors = <&tsens0 8>;
3448 trip-point0 {
3454 trip-point1 {
3460 nspss2-critical {
3468 nspss2-thermal {
3469 thermal-sensors = <&tsens0 9>;
3472 trip-point0 {
3478 trip-point1 {
3484 nspss2-critical {
3492 video-thermal {
3493 thermal-sensors = <&tsens0 10>;
3496 trip-point0 {
3502 video-critical {
3510 ddr-thermal {
3511 thermal-sensors = <&tsens0 11>;
3514 trip-point0 {
3520 ddr-critical {
3528 camera0-thermal {
3529 thermal-sensors = <&tsens0 12>;
3532 trip-point0 {
3538 camera0-critical {
3546 camera1-thermal {
3547 thermal-sensors = <&tsens0 13>;
3550 trip-point0 {
3556 camera1-critical {
3564 mdmss-thermal {
3565 thermal-sensors = <&tsens0 14>;
3568 trip-point0 {
3574 mdmss-critical {