Lines Matching +full:sa8775p +full:- +full:dp
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/interconnect/qcom,icc.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
12 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
13 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
14 #include <dt-bindings/clock/qcom,sa8775p-videocc.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/firmware/qcom,scm.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
43 #address-cells = <2>;
44 #size-cells = <0>;
50 enable-method = "psci";
51 power-domains = <&cpu_pd0>;
52 power-domain-names = "psci";
53 qcom,freq-domain = <&cpufreq_hw 0>;
54 next-level-cache = <&l2_0>;
55 capacity-dmips-mhz = <1024>;
56 dynamic-power-coefficient = <100>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 l2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&l3_0>;
67 l3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
79 enable-method = "psci";
80 power-domains = <&cpu_pd1>;
81 power-domain-names = "psci";
82 qcom,freq-domain = <&cpufreq_hw 0>;
83 next-level-cache = <&l2_1>;
84 capacity-dmips-mhz = <1024>;
85 dynamic-power-coefficient = <100>;
86 operating-points-v2 = <&cpu0_opp_table>;
91 l2_1: l2-cache {
93 cache-level = <2>;
94 cache-unified;
95 next-level-cache = <&l3_0>;
103 enable-method = "psci";
104 power-domains = <&cpu_pd2>;
105 power-domain-names = "psci";
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 next-level-cache = <&l2_2>;
108 capacity-dmips-mhz = <1024>;
109 dynamic-power-coefficient = <100>;
110 operating-points-v2 = <&cpu0_opp_table>;
115 l2_2: l2-cache {
117 cache-level = <2>;
118 cache-unified;
119 next-level-cache = <&l3_0>;
127 enable-method = "psci";
128 power-domains = <&cpu_pd3>;
129 power-domain-names = "psci";
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 next-level-cache = <&l2_3>;
132 capacity-dmips-mhz = <1024>;
133 dynamic-power-coefficient = <100>;
134 operating-points-v2 = <&cpu0_opp_table>;
139 l2_3: l2-cache {
141 cache-level = <2>;
142 cache-unified;
143 next-level-cache = <&l3_0>;
151 enable-method = "psci";
152 power-domains = <&cpu_pd4>;
153 power-domain-names = "psci";
154 qcom,freq-domain = <&cpufreq_hw 1>;
155 next-level-cache = <&l2_4>;
156 capacity-dmips-mhz = <1024>;
157 dynamic-power-coefficient = <100>;
158 operating-points-v2 = <&cpu4_opp_table>;
163 l2_4: l2-cache {
165 cache-level = <2>;
166 cache-unified;
167 next-level-cache = <&l3_1>;
168 l3_1: l3-cache {
170 cache-level = <3>;
171 cache-unified;
181 enable-method = "psci";
182 power-domains = <&cpu_pd5>;
183 power-domain-names = "psci";
184 qcom,freq-domain = <&cpufreq_hw 1>;
185 next-level-cache = <&l2_5>;
186 capacity-dmips-mhz = <1024>;
187 dynamic-power-coefficient = <100>;
188 operating-points-v2 = <&cpu4_opp_table>;
193 l2_5: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&l3_1>;
205 enable-method = "psci";
206 power-domains = <&cpu_pd6>;
207 power-domain-names = "psci";
208 qcom,freq-domain = <&cpufreq_hw 1>;
209 next-level-cache = <&l2_6>;
210 capacity-dmips-mhz = <1024>;
211 dynamic-power-coefficient = <100>;
212 operating-points-v2 = <&cpu4_opp_table>;
217 l2_6: l2-cache {
219 cache-level = <2>;
220 cache-unified;
221 next-level-cache = <&l3_1>;
229 enable-method = "psci";
230 power-domains = <&cpu_pd7>;
231 power-domain-names = "psci";
232 qcom,freq-domain = <&cpufreq_hw 1>;
233 next-level-cache = <&l2_7>;
234 capacity-dmips-mhz = <1024>;
235 dynamic-power-coefficient = <100>;
236 operating-points-v2 = <&cpu4_opp_table>;
241 l2_7: l2-cache {
243 cache-level = <2>;
244 cache-unified;
245 next-level-cache = <&l3_1>;
249 cpu-map {
287 idle-states {
288 entry-method = "psci";
290 gold_cpu_sleep_0: cpu-sleep-0 {
291 compatible = "arm,idle-state";
292 idle-state-name = "gold-power-collapse";
293 arm,psci-suspend-param = <0x40000003>;
294 entry-latency-us = <549>;
295 exit-latency-us = <901>;
296 min-residency-us = <1774>;
297 local-timer-stop;
300 gold_rail_cpu_sleep_0: cpu-sleep-1 {
301 compatible = "arm,idle-state";
302 idle-state-name = "gold-rail-power-collapse";
303 arm,psci-suspend-param = <0x40000004>;
304 entry-latency-us = <702>;
305 exit-latency-us = <1061>;
306 min-residency-us = <4488>;
307 local-timer-stop;
311 domain-idle-states {
312 cluster_sleep_gold: cluster-sleep-0 {
313 compatible = "domain-idle-state";
314 arm,psci-suspend-param = <0x41000044>;
315 entry-latency-us = <2752>;
316 exit-latency-us = <3048>;
317 min-residency-us = <6118>;
320 cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
321 compatible = "domain-idle-state";
322 arm,psci-suspend-param = <0x42000144>;
323 entry-latency-us = <3263>;
324 exit-latency-us = <6562>;
325 min-residency-us = <9987>;
330 cpu0_opp_table: opp-table-cpu0 {
331 compatible = "operating-points-v2";
332 opp-shared;
334 opp-1267200000 {
335 opp-hz = /bits/ 64 <1267200000>;
336 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
339 opp-1363200000 {
340 opp-hz = /bits/ 64 <1363200000>;
341 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
344 opp-1459200000 {
345 opp-hz = /bits/ 64 <1459200000>;
346 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
349 opp-1536000000 {
350 opp-hz = /bits/ 64 <1536000000>;
351 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
354 opp-1632000000 {
355 opp-hz = /bits/ 64 <1632000000>;
356 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
359 opp-1708800000 {
360 opp-hz = /bits/ 64 <1708800000>;
361 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
364 opp-1785600000 {
365 opp-hz = /bits/ 64 <1785600000>;
366 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
369 opp-1862400000 {
370 opp-hz = /bits/ 64 <1862400000>;
371 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
374 opp-1939200000 {
375 opp-hz = /bits/ 64 <1939200000>;
376 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
379 opp-2016000000 {
380 opp-hz = /bits/ 64 <2016000000>;
381 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
384 opp-2112000000 {
385 opp-hz = /bits/ 64 <2112000000>;
386 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
389 opp-2188800000 {
390 opp-hz = /bits/ 64 <2188800000>;
391 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
394 opp-2265600000 {
395 opp-hz = /bits/ 64 <2265600000>;
396 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
399 opp-2361600000 {
400 opp-hz = /bits/ 64 <2361600000>;
401 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
404 opp-2457600000 {
405 opp-hz = /bits/ 64 <2457600000>;
406 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
409 opp-2553600000 {
410 opp-hz = /bits/ 64 <2553600000>;
411 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
415 cpu4_opp_table: opp-table-cpu4 {
416 compatible = "operating-points-v2";
417 opp-shared;
419 opp-1267200000 {
420 opp-hz = /bits/ 64 <1267200000>;
421 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
424 opp-1363200000 {
425 opp-hz = /bits/ 64 <1363200000>;
426 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
429 opp-1459200000 {
430 opp-hz = /bits/ 64 <1459200000>;
431 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
434 opp-1536000000 {
435 opp-hz = /bits/ 64 <1536000000>;
436 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
439 opp-1632000000 {
440 opp-hz = /bits/ 64 <1632000000>;
441 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
444 opp-1708800000 {
445 opp-hz = /bits/ 64 <1708800000>;
446 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
449 opp-1785600000 {
450 opp-hz = /bits/ 64 <1785600000>;
451 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
454 opp-1862400000 {
455 opp-hz = /bits/ 64 <1862400000>;
456 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
459 opp-1939200000 {
460 opp-hz = /bits/ 64 <1939200000>;
461 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
464 opp-2016000000 {
465 opp-hz = /bits/ 64 <2016000000>;
466 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
469 opp-2112000000 {
470 opp-hz = /bits/ 64 <2112000000>;
471 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
474 opp-2188800000 {
475 opp-hz = /bits/ 64 <2188800000>;
476 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
479 opp-2265600000 {
480 opp-hz = /bits/ 64 <2265600000>;
481 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
484 opp-2361600000 {
485 opp-hz = /bits/ 64 <2361600000>;
486 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
489 opp-2457600000 {
490 opp-hz = /bits/ 64 <2457600000>;
491 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
494 opp-2553600000 {
495 opp-hz = /bits/ 64 <2553600000>;
496 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
500 dummy-sink {
501 compatible = "arm,coresight-dummy-sink";
503 in-ports {
506 remote-endpoint =
515 compatible = "qcom,scm-sa8775p", "qcom,scm";
516 qcom,dload-mode = <&tcsr 0x13000>;
517 memory-region = <&tz_ffi_mem>;
521 aggre1_noc: interconnect-aggre1-noc {
522 compatible = "qcom,sa8775p-aggre1-noc";
523 #interconnect-cells = <2>;
524 qcom,bcm-voters = <&apps_bcm_voter>;
527 aggre2_noc: interconnect-aggre2-noc {
528 compatible = "qcom,sa8775p-aggre2-noc";
529 #interconnect-cells = <2>;
530 qcom,bcm-voters = <&apps_bcm_voter>;
533 clk_virt: interconnect-clk-virt {
534 compatible = "qcom,sa8775p-clk-virt";
535 #interconnect-cells = <2>;
536 qcom,bcm-voters = <&apps_bcm_voter>;
539 config_noc: interconnect-config-noc {
540 compatible = "qcom,sa8775p-config-noc";
541 #interconnect-cells = <2>;
542 qcom,bcm-voters = <&apps_bcm_voter>;
545 dc_noc: interconnect-dc-noc {
546 compatible = "qcom,sa8775p-dc-noc";
547 #interconnect-cells = <2>;
548 qcom,bcm-voters = <&apps_bcm_voter>;
551 gem_noc: interconnect-gem-noc {
552 compatible = "qcom,sa8775p-gem-noc";
553 #interconnect-cells = <2>;
554 qcom,bcm-voters = <&apps_bcm_voter>;
557 gpdsp_anoc: interconnect-gpdsp-anoc {
558 compatible = "qcom,sa8775p-gpdsp-anoc";
559 #interconnect-cells = <2>;
560 qcom,bcm-voters = <&apps_bcm_voter>;
563 lpass_ag_noc: interconnect-lpass-ag-noc {
564 compatible = "qcom,sa8775p-lpass-ag-noc";
565 #interconnect-cells = <2>;
566 qcom,bcm-voters = <&apps_bcm_voter>;
569 mc_virt: interconnect-mc-virt {
570 compatible = "qcom,sa8775p-mc-virt";
571 #interconnect-cells = <2>;
572 qcom,bcm-voters = <&apps_bcm_voter>;
575 mmss_noc: interconnect-mmss-noc {
576 compatible = "qcom,sa8775p-mmss-noc";
577 #interconnect-cells = <2>;
578 qcom,bcm-voters = <&apps_bcm_voter>;
581 nspa_noc: interconnect-nspa-noc {
582 compatible = "qcom,sa8775p-nspa-noc";
583 #interconnect-cells = <2>;
584 qcom,bcm-voters = <&apps_bcm_voter>;
587 nspb_noc: interconnect-nspb-noc {
588 compatible = "qcom,sa8775p-nspb-noc";
589 #interconnect-cells = <2>;
590 qcom,bcm-voters = <&apps_bcm_voter>;
593 pcie_anoc: interconnect-pcie-anoc {
594 compatible = "qcom,sa8775p-pcie-anoc";
595 #interconnect-cells = <2>;
596 qcom,bcm-voters = <&apps_bcm_voter>;
599 system_noc: interconnect-system-noc {
600 compatible = "qcom,sa8775p-system-noc";
601 #interconnect-cells = <2>;
602 qcom,bcm-voters = <&apps_bcm_voter>;
611 qup_opp_table_100mhz: opp-table-qup100mhz {
612 compatible = "operating-points-v2";
614 opp-100000000 {
615 opp-hz = /bits/ 64 <100000000>;
616 required-opps = <&rpmhpd_opp_svs_l1>;
621 compatible = "arm,armv8-pmuv3";
626 compatible = "arm,psci-1.0";
629 cpu_pd0: power-domain-cpu0 {
630 #power-domain-cells = <0>;
631 power-domains = <&cluster_0_pd>;
632 domain-idle-states = <&gold_cpu_sleep_0>,
636 cpu_pd1: power-domain-cpu1 {
637 #power-domain-cells = <0>;
638 power-domains = <&cluster_0_pd>;
639 domain-idle-states = <&gold_cpu_sleep_0>,
643 cpu_pd2: power-domain-cpu2 {
644 #power-domain-cells = <0>;
645 power-domains = <&cluster_0_pd>;
646 domain-idle-states = <&gold_cpu_sleep_0>,
650 cpu_pd3: power-domain-cpu3 {
651 #power-domain-cells = <0>;
652 power-domains = <&cluster_0_pd>;
653 domain-idle-states = <&gold_cpu_sleep_0>,
657 cpu_pd4: power-domain-cpu4 {
658 #power-domain-cells = <0>;
659 power-domains = <&cluster_1_pd>;
660 domain-idle-states = <&gold_cpu_sleep_0>,
664 cpu_pd5: power-domain-cpu5 {
665 #power-domain-cells = <0>;
666 power-domains = <&cluster_1_pd>;
667 domain-idle-states = <&gold_cpu_sleep_0>,
671 cpu_pd6: power-domain-cpu6 {
672 #power-domain-cells = <0>;
673 power-domains = <&cluster_1_pd>;
674 domain-idle-states = <&gold_cpu_sleep_0>,
678 cpu_pd7: power-domain-cpu7 {
679 #power-domain-cells = <0>;
680 power-domains = <&cluster_1_pd>;
681 domain-idle-states = <&gold_cpu_sleep_0>,
685 cluster_0_pd: power-domain-cluster0 {
686 #power-domain-cells = <0>;
687 domain-idle-states = <&cluster_sleep_gold>;
688 power-domains = <&system_pd>;
691 cluster_1_pd: power-domain-cluster1 {
692 #power-domain-cells = <0>;
693 domain-idle-states = <&cluster_sleep_gold>;
694 power-domains = <&system_pd>;
697 system_pd: power-domain-system {
698 #power-domain-cells = <0>;
699 domain-idle-states = <&cluster_sleep_apss_rsc_pc>;
703 reserved-memory {
704 #address-cells = <2>;
705 #size-cells = <2>;
708 sail_ss_mem: sail-ss@80000000 {
710 no-map;
715 no-map;
718 xbl_boot_mem: xbl-boot@90600000 {
720 no-map;
723 aop_image_mem: aop-image@90800000 {
725 no-map;
728 aop_cmd_db_mem: aop-cmd-db@90860000 {
729 compatible = "qcom,cmd-db";
731 no-map;
734 uefi_log: uefi-log@908b0000 {
736 no-map;
739 ddr_training_checksum: ddr-training-checksum@908c0000 {
741 no-map;
746 no-map;
749 secdata_apss_mem: secdata-apss@908fe000 {
751 no-map;
757 no-map;
761 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
763 no-map;
766 sail_mailbox_mem: sail-ss@90d00000 {
768 no-map;
771 sail_ota_mem: sail-ss@90e00000 {
773 no-map;
776 aoss_backup_mem: aoss-backup@91b00000 {
778 no-map;
781 cpucp_backup_mem: cpucp-backup@91b40000 {
783 no-map;
786 tz_config_backup_mem: tz-config-backup@91b80000 {
788 no-map;
791 ddr_training_data_mem: ddr-training-data@91b90000 {
793 no-map;
796 cdt_data_backup_mem: cdt-data-backup@91ba0000 {
798 no-map;
801 tz_ffi_mem: tz-ffi@91c00000 {
802 compatible = "shared-dma-pool";
804 no-map;
807 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
809 no-map;
812 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
814 no-map;
817 pil_camera_mem: pil-camera@95200000 {
819 no-map;
822 pil_adsp_mem: pil-adsp@95c00000 {
824 no-map;
827 pil_gdsp0_mem: pil-gdsp0@97b00000 {
829 no-map;
832 pil_gdsp1_mem: pil-gdsp1@99900000 {
834 no-map;
837 pil_cdsp0_mem: pil-cdsp0@9b800000 {
839 no-map;
842 pil_gpu_mem: pil-gpu@9d600000 {
844 no-map;
847 pil_cdsp1_mem: pil-cdsp1@9d700000 {
849 no-map;
852 pil_cvp_mem: pil-cvp@9f500000 {
854 no-map;
857 pil_video_mem: pil-video@9fc00000 {
859 no-map;
862 audio_mdf_mem: audio-mdf-region@ae000000 {
864 no-map;
867 firmware_mem: firmware-region@b0000000 {
869 no-map;
872 hyptz_reserved_mem: hyptz-reserved@beb00000 {
874 no-map;
877 scmi_mem: scmi-region@d0000000 {
879 no-map;
882 firmware_logs_mem: firmware-logs@d0040000 {
884 no-map;
887 firmware_audio_mem: firmware-audio@d0050000 {
889 no-map;
892 firmware_reserved_mem: firmware-reserved@d0054000 {
894 no-map;
897 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
899 no-map;
904 no-map;
909 no-map;
912 deepsleep_backup_mem: deepsleep-backup@d1800000 {
914 no-map;
917 trusted_apps_mem: trusted-apps@d1900000 {
919 no-map;
922 tz_stat_mem: tz-stat@db100000 {
924 no-map;
927 cpucp_fw_mem: cpucp-fw@db200000 {
929 no-map;
933 smp2p-adsp {
936 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
941 qcom,local-pid = <0>;
942 qcom,remote-pid = <2>;
944 smp2p_adsp_out: master-kernel {
945 qcom,entry-name = "master-kernel";
946 #qcom,smem-state-cells = <1>;
949 smp2p_adsp_in: slave-kernel {
950 qcom,entry-name = "slave-kernel";
951 interrupt-controller;
952 #interrupt-cells = <2>;
956 smp2p-cdsp0 {
959 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
964 qcom,local-pid = <0>;
965 qcom,remote-pid = <5>;
967 smp2p_cdsp0_out: master-kernel {
968 qcom,entry-name = "master-kernel";
969 #qcom,smem-state-cells = <1>;
972 smp2p_cdsp0_in: slave-kernel {
973 qcom,entry-name = "slave-kernel";
974 interrupt-controller;
975 #interrupt-cells = <2>;
979 smp2p-cdsp1 {
982 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
987 qcom,local-pid = <0>;
988 qcom,remote-pid = <12>;
990 smp2p_cdsp1_out: master-kernel {
991 qcom,entry-name = "master-kernel";
992 #qcom,smem-state-cells = <1>;
995 smp2p_cdsp1_in: slave-kernel {
996 qcom,entry-name = "slave-kernel";
997 interrupt-controller;
998 #interrupt-cells = <2>;
1002 smp2p-gpdsp0 {
1005 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
1010 qcom,local-pid = <0>;
1011 qcom,remote-pid = <17>;
1013 smp2p_gpdsp0_out: master-kernel {
1014 qcom,entry-name = "master-kernel";
1015 #qcom,smem-state-cells = <1>;
1018 smp2p_gpdsp0_in: slave-kernel {
1019 qcom,entry-name = "slave-kernel";
1020 interrupt-controller;
1021 #interrupt-cells = <2>;
1025 smp2p-gpdsp1 {
1028 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
1033 qcom,local-pid = <0>;
1034 qcom,remote-pid = <18>;
1036 smp2p_gpdsp1_out: master-kernel {
1037 qcom,entry-name = "master-kernel";
1038 #qcom,smem-state-cells = <1>;
1041 smp2p_gpdsp1_in: slave-kernel {
1042 qcom,entry-name = "slave-kernel";
1043 interrupt-controller;
1044 #interrupt-cells = <2>;
1049 compatible = "simple-bus";
1050 #address-cells = <2>;
1051 #size-cells = <2>;
1054 gcc: clock-controller@100000 {
1055 compatible = "qcom,sa8775p-gcc";
1057 #clock-cells = <1>;
1058 #reset-cells = <1>;
1059 #power-domain-cells = <1>;
1075 power-domains = <&rpmhpd SA8775P_CX>;
1079 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
1082 interrupt-controller;
1083 #interrupt-cells = <3>;
1084 #mbox-cells = <2>;
1087 gpi_dma2: dma-controller@800000 {
1088 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
1090 #dma-cells = <3>;
1103 dma-channels = <12>;
1104 dma-channel-mask = <0xfff>;
1110 compatible = "qcom,geni-se-qup";
1115 clock-names = "m-ahb", "s-ahb";
1117 #address-cells = <2>;
1118 #size-cells = <2>;
1122 compatible = "qcom,geni-i2c";
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1128 clock-names = "se";
1129 pinctrl-0 = <&qup_i2c14_default>;
1130 pinctrl-names = "default";
1137 interconnect-names = "qup-core",
1138 "qup-config",
1139 "qup-memory";
1140 power-domains = <&rpmhpd SA8775P_CX>;
1143 dma-names = "tx",
1149 compatible = "qcom,geni-spi";
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1155 clock-names = "se";
1156 pinctrl-0 = <&qup_spi14_default>;
1157 pinctrl-names = "default";
1164 interconnect-names = "qup-core",
1165 "qup-config",
1166 "qup-memory";
1167 power-domains = <&rpmhpd SA8775P_CX>;
1170 dma-names = "tx",
1176 compatible = "qcom,geni-uart";
1180 clock-names = "se";
1181 pinctrl-0 = <&qup_uart14_default>;
1182 pinctrl-names = "default";
1187 interconnect-names = "qup-core", "qup-config";
1188 power-domains = <&rpmhpd SA8775P_CX>;
1193 compatible = "qcom,geni-i2c";
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1199 clock-names = "se";
1200 pinctrl-0 = <&qup_i2c15_default>;
1201 pinctrl-names = "default";
1208 interconnect-names = "qup-core",
1209 "qup-config",
1210 "qup-memory";
1211 power-domains = <&rpmhpd SA8775P_CX>;
1214 dma-names = "tx",
1220 compatible = "qcom,geni-spi";
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1226 clock-names = "se";
1227 pinctrl-0 = <&qup_spi15_default>;
1228 pinctrl-names = "default";
1235 interconnect-names = "qup-core",
1236 "qup-config",
1237 "qup-memory";
1238 power-domains = <&rpmhpd SA8775P_CX>;
1241 dma-names = "tx",
1247 compatible = "qcom,geni-uart";
1251 clock-names = "se";
1252 pinctrl-0 = <&qup_uart15_default>;
1253 pinctrl-names = "default";
1258 interconnect-names = "qup-core", "qup-config";
1259 power-domains = <&rpmhpd SA8775P_CX>;
1264 compatible = "qcom,geni-i2c";
1266 #address-cells = <1>;
1267 #size-cells = <0>;
1270 clock-names = "se";
1271 pinctrl-0 = <&qup_i2c16_default>;
1272 pinctrl-names = "default";
1279 interconnect-names = "qup-core",
1280 "qup-config",
1281 "qup-memory";
1282 power-domains = <&rpmhpd SA8775P_CX>;
1285 dma-names = "tx",
1291 compatible = "qcom,geni-spi";
1295 clock-names = "se";
1296 pinctrl-0 = <&qup_spi16_default>;
1297 pinctrl-names = "default";
1304 interconnect-names = "qup-core",
1305 "qup-config",
1306 "qup-memory";
1307 power-domains = <&rpmhpd SA8775P_CX>;
1310 dma-names = "tx",
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1318 compatible = "qcom,geni-uart";
1322 clock-names = "se";
1323 pinctrl-0 = <&qup_uart16_default>;
1324 pinctrl-names = "default";
1329 interconnect-names = "qup-core", "qup-config";
1330 power-domains = <&rpmhpd SA8775P_CX>;
1335 compatible = "qcom,geni-i2c";
1337 #address-cells = <1>;
1338 #size-cells = <0>;
1341 clock-names = "se";
1342 pinctrl-0 = <&qup_i2c17_default>;
1343 pinctrl-names = "default";
1350 interconnect-names = "qup-core",
1351 "qup-config",
1352 "qup-memory";
1353 power-domains = <&rpmhpd SA8775P_CX>;
1356 dma-names = "tx",
1362 compatible = "qcom,geni-spi";
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1368 clock-names = "se";
1369 pinctrl-0 = <&qup_spi17_default>;
1370 pinctrl-names = "default";
1377 interconnect-names = "qup-core",
1378 "qup-config",
1379 "qup-memory";
1380 power-domains = <&rpmhpd SA8775P_CX>;
1383 dma-names = "tx",
1389 compatible = "qcom,geni-uart";
1393 clock-names = "se";
1394 pinctrl-0 = <&qup_uart17_default>;
1395 pinctrl-names = "default";
1400 interconnect-names = "qup-core", "qup-config";
1401 power-domains = <&rpmhpd SA8775P_CX>;
1406 compatible = "qcom,geni-i2c";
1410 clock-names = "se";
1411 pinctrl-0 = <&qup_i2c18_default>;
1412 pinctrl-names = "default";
1419 interconnect-names = "qup-core",
1420 "qup-config",
1421 "qup-memory";
1422 power-domains = <&rpmhpd SA8775P_CX>;
1425 dma-names = "tx",
1427 #address-cells = <1>;
1428 #size-cells = <0>;
1433 compatible = "qcom,geni-spi";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1439 clock-names = "se";
1440 pinctrl-0 = <&qup_spi18_default>;
1441 pinctrl-names = "default";
1448 interconnect-names = "qup-core",
1449 "qup-config",
1450 "qup-memory";
1451 power-domains = <&rpmhpd SA8775P_CX>;
1454 dma-names = "tx",
1460 compatible = "qcom,geni-uart";
1464 clock-names = "se";
1465 pinctrl-0 = <&qup_uart18_default>;
1466 pinctrl-names = "default";
1471 interconnect-names = "qup-core", "qup-config";
1472 power-domains = <&rpmhpd SA8775P_CX>;
1477 compatible = "qcom,geni-i2c";
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1483 clock-names = "se";
1484 pinctrl-0 = <&qup_i2c19_default>;
1485 pinctrl-names = "default";
1492 interconnect-names = "qup-core",
1493 "qup-config",
1494 "qup-memory";
1495 power-domains = <&rpmhpd SA8775P_CX>;
1498 dma-names = "tx",
1504 compatible = "qcom,geni-spi";
1506 #address-cells = <1>;
1507 #size-cells = <0>;
1510 clock-names = "se";
1511 pinctrl-0 = <&qup_spi19_default>;
1512 pinctrl-names = "default";
1519 interconnect-names = "qup-core",
1520 "qup-config",
1521 "qup-memory";
1522 power-domains = <&rpmhpd SA8775P_CX>;
1525 dma-names = "tx",
1531 compatible = "qcom,geni-uart";
1535 clock-names = "se";
1536 pinctrl-0 = <&qup_uart19_default>;
1537 pinctrl-names = "default";
1542 interconnect-names = "qup-core", "qup-config";
1543 power-domains = <&rpmhpd SA8775P_CX>;
1548 compatible = "qcom,geni-i2c";
1550 #address-cells = <1>;
1551 #size-cells = <0>;
1554 clock-names = "se";
1555 pinctrl-0 = <&qup_i2c20_default>;
1556 pinctrl-names = "default";
1563 interconnect-names = "qup-core",
1564 "qup-config",
1565 "qup-memory";
1566 power-domains = <&rpmhpd SA8775P_CX>;
1569 dma-names = "tx",
1575 compatible = "qcom,geni-spi";
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1581 clock-names = "se";
1582 pinctrl-0 = <&qup_spi20_default>;
1583 pinctrl-names = "default";
1590 interconnect-names = "qup-core",
1591 "qup-config",
1592 "qup-memory";
1593 power-domains = <&rpmhpd SA8775P_CX>;
1596 dma-names = "tx",
1602 compatible = "qcom,geni-uart";
1606 clock-names = "se";
1607 pinctrl-0 = <&qup_uart20_default>;
1608 pinctrl-names = "default";
1613 interconnect-names = "qup-core", "qup-config";
1614 power-domains = <&rpmhpd SA8775P_CX>;
1620 gpi_dma0: dma-controller@900000 {
1621 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
1623 #dma-cells = <3>;
1636 dma-channels = <12>;
1637 dma-channel-mask = <0xfff>;
1643 compatible = "qcom,geni-se-qup";
1645 #address-cells = <2>;
1646 #size-cells = <2>;
1648 clock-names = "m-ahb", "s-ahb";
1655 compatible = "qcom,geni-i2c";
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1661 clock-names = "se";
1662 pinctrl-0 = <&qup_i2c0_default>;
1663 pinctrl-names = "default";
1670 interconnect-names = "qup-core",
1671 "qup-config",
1672 "qup-memory";
1673 power-domains = <&rpmhpd SA8775P_CX>;
1676 dma-names = "tx",
1682 compatible = "qcom,geni-spi";
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1688 clock-names = "se";
1689 pinctrl-0 = <&qup_spi0_default>;
1690 pinctrl-names = "default";
1697 interconnect-names = "qup-core",
1698 "qup-config",
1699 "qup-memory";
1700 power-domains = <&rpmhpd SA8775P_CX>;
1703 dma-names = "tx",
1709 compatible = "qcom,geni-uart";
1713 clock-names = "se";
1714 pinctrl-0 = <&qup_uart0_default>;
1715 pinctrl-names = "default";
1720 interconnect-names = "qup-core", "qup-config";
1721 power-domains = <&rpmhpd SA8775P_CX>;
1726 compatible = "qcom,geni-i2c";
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1732 clock-names = "se";
1733 pinctrl-0 = <&qup_i2c1_default>;
1734 pinctrl-names = "default";
1741 interconnect-names = "qup-core",
1742 "qup-config",
1743 "qup-memory";
1744 power-domains = <&rpmhpd SA8775P_CX>;
1747 dma-names = "tx",
1753 compatible = "qcom,geni-spi";
1755 #address-cells = <1>;
1756 #size-cells = <0>;
1759 clock-names = "se";
1760 pinctrl-0 = <&qup_spi1_default>;
1761 pinctrl-names = "default";
1768 interconnect-names = "qup-core",
1769 "qup-config",
1770 "qup-memory";
1771 power-domains = <&rpmhpd SA8775P_CX>;
1774 dma-names = "tx",
1780 compatible = "qcom,geni-uart";
1784 clock-names = "se";
1785 pinctrl-0 = <&qup_uart1_default>;
1786 pinctrl-names = "default";
1791 interconnect-names = "qup-core", "qup-config";
1792 power-domains = <&rpmhpd SA8775P_CX>;
1797 compatible = "qcom,geni-i2c";
1799 #address-cells = <1>;
1800 #size-cells = <0>;
1803 clock-names = "se";
1804 pinctrl-0 = <&qup_i2c2_default>;
1805 pinctrl-names = "default";
1812 interconnect-names = "qup-core",
1813 "qup-config",
1814 "qup-memory";
1815 power-domains = <&rpmhpd SA8775P_CX>;
1818 dma-names = "tx",
1824 compatible = "qcom,geni-spi";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1830 clock-names = "se";
1831 pinctrl-0 = <&qup_spi2_default>;
1832 pinctrl-names = "default";
1839 interconnect-names = "qup-core",
1840 "qup-config",
1841 "qup-memory";
1842 power-domains = <&rpmhpd SA8775P_CX>;
1845 dma-names = "tx",
1851 compatible = "qcom,geni-uart";
1855 clock-names = "se";
1856 pinctrl-0 = <&qup_uart2_default>;
1857 pinctrl-names = "default";
1862 interconnect-names = "qup-core", "qup-config";
1863 power-domains = <&rpmhpd SA8775P_CX>;
1868 compatible = "qcom,geni-i2c";
1870 #address-cells = <1>;
1871 #size-cells = <0>;
1874 clock-names = "se";
1875 pinctrl-0 = <&qup_i2c3_default>;
1876 pinctrl-names = "default";
1883 interconnect-names = "qup-core",
1884 "qup-config",
1885 "qup-memory";
1886 power-domains = <&rpmhpd SA8775P_CX>;
1889 dma-names = "tx",
1895 compatible = "qcom,geni-spi";
1897 #address-cells = <1>;
1898 #size-cells = <0>;
1901 clock-names = "se";
1902 pinctrl-0 = <&qup_spi3_default>;
1903 pinctrl-names = "default";
1910 interconnect-names = "qup-core",
1911 "qup-config",
1912 "qup-memory";
1913 power-domains = <&rpmhpd SA8775P_CX>;
1916 dma-names = "tx",
1922 compatible = "qcom,geni-uart";
1926 clock-names = "se";
1927 pinctrl-0 = <&qup_uart3_default>;
1928 pinctrl-names = "default";
1933 interconnect-names = "qup-core", "qup-config";
1934 power-domains = <&rpmhpd SA8775P_CX>;
1939 compatible = "qcom,geni-i2c";
1941 #address-cells = <1>;
1942 #size-cells = <0>;
1945 clock-names = "se";
1946 pinctrl-0 = <&qup_i2c4_default>;
1947 pinctrl-names = "default";
1954 interconnect-names = "qup-core",
1955 "qup-config",
1956 "qup-memory";
1957 power-domains = <&rpmhpd SA8775P_CX>;
1960 dma-names = "tx",
1966 compatible = "qcom,geni-spi";
1968 #address-cells = <1>;
1969 #size-cells = <0>;
1972 clock-names = "se";
1973 pinctrl-0 = <&qup_spi4_default>;
1974 pinctrl-names = "default";
1981 interconnect-names = "qup-core",
1982 "qup-config",
1983 "qup-memory";
1984 power-domains = <&rpmhpd SA8775P_CX>;
1987 dma-names = "tx",
1993 compatible = "qcom,geni-uart";
1997 clock-names = "se";
1998 pinctrl-0 = <&qup_uart4_default>;
1999 pinctrl-names = "default";
2004 interconnect-names = "qup-core", "qup-config";
2005 power-domains = <&rpmhpd SA8775P_CX>;
2010 compatible = "qcom,geni-i2c";
2012 #address-cells = <1>;
2013 #size-cells = <0>;
2016 clock-names = "se";
2017 pinctrl-0 = <&qup_i2c5_default>;
2018 pinctrl-names = "default";
2025 interconnect-names = "qup-core",
2026 "qup-config",
2027 "qup-memory";
2028 power-domains = <&rpmhpd SA8775P_CX>;
2031 dma-names = "tx",
2037 compatible = "qcom,geni-spi";
2039 #address-cells = <1>;
2040 #size-cells = <0>;
2043 clock-names = "se";
2044 pinctrl-0 = <&qup_spi5_default>;
2045 pinctrl-names = "default";
2052 interconnect-names = "qup-core",
2053 "qup-config",
2054 "qup-memory";
2055 power-domains = <&rpmhpd SA8775P_CX>;
2058 dma-names = "tx",
2064 compatible = "qcom,geni-uart";
2068 clock-names = "se";
2069 pinctrl-0 = <&qup_uart5_default>;
2070 pinctrl-names = "default";
2075 interconnect-names = "qup-core", "qup-config";
2076 power-domains = <&rpmhpd SA8775P_CX>;
2081 gpi_dma1: dma-controller@a00000 {
2082 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
2084 #dma-cells = <3>;
2098 dma-channels = <12>;
2099 dma-channel-mask = <0xfff>;
2104 compatible = "qcom,geni-se-qup";
2106 #address-cells = <2>;
2107 #size-cells = <2>;
2109 clock-names = "m-ahb", "s-ahb";
2116 compatible = "qcom,geni-i2c";
2118 #address-cells = <1>;
2119 #size-cells = <0>;
2122 clock-names = "se";
2123 pinctrl-0 = <&qup_i2c7_default>;
2124 pinctrl-names = "default";
2131 interconnect-names = "qup-core",
2132 "qup-config",
2133 "qup-memory";
2134 power-domains = <&rpmhpd SA8775P_CX>;
2137 dma-names = "tx",
2143 compatible = "qcom,geni-spi";
2145 #address-cells = <1>;
2146 #size-cells = <0>;
2149 clock-names = "se";
2150 pinctrl-0 = <&qup_spi7_default>;
2151 pinctrl-names = "default";
2158 interconnect-names = "qup-core",
2159 "qup-config",
2160 "qup-memory";
2161 power-domains = <&rpmhpd SA8775P_CX>;
2164 dma-names = "tx",
2170 compatible = "qcom,geni-uart";
2173 clock-names = "se";
2175 pinctrl-0 = <&qup_uart7_default>;
2176 pinctrl-names = "default";
2177 interconnect-names = "qup-core", "qup-config";
2182 power-domains = <&rpmhpd SA8775P_CX>;
2183 operating-points-v2 = <&qup_opp_table_100mhz>;
2188 compatible = "qcom,geni-i2c";
2190 #address-cells = <1>;
2191 #size-cells = <0>;
2194 clock-names = "se";
2195 pinctrl-0 = <&qup_i2c8_default>;
2196 pinctrl-names = "default";
2203 interconnect-names = "qup-core",
2204 "qup-config",
2205 "qup-memory";
2206 power-domains = <&rpmhpd SA8775P_CX>;
2209 dma-names = "tx",
2215 compatible = "qcom,geni-spi";
2217 #address-cells = <1>;
2218 #size-cells = <0>;
2221 clock-names = "se";
2222 pinctrl-0 = <&qup_spi8_default>;
2223 pinctrl-names = "default";
2230 interconnect-names = "qup-core",
2231 "qup-config",
2232 "qup-memory";
2233 power-domains = <&rpmhpd SA8775P_CX>;
2236 dma-names = "tx",
2242 compatible = "qcom,geni-uart";
2245 clock-names = "se";
2247 pinctrl-0 = <&qup_uart8_default>;
2248 pinctrl-names = "default";
2249 interconnect-names = "qup-core", "qup-config";
2254 power-domains = <&rpmhpd SA8775P_CX>;
2255 operating-points-v2 = <&qup_opp_table_100mhz>;
2260 compatible = "qcom,geni-i2c";
2262 #address-cells = <1>;
2263 #size-cells = <0>;
2266 clock-names = "se";
2267 pinctrl-0 = <&qup_i2c9_default>;
2268 pinctrl-names = "default";
2275 interconnect-names = "qup-core",
2276 "qup-config",
2277 "qup-memory";
2278 power-domains = <&rpmhpd SA8775P_CX>;
2281 dma-names = "tx",
2287 compatible = "qcom,geni-spi";
2289 #address-cells = <1>;
2290 #size-cells = <0>;
2293 clock-names = "se";
2294 pinctrl-0 = <&qup_spi9_default>;
2295 pinctrl-names = "default";
2302 interconnect-names = "qup-core",
2303 "qup-config",
2304 "qup-memory";
2305 power-domains = <&rpmhpd SA8775P_CX>;
2308 dma-names = "tx",
2314 compatible = "qcom,geni-uart";
2318 clock-names = "se";
2319 pinctrl-0 = <&qup_uart9_default>;
2320 pinctrl-names = "default";
2325 interconnect-names = "qup-core", "qup-config";
2326 power-domains = <&rpmhpd SA8775P_CX>;
2331 compatible = "qcom,geni-i2c";
2333 #address-cells = <1>;
2334 #size-cells = <0>;
2337 clock-names = "se";
2338 pinctrl-0 = <&qup_i2c10_default>;
2339 pinctrl-names = "default";
2346 interconnect-names = "qup-core",
2347 "qup-config",
2348 "qup-memory";
2349 power-domains = <&rpmhpd SA8775P_CX>;
2352 dma-names = "tx",
2358 compatible = "qcom,geni-spi";
2360 #address-cells = <1>;
2361 #size-cells = <0>;
2364 clock-names = "se";
2365 pinctrl-0 = <&qup_spi10_default>;
2366 pinctrl-names = "default";
2373 interconnect-names = "qup-core",
2374 "qup-config",
2375 "qup-memory";
2376 power-domains = <&rpmhpd SA8775P_CX>;
2379 dma-names = "tx",
2385 compatible = "qcom,geni-uart";
2388 clock-names = "se";
2390 pinctrl-0 = <&qup_uart10_default>;
2391 pinctrl-names = "default";
2392 interconnect-names = "qup-core", "qup-config";
2397 power-domains = <&rpmhpd SA8775P_CX>;
2398 operating-points-v2 = <&qup_opp_table_100mhz>;
2403 compatible = "qcom,geni-i2c";
2405 #address-cells = <1>;
2406 #size-cells = <0>;
2409 clock-names = "se";
2410 pinctrl-0 = <&qup_i2c11_default>;
2411 pinctrl-names = "default";
2418 interconnect-names = "qup-core",
2419 "qup-config",
2420 "qup-memory";
2421 power-domains = <&rpmhpd SA8775P_CX>;
2424 dma-names = "tx",
2430 compatible = "qcom,geni-spi";
2432 #address-cells = <1>;
2433 #size-cells = <0>;
2436 clock-names = "se";
2437 pinctrl-0 = <&qup_spi11_default>;
2438 pinctrl-names = "default";
2445 interconnect-names = "qup-core",
2446 "qup-config",
2447 "qup-memory";
2448 power-domains = <&rpmhpd SA8775P_CX>;
2451 dma-names = "tx",
2457 compatible = "qcom,geni-uart";
2460 clock-names = "se";
2462 pinctrl-0 = <&qup_uart11_default>;
2463 pinctrl-names = "default";
2464 interconnect-names = "qup-core", "qup-config";
2469 power-domains = <&rpmhpd SA8775P_CX>;
2470 operating-points-v2 = <&qup_opp_table_100mhz>;
2475 compatible = "qcom,geni-i2c";
2477 #address-cells = <1>;
2478 #size-cells = <0>;
2481 clock-names = "se";
2482 pinctrl-0 = <&qup_i2c12_default>;
2483 pinctrl-names = "default";
2490 interconnect-names = "qup-core",
2491 "qup-config",
2492 "qup-memory";
2493 power-domains = <&rpmhpd SA8775P_CX>;
2496 dma-names = "tx",
2502 compatible = "qcom,geni-spi";
2504 #address-cells = <1>;
2505 #size-cells = <0>;
2508 clock-names = "se";
2509 pinctrl-0 = <&qup_spi12_default>;
2510 pinctrl-names = "default";
2517 interconnect-names = "qup-core",
2518 "qup-config",
2519 "qup-memory";
2520 power-domains = <&rpmhpd SA8775P_CX>;
2523 dma-names = "tx",
2529 compatible = "qcom,geni-uart";
2533 clock-names = "se";
2534 pinctrl-0 = <&qup_uart12_default>;
2535 pinctrl-names = "default";
2540 interconnect-names = "qup-core", "qup-config";
2541 power-domains = <&rpmhpd SA8775P_CX>;
2546 compatible = "qcom,geni-i2c";
2548 #address-cells = <1>;
2549 #size-cells = <0>;
2552 clock-names = "se";
2553 pinctrl-0 = <&qup_i2c13_default>;
2554 pinctrl-names = "default";
2561 interconnect-names = "qup-core",
2562 "qup-config",
2563 "qup-memory";
2564 power-domains = <&rpmhpd SA8775P_CX>;
2567 dma-names = "tx",
2574 gpi_dma3: dma-controller@b00000 {
2575 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
2577 #dma-cells = <3>;
2583 dma-channels = <4>;
2584 dma-channel-mask = <0xf>;
2589 compatible = "qcom,geni-se-qup";
2591 #address-cells = <2>;
2592 #size-cells = <2>;
2594 clock-names = "m-ahb", "s-ahb";
2601 compatible = "qcom,geni-i2c";
2603 #address-cells = <1>;
2604 #size-cells = <0>;
2607 clock-names = "se";
2608 pinctrl-0 = <&qup_i2c21_default>;
2609 pinctrl-names = "default";
2616 interconnect-names = "qup-core",
2617 "qup-config",
2618 "qup-memory";
2619 power-domains = <&rpmhpd SA8775P_CX>;
2622 dma-names = "tx",
2628 compatible = "qcom,geni-spi";
2630 #address-cells = <1>;
2631 #size-cells = <0>;
2634 clock-names = "se";
2635 pinctrl-0 = <&qup_spi21_default>;
2636 pinctrl-names = "default";
2643 interconnect-names = "qup-core",
2644 "qup-config",
2645 "qup-memory";
2646 power-domains = <&rpmhpd SA8775P_CX>;
2649 dma-names = "tx",
2655 compatible = "qcom,geni-uart";
2658 clock-names = "se";
2660 interconnect-names = "qup-core", "qup-config";
2661 pinctrl-0 = <&qup_uart21_default>;
2662 pinctrl-names = "default";
2667 power-domains = <&rpmhpd SA8775P_CX>;
2668 operating-points-v2 = <&qup_opp_table_100mhz>;
2674 compatible = "qcom,sa8775p-trng", "qcom,trng";
2679 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2683 phy-names = "ufsphy";
2684 lanes-per-direction = <2>;
2685 #reset-cells = <1>;
2687 reset-names = "rst";
2688 power-domains = <&gcc UFS_PHY_GDSC>;
2689 required-opps = <&rpmhpd_opp_nom>;
2691 dma-coherent;
2700 clock-names = "core_clk",
2708 freq-table-hz = <75000000 300000000>,
2721 compatible = "qcom,sa8775p-qmp-ufs-phy";
2730 clock-names = "ref", "ref_aux", "qref";
2731 power-domains = <&gcc UFS_PHY_GDSC>;
2733 reset-names = "ufsphy";
2734 #phy-cells = <0>;
2739 compatible = "qcom,sa8775p-inline-crypto-engine",
2740 "qcom,inline-crypto-engine";
2745 cryptobam: dma-controller@1dc4000 {
2746 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2749 #dma-cells = <1>;
2751 qcom,num-ees = <4>;
2752 num-channels = <20>;
2753 qcom,controlled-remotely;
2759 compatible = "qcom,sa8775p-ctcu";
2763 clock-names = "apb";
2765 in-ports {
2766 #address-cells = <1>;
2767 #size-cells = <0>;
2773 remote-endpoint = <&etr0_out>;
2781 remote-endpoint = <&etr1_out>;
2788 compatible = "arm,coresight-stm", "arm,primecell";
2791 reg-names = "stm-base", "stm-stimulus-base";
2794 clock-names = "apb_pclk";
2796 out-ports {
2799 remote-endpoint =
2807 compatible = "qcom,coresight-tpdm", "arm,primecell";
2811 clock-names = "apb_pclk";
2813 qcom,cmb-element-bits = <32>;
2814 qcom,cmb-msrs-num = <32>;
2817 out-ports {
2820 remote-endpoint =
2828 compatible = "qcom,coresight-tpda", "arm,primecell";
2832 clock-names = "apb_pclk";
2834 out-ports {
2837 remote-endpoint =
2843 in-ports {
2844 #address-cells = <1>;
2845 #size-cells = <0>;
2850 remote-endpoint =
2858 remote-endpoint =
2866 compatible = "qcom,coresight-tpdm", "arm,primecell";
2870 clock-names = "apb_pclk";
2872 qcom,cmb-element-bits = <32>;
2873 qcom,cmb-msrs-num = <32>;
2875 out-ports {
2878 remote-endpoint =
2886 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2890 clock-names = "apb_pclk";
2892 out-ports {
2895 remote-endpoint =
2901 in-ports {
2902 #address-cells = <1>;
2903 #size-cells = <0>;
2908 remote-endpoint =
2916 remote-endpoint =
2924 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2928 clock-names = "apb_pclk";
2930 out-ports {
2933 remote-endpoint =
2939 in-ports {
2940 #address-cells = <1>;
2941 #size-cells = <0>;
2946 remote-endpoint =
2954 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2958 clock-names = "apb_pclk";
2960 out-ports {
2963 remote-endpoint =
2969 in-ports {
2970 #address-cells = <1>;
2971 #size-cells = <0>;
2976 remote-endpoint =
2984 remote-endpoint =
2992 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2996 clock-names = "apb_pclk";
2998 in-ports {
3001 remote-endpoint = <&swao_rep_out0>;
3006 out-ports {
3009 remote-endpoint = <&etr_rep_in>;
3016 compatible = "arm,coresight-tmc", "arm,primecell";
3020 clock-names = "apb_pclk";
3023 arm,scatter-gather;
3025 in-ports {
3028 remote-endpoint = <&etr_rep_out0>;
3033 out-ports {
3036 remote-endpoint = <&ctcu_in0>;
3043 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3047 clock-names = "apb_pclk";
3049 in-ports {
3052 remote-endpoint = <&qdss_rep_out0>;
3057 out-ports {
3058 #address-cells = <1>;
3059 #size-cells = <0>;
3065 remote-endpoint = <&etr0_in>;
3073 remote-endpoint = <&etr1_in>;
3080 compatible = "arm,coresight-tmc", "arm,primecell";
3084 clock-names = "apb_pclk";
3087 arm,scatter-gather;
3088 arm,buffer-size = <0x400000>;
3090 in-ports {
3093 remote-endpoint = <&etr_rep_out1>;
3098 out-ports {
3101 remote-endpoint = <&ctcu_in1>;
3108 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3112 clock-names = "apb_pclk";
3114 out-ports {
3117 remote-endpoint =
3123 in-ports {
3124 #address-cells = <1>;
3125 #size-cells = <0>;
3130 remote-endpoint =
3138 remote-endpoint =
3146 compatible = "arm,coresight-tmc", "arm,primecell";
3150 clock-names = "apb_pclk";
3152 out-ports {
3155 remote-endpoint =
3161 in-ports {
3164 remote-endpoint =
3172 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3176 clock-names = "apb_pclk";
3178 out-ports {
3179 #address-cells = <1>;
3180 #size-cells = <0>;
3186 remote-endpoint = <&qdss_rep_in>;
3193 remote-endpoint =
3199 in-ports {
3202 remote-endpoint =
3210 compatible = "qcom,coresight-tpda", "arm,primecell";
3214 clock-names = "apb_pclk";
3216 out-ports {
3219 remote-endpoint =
3225 in-ports {
3226 #address-cells = <1>;
3227 #size-cells = <0>;
3232 remote-endpoint =
3240 remote-endpoint =
3248 remote-endpoint =
3256 remote-endpoint =
3264 remote-endpoint =
3272 compatible = "qcom,coresight-tpdm", "arm,primecell";
3276 clock-names = "apb_pclk";
3278 qcom,cmb-element-bits = <64>;
3279 qcom,cmb-msrs-num = <32>;
3281 out-ports {
3284 remote-endpoint =
3292 compatible = "qcom,coresight-tpdm", "arm,primecell";
3296 clock-names = "apb_pclk";
3298 qcom,cmb-element-bits = <64>;
3299 qcom,cmb-msrs-num = <32>;
3301 out-ports {
3304 remote-endpoint =
3312 compatible = "qcom,coresight-tpdm", "arm,primecell";
3316 clock-names = "apb_pclk";
3318 qcom,cmb-element-bits = <64>;
3319 qcom,cmb-msrs-num = <32>;
3321 out-ports {
3324 remote-endpoint =
3332 compatible = "qcom,coresight-tpdm", "arm,primecell";
3336 clock-names = "apb_pclk";
3338 qcom,cmb-element-bits = <64>;
3339 qcom,cmb-msrs-num = <32>;
3341 out-ports {
3344 remote-endpoint =
3352 compatible = "qcom,coresight-tpdm", "arm,primecell";
3356 clock-names = "apb_pclk";
3358 qcom,dsb-element-bits = <32>;
3359 qcom,dsb-msrs-num = <32>;
3361 out-ports {
3364 remote-endpoint =
3372 compatible = "arm,coresight-cti", "arm,primecell";
3376 clock-names = "apb_pclk";
3385 clock-names = "apb_pclk";
3386 arm,coresight-loses-context-with-cpu;
3387 qcom,skip-power-up;
3389 out-ports {
3392 remote-endpoint =
3405 clock-names = "apb_pclk";
3406 arm,coresight-loses-context-with-cpu;
3407 qcom,skip-power-up;
3409 out-ports {
3412 remote-endpoint =
3425 clock-names = "apb_pclk";
3426 arm,coresight-loses-context-with-cpu;
3427 qcom,skip-power-up;
3429 out-ports {
3432 remote-endpoint =
3445 clock-names = "apb_pclk";
3446 arm,coresight-loses-context-with-cpu;
3447 qcom,skip-power-up;
3449 out-ports {
3452 remote-endpoint =
3465 clock-names = "apb_pclk";
3466 arm,coresight-loses-context-with-cpu;
3467 qcom,skip-power-up;
3469 out-ports {
3472 remote-endpoint =
3485 clock-names = "apb_pclk";
3486 arm,coresight-loses-context-with-cpu;
3487 qcom,skip-power-up;
3489 out-ports {
3492 remote-endpoint =
3505 clock-names = "apb_pclk";
3506 arm,coresight-loses-context-with-cpu;
3507 qcom,skip-power-up;
3509 out-ports {
3512 remote-endpoint =
3525 clock-names = "apb_pclk";
3526 arm,coresight-loses-context-with-cpu;
3527 qcom,skip-power-up;
3529 out-ports {
3532 remote-endpoint =
3540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3544 clock-names = "apb_pclk";
3546 out-ports {
3549 remote-endpoint =
3555 in-ports {
3556 #address-cells = <1>;
3557 #size-cells = <0>;
3562 remote-endpoint =
3570 remote-endpoint =
3578 remote-endpoint =
3586 remote-endpoint =
3594 remote-endpoint =
3602 remote-endpoint =
3610 remote-endpoint =
3618 remote-endpoint =
3626 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3630 clock-names = "apb_pclk";
3632 out-ports {
3635 remote-endpoint =
3641 in-ports {
3642 #address-cells = <1>;
3643 #size-cells = <0>;
3648 remote-endpoint =
3656 remote-endpoint =
3664 compatible = "qcom,coresight-tpdm", "arm,primecell";
3668 clock-names = "apb_pclk";
3670 qcom,cmb-element-bits = <64>;
3671 qcom,cmb-msrs-num = <32>;
3673 out-ports {
3676 remote-endpoint =
3684 compatible = "qcom,coresight-tpdm", "arm,primecell";
3688 clock-names = "apb_pclk";
3690 qcom,dsb-element-bits = <32>;
3691 qcom,dsb-msrs-num = <32>;
3693 out-ports {
3696 remote-endpoint =
3704 compatible = "qcom,coresight-tpda", "arm,primecell";
3708 clock-names = "apb_pclk";
3710 out-ports {
3713 remote-endpoint =
3719 in-ports {
3720 #address-cells = <1>;
3721 #size-cells = <0>;
3726 remote-endpoint =
3734 remote-endpoint =
3742 remote-endpoint =
3750 remote-endpoint =
3758 remote-endpoint =
3766 compatible = "qcom,coresight-tpdm", "arm,primecell";
3770 clock-names = "apb_pclk";
3772 qcom,cmb-element-bits = <32>;
3773 qcom,cmb-msrs-num = <32>;
3775 out-ports {
3778 remote-endpoint =
3786 compatible = "qcom,coresight-tpdm", "arm,primecell";
3790 clock-names = "apb_pclk";
3792 qcom,cmb-element-bits = <32>;
3793 qcom,cmb-msrs-num = <32>;
3795 out-ports {
3798 remote-endpoint =
3806 compatible = "qcom,coresight-tpdm", "arm,primecell";
3810 clock-names = "apb_pclk";
3812 qcom,dsb-element-bits = <32>;
3813 qcom,dsb-msrs-num = <32>;
3815 out-ports {
3818 remote-endpoint =
3826 compatible = "qcom,sa8775p-usb-hs-phy",
3827 "qcom,usb-snps-hs-5nm-phy";
3830 clock-names = "ref";
3833 #phy-cells = <0>;
3839 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
3846 clock-names = "aux", "ref", "com_aux", "pipe";
3850 reset-names = "phy", "phy_phy";
3852 power-domains = <&gcc USB30_PRIM_GDSC>;
3854 #clock-cells = <0>;
3855 clock-output-names = "usb3_prim_phy_pipe_clk_src";
3857 #phy-cells = <0>;
3863 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
3865 #address-cells = <2>;
3866 #size-cells = <2>;
3874 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
3876 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3878 assigned-clock-rates = <19200000>, <200000000>;
3880 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
3885 interrupt-names = "pwr_event",
3891 power-domains = <&gcc USB30_PRIM_GDSC>;
3892 required-opps = <&rpmhpd_opp_nom>;
3898 interconnect-names = "usb-ddr", "apps-usb";
3900 wakeup-source;
3910 phy-names = "usb2-phy", "usb3-phy";
3911 snps,dis-u1-entry-quirk;
3912 snps,dis-u2-entry-quirk;
3917 compatible = "qcom,sa8775p-usb-hs-phy",
3918 "qcom,usb-snps-hs-5nm-phy";
3921 clock-names = "ref";
3924 #phy-cells = <0>;
3930 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
3937 clock-names = "aux", "ref", "com_aux", "pipe";
3941 reset-names = "phy", "phy_phy";
3943 power-domains = <&gcc USB30_SEC_GDSC>;
3945 #clock-cells = <0>;
3946 clock-output-names = "usb3_sec_phy_pipe_clk_src";
3948 #phy-cells = <0>;
3954 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
3956 #address-cells = <2>;
3957 #size-cells = <2>;
3965 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
3967 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3969 assigned-clock-rates = <19200000>, <200000000>;
3971 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
3976 interrupt-names = "pwr_event",
3982 power-domains = <&gcc USB30_SEC_GDSC>;
3983 required-opps = <&rpmhpd_opp_nom>;
3989 interconnect-names = "usb-ddr", "apps-usb";
3991 wakeup-source;
4001 phy-names = "usb2-phy", "usb3-phy";
4002 snps,dis-u1-entry-quirk;
4003 snps,dis-u2-entry-quirk;
4008 compatible = "qcom,sa8775p-usb-hs-phy",
4009 "qcom,usb-snps-hs-5nm-phy";
4012 clock-names = "ref";
4015 #phy-cells = <0>;
4021 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
4023 #address-cells = <2>;
4024 #size-cells = <2>;
4032 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
4034 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4036 assigned-clock-rates = <19200000>, <200000000>;
4038 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
4042 interrupt-names = "pwr_event",
4047 power-domains = <&gcc USB20_PRIM_GDSC>;
4048 required-opps = <&rpmhpd_opp_nom>;
4054 interconnect-names = "usb-ddr", "apps-usb";
4056 wakeup-source;
4066 phy-names = "usb2-phy";
4067 snps,dis-u1-entry-quirk;
4068 snps,dis-u2-entry-quirk;
4073 compatible = "qcom,tcsr-mutex";
4075 #hwlock-cells = <1>;
4079 compatible = "qcom,sa8775p-tcsr", "syscon";
4083 gpucc: clock-controller@3d90000 {
4084 compatible = "qcom,sa8775p-gpucc";
4089 clock-names = "bi_tcxo",
4092 #clock-cells = <1>;
4093 #reset-cells = <1>;
4094 #power-domain-cells = <1>;
4098 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
4099 "qcom,smmu-500", "arm,mmu-500";
4101 #iommu-cells = <2>;
4102 #global-interrupts = <2>;
4103 dma-coherent;
4104 power-domains = <&gpucc GPU_CC_CX_GDSC>;
4112 clock-names = "gcc_gpu_memnoc_gfx_clk",
4134 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
4137 clock-names = "sgmi_ref";
4138 #phy-cells = <0>;
4143 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
4146 clock-names = "sgmi_ref";
4147 #phy-cells = <0>;
4152 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4158 operating-points-v2 = <&llcc_bwmon_opp_table>;
4160 llcc_bwmon_opp_table: opp-table {
4161 compatible = "operating-points-v2";
4163 opp-0 {
4164 opp-peak-kBps = <762000>;
4167 opp-1 {
4168 opp-peak-kBps = <1720000>;
4171 opp-2 {
4172 opp-peak-kBps = <2086000>;
4175 opp-3 {
4176 opp-peak-kBps = <2601000>;
4179 opp-4 {
4180 opp-peak-kBps = <2929000>;
4183 opp-5 {
4184 opp-peak-kBps = <5931000>;
4187 opp-6 {
4188 opp-peak-kBps = <6515000>;
4191 opp-7 {
4192 opp-peak-kBps = <7984000>;
4195 opp-8 {
4196 opp-peak-kBps = <10437000>;
4199 opp-9 {
4200 opp-peak-kBps = <12195000>;
4206 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
4212 operating-points-v2 = <&cpu_bwmon_opp_table>;
4214 cpu_bwmon_opp_table: opp-table {
4215 compatible = "operating-points-v2";
4217 opp-0 {
4218 opp-peak-kBps = <9155000>;
4221 opp-1 {
4222 opp-peak-kBps = <12298000>;
4225 opp-2 {
4226 opp-peak-kBps = <14236000>;
4229 opp-3 {
4230 opp-peak-kBps = <16265000>;
4237 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
4243 operating-points-v2 = <&cpu_bwmon_opp_table>;
4246 llcc: system-cache-controller@9200000 {
4247 compatible = "qcom,sa8775p-llcc";
4255 reg-names = "llcc0_base",
4265 iris: video-codec@aa00000 {
4266 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris";
4271 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
4275 power-domain-names = "venus",
4279 operating-points-v2 = <&iris_opp_table>;
4284 clock-names = "iface",
4292 interconnect-names = "cpu-cfg",
4293 "video-mem";
4295 memory-region = <&pil_video_mem>;
4298 reset-names = "bus";
4302 dma-coherent;
4306 iris_opp_table: opp-table {
4307 compatible = "operating-points-v2";
4309 opp-366000000 {
4310 opp-hz = /bits/ 64 <366000000>;
4311 required-opps = <&rpmhpd_opp_svs_l1>,
4315 opp-444000000 {
4316 opp-hz = /bits/ 64 <444000000>;
4317 required-opps = <&rpmhpd_opp_nom>,
4321 opp-533000000 {
4322 opp-hz = /bits/ 64 <533000000>;
4323 required-opps = <&rpmhpd_opp_turbo>,
4327 opp-560000000 {
4328 opp-hz = /bits/ 64 <560000000>;
4329 required-opps = <&rpmhpd_opp_turbo_l1>,
4335 videocc: clock-controller@abf0000 {
4336 compatible = "qcom,sa8775p-videocc";
4342 power-domains = <&rpmhpd SA8775P_MMCX>;
4343 #clock-cells = <1>;
4344 #reset-cells = <1>;
4345 #power-domain-cells = <1>;
4348 camcc: clock-controller@ade0000 {
4349 compatible = "qcom,sa8775p-camcc";
4355 power-domains = <&rpmhpd SA8775P_MMCX>;
4356 #clock-cells = <1>;
4357 #reset-cells = <1>;
4358 #power-domain-cells = <1>;
4361 mdss0: display-subsystem@ae00000 {
4362 compatible = "qcom,sa8775p-mdss";
4364 reg-names = "mdss";
4373 interconnect-names = "mdp0-mem",
4374 "mdp1-mem",
4375 "cpu-cfg";
4379 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
4386 interrupt-controller;
4387 #interrupt-cells = <1>;
4391 #address-cells = <2>;
4392 #size-cells = <2>;
4397 mdss0_mdp: display-controller@ae01000 {
4398 compatible = "qcom,sa8775p-dpu";
4401 reg-names = "mdp", "vbif";
4408 clock-names = "bus",
4414 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
4415 assigned-clock-rates = <19200000>;
4417 operating-points-v2 = <&mdss0_mdp_opp_table>;
4418 power-domains = <&rpmhpd SA8775P_MMCX>;
4420 interrupt-parent = <&mdss0>;
4424 #address-cells = <1>;
4425 #size-cells = <0>;
4431 remote-endpoint = <&mdss0_dp0_in>;
4439 remote-endpoint = <&mdss0_dp1_in>;
4447 remote-endpoint = <&mdss0_dsi0_in>;
4455 remote-endpoint = <&mdss0_dsi1_in>;
4460 mdss0_mdp_opp_table: opp-table {
4461 compatible = "operating-points-v2";
4463 opp-375000000 {
4464 opp-hz = /bits/ 64 <375000000>;
4465 required-opps = <&rpmhpd_opp_svs_l1>;
4468 opp-500000000 {
4469 opp-hz = /bits/ 64 <500000000>;
4470 required-opps = <&rpmhpd_opp_nom>;
4473 opp-575000000 {
4474 opp-hz = /bits/ 64 <575000000>;
4475 required-opps = <&rpmhpd_opp_turbo>;
4478 opp-650000000 {
4479 opp-hz = /bits/ 64 <650000000>;
4480 required-opps = <&rpmhpd_opp_turbo_l1>;
4486 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4488 reg-names = "dsi_ctrl";
4490 interrupt-parent = <&mdss0>;
4499 clock-names = "byte",
4505 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
4507 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
4511 operating-points-v2 = <&mdss_dsi_opp_table>;
4512 power-domains = <&rpmhpd SA8775P_MMCX>;
4514 #address-cells = <1>;
4515 #size-cells = <0>;
4520 #address-cells = <1>;
4521 #size-cells = <0>;
4527 remote-endpoint = <&dpu_intf1_out>;
4538 mdss_dsi_opp_table: opp-table {
4539 compatible = "operating-points-v2";
4541 opp-358000000 {
4542 opp-hz = /bits/ 64 <358000000>;
4543 required-opps = <&rpmhpd_opp_svs_l1>;
4549 compatible = "qcom,sa8775p-dsi-phy-5nm";
4553 reg-names = "dsi_phy",
4557 #clock-cells = <1>;
4558 #phy-cells = <0>;
4562 clock-names = "iface", "ref";
4568 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4570 reg-names = "dsi_ctrl";
4572 interrupt-parent = <&mdss0>;
4581 clock-names = "byte",
4587 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>,
4589 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
4593 operating-points-v2 = <&mdss_dsi_opp_table>;
4594 power-domains = <&rpmhpd SA8775P_MMCX>;
4596 #address-cells = <1>;
4597 #size-cells = <0>;
4602 #address-cells = <1>;
4603 #size-cells = <0>;
4609 remote-endpoint = <&dpu_intf2_out>;
4622 compatible = "qcom,sa8775p-dsi-phy-5nm";
4626 reg-names = "dsi_phy",
4630 #clock-cells = <1>;
4631 #phy-cells = <0>;
4635 clock-names = "iface", "ref";
4641 compatible = "qcom,sa8775p-edp-phy";
4650 clock-names = "aux",
4653 #clock-cells = <1>;
4654 #phy-cells = <0>;
4660 compatible = "qcom,sa8775p-edp-phy";
4669 clock-names = "aux",
4672 #clock-cells = <1>;
4673 #phy-cells = <0>;
4678 mdss0_dp0: displayport-controller@af54000 {
4679 compatible = "qcom,sa8775p-dp";
4687 interrupt-parent = <&mdss0>;
4695 clock-names = "core_iface",
4700 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4702 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
4704 phy-names = "dp";
4706 operating-points-v2 = <&dp_opp_table>;
4707 power-domains = <&rpmhpd SA8775P_MMCX>;
4709 #sound-dai-cells = <0>;
4714 #address-cells = <1>;
4715 #size-cells = <0>;
4721 remote-endpoint = <&dpu_intf0_out>;
4732 dp_opp_table: opp-table {
4733 compatible = "operating-points-v2";
4735 opp-160000000 {
4736 opp-hz = /bits/ 64 <160000000>;
4737 required-opps = <&rpmhpd_opp_low_svs>;
4740 opp-270000000 {
4741 opp-hz = /bits/ 64 <270000000>;
4742 required-opps = <&rpmhpd_opp_svs>;
4745 opp-540000000 {
4746 opp-hz = /bits/ 64 <540000000>;
4747 required-opps = <&rpmhpd_opp_svs_l1>;
4750 opp-810000000 {
4751 opp-hz = /bits/ 64 <810000000>;
4752 required-opps = <&rpmhpd_opp_nom>;
4757 mdss0_dp1: displayport-controller@af5c000 {
4758 compatible = "qcom,sa8775p-dp";
4766 interrupt-parent = <&mdss0>;
4774 clock-names = "core_iface",
4779 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4781 assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
4783 phy-names = "dp";
4785 operating-points-v2 = <&dp1_opp_table>;
4786 power-domains = <&rpmhpd SA8775P_MMCX>;
4788 #sound-dai-cells = <0>;
4793 #address-cells = <1>;
4794 #size-cells = <0>;
4800 remote-endpoint = <&dpu_intf4_out>;
4811 dp1_opp_table: opp-table {
4812 compatible = "operating-points-v2";
4814 opp-160000000 {
4815 opp-hz = /bits/ 64 <160000000>;
4816 required-opps = <&rpmhpd_opp_low_svs>;
4819 opp-270000000 {
4820 opp-hz = /bits/ 64 <270000000>;
4821 required-opps = <&rpmhpd_opp_svs>;
4824 opp-540000000 {
4825 opp-hz = /bits/ 64 <540000000>;
4826 required-opps = <&rpmhpd_opp_svs_l1>;
4829 opp-810000000 {
4830 opp-hz = /bits/ 64 <810000000>;
4831 required-opps = <&rpmhpd_opp_nom>;
4837 dispcc0: clock-controller@af00000 {
4838 compatible = "qcom,sa8775p-dispcc0";
4850 power-domains = <&rpmhpd SA8775P_MMCX>;
4851 #clock-cells = <1>;
4852 #reset-cells = <1>;
4853 #power-domain-cells = <1>;
4856 pdc: interrupt-controller@b220000 {
4857 compatible = "qcom,sa8775p-pdc", "qcom,pdc";
4860 qcom,pdc-ranges = <0 480 40>,
4898 #interrupt-cells = <2>;
4899 interrupt-parent = <&intc>;
4900 interrupt-controller;
4903 tsens2: thermal-sensor@c251000 {
4904 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
4910 interrupt-names = "uplow", "critical";
4911 #thermal-sensor-cells = <1>;
4914 tsens3: thermal-sensor@c252000 {
4915 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
4921 interrupt-names = "uplow", "critical";
4922 #thermal-sensor-cells = <1>;
4925 tsens0: thermal-sensor@c263000 {
4926 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
4932 interrupt-names = "uplow", "critical";
4933 #thermal-sensor-cells = <1>;
4936 tsens1: thermal-sensor@c265000 {
4937 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
4943 interrupt-names = "uplow", "critical";
4944 #thermal-sensor-cells = <1>;
4947 aoss_qmp: power-management@c300000 {
4948 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
4950 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4954 #clock-cells = <0>;
4958 compatible = "qcom,rpmh-stats";
4963 compatible = "qcom,spmi-pmic-arb";
4969 reg-names = "core",
4976 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4977 interrupt-names = "periph_irq";
4978 interrupt-controller;
4979 #interrupt-cells = <4>;
4980 #address-cells = <2>;
4981 #size-cells = <0>;
4985 compatible = "qcom,sa8775p-tlmm";
4988 gpio-controller;
4989 #gpio-cells = <2>;
4990 interrupt-controller;
4991 #interrupt-cells = <2>;
4992 gpio-ranges = <&tlmm 0 0 149>;
4993 wakeup-parent = <&pdc>;
4995 qup_i2c0_default: qup-i2c0-state {
5000 qup_i2c1_default: qup-i2c1-state {
5005 qup_i2c2_default: qup-i2c2-state {
5010 qup_i2c3_default: qup-i2c3-state {
5015 qup_i2c4_default: qup-i2c4-state {
5020 qup_i2c5_default: qup-i2c5-state {
5025 qup_i2c7_default: qup-i2c7-state {
5030 qup_i2c8_default: qup-i2c8-state {
5035 qup_i2c9_default: qup-i2c9-state {
5040 qup_i2c10_default: qup-i2c10-state {
5045 qup_i2c11_default: qup-i2c11-state {
5050 qup_i2c12_default: qup-i2c12-state {
5055 qup_i2c13_default: qup-i2c13-state {
5060 qup_i2c14_default: qup-i2c14-state {
5065 qup_i2c15_default: qup-i2c15-state {
5070 qup_i2c16_default: qup-i2c16-state {
5075 qup_i2c17_default: qup-i2c17-state {
5080 qup_i2c18_default: qup-i2c18-state {
5085 qup_i2c19_default: qup-i2c19-state {
5090 qup_i2c20_default: qup-i2c20-state {
5095 qup_i2c21_default: qup-i2c21-state {
5100 qup_spi0_default: qup-spi0-state {
5105 qup_spi1_default: qup-spi1-state {
5110 qup_spi2_default: qup-spi2-state {
5115 qup_spi3_default: qup-spi3-state {
5120 qup_spi4_default: qup-spi4-state {
5125 qup_spi5_default: qup-spi5-state {
5130 qup_spi7_default: qup-spi7-state {
5135 qup_spi8_default: qup-spi8-state {
5140 qup_spi9_default: qup-spi9-state {
5145 qup_spi10_default: qup-spi10-state {
5150 qup_spi11_default: qup-spi11-state {
5155 qup_spi12_default: qup-spi12-state {
5160 qup_spi14_default: qup-spi14-state {
5165 qup_spi15_default: qup-spi15-state {
5170 qup_spi16_default: qup-spi16-state {
5175 qup_spi17_default: qup-spi17-state {
5180 qup_spi18_default: qup-spi18-state {
5185 qup_spi19_default: qup-spi19-state {
5190 qup_spi20_default: qup-spi20-state {
5195 qup_spi21_default: qup-spi21-state {
5200 qup_uart0_default: qup-uart0-state {
5201 qup_uart0_cts: qup-uart0-cts-pins {
5206 qup_uart0_rts: qup-uart0-rts-pins {
5211 qup_uart0_tx: qup-uart0-tx-pins {
5216 qup_uart0_rx: qup-uart0-rx-pins {
5222 qup_uart1_default: qup-uart1-state {
5223 qup_uart1_cts: qup-uart1-cts-pins {
5228 qup_uart1_rts: qup-uart1-rts-pins {
5233 qup_uart1_tx: qup-uart1-tx-pins {
5238 qup_uart1_rx: qup-uart1-rx-pins {
5244 qup_uart2_default: qup-uart2-state {
5245 qup_uart2_cts: qup-uart2-cts-pins {
5250 qup_uart2_rts: qup-uart2-rts-pins {
5255 qup_uart2_tx: qup-uart2-tx-pins {
5260 qup_uart2_rx: qup-uart2-rx-pins {
5266 qup_uart3_default: qup-uart3-state {
5267 qup_uart3_cts: qup-uart3-cts-pins {
5272 qup_uart3_rts: qup-uart3-rts-pins {
5277 qup_uart3_tx: qup-uart3-tx-pins {
5282 qup_uart3_rx: qup-uart3-rx-pins {
5288 qup_uart4_default: qup-uart4-state {
5289 qup_uart4_cts: qup-uart4-cts-pins {
5294 qup_uart4_rts: qup-uart4-rts-pins {
5299 qup_uart4_tx: qup-uart4-tx-pins {
5304 qup_uart4_rx: qup-uart4-rx-pins {
5310 qup_uart5_default: qup-uart5-state {
5311 qup_uart5_cts: qup-uart5-cts-pins {
5316 qup_uart5_rts: qup-uart5-rts-pins {
5321 qup_uart5_tx: qup-uart5-tx-pins {
5326 qup_uart5_rx: qup-uart5-rx-pins {
5332 qup_uart7_default: qup-uart7-state {
5333 qup_uart7_cts: qup-uart7-cts-pins {
5338 qup_uart7_rts: qup-uart7-rts-pins {
5343 qup_uart7_tx: qup-uart7-tx-pins {
5348 qup_uart7_rx: qup-uart7-rx-pins {
5354 qup_uart8_default: qup-uart8-state {
5355 qup_uart8_cts: qup-uart8-cts-pins {
5360 qup_uart8_rts: qup-uart8-rts-pins {
5365 qup_uart8_tx: qup-uart8-tx-pins {
5370 qup_uart8_rx: qup-uart8-rx-pins {
5376 qup_uart9_default: qup-uart9-state {
5377 qup_uart9_cts: qup-uart9-cts-pins {
5382 qup_uart9_rts: qup-uart9-rts-pins {
5387 qup_uart9_tx: qup-uart9-tx-pins {
5392 qup_uart9_rx: qup-uart9-rx-pins {
5398 qup_uart10_default: qup-uart10-state {
5403 qup_uart11_default: qup-uart11-state {
5404 qup_uart11_cts: qup-uart11-cts-pins {
5409 qup_uart11_rts: qup-uart11-rts-pins {
5414 qup_uart11_tx: qup-uart11-tx-pins {
5419 qup_uart11_rx: qup-uart11-rx-pins {
5425 qup_uart12_default: qup-uart12-state {
5426 qup_uart12_cts: qup-uart12-cts-pins {
5431 qup_uart12_rts: qup-uart12-rts-pins {
5436 qup_uart12_tx: qup-uart12-tx-pins {
5441 qup_uart12_rx: qup-uart12-rx-pins {
5447 qup_uart14_default: qup-uart14-state {
5448 qup_uart14_cts: qup-uart14-cts-pins {
5453 qup_uart14_rts: qup-uart14-rts-pins {
5458 qup_uart14_tx: qup-uart14-tx-pins {
5463 qup_uart14_rx: qup-uart14-rx-pins {
5469 qup_uart15_default: qup-uart15-state {
5470 qup_uart15_cts: qup-uart15-cts-pins {
5475 qup_uart15_rts: qup-uart15-rts-pins {
5480 qup_uart15_tx: qup-uart15-tx-pins {
5485 qup_uart15_rx: qup-uart15-rx-pins {
5491 qup_uart16_default: qup-uart16-state {
5492 qup_uart16_cts: qup-uart16-cts-pins {
5497 qup_uart16_rts: qup-uart16-rts-pins {
5502 qup_uart16_tx: qup-uart16-tx-pins {
5507 qup_uart16_rx: qup-uart16-rx-pins {
5513 qup_uart17_default: qup-uart17-state {
5514 qup_uart17_cts: qup-uart17-cts-pins {
5519 qup_uart17_rts: qup0-uart17-rts-pins {
5524 qup_uart17_tx: qup0-uart17-tx-pins {
5529 qup_uart17_rx: qup0-uart17-rx-pins {
5535 qup_uart18_default: qup-uart18-state {
5536 qup_uart18_cts: qup-uart18-cts-pins {
5541 qup_uart18_rts: qup-uart18-rts-pins {
5546 qup_uart18_tx: qup-uart18-tx-pins {
5551 qup_uart18_rx: qup-uart18-rx-pins {
5557 qup_uart19_default: qup-uart19-state {
5558 qup_uart19_cts: qup-uart19-cts-pins {
5563 qup_uart19_rts: qup-uart19-rts-pins {
5568 qup_uart19_tx: qup-uart19-tx-pins {
5573 qup_uart19_rx: qup-uart19-rx-pins {
5579 qup_uart20_default: qup-uart20-state {
5580 qup_uart20_cts: qup-uart20-cts-pins {
5585 qup_uart20_rts: qup-uart20-rts-pins {
5590 qup_uart20_tx: qup-uart20-tx-pins {
5595 qup_uart20_rx: qup-uart20-rx-pins {
5601 qup_uart21_default: qup-uart21-state {
5602 qup_uart21_cts: qup-uart21-cts-pins {
5607 qup_uart21_rts: qup-uart21-rts-pins {
5612 qup_uart21_tx: qup-uart21-tx-pins {
5617 qup_uart21_rx: qup-uart21-rx-pins {
5625 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd";
5629 #address-cells = <1>;
5630 #size-cells = <1>;
5632 pil-reloc@94c {
5633 compatible = "qcom,pil-reloc-info";
5639 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5641 #iommu-cells = <2>;
5642 #global-interrupts = <2>;
5643 dma-coherent;
5778 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5780 #iommu-cells = <2>;
5781 #global-interrupts = <2>;
5782 dma-coherent;
5852 intc: interrupt-controller@17a00000 {
5853 compatible = "arm,gic-v3";
5856 interrupt-controller;
5857 #interrupt-cells = <3>;
5859 #redistributor-regions = <1>;
5860 redistributor-stride = <0x0 0x20000>;
5864 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
5871 compatible = "arm,armv7-timer-mem";
5874 #address-cells = <1>;
5875 #size-cells = <1>;
5882 frame-number = <0>;
5888 frame-number = <1>;
5895 frame-number = <2>;
5902 frame-number = <3>;
5909 frame-number = <4>;
5916 frame-number = <5>;
5923 frame-number = <6>;
5929 compatible = "qcom,rpmh-rsc";
5933 reg-names = "drv-0", "drv-1", "drv-2";
5937 qcom,tcs-offset = <0xd00>;
5938 qcom,drv-id = <2>;
5939 qcom,tcs-config = <ACTIVE_TCS 2>,
5944 power-domains = <&system_pd>;
5946 apps_bcm_voter: bcm-voter {
5947 compatible = "qcom,bcm-voter";
5950 rpmhcc: clock-controller {
5951 compatible = "qcom,sa8775p-rpmh-clk";
5952 #clock-cells = <1>;
5953 clock-names = "xo";
5957 rpmhpd: power-controller {
5958 compatible = "qcom,sa8775p-rpmhpd";
5959 #power-domain-cells = <1>;
5960 operating-points-v2 = <&rpmhpd_opp_table>;
5962 rpmhpd_opp_table: opp-table {
5963 compatible = "operating-points-v2";
5965 rpmhpd_opp_ret: opp-0 {
5966 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5969 rpmhpd_opp_min_svs: opp-1 {
5970 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5974 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5978 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5981 rpmhpd_opp_svs_l1: opp-4 {
5982 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5985 rpmhpd_opp_nom: opp-5 {
5986 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5989 rpmhpd_opp_nom_l1: opp-6 {
5990 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5993 rpmhpd_opp_nom_l2: opp-7 {
5994 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5997 rpmhpd_opp_turbo: opp-8 {
5998 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6001 rpmhpd_opp_turbo_l1: opp-9 {
6002 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6009 compatible = "qcom,sa8775p-epss-l3",
6010 "qcom,epss-l3";
6013 clock-names = "xo", "alternate";
6014 #interconnect-cells = <1>;
6018 compatible = "qcom,sa8775p-cpufreq-epss",
6019 "qcom,cpufreq-epss";
6022 reg-names = "freq-domain0", "freq-domain1";
6026 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
6029 clock-names = "xo", "alternate";
6031 #freq-domain-cells = <1>;
6035 compatible = "qcom,sa8775p-epss-l3",
6036 "qcom,epss-l3";
6039 clock-names = "xo", "alternate";
6040 #interconnect-cells = <1>;
6044 compatible = "qcom,sa8775p-gpdsp0-pas";
6047 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
6052 interrupt-names = "wdog", "fatal", "ready",
6053 "handover", "stop-ack";
6056 clock-names = "xo";
6058 power-domains = <&rpmhpd RPMHPD_CX>,
6060 power-domain-names = "cx", "mxc";
6065 memory-region = <&pil_gdsp0_mem>;
6069 qcom,smem-states = <&smp2p_gpdsp0_out 0>;
6070 qcom,smem-state-names = "stop";
6074 glink-edge {
6075 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
6082 qcom,remote-pid = <17>;
6087 compatible = "qcom,sa8775p-gpdsp1-pas";
6090 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
6095 interrupt-names = "wdog", "fatal", "ready",
6096 "handover", "stop-ack";
6099 clock-names = "xo";
6101 power-domains = <&rpmhpd RPMHPD_CX>,
6103 power-domain-names = "cx", "mxc";
6108 memory-region = <&pil_gdsp1_mem>;
6112 qcom,smem-states = <&smp2p_gpdsp1_out 0>;
6113 qcom,smem-state-names = "stop";
6117 glink-edge {
6118 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
6125 qcom,remote-pid = <18>;
6129 dispcc1: clock-controller@22100000 {
6130 compatible = "qcom,sa8775p-dispcc1";
6138 power-domains = <&rpmhpd SA8775P_MMCX>;
6139 #clock-cells = <1>;
6140 #reset-cells = <1>;
6141 #power-domain-cells = <1>;
6146 compatible = "qcom,sa8775p-ethqos";
6149 reg-names = "stmmaceth", "rgmii";
6153 interrupt-names = "macirq", "sfty";
6159 clock-names = "stmmaceth",
6168 interconnect-names = "mac-mem", "cpu-mac";
6170 power-domains = <&gcc EMAC1_GDSC>;
6173 phy-names = "serdes";
6176 dma-coherent;
6180 rx-fifo-depth = <16384>;
6181 tx-fifo-depth = <16384>;
6187 compatible = "qcom,sa8775p-ethqos";
6190 reg-names = "stmmaceth", "rgmii";
6194 interrupt-names = "macirq", "sfty";
6200 clock-names = "stmmaceth",
6209 interconnect-names = "mac-mem", "cpu-mac";
6211 power-domains = <&gcc EMAC0_GDSC>;
6214 phy-names = "serdes";
6217 dma-coherent;
6221 rx-fifo-depth = <16384>;
6222 tx-fifo-depth = <16384>;
6228 compatible = "qcom,sa8775p-cdsp0-pas";
6231 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6236 interrupt-names = "wdog", "fatal", "ready",
6237 "handover", "stop-ack";
6240 clock-names = "xo";
6242 power-domains = <&rpmhpd RPMHPD_CX>,
6245 power-domain-names = "cx", "mxc", "nsp";
6250 memory-region = <&pil_cdsp0_mem>;
6254 qcom,smem-states = <&smp2p_cdsp0_out 0>;
6255 qcom,smem-state-names = "stop";
6259 glink-edge {
6260 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6267 qcom,remote-pid = <5>;
6271 qcom,glink-channels = "fastrpcglink-apps-dsp";
6273 #address-cells = <1>;
6274 #size-cells = <0>;
6276 compute-cb@1 {
6277 compatible = "qcom,fastrpc-compute-cb";
6281 dma-coherent;
6284 compute-cb@2 {
6285 compatible = "qcom,fastrpc-compute-cb";
6289 dma-coherent;
6292 compute-cb@3 {
6293 compatible = "qcom,fastrpc-compute-cb";
6297 dma-coherent;
6300 compute-cb@4 {
6301 compatible = "qcom,fastrpc-compute-cb";
6305 dma-coherent;
6308 compute-cb@5 {
6309 compatible = "qcom,fastrpc-compute-cb";
6313 dma-coherent;
6316 compute-cb@6 {
6317 compatible = "qcom,fastrpc-compute-cb";
6321 dma-coherent;
6324 compute-cb@7 {
6325 compatible = "qcom,fastrpc-compute-cb";
6329 dma-coherent;
6332 compute-cb@8 {
6333 compatible = "qcom,fastrpc-compute-cb";
6337 dma-coherent;
6340 compute-cb@9 {
6341 compatible = "qcom,fastrpc-compute-cb";
6345 dma-coherent;
6348 compute-cb@11 {
6349 compatible = "qcom,fastrpc-compute-cb";
6353 dma-coherent;
6360 compatible = "qcom,sa8775p-cdsp1-pas";
6363 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
6368 interrupt-names = "wdog", "fatal", "ready",
6369 "handover", "stop-ack";
6372 clock-names = "xo";
6374 power-domains = <&rpmhpd RPMHPD_CX>,
6377 power-domain-names = "cx", "mxc", "nsp";
6382 memory-region = <&pil_cdsp1_mem>;
6386 qcom,smem-states = <&smp2p_cdsp1_out 0>;
6387 qcom,smem-state-names = "stop";
6391 glink-edge {
6392 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
6399 qcom,remote-pid = <12>;
6403 qcom,glink-channels = "fastrpcglink-apps-dsp";
6405 #address-cells = <1>;
6406 #size-cells = <0>;
6408 compute-cb@1 {
6409 compatible = "qcom,fastrpc-compute-cb";
6413 dma-coherent;
6416 compute-cb@2 {
6417 compatible = "qcom,fastrpc-compute-cb";
6421 dma-coherent;
6424 compute-cb@3 {
6425 compatible = "qcom,fastrpc-compute-cb";
6429 dma-coherent;
6432 compute-cb@4 {
6433 compatible = "qcom,fastrpc-compute-cb";
6437 dma-coherent;
6440 compute-cb@5 {
6441 compatible = "qcom,fastrpc-compute-cb";
6445 dma-coherent;
6448 compute-cb@6 {
6449 compatible = "qcom,fastrpc-compute-cb";
6453 dma-coherent;
6456 compute-cb@7 {
6457 compatible = "qcom,fastrpc-compute-cb";
6461 dma-coherent;
6464 compute-cb@8 {
6465 compatible = "qcom,fastrpc-compute-cb";
6469 dma-coherent;
6472 compute-cb@9 {
6473 compatible = "qcom,fastrpc-compute-cb";
6477 dma-coherent;
6480 compute-cb@10 {
6481 compatible = "qcom,fastrpc-compute-cb";
6485 dma-coherent;
6488 compute-cb@11 {
6489 compatible = "qcom,fastrpc-compute-cb";
6493 dma-coherent;
6496 compute-cb@12 {
6497 compatible = "qcom,fastrpc-compute-cb";
6501 dma-coherent;
6504 compute-cb@13 {
6505 compatible = "qcom,fastrpc-compute-cb";
6509 dma-coherent;
6516 compatible = "qcom,sa8775p-adsp-pas";
6519 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6524 interrupt-names = "wdog", "fatal", "ready", "handover",
6525 "stop-ack";
6528 clock-names = "xo";
6530 power-domains = <&rpmhpd RPMHPD_LCX>,
6532 power-domain-names = "lcx", "lmx";
6536 memory-region = <&pil_adsp_mem>;
6540 qcom,smem-states = <&smp2p_adsp_out 0>;
6541 qcom,smem-state-names = "stop";
6545 remoteproc_adsp_glink: glink-edge {
6546 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6553 qcom,remote-pid = <2>;
6557 qcom,glink-channels = "fastrpcglink-apps-dsp";
6559 memory-region = <&adsp_rpc_remote_heap_mem>;
6562 #address-cells = <1>;
6563 #size-cells = <0>;
6565 compute-cb@3 {
6566 compatible = "qcom,fastrpc-compute-cb";
6569 dma-coherent;
6572 compute-cb@4 {
6573 compatible = "qcom,fastrpc-compute-cb";
6576 dma-coherent;
6579 compute-cb@5 {
6580 compatible = "qcom,fastrpc-compute-cb";
6584 dma-coherent;
6591 thermal-zones {
6592 aoss-0-thermal {
6593 thermal-sensors = <&tsens0 0>;
6596 trip-point0 {
6602 trip-point1 {
6610 cpu-0-0-0-thermal {
6611 polling-delay-passive = <10>;
6613 thermal-sensors = <&tsens0 1>;
6616 trip-point0 {
6622 trip-point1 {
6630 cpu-0-1-0-thermal {
6631 polling-delay-passive = <10>;
6633 thermal-sensors = <&tsens0 2>;
6636 trip-point0 {
6642 trip-point1 {
6650 cpu-0-2-0-thermal {
6651 polling-delay-passive = <10>;
6653 thermal-sensors = <&tsens0 3>;
6656 trip-point0 {
6662 trip-point1 {
6670 cpu-0-3-0-thermal {
6671 polling-delay-passive = <10>;
6673 thermal-sensors = <&tsens0 4>;
6676 trip-point0 {
6682 trip-point1 {
6690 gpuss-0-thermal {
6691 polling-delay-passive = <10>;
6693 thermal-sensors = <&tsens0 5>;
6696 trip-point0 {
6702 trip-point1 {
6710 gpuss-1-thermal {
6711 polling-delay-passive = <10>;
6713 thermal-sensors = <&tsens0 6>;
6716 trip-point0 {
6722 trip-point1 {
6730 gpuss-2-thermal {
6731 polling-delay-passive = <10>;
6733 thermal-sensors = <&tsens0 7>;
6736 trip-point0 {
6742 trip-point1 {
6750 audio-thermal {
6751 thermal-sensors = <&tsens0 8>;
6754 trip-point0 {
6760 trip-point1 {
6768 camss-0-thermal {
6769 thermal-sensors = <&tsens0 9>;
6772 trip-point0 {
6778 trip-point1 {
6786 pcie-0-thermal {
6787 thermal-sensors = <&tsens0 10>;
6790 trip-point0 {
6796 trip-point1 {
6804 cpuss-0-0-thermal {
6805 thermal-sensors = <&tsens0 11>;
6808 trip-point0 {
6814 trip-point1 {
6822 aoss-1-thermal {
6823 thermal-sensors = <&tsens1 0>;
6826 trip-point0 {
6832 trip-point1 {
6840 cpu-0-0-1-thermal {
6841 polling-delay-passive = <10>;
6843 thermal-sensors = <&tsens1 1>;
6846 trip-point0 {
6852 trip-point1 {
6860 cpu-0-1-1-thermal {
6861 polling-delay-passive = <10>;
6863 thermal-sensors = <&tsens1 2>;
6866 trip-point0 {
6872 trip-point1 {
6880 cpu-0-2-1-thermal {
6881 polling-delay-passive = <10>;
6883 thermal-sensors = <&tsens1 3>;
6886 trip-point0 {
6892 trip-point1 {
6900 cpu-0-3-1-thermal {
6901 polling-delay-passive = <10>;
6903 thermal-sensors = <&tsens1 4>;
6906 trip-point0 {
6912 trip-point1 {
6920 gpuss-3-thermal {
6921 polling-delay-passive = <10>;
6923 thermal-sensors = <&tsens1 5>;
6926 trip-point0 {
6932 trip-point1 {
6940 gpuss-4-thermal {
6941 polling-delay-passive = <10>;
6943 thermal-sensors = <&tsens1 6>;
6946 trip-point0 {
6952 trip-point1 {
6960 gpuss-5-thermal {
6961 polling-delay-passive = <10>;
6963 thermal-sensors = <&tsens1 7>;
6966 trip-point0 {
6972 trip-point1 {
6980 video-thermal {
6981 thermal-sensors = <&tsens1 8>;
6984 trip-point0 {
6990 trip-point1 {
6998 camss-1-thermal {
6999 thermal-sensors = <&tsens1 9>;
7002 trip-point0 {
7008 trip-point1 {
7016 pcie-1-thermal {
7017 thermal-sensors = <&tsens1 10>;
7020 trip-point0 {
7026 trip-point1 {
7034 cpuss-0-1-thermal {
7035 thermal-sensors = <&tsens1 11>;
7038 trip-point0 {
7044 trip-point1 {
7052 aoss-2-thermal {
7053 thermal-sensors = <&tsens2 0>;
7056 trip-point0 {
7062 trip-point1 {
7070 cpu-1-0-0-thermal {
7071 polling-delay-passive = <10>;
7073 thermal-sensors = <&tsens2 1>;
7076 trip-point0 {
7082 trip-point1 {
7090 cpu-1-1-0-thermal {
7091 polling-delay-passive = <10>;
7093 thermal-sensors = <&tsens2 2>;
7096 trip-point0 {
7102 trip-point1 {
7110 cpu-1-2-0-thermal {
7111 polling-delay-passive = <10>;
7113 thermal-sensors = <&tsens2 3>;
7116 trip-point0 {
7122 trip-point1 {
7130 cpu-1-3-0-thermal {
7131 polling-delay-passive = <10>;
7133 thermal-sensors = <&tsens2 4>;
7136 trip-point0 {
7142 trip-point1 {
7150 nsp-0-0-0-thermal {
7151 polling-delay-passive = <10>;
7153 thermal-sensors = <&tsens2 5>;
7156 trip-point0 {
7162 trip-point1 {
7170 nsp-0-1-0-thermal {
7171 polling-delay-passive = <10>;
7173 thermal-sensors = <&tsens2 6>;
7176 trip-point0 {
7182 trip-point1 {
7190 nsp-0-2-0-thermal {
7191 polling-delay-passive = <10>;
7193 thermal-sensors = <&tsens2 7>;
7196 trip-point0 {
7202 trip-point1 {
7210 nsp-1-0-0-thermal {
7211 polling-delay-passive = <10>;
7213 thermal-sensors = <&tsens2 8>;
7216 trip-point0 {
7222 trip-point1 {
7230 nsp-1-1-0-thermal {
7231 polling-delay-passive = <10>;
7233 thermal-sensors = <&tsens2 9>;
7236 trip-point0 {
7242 trip-point1 {
7250 nsp-1-2-0-thermal {
7251 polling-delay-passive = <10>;
7253 thermal-sensors = <&tsens2 10>;
7256 trip-point0 {
7262 trip-point1 {
7270 ddrss-0-thermal {
7271 thermal-sensors = <&tsens2 11>;
7274 trip-point0 {
7280 trip-point1 {
7288 cpuss-1-0-thermal {
7289 thermal-sensors = <&tsens2 12>;
7292 trip-point0 {
7298 trip-point1 {
7306 aoss-3-thermal {
7307 thermal-sensors = <&tsens3 0>;
7310 trip-point0 {
7316 trip-point1 {
7324 cpu-1-0-1-thermal {
7325 polling-delay-passive = <10>;
7327 thermal-sensors = <&tsens3 1>;
7330 trip-point0 {
7336 trip-point1 {
7344 cpu-1-1-1-thermal {
7345 polling-delay-passive = <10>;
7347 thermal-sensors = <&tsens3 2>;
7350 trip-point0 {
7356 trip-point1 {
7364 cpu-1-2-1-thermal {
7365 polling-delay-passive = <10>;
7367 thermal-sensors = <&tsens3 3>;
7370 trip-point0 {
7376 trip-point1 {
7384 cpu-1-3-1-thermal {
7385 polling-delay-passive = <10>;
7387 thermal-sensors = <&tsens3 4>;
7390 trip-point0 {
7396 trip-point1 {
7404 nsp-0-0-1-thermal {
7405 polling-delay-passive = <10>;
7407 thermal-sensors = <&tsens3 5>;
7410 trip-point0 {
7416 trip-point1 {
7424 nsp-0-1-1-thermal {
7425 polling-delay-passive = <10>;
7427 thermal-sensors = <&tsens3 6>;
7430 trip-point0 {
7436 trip-point1 {
7444 nsp-0-2-1-thermal {
7445 polling-delay-passive = <10>;
7447 thermal-sensors = <&tsens3 7>;
7450 trip-point0 {
7456 trip-point1 {
7464 nsp-1-0-1-thermal {
7465 polling-delay-passive = <10>;
7467 thermal-sensors = <&tsens3 8>;
7470 trip-point0 {
7476 trip-point1 {
7484 nsp-1-1-1-thermal {
7485 polling-delay-passive = <10>;
7487 thermal-sensors = <&tsens3 9>;
7490 trip-point0 {
7496 trip-point1 {
7504 nsp-1-2-1-thermal {
7505 polling-delay-passive = <10>;
7507 thermal-sensors = <&tsens3 10>;
7510 trip-point0 {
7516 trip-point1 {
7524 ddrss-1-thermal {
7525 thermal-sensors = <&tsens3 11>;
7528 trip-point0 {
7534 trip-point1 {
7542 cpuss-1-1-thermal {
7543 thermal-sensors = <&tsens3 12>;
7546 trip-point0 {
7552 trip-point1 {
7562 compatible = "arm,armv8-timer";
7570 compatible = "qcom,pcie-sa8775p";
7577 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
7580 #address-cells = <3>;
7581 #size-cells = <2>;
7584 bus-range = <0x00 0xff>;
7586 dma-coherent;
7588 linux,pci-domain = <0>;
7589 num-lanes = <2>;
7600 interrupt-names = "msi0",
7609 #interrupt-cells = <1>;
7610 interrupt-map-mask = <0 0 0 0x7>;
7611 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
7622 clock-names = "aux",
7628 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
7629 assigned-clock-rates = <19200000>;
7633 interconnect-names = "pcie-mem", "cpu-pcie";
7635 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
7639 reset-names = "pci";
7640 power-domains = <&gcc PCIE_0_GDSC>;
7643 phy-names = "pciephy";
7650 bus-range = <0x01 0xff>;
7652 #address-cells = <3>;
7653 #size-cells = <2>;
7658 pcie0_ep: pcie-ep@1c00000 {
7659 compatible = "qcom,sa8775p-pcie-ep";
7667 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
7676 clock-names = "aux",
7686 interrupt-names = "global", "doorbell", "dma";
7690 interconnect-names = "pcie-mem", "cpu-pcie";
7692 dma-coherent;
7695 reset-names = "core";
7696 power-domains = <&gcc PCIE_0_GDSC>;
7698 phy-names = "pciephy";
7699 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
7700 num-lanes = <2>;
7701 linux,pci-domain = <0>;
7707 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
7718 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
7721 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
7722 assigned-clock-rates = <100000000>;
7725 reset-names = "phy";
7727 #clock-cells = <0>;
7728 clock-output-names = "pcie_0_pipe_clk";
7730 #phy-cells = <0>;
7736 compatible = "qcom,pcie-sa8775p";
7743 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
7746 #address-cells = <3>;
7747 #size-cells = <2>;
7750 bus-range = <0x00 0xff>;
7752 dma-coherent;
7754 linux,pci-domain = <1>;
7755 num-lanes = <4>;
7766 interrupt-names = "msi0",
7775 #interrupt-cells = <1>;
7776 interrupt-map-mask = <0 0 0 0x7>;
7777 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
7788 clock-names = "aux",
7794 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
7795 assigned-clock-rates = <19200000>;
7799 interconnect-names = "pcie-mem", "cpu-pcie";
7801 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
7805 reset-names = "pci";
7806 power-domains = <&gcc PCIE_1_GDSC>;
7809 phy-names = "pciephy";
7816 bus-range = <0x01 0xff>;
7818 #address-cells = <3>;
7819 #size-cells = <2>;
7824 pcie1_ep: pcie-ep@1c10000 {
7825 compatible = "qcom,sa8775p-pcie-ep";
7833 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
7842 clock-names = "aux",
7852 interrupt-names = "global", "doorbell", "dma";
7856 interconnect-names = "pcie-mem", "cpu-pcie";
7858 dma-coherent;
7861 reset-names = "core";
7862 power-domains = <&gcc PCIE_1_GDSC>;
7864 phy-names = "pciephy";
7865 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
7866 num-lanes = <4>;
7867 linux,pci-domain = <1>;
7873 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
7884 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
7887 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
7888 assigned-clock-rates = <100000000>;
7891 reset-names = "phy";
7893 #clock-cells = <0>;
7894 clock-output-names = "pcie_1_pipe_clk";
7896 #phy-cells = <0>;