Lines Matching +full:1 +full:fc0000

154 			qcom,freq-domain = <&cpufreq_hw 1>;
184 qcom,freq-domain = <&cpufreq_hw 1>;
208 qcom,freq-domain = <&cpufreq_hw 1>;
232 qcom,freq-domain = <&cpufreq_hw 1>;
300 gold_rail_cpu_sleep_0: cpu-sleep-1 {
320 cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
946 #qcom,smem-state-cells = <1>;
969 #qcom,smem-state-cells = <1>;
992 #qcom,smem-state-cells = <1>;
1015 #qcom,smem-state-cells = <1>;
1038 #qcom,smem-state-cells = <1>;
1057 #clock-cells = <1>;
1058 #reset-cells = <1>;
1059 #power-domain-cells = <1>;
1124 #address-cells = <1>;
1142 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1151 #address-cells = <1>;
1169 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1195 #address-cells = <1>;
1212 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1213 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1222 #address-cells = <1>;
1239 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1240 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1266 #address-cells = <1>;
1284 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1309 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1312 #address-cells = <1>;
1337 #address-cells = <1>;
1355 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1364 #address-cells = <1>;
1382 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1424 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1427 #address-cells = <1>;
1435 #address-cells = <1>;
1453 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1479 #address-cells = <1>;
1497 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1506 #address-cells = <1>;
1524 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1550 #address-cells = <1>;
1568 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1577 #address-cells = <1>;
1595 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1657 #address-cells = <1>;
1675 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1684 #address-cells = <1>;
1702 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1728 #address-cells = <1>;
1745 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1746 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1755 #address-cells = <1>;
1772 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1773 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1799 #address-cells = <1>;
1817 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1826 #address-cells = <1>;
1844 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1870 #address-cells = <1>;
1888 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1897 #address-cells = <1>;
1915 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1941 #address-cells = <1>;
1959 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1968 #address-cells = <1>;
1986 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2012 #address-cells = <1>;
2030 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2039 #address-cells = <1>;
2057 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2118 #address-cells = <1>;
2136 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
2145 #address-cells = <1>;
2163 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
2190 #address-cells = <1>;
2207 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
2208 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
2217 #address-cells = <1>;
2234 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
2235 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
2262 #address-cells = <1>;
2280 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
2289 #address-cells = <1>;
2307 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
2333 #address-cells = <1>;
2351 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
2360 #address-cells = <1>;
2378 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
2405 #address-cells = <1>;
2423 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2432 #address-cells = <1>;
2450 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2477 #address-cells = <1>;
2495 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2504 #address-cells = <1>;
2522 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2548 #address-cells = <1>;
2566 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2603 #address-cells = <1>;
2621 <&gpi_dma3 1 0 QCOM_GPI_I2C>;
2630 #address-cells = <1>;
2648 <&gpi_dma3 1 0 QCOM_GPI_SPI>;
2678 ufs_mem_hc: ufshc@1d84000 {
2685 #reset-cells = <1>;
2720 ufs_mem_phy: phy@1d87000 {
2738 ice: crypto@1d88000 {
2745 cryptobam: dma-controller@1dc4000 {
2749 #dma-cells = <1>;
2766 #address-cells = <1>;
2777 port@1 {
2778 reg = <1>;
2844 #address-cells = <1>;
2855 port@1 {
2856 reg = <1>;
2902 #address-cells = <1>;
2940 #address-cells = <1>;
2970 #address-cells = <1>;
2981 port@1 {
2982 reg = <1>;
3058 #address-cells = <1>;
3069 port@1 {
3070 reg = <1>;
3124 #address-cells = <1>;
3179 #address-cells = <1>;
3190 port@1 {
3191 reg = <1>;
3226 #address-cells = <1>;
3237 port@1 {
3238 reg = <1>;
3556 #address-cells = <1>;
3567 port@1 {
3568 reg = <1>;
3642 #address-cells = <1>;
3720 #address-cells = <1>;
3731 port@1 {
3732 reg = <1>;
4072 tcsr_mutex: hwlock@1f40000 {
4075 #hwlock-cells = <1>;
4078 tcsr: syscon@1fc0000 {
4092 #clock-cells = <1>;
4093 #reset-cells = <1>;
4094 #power-domain-cells = <1>;
4167 opp-1 {
4221 opp-1 {
4343 #clock-cells = <1>;
4344 #reset-cells = <1>;
4345 #power-domain-cells = <1>;
4356 #clock-cells = <1>;
4357 #reset-cells = <1>;
4358 #power-domain-cells = <1>;
4387 #interrupt-cells = <1>;
4424 #address-cells = <1>;
4435 port@1 {
4436 reg = <1>;
4514 #address-cells = <1>;
4520 #address-cells = <1>;
4531 port@1 {
4532 reg = <1>;
4557 #clock-cells = <1>;
4596 #address-cells = <1>;
4602 #address-cells = <1>;
4613 port@1 {
4614 reg = <1>;
4630 #clock-cells = <1>;
4653 #clock-cells = <1>;
4672 #clock-cells = <1>;
4702 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
4714 #address-cells = <1>;
4725 port@1 {
4726 reg = <1>;
4781 assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
4793 #address-cells = <1>;
4804 port@1 {
4805 reg = <1>;
4844 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
4845 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
4851 #clock-cells = <1>;
4852 #reset-cells = <1>;
4853 #power-domain-cells = <1>;
4862 <54 263 1>,
4868 <70 520 1>,
4869 <73 523 1>,
4872 <159 638 1>,
4876 <201 449 1>,
4877 <202 89 1>,
4878 <203 451 1>,
4879 <204 462 1>,
4880 <205 264 1>,
4881 <206 579 1>,
4882 <207 653 1>,
4883 <208 656 1>,
4884 <209 659 1>,
4885 <210 122 1>,
4886 <211 699 1>,
4887 <212 705 1>,
4888 <213 450 1>,
4893 <228 440 1>,
4894 <229 663 1>,
4911 #thermal-sensor-cells = <1>;
4922 #thermal-sensor-cells = <1>;
4933 #thermal-sensor-cells = <1>;
4944 #thermal-sensor-cells = <1>;
4976 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5629 #address-cells = <1>;
5630 #size-cells = <1>;
5859 #redistributor-regions = <1>;
5874 #address-cells = <1>;
5875 #size-cells = <1>;
5888 frame-number = <1>;
5933 reg-names = "drv-0", "drv-1", "drv-2";
5952 #clock-cells = <1>;
5959 #power-domain-cells = <1>;
5969 rpmhpd_opp_min_svs: opp-1 {
6014 #interconnect-cells = <1>;
6026 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
6031 #freq-domain-cells = <1>;
6040 #interconnect-cells = <1>;
6049 <&smp2p_gpdsp0_in 1 0>,
6092 <&smp2p_gpdsp1_in 1 0>,
6139 #clock-cells = <1>;
6140 #reset-cells = <1>;
6141 #power-domain-cells = <1>;
6233 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>,
6273 #address-cells = <1>;
6276 compute-cb@1 {
6278 reg = <1>;
6365 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>,
6405 #address-cells = <1>;
6408 compute-cb@1 {
6410 reg = <1>;
6521 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
6562 #address-cells = <1>;
6613 thermal-sensors = <&tsens0 1>;
6630 cpu-0-1-0-thermal {
6710 gpuss-1-thermal {
6822 aoss-1-thermal {
6840 cpu-0-0-1-thermal {
6843 thermal-sensors = <&tsens1 1>;
6860 cpu-0-1-1-thermal {
6880 cpu-0-2-1-thermal {
6900 cpu-0-3-1-thermal {
6998 camss-1-thermal {
7016 pcie-1-thermal {
7034 cpuss-0-1-thermal {
7070 cpu-1-0-0-thermal {
7073 thermal-sensors = <&tsens2 1>;
7090 cpu-1-1-0-thermal {
7110 cpu-1-2-0-thermal {
7130 cpu-1-3-0-thermal {
7170 nsp-0-1-0-thermal {
7210 nsp-1-0-0-thermal {
7230 nsp-1-1-0-thermal {
7250 nsp-1-2-0-thermal {
7288 cpuss-1-0-thermal {
7324 cpu-1-0-1-thermal {
7327 thermal-sensors = <&tsens3 1>;
7344 cpu-1-1-1-thermal {
7364 cpu-1-2-1-thermal {
7384 cpu-1-3-1-thermal {
7404 nsp-0-0-1-thermal {
7424 nsp-0-1-1-thermal {
7444 nsp-0-2-1-thermal {
7464 nsp-1-0-1-thermal {
7484 nsp-1-1-1-thermal {
7504 nsp-1-2-1-thermal {
7524 ddrss-1-thermal {
7542 cpuss-1-1-thermal {
7569 pcie0: pcie@1c00000 {
7609 #interrupt-cells = <1>;
7611 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
7658 pcie0_ep: pcie-ep@1c00000 {
7706 pcie0_phy: phy@1c04000 {
7735 pcie1: pcie@1c10000 {
7754 linux,pci-domain = <1>;
7775 #interrupt-cells = <1>;
7777 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
7824 pcie1_ep: pcie-ep@1c10000 {
7867 linux,pci-domain = <1>;
7872 pcie1_phy: phy@1c14000 {