Lines Matching +full:0 +full:x990000
33 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x300>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
150 reg = <0x0 0x10000>;
180 reg = <0x0 0x10100>;
204 reg = <0x0 0x10200>;
228 reg = <0x0 0x10300>;
290 gold_cpu_sleep_0: cpu-sleep-0 {
293 arm,psci-suspend-param = <0x40000003>;
303 arm,psci-suspend-param = <0x40000004>;
312 cluster_sleep_gold: cluster-sleep-0 {
314 arm,psci-suspend-param = <0x41000044>;
322 arm,psci-suspend-param = <0x42000144>;
516 qcom,dload-mode = <&tcsr 0x13000>;
608 reg = <0x0 0x80000000 0x0 0x0>;
630 #power-domain-cells = <0>;
637 #power-domain-cells = <0>;
644 #power-domain-cells = <0>;
651 #power-domain-cells = <0>;
658 #power-domain-cells = <0>;
665 #power-domain-cells = <0>;
672 #power-domain-cells = <0>;
679 #power-domain-cells = <0>;
686 #power-domain-cells = <0>;
692 #power-domain-cells = <0>;
698 #power-domain-cells = <0>;
709 reg = <0x0 0x80000000 0x0 0x10000000>;
714 reg = <0x0 0x90000000 0x0 0x600000>;
719 reg = <0x0 0x90600000 0x0 0x200000>;
724 reg = <0x0 0x90800000 0x0 0x60000>;
730 reg = <0x0 0x90860000 0x0 0x20000>;
735 reg = <0x0 0x908b0000 0x0 0x10000>;
740 reg = <0x0 0x908c0000 0x0 0x1000>;
745 reg = <0x0 0x908f0000 0x0 0xe000>;
750 reg = <0x0 0x908fe000 0x0 0x2000>;
756 reg = <0x0 0x90900000 0x0 0x200000>;
762 reg = <0x0 0x90c00000 0x0 0x100000>;
767 reg = <0x0 0x90d00000 0x0 0x100000>;
772 reg = <0x0 0x90e00000 0x0 0x300000>;
777 reg = <0x0 0x91b00000 0x0 0x40000>;
782 reg = <0x0 0x91b40000 0x0 0x40000>;
787 reg = <0x0 0x91b80000 0x0 0x10000>;
792 reg = <0x0 0x91b90000 0x0 0x10000>;
797 reg = <0x0 0x91ba0000 0x0 0x1000>;
803 reg = <0x0 0x91c00000 0x0 0x1400000>;
808 reg = <0x0 0x93b00000 0x0 0xf00000>;
813 reg = <0x0 0x94a00000 0x0 0x800000>;
818 reg = <0x0 0x95200000 0x0 0x500000>;
823 reg = <0x0 0x95c00000 0x0 0x1e00000>;
828 reg = <0x0 0x97b00000 0x0 0x1e00000>;
833 reg = <0x0 0x99900000 0x0 0x1e00000>;
838 reg = <0x0 0x9b800000 0x0 0x1e00000>;
843 reg = <0x0 0x9d600000 0x0 0x2000>;
848 reg = <0x0 0x9d700000 0x0 0x1e00000>;
853 reg = <0x0 0x9f500000 0x0 0x700000>;
858 reg = <0x0 0x9fc00000 0x0 0x700000>;
863 reg = <0x0 0xae000000 0x0 0x1000000>;
868 reg = <0x0 0xb0000000 0x0 0x800000>;
873 reg = <0x0 0xbeb00000 0x0 0x11500000>;
878 reg = <0x0 0xd0000000 0x0 0x40000>;
883 reg = <0x0 0xd0040000 0x0 0x10000>;
888 reg = <0x0 0xd0050000 0x0 0x4000>;
893 reg = <0x0 0xd0054000 0x0 0x9c000>;
898 reg = <0x0 0xd00f0000 0x0 0x10000>;
903 reg = <0x0 0xd0100000 0x0 0x1200000>;
908 reg = <0x0 0xd1300000 0x0 0x500000>;
913 reg = <0x0 0xd1800000 0x0 0x100000>;
918 reg = <0x0 0xd1900000 0x0 0x3800000>;
923 reg = <0x0 0xdb100000 0x0 0x100000>;
928 reg = <0x0 0xdb200000 0x0 0x100000>;
941 qcom,local-pid = <0>;
964 qcom,local-pid = <0>;
987 qcom,local-pid = <0>;
1010 qcom,local-pid = <0>;
1033 qcom,local-pid = <0>;
1048 soc: soc@0 {
1052 ranges = <0 0 0 0 0x10 0>;
1056 reg = <0x0 0x00100000 0x0 0xc7018>;
1062 <0>,
1063 <0>,
1064 <0>,
1067 <0>,
1068 <0>,
1069 <0>,
1072 <0>,
1073 <0>,
1074 <0>;
1080 reg = <0x0 0x00408000 0x0 0x1000>;
1089 reg = <0x0 0x00800000 0x0 0x60000>;
1104 dma-channel-mask = <0xfff>;
1105 iommus = <&apps_smmu 0x5b6 0x0>;
1111 reg = <0x0 0x008c0000 0x0 0x6000>;
1116 iommus = <&apps_smmu 0x5a3 0x0>;
1123 reg = <0x0 0x880000 0x0 0x4000>;
1125 #size-cells = <0>;
1129 pinctrl-0 = <&qup_i2c14_default>;
1141 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1142 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1150 reg = <0x0 0x880000 0x0 0x4000>;
1152 #size-cells = <0>;
1156 pinctrl-0 = <&qup_spi14_default>;
1168 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1169 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1177 reg = <0x0 0x00880000 0x0 0x4000>;
1181 pinctrl-0 = <&qup_uart14_default>;
1194 reg = <0x0 0x884000 0x0 0x4000>;
1196 #size-cells = <0>;
1200 pinctrl-0 = <&qup_i2c15_default>;
1212 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1221 reg = <0x0 0x884000 0x0 0x4000>;
1223 #size-cells = <0>;
1227 pinctrl-0 = <&qup_spi15_default>;
1239 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1248 reg = <0x0 0x00884000 0x0 0x4000>;
1252 pinctrl-0 = <&qup_uart15_default>;
1265 reg = <0x0 0x888000 0x0 0x4000>;
1267 #size-cells = <0>;
1271 pinctrl-0 = <&qup_i2c16_default>;
1283 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1292 reg = <0x0 0x00888000 0x0 0x4000>;
1296 pinctrl-0 = <&qup_spi16_default>;
1308 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1313 #size-cells = <0>;
1319 reg = <0x0 0x00888000 0x0 0x4000>;
1323 pinctrl-0 = <&qup_uart16_default>;
1336 reg = <0x0 0x88c000 0x0 0x4000>;
1338 #size-cells = <0>;
1342 pinctrl-0 = <&qup_i2c17_default>;
1354 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1363 reg = <0x0 0x88c000 0x0 0x4000>;
1365 #size-cells = <0>;
1369 pinctrl-0 = <&qup_spi17_default>;
1381 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1390 reg = <0x0 0x0088c000 0x0 0x4000>;
1394 pinctrl-0 = <&qup_uart17_default>;
1407 reg = <0x0 0x00890000 0x0 0x4000>;
1411 pinctrl-0 = <&qup_i2c18_default>;
1423 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1428 #size-cells = <0>;
1434 reg = <0x0 0x890000 0x0 0x4000>;
1436 #size-cells = <0>;
1440 pinctrl-0 = <&qup_spi18_default>;
1452 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1461 reg = <0x0 0x00890000 0x0 0x4000>;
1465 pinctrl-0 = <&qup_uart18_default>;
1478 reg = <0x0 0x894000 0x0 0x4000>;
1480 #size-cells = <0>;
1484 pinctrl-0 = <&qup_i2c19_default>;
1496 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1505 reg = <0x0 0x894000 0x0 0x4000>;
1507 #size-cells = <0>;
1511 pinctrl-0 = <&qup_spi19_default>;
1523 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1532 reg = <0x0 0x00894000 0x0 0x4000>;
1536 pinctrl-0 = <&qup_uart19_default>;
1549 reg = <0x0 0x898000 0x0 0x4000>;
1551 #size-cells = <0>;
1555 pinctrl-0 = <&qup_i2c20_default>;
1567 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1576 reg = <0x0 0x898000 0x0 0x4000>;
1578 #size-cells = <0>;
1582 pinctrl-0 = <&qup_spi20_default>;
1594 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1603 reg = <0x0 0x00898000 0x0 0x4000>;
1607 pinctrl-0 = <&qup_uart20_default>;
1622 reg = <0x0 0x00900000 0x0 0x60000>;
1637 dma-channel-mask = <0xfff>;
1638 iommus = <&apps_smmu 0x416 0x0>;
1644 reg = <0x0 0x9c0000 0x0 0x6000>;
1651 iommus = <&apps_smmu 0x403 0x0>;
1656 reg = <0x0 0x980000 0x0 0x4000>;
1658 #size-cells = <0>;
1662 pinctrl-0 = <&qup_i2c0_default>;
1674 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1675 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1683 reg = <0x0 0x980000 0x0 0x4000>;
1685 #size-cells = <0>;
1689 pinctrl-0 = <&qup_spi0_default>;
1701 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1702 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1710 reg = <0x0 0x980000 0x0 0x4000>;
1714 pinctrl-0 = <&qup_uart0_default>;
1727 reg = <0x0 0x984000 0x0 0x4000>;
1729 #size-cells = <0>;
1733 pinctrl-0 = <&qup_i2c1_default>;
1745 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1754 reg = <0x0 0x984000 0x0 0x4000>;
1756 #size-cells = <0>;
1760 pinctrl-0 = <&qup_spi1_default>;
1772 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1781 reg = <0x0 0x984000 0x0 0x4000>;
1785 pinctrl-0 = <&qup_uart1_default>;
1798 reg = <0x0 0x988000 0x0 0x4000>;
1800 #size-cells = <0>;
1804 pinctrl-0 = <&qup_i2c2_default>;
1816 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1825 reg = <0x0 0x988000 0x0 0x4000>;
1827 #size-cells = <0>;
1831 pinctrl-0 = <&qup_spi2_default>;
1843 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1852 reg = <0x0 0x988000 0x0 0x4000>;
1856 pinctrl-0 = <&qup_uart2_default>;
1869 reg = <0x0 0x98c000 0x0 0x4000>;
1871 #size-cells = <0>;
1875 pinctrl-0 = <&qup_i2c3_default>;
1887 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1896 reg = <0x0 0x98c000 0x0 0x4000>;
1898 #size-cells = <0>;
1902 pinctrl-0 = <&qup_spi3_default>;
1914 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1923 reg = <0x0 0x98c000 0x0 0x4000>;
1927 pinctrl-0 = <&qup_uart3_default>;
1940 reg = <0x0 0x990000 0x0 0x4000>;
1942 #size-cells = <0>;
1946 pinctrl-0 = <&qup_i2c4_default>;
1958 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1967 reg = <0x0 0x990000 0x0 0x4000>;
1969 #size-cells = <0>;
1973 pinctrl-0 = <&qup_spi4_default>;
1985 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1994 reg = <0x0 0x990000 0x0 0x4000>;
1998 pinctrl-0 = <&qup_uart4_default>;
2011 reg = <0x0 0x994000 0x0 0x4000>;
2013 #size-cells = <0>;
2017 pinctrl-0 = <&qup_i2c5_default>;
2029 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2038 reg = <0x0 0x994000 0x0 0x4000>;
2040 #size-cells = <0>;
2044 pinctrl-0 = <&qup_spi5_default>;
2056 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2065 reg = <0x0 0x994000 0x0 0x4000>;
2069 pinctrl-0 = <&qup_uart5_default>;
2083 reg = <0x0 0x00a00000 0x0 0x60000>;
2097 iommus = <&apps_smmu 0x456 0x0>;
2099 dma-channel-mask = <0xfff>;
2105 reg = <0x0 0x00ac0000 0x0 0x6000>;
2112 iommus = <&apps_smmu 0x443 0x0>;
2117 reg = <0x0 0xa80000 0x0 0x4000>;
2119 #size-cells = <0>;
2123 pinctrl-0 = <&qup_i2c7_default>;
2135 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
2136 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
2144 reg = <0x0 0xa80000 0x0 0x4000>;
2146 #size-cells = <0>;
2150 pinctrl-0 = <&qup_spi7_default>;
2162 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
2163 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
2171 reg = <0x0 0x00a80000 0x0 0x4000>;
2175 pinctrl-0 = <&qup_uart7_default>;
2189 reg = <0x0 0xa84000 0x0 0x4000>;
2191 #size-cells = <0>;
2195 pinctrl-0 = <&qup_i2c8_default>;
2207 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
2216 reg = <0x0 0xa84000 0x0 0x4000>;
2218 #size-cells = <0>;
2222 pinctrl-0 = <&qup_spi8_default>;
2234 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
2243 reg = <0x0 0x00a84000 0x0 0x4000>;
2247 pinctrl-0 = <&qup_uart8_default>;
2261 reg = <0x0 0xa88000 0x0 0x4000>;
2263 #size-cells = <0>;
2267 pinctrl-0 = <&qup_i2c9_default>;
2279 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
2288 reg = <0x0 0xa88000 0x0 0x4000>;
2290 #size-cells = <0>;
2294 pinctrl-0 = <&qup_spi9_default>;
2306 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
2315 reg = <0x0 0xa88000 0x0 0x4000>;
2319 pinctrl-0 = <&qup_uart9_default>;
2332 reg = <0x0 0xa8c000 0x0 0x4000>;
2334 #size-cells = <0>;
2338 pinctrl-0 = <&qup_i2c10_default>;
2350 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
2359 reg = <0x0 0xa8c000 0x0 0x4000>;
2361 #size-cells = <0>;
2365 pinctrl-0 = <&qup_spi10_default>;
2377 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
2386 reg = <0x0 0x00a8c000 0x0 0x4000>;
2390 pinctrl-0 = <&qup_uart10_default>;
2393 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
2394 &clk_virt SLAVE_QUP_CORE_1 0>,
2395 <&gem_noc MASTER_APPSS_PROC 0
2396 &config_noc SLAVE_QUP_1 0>;
2404 reg = <0x0 0xa90000 0x0 0x4000>;
2406 #size-cells = <0>;
2410 pinctrl-0 = <&qup_i2c11_default>;
2422 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2431 reg = <0x0 0xa90000 0x0 0x4000>;
2433 #size-cells = <0>;
2437 pinctrl-0 = <&qup_spi11_default>;
2449 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2458 reg = <0x0 0x00a90000 0x0 0x4000>;
2462 pinctrl-0 = <&qup_uart11_default>;
2476 reg = <0x0 0xa94000 0x0 0x4000>;
2478 #size-cells = <0>;
2482 pinctrl-0 = <&qup_i2c12_default>;
2494 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2503 reg = <0x0 0xa94000 0x0 0x4000>;
2505 #size-cells = <0>;
2509 pinctrl-0 = <&qup_spi12_default>;
2521 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2530 reg = <0x0 0x00a94000 0x0 0x4000>;
2534 pinctrl-0 = <&qup_uart12_default>;
2547 reg = <0x0 0xa98000 0x0 0x4000>;
2549 #size-cells = <0>;
2553 pinctrl-0 = <&qup_i2c13_default>;
2565 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2576 reg = <0x0 0x00b00000 0x0 0x58000>;
2582 iommus = <&apps_smmu 0x056 0x0>;
2584 dma-channel-mask = <0xf>;
2590 reg = <0x0 0xbc0000 0x0 0x6000>;
2597 iommus = <&apps_smmu 0x43 0x0>;
2602 reg = <0x0 0xb80000 0x0 0x4000>;
2604 #size-cells = <0>;
2608 pinctrl-0 = <&qup_i2c21_default>;
2620 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>,
2621 <&gpi_dma3 1 0 QCOM_GPI_I2C>;
2629 reg = <0x0 0xb80000 0x0 0x4000>;
2631 #size-cells = <0>;
2635 pinctrl-0 = <&qup_spi21_default>;
2647 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>,
2648 <&gpi_dma3 1 0 QCOM_GPI_SPI>;
2656 reg = <0x0 0x00b80000 0x0 0x4000>;
2661 pinctrl-0 = <&qup_uart21_default>;
2675 reg = <0 0x010d2000 0 0x1000>;
2680 reg = <0x0 0x01d84000 0x0 0x3000>;
2690 iommus = <&apps_smmu 0x100 0x0>;
2709 <0 0>,
2710 <0 0>,
2712 <0 0>,
2713 <0 0>,
2714 <0 0>,
2715 <0 0>;
2722 reg = <0x0 0x01d87000 0x0 0xe10>;
2732 resets = <&ufs_mem_hc 0>;
2734 #phy-cells = <0>;
2741 reg = <0x0 0x01d88000 0x0 0x18000>;
2747 reg = <0x0 0x01dc4000 0x0 0x28000>;
2750 qcom,ee = <0>;
2754 iommus = <&apps_smmu 0x480 0x00>,
2755 <&apps_smmu 0x481 0x00>;
2760 reg = <0x0 0x04001000 0x0 0x1000>;
2767 #size-cells = <0>;
2769 port@0 {
2770 reg = <0>;
2789 reg = <0x0 0x4002000 0x0 0x1000>,
2790 <0x0 0x16280000 0x0 0x180000>;
2808 reg = <0x0 0x4003000 0x0 0x1000>;
2829 reg = <0x0 0x4004000 0x0 0x1000>;
2845 #size-cells = <0>;
2847 port@0 {
2848 reg = <0>;
2867 reg = <0x0 0x400f000 0x0 0x1000>;
2887 reg = <0x0 0x4041000 0x0 0x1000>;
2903 #size-cells = <0>;
2925 reg = <0x0 0x4042000 0x0 0x1000>;
2941 #size-cells = <0>;
2955 reg = <0x0 0x4045000 0x0 0x1000>;
2971 #size-cells = <0>;
2973 port@0 {
2974 reg = <0>;
2993 reg = <0x0 0x04046000 0x0 0x1000>;
3017 reg = <0x0 0x04048000 0x0 0x1000>;
3021 iommus = <&apps_smmu 0x04c0 0x00>;
3044 reg = <0x0 0x0404e000 0x0 0x1000>;
3059 #size-cells = <0>;
3061 port@0 {
3062 reg = <0>;
3081 reg = <0x0 0x0404f000 0x0 0x1000>;
3085 iommus = <&apps_smmu 0x04a0 0x40>;
3088 arm,buffer-size = <0x400000>;
3109 reg = <0x0 0x4b04000 0x0 0x1000>;
3125 #size-cells = <0>;
3147 reg = <0x0 0x4b05000 0x0 0x1000>;
3173 reg = <0x0 0x4b06000 0x0 0x1000>;
3180 #size-cells = <0>;
3182 port@0 {
3183 reg = <0>;
3211 reg = <0x0 0x4b08000 0x0 0x1000>;
3227 #size-cells = <0>;
3229 port@0 {
3230 reg = <0>;
3273 reg = <0x0 0x4b09000 0x0 0x1000>;
3293 reg = <0x0 0x4b0a000 0x0 0x1000>;
3313 reg = <0x0 0x4b0b000 0x0 0x1000>;
3333 reg = <0x0 0x4b0c000 0x0 0x1000>;
3353 reg = <0x0 0x4b0d000 0x0 0x1000>;
3373 reg = <0x0 0x4b13000 0x0 0x1000>;
3381 reg = <0x0 0x6040000 0x0 0x1000>;
3401 reg = <0x0 0x6140000 0x0 0x1000>;
3421 reg = <0x0 0x6240000 0x0 0x1000>;
3441 reg = <0x0 0x6340000 0x0 0x1000>;
3461 reg = <0x0 0x6440000 0x0 0x1000>;
3481 reg = <0x0 0x6540000 0x0 0x1000>;
3501 reg = <0x0 0x6640000 0x0 0x1000>;
3521 reg = <0x0 0x6740000 0x0 0x1000>;
3541 reg = <0x0 0x6800000 0x0 0x1000>;
3557 #size-cells = <0>;
3559 port@0 {
3560 reg = <0>;
3627 reg = <0x0 0x6810000 0x0 0x1000>;
3643 #size-cells = <0>;
3645 port@0 {
3646 reg = <0>;
3665 reg = <0x0 0x6860000 0x0 0x1000>;
3685 reg = <0x0 0x6861000 0x0 0x1000>;
3705 reg = <0x0 0x6863000 0x0 0x1000>;
3721 #size-cells = <0>;
3723 port@0 {
3724 reg = <0>;
3767 reg = <0x0 0x68a0000 0x0 0x1000>;
3787 reg = <0x0 0x68b0000 0x0 0x1000>;
3807 reg = <0x0 0x68c0000 0x0 0x1000>;
3828 reg = <0 0x088e4000 0 0x120>;
3833 #phy-cells = <0>;
3840 reg = <0 0x088e8000 0 0x2000>;
3854 #clock-cells = <0>;
3857 #phy-cells = <0>;
3864 reg = <0 0x0a6f8800 0 0x400>;
3896 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3906 reg = <0 0x0a600000 0 0xe000>;
3908 iommus = <&apps_smmu 0x080 0x0>;
3919 reg = <0 0x088e6000 0 0x120>;
3924 #phy-cells = <0>;
3931 reg = <0 0x088ea000 0 0x2000>;
3945 #clock-cells = <0>;
3948 #phy-cells = <0>;
3955 reg = <0 0x0a8f8800 0 0x400>;
3987 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3997 reg = <0 0x0a800000 0 0xe000>;
3999 iommus = <&apps_smmu 0x0a0 0x0>;
4010 reg = <0 0x088e7000 0 0x120>;
4015 #phy-cells = <0>;
4022 reg = <0 0x0a4f8800 0 0x400>;
4052 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
4053 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
4062 reg = <0 0x0a400000 0 0xe000>;
4064 iommus = <&apps_smmu 0x020 0x0>;
4074 reg = <0x0 0x01f40000 0x0 0x20000>;
4080 reg = <0x0 0x1fc0000 0x0 0x30000>;
4085 reg = <0x0 0x03d90000 0x0 0xa000>;
4100 reg = <0x0 0x03da0000 0x0 0x20000>;
4135 reg = <0x0 0x08901000 0x0 0xe10>;
4138 #phy-cells = <0>;
4144 reg = <0x0 0x08902000 0x0 0xe10>;
4147 #phy-cells = <0>;
4153 reg = <0x0 0x9091000 0x0 0x1000>;
4163 opp-0 {
4207 reg = <0x0 0x90b5400 0x0 0x600>;
4217 opp-0 {
4238 reg = <0x0 0x90b6400 0x0 0x600>;
4248 reg = <0x0 0x09200000 0x0 0x80000>,
4249 <0x0 0x09300000 0x0 0x80000>,
4250 <0x0 0x09400000 0x0 0x80000>,
4251 <0x0 0x09500000 0x0 0x80000>,
4252 <0x0 0x09600000 0x0 0x80000>,
4253 <0x0 0x09700000 0x0 0x80000>,
4254 <0x0 0x09a00000 0x0 0x80000>;
4268 reg = <0x0 0x0aa00000 0x0 0xf0000>;
4300 iommus = <&apps_smmu 0x0880 0x0400>,
4301 <&apps_smmu 0x0887 0x0400>;
4337 reg = <0x0 0x0abf0000 0x0 0x10000>;
4350 reg = <0x0 0x0ade0000 0x0 0x20000>;
4363 reg = <0x0 0x0ae00000 0x0 0x1000>;
4389 iommus = <&apps_smmu 0x1000 0x402>;
4399 reg = <0x0 0x0ae01000 0x0 0x8f000>,
4400 <0x0 0x0aeb0000 0x0 0x3000>;
4421 interrupts = <0>;
4425 #size-cells = <0>;
4427 port@0 {
4428 reg = <0>;
4487 reg = <0x0 0x0ae94000 0x0 0x400>;
4515 #size-cells = <0>;
4521 #size-cells = <0>;
4523 port@0 {
4524 reg = <0>;
4550 reg = <0x0 0x0ae94400 0x0 0x200>,
4551 <0x0 0x0ae94600 0x0 0x280>,
4552 <0x0 0x0ae94900 0x0 0x27c>;
4558 #phy-cells = <0>;
4569 reg = <0x0 0x0ae96000 0x0 0x400>;
4597 #size-cells = <0>;
4603 #size-cells = <0>;
4605 port@0 {
4606 reg = <0>;
4623 reg = <0x0 0x0ae96400 0x0 0x200>,
4624 <0x0 0x0ae96600 0x0 0x280>,
4625 <0x0 0x0ae96900 0x0 0x27c>;
4631 #phy-cells = <0>;
4643 reg = <0x0 0x0aec2a00 0x0 0x200>,
4644 <0x0 0x0aec2200 0x0 0xd0>,
4645 <0x0 0x0aec2600 0x0 0xd0>,
4646 <0x0 0x0aec2000 0x0 0x1c8>;
4654 #phy-cells = <0>;
4662 reg = <0x0 0x0aec5a00 0x0 0x200>,
4663 <0x0 0x0aec5200 0x0 0xd0>,
4664 <0x0 0x0aec5600 0x0 0xd0>,
4665 <0x0 0x0aec5000 0x0 0x1c8>;
4673 #phy-cells = <0>;
4681 reg = <0x0 0x0af54000 0x0 0x104>,
4682 <0x0 0x0af54200 0x0 0x0c0>,
4683 <0x0 0x0af55000 0x0 0x770>,
4684 <0x0 0x0af56000 0x0 0x09c>,
4685 <0x0 0x0af57000 0x0 0x09c>;
4702 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
4709 #sound-dai-cells = <0>;
4715 #size-cells = <0>;
4717 port@0 {
4718 reg = <0>;
4760 reg = <0x0 0x0af5c000 0x0 0x104>,
4761 <0x0 0x0af5c200 0x0 0x0c0>,
4762 <0x0 0x0af5d000 0x0 0x770>,
4763 <0x0 0x0af5e000 0x0 0x09c>,
4764 <0x0 0x0af5f000 0x0 0x09c>;
4781 assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
4788 #sound-dai-cells = <0>;
4794 #size-cells = <0>;
4796 port@0 {
4797 reg = <0>;
4839 reg = <0x0 0x0af00000 0x0 0x20000>;
4844 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
4845 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
4858 reg = <0x0 0x0b220000 0x0 0x30000>,
4859 <0x0 0x17c000f0 0x0 0x64>;
4860 qcom,pdc-ranges = <0 480 40>,
4905 reg = <0x0 0x0c251000 0x0 0x1ff>,
4906 <0x0 0x0c224000 0x0 0x8>;
4916 reg = <0x0 0x0c252000 0x0 0x1ff>,
4917 <0x0 0x0c225000 0x0 0x8>;
4927 reg = <0x0 0x0c263000 0x0 0x1ff>,
4928 <0x0 0x0c222000 0x0 0x8>;
4938 reg = <0x0 0x0c265000 0x0 0x1ff>,
4939 <0x0 0x0c223000 0x0 0x8>;
4949 reg = <0x0 0x0c300000 0x0 0x400>;
4954 #clock-cells = <0>;
4959 reg = <0x0 0x0c3f0000 0x0 0x400>;
4964 reg = <0x0 0x0c440000 0x0 0x1100>,
4965 <0x0 0x0c600000 0x0 0x2000000>,
4966 <0x0 0x0e600000 0x0 0x100000>,
4967 <0x0 0x0e700000 0x0 0xa0000>,
4968 <0x0 0x0c40a000 0x0 0x26000>;
4974 qcom,channel = <0>;
4975 qcom,ee = <0>;
4981 #size-cells = <0>;
4986 reg = <0x0 0x0f000000 0x0 0x1000000>;
4992 gpio-ranges = <&tlmm 0 0 149>;
5626 reg = <0x0 0x146d8000 0x0 0x1000>;
5627 ranges = <0x0 0x0 0x146d8000 0x1000>;
5634 reg = <0x94c 0xc8>;
5640 reg = <0x0 0x15000000 0x0 0x100000>;
5779 reg = <0x0 0x15200000 0x0 0x80000>;
5854 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5855 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5860 redistributor-stride = <0x0 0x20000>;
5865 reg = <0x0 0x17c10000 0x0 0x1000>;
5867 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5872 reg = <0x0 0x17c20000 0x0 0x1000>;
5873 ranges = <0x0 0x0 0x0 0x20000000>;
5878 reg = <0x17c21000 0x1000>,
5879 <0x17c22000 0x1000>;
5882 frame-number = <0>;
5886 reg = <0x17c23000 0x1000>;
5893 reg = <0x17c25000 0x1000>;
5900 reg = <0x17c27000 0x1000>;
5907 reg = <0x17c29000 0x1000>;
5914 reg = <0x17c2b000 0x1000>;
5921 reg = <0x17c2d000 0x1000>;
5930 reg = <0x0 0x18200000 0x0 0x10000>,
5931 <0x0 0x18210000 0x0 0x10000>,
5932 <0x0 0x18220000 0x0 0x10000>;
5933 reg-names = "drv-0", "drv-1", "drv-2";
5937 qcom,tcs-offset = <0xd00>;
5942 <CONTROL_TCS 0>;
5965 rpmhpd_opp_ret: opp-0 {
6011 reg = <0x0 0x18590000 0x0 0x1000>;
6020 reg = <0x0 0x18591000 0x0 0x1000>,
6021 <0x0 0x18593000 0x0 0x1000>;
6026 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
6037 reg = <0x0 0x18592000 0x0 0x1000>;
6045 reg = <0x0 0x20c00000 0x0 0x10000>;
6048 <&smp2p_gpdsp0_in 0 0>,
6049 <&smp2p_gpdsp0_in 1 0>,
6050 <&smp2p_gpdsp0_in 2 0>,
6051 <&smp2p_gpdsp0_in 3 0>;
6062 interconnects = <&gpdsp_anoc MASTER_DSP0 0
6063 &config_noc SLAVE_CLK_CTL 0>;
6069 qcom,smem-states = <&smp2p_gpdsp0_out 0>;
6088 reg = <0x0 0x21c00000 0x0 0x10000>;
6091 <&smp2p_gpdsp1_in 0 0>,
6092 <&smp2p_gpdsp1_in 1 0>,
6093 <&smp2p_gpdsp1_in 2 0>,
6094 <&smp2p_gpdsp1_in 3 0>;
6105 interconnects = <&gpdsp_anoc MASTER_DSP1 0
6106 &config_noc SLAVE_CLK_CTL 0>;
6112 qcom,smem-states = <&smp2p_gpdsp1_out 0>;
6131 reg = <0x0 0x22100000 0x0 0x20000>;
6136 <0>, <0>, <0>, <0>,
6137 <0>, <0>, <0>, <0>;
6147 reg = <0x0 0x23000000 0x0 0x10000>,
6148 <0x0 0x23016000 0x0 0x100>;
6175 iommus = <&apps_smmu 0x140 0xf>;
6188 reg = <0x0 0x23040000 0x0 0x10000>,
6189 <0x0 0x23056000 0x0 0x100>;
6216 iommus = <&apps_smmu 0x120 0xf>;
6229 reg = <0x0 0x26300000 0x0 0x10000>;
6232 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>,
6247 interconnects = <&nspa_noc MASTER_CDSP_PROC 0
6248 &mc_virt SLAVE_EBI1 0>;
6254 qcom,smem-states = <&smp2p_cdsp0_out 0>;
6274 #size-cells = <0>;
6279 iommus = <&apps_smmu 0x2141 0x04a0>,
6280 <&apps_smmu 0x2181 0x0400>;
6287 iommus = <&apps_smmu 0x2142 0x04a0>,
6288 <&apps_smmu 0x2182 0x0400>;
6295 iommus = <&apps_smmu 0x2143 0x04a0>,
6296 <&apps_smmu 0x2183 0x0400>;
6303 iommus = <&apps_smmu 0x2144 0x04a0>,
6304 <&apps_smmu 0x2184 0x0400>;
6311 iommus = <&apps_smmu 0x2145 0x04a0>,
6312 <&apps_smmu 0x2185 0x0400>;
6319 iommus = <&apps_smmu 0x2146 0x04a0>,
6320 <&apps_smmu 0x2186 0x0400>;
6327 iommus = <&apps_smmu 0x2147 0x04a0>,
6328 <&apps_smmu 0x2187 0x0400>;
6335 iommus = <&apps_smmu 0x2148 0x04a0>,
6336 <&apps_smmu 0x2188 0x0400>;
6343 iommus = <&apps_smmu 0x2149 0x04a0>,
6344 <&apps_smmu 0x2189 0x0400>;
6351 iommus = <&apps_smmu 0x214b 0x04a0>,
6352 <&apps_smmu 0x218b 0x0400>;
6361 reg = <0x0 0x2A300000 0x0 0x10000>;
6364 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
6379 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
6380 &mc_virt SLAVE_EBI1 0>;
6386 qcom,smem-states = <&smp2p_cdsp1_out 0>;
6406 #size-cells = <0>;
6411 iommus = <&apps_smmu 0x2941 0x04a0>,
6412 <&apps_smmu 0x2981 0x0400>;
6419 iommus = <&apps_smmu 0x2942 0x04a0>,
6420 <&apps_smmu 0x2982 0x0400>;
6427 iommus = <&apps_smmu 0x2943 0x04a0>,
6428 <&apps_smmu 0x2983 0x0400>;
6435 iommus = <&apps_smmu 0x2944 0x04a0>,
6436 <&apps_smmu 0x2984 0x0400>;
6443 iommus = <&apps_smmu 0x2945 0x04a0>,
6444 <&apps_smmu 0x2985 0x0400>;
6451 iommus = <&apps_smmu 0x2946 0x04a0>,
6452 <&apps_smmu 0x2986 0x0400>;
6459 iommus = <&apps_smmu 0x2947 0x04a0>,
6460 <&apps_smmu 0x2987 0x0400>;
6467 iommus = <&apps_smmu 0x2948 0x04a0>,
6468 <&apps_smmu 0x2988 0x0400>;
6475 iommus = <&apps_smmu 0x2949 0x04a0>,
6476 <&apps_smmu 0x2989 0x0400>;
6483 iommus = <&apps_smmu 0x294a 0x04a0>,
6484 <&apps_smmu 0x298a 0x0400>;
6491 iommus = <&apps_smmu 0x294b 0x04a0>,
6492 <&apps_smmu 0x298b 0x0400>;
6499 iommus = <&apps_smmu 0x294c 0x04a0>,
6500 <&apps_smmu 0x298c 0x0400>;
6507 iommus = <&apps_smmu 0x294d 0x04a0>,
6508 <&apps_smmu 0x298d 0x0400>;
6517 reg = <0x0 0x30000000 0x0 0x100>;
6520 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
6534 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
6540 qcom,smem-states = <&smp2p_adsp_out 0>;
6563 #size-cells = <0>;
6568 iommus = <&apps_smmu 0x3003 0x0>;
6575 iommus = <&apps_smmu 0x3004 0x0>;
6582 iommus = <&apps_smmu 0x3005 0x0>;
6592 aoss-0-thermal {
6593 thermal-sensors = <&tsens0 0>;
6610 cpu-0-0-0-thermal {
6630 cpu-0-1-0-thermal {
6650 cpu-0-2-0-thermal {
6670 cpu-0-3-0-thermal {
6690 gpuss-0-thermal {
6768 camss-0-thermal {
6786 pcie-0-thermal {
6804 cpuss-0-0-thermal {
6823 thermal-sensors = <&tsens1 0>;
6840 cpu-0-0-1-thermal {
6860 cpu-0-1-1-thermal {
6880 cpu-0-2-1-thermal {
6900 cpu-0-3-1-thermal {
7034 cpuss-0-1-thermal {
7053 thermal-sensors = <&tsens2 0>;
7070 cpu-1-0-0-thermal {
7090 cpu-1-1-0-thermal {
7110 cpu-1-2-0-thermal {
7130 cpu-1-3-0-thermal {
7150 nsp-0-0-0-thermal {
7170 nsp-0-1-0-thermal {
7190 nsp-0-2-0-thermal {
7210 nsp-1-0-0-thermal {
7230 nsp-1-1-0-thermal {
7250 nsp-1-2-0-thermal {
7270 ddrss-0-thermal {
7288 cpuss-1-0-thermal {
7307 thermal-sensors = <&tsens3 0>;
7324 cpu-1-0-1-thermal {
7404 nsp-0-0-1-thermal {
7424 nsp-0-1-1-thermal {
7444 nsp-0-2-1-thermal {
7464 nsp-1-0-1-thermal {
7571 reg = <0x0 0x01c00000 0x0 0x3000>,
7572 <0x0 0x40000000 0x0 0xf20>,
7573 <0x0 0x40000f20 0x0 0xa8>,
7574 <0x0 0x40001000 0x0 0x4000>,
7575 <0x0 0x40100000 0x0 0x100000>,
7576 <0x0 0x01c03000 0x0 0x1000>;
7582 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
7583 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
7584 bus-range = <0x00 0xff>;
7588 linux,pci-domain = <0>;
7610 interrupt-map-mask = <0 0 0 0x7>;
7611 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
7612 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
7613 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
7614 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
7631 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
7632 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
7635 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
7636 <0x100 &pcie_smmu 0x0001 0x1>;
7647 pcieport0: pcie@0 {
7649 reg = <0x0 0x0 0x0 0x0 0x0>;
7650 bus-range = <0x01 0xff>;
7660 reg = <0x0 0x01c00000 0x0 0x3000>,
7661 <0x0 0x40000000 0x0 0xf20>,
7662 <0x0 0x40000f20 0x0 0xa8>,
7663 <0x0 0x40001000 0x0 0x4000>,
7664 <0x0 0x40200000 0x0 0x1fe00000>,
7665 <0x0 0x01c03000 0x0 0x1000>,
7666 <0x0 0x40005000 0x0 0x2000>;
7688 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
7689 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
7693 iommus = <&pcie_smmu 0x0000 0x7f>;
7701 linux,pci-domain = <0>;
7708 reg = <0x0 0x1c04000 0x0 0x2000>;
7727 #clock-cells = <0>;
7730 #phy-cells = <0>;
7737 reg = <0x0 0x01c10000 0x0 0x3000>,
7738 <0x0 0x60000000 0x0 0xf20>,
7739 <0x0 0x60000f20 0x0 0xa8>,
7740 <0x0 0x60001000 0x0 0x4000>,
7741 <0x0 0x60100000 0x0 0x100000>,
7742 <0x0 0x01c13000 0x0 0x1000>;
7748 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
7749 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
7750 bus-range = <0x00 0xff>;
7776 interrupt-map-mask = <0 0 0 0x7>;
7777 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
7778 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
7779 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
7780 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
7797 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
7798 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
7801 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
7802 <0x100 &pcie_smmu 0x0081 0x1>;
7813 pcie@0 {
7815 reg = <0x0 0x0 0x0 0x0 0x0>;
7816 bus-range = <0x01 0xff>;
7826 reg = <0x0 0x01c10000 0x0 0x3000>,
7827 <0x0 0x60000000 0x0 0xf20>,
7828 <0x0 0x60000f20 0x0 0xa8>,
7829 <0x0 0x60001000 0x0 0x4000>,
7830 <0x0 0x60200000 0x0 0x1fe00000>,
7831 <0x0 0x01c13000 0x0 0x1000>,
7832 <0x0 0x60005000 0x0 0x2000>;
7854 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
7855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
7859 iommus = <&pcie_smmu 0x80 0x7f>;
7874 reg = <0x0 0x1c14000 0x0 0x4000>;
7893 #clock-cells = <0>;
7896 #phy-cells = <0>;