Lines Matching +full:0 +full:x1fe00000
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
89 reg = <0x0 0x200>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x300>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x10000>;
152 reg = <0x0 0x10100>;
171 reg = <0x0 0x10200>;
190 reg = <0x0 0x10300>;
247 gold_cpu_sleep_0: cpu-sleep-0 {
250 arm,psci-suspend-param = <0x40000003>;
260 arm,psci-suspend-param = <0x40000004>;
269 cluster_sleep_gold: cluster-sleep-0 {
271 arm,psci-suspend-param = <0x41000044>;
279 arm,psci-suspend-param = <0x42000144>;
303 qcom,dload-mode = <&tcsr 0x13000>;
395 reg = <0x0 0x80000000 0x0 0x0>;
417 #power-domain-cells = <0>;
424 #power-domain-cells = <0>;
431 #power-domain-cells = <0>;
438 #power-domain-cells = <0>;
445 #power-domain-cells = <0>;
452 #power-domain-cells = <0>;
459 #power-domain-cells = <0>;
466 #power-domain-cells = <0>;
473 #power-domain-cells = <0>;
479 #power-domain-cells = <0>;
485 #power-domain-cells = <0>;
496 reg = <0x0 0x80000000 0x0 0x10000000>;
501 reg = <0x0 0x90000000 0x0 0x600000>;
506 reg = <0x0 0x90600000 0x0 0x200000>;
511 reg = <0x0 0x90800000 0x0 0x60000>;
517 reg = <0x0 0x90860000 0x0 0x20000>;
522 reg = <0x0 0x908b0000 0x0 0x10000>;
527 reg = <0x0 0x908c0000 0x0 0x1000>;
532 reg = <0x0 0x908f0000 0x0 0xe000>;
537 reg = <0x0 0x908fe000 0x0 0x2000>;
543 reg = <0x0 0x90900000 0x0 0x200000>;
549 reg = <0x0 0x90c00000 0x0 0x100000>;
554 reg = <0x0 0x90d00000 0x0 0x100000>;
559 reg = <0x0 0x90e00000 0x0 0x300000>;
564 reg = <0x0 0x91b00000 0x0 0x40000>;
569 reg = <0x0 0x91b40000 0x0 0x40000>;
574 reg = <0x0 0x91b80000 0x0 0x10000>;
579 reg = <0x0 0x91b90000 0x0 0x10000>;
584 reg = <0x0 0x91ba0000 0x0 0x1000>;
590 reg = <0x0 0x91c00000 0x0 0x1400000>;
595 reg = <0x0 0x93b00000 0x0 0xf00000>;
600 reg = <0x0 0x94a00000 0x0 0x800000>;
605 reg = <0x0 0x95200000 0x0 0x500000>;
610 reg = <0x0 0x95c00000 0x0 0x1e00000>;
615 reg = <0x0 0x97b00000 0x0 0x1e00000>;
620 reg = <0x0 0x99900000 0x0 0x1e00000>;
625 reg = <0x0 0x9b800000 0x0 0x1e00000>;
630 reg = <0x0 0x9d600000 0x0 0x2000>;
635 reg = <0x0 0x9d700000 0x0 0x1e00000>;
640 reg = <0x0 0x9f500000 0x0 0x700000>;
645 reg = <0x0 0x9fc00000 0x0 0x700000>;
650 reg = <0x0 0xae000000 0x0 0x1000000>;
655 reg = <0x0 0xb0000000 0x0 0x800000>;
660 reg = <0x0 0xbeb00000 0x0 0x11500000>;
665 reg = <0x0 0xd0000000 0x0 0x40000>;
670 reg = <0x0 0xd0040000 0x0 0x10000>;
675 reg = <0x0 0xd0050000 0x0 0x4000>;
680 reg = <0x0 0xd0054000 0x0 0x9c000>;
685 reg = <0x0 0xd00f0000 0x0 0x10000>;
690 reg = <0x0 0xd0100000 0x0 0x1200000>;
695 reg = <0x0 0xd1300000 0x0 0x500000>;
700 reg = <0x0 0xd1800000 0x0 0x100000>;
705 reg = <0x0 0xd1900000 0x0 0x3800000>;
710 reg = <0x0 0xdb100000 0x0 0x100000>;
715 reg = <0x0 0xdb200000 0x0 0x100000>;
728 qcom,local-pid = <0>;
751 qcom,local-pid = <0>;
774 qcom,local-pid = <0>;
797 qcom,local-pid = <0>;
820 qcom,local-pid = <0>;
835 soc: soc@0 {
839 ranges = <0 0 0 0 0x10 0>;
843 reg = <0x0 0x00100000 0x0 0xc7018>;
849 <0>,
850 <0>,
851 <0>,
854 <0>,
855 <0>,
856 <0>,
859 <0>,
860 <0>,
861 <0>;
867 reg = <0x0 0x00408000 0x0 0x1000>;
876 reg = <0x0 0x00800000 0x0 0x60000>;
891 dma-channel-mask = <0xfff>;
892 iommus = <&apps_smmu 0x5b6 0x0>;
898 reg = <0x0 0x008c0000 0x0 0x6000>;
903 iommus = <&apps_smmu 0x5a3 0x0>;
910 reg = <0x0 0x880000 0x0 0x4000>;
912 #size-cells = <0>;
926 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
927 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
935 reg = <0x0 0x880000 0x0 0x4000>;
937 #size-cells = <0>;
951 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
952 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
960 reg = <0x0 0x00880000 0x0 0x4000>;
975 reg = <0x0 0x884000 0x0 0x4000>;
977 #size-cells = <0>;
991 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1000 reg = <0x0 0x884000 0x0 0x4000>;
1002 #size-cells = <0>;
1016 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1025 reg = <0x0 0x00884000 0x0 0x4000>;
1040 reg = <0x0 0x888000 0x0 0x4000>;
1042 #size-cells = <0>;
1056 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1065 reg = <0x0 0x00888000 0x0 0x4000>;
1079 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1084 #size-cells = <0>;
1090 reg = <0x0 0x00888000 0x0 0x4000>;
1105 reg = <0x0 0x88c000 0x0 0x4000>;
1107 #size-cells = <0>;
1121 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1130 reg = <0x0 0x88c000 0x0 0x4000>;
1132 #size-cells = <0>;
1146 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1155 reg = <0x0 0x0088c000 0x0 0x4000>;
1170 reg = <0x0 0x00890000 0x0 0x4000>;
1184 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1189 #size-cells = <0>;
1195 reg = <0x0 0x890000 0x0 0x4000>;
1197 #size-cells = <0>;
1211 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1220 reg = <0x0 0x00890000 0x0 0x4000>;
1235 reg = <0x0 0x894000 0x0 0x4000>;
1237 #size-cells = <0>;
1251 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1260 reg = <0x0 0x894000 0x0 0x4000>;
1262 #size-cells = <0>;
1276 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1285 reg = <0x0 0x00894000 0x0 0x4000>;
1300 reg = <0x0 0x898000 0x0 0x4000>;
1302 #size-cells = <0>;
1316 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1325 reg = <0x0 0x898000 0x0 0x4000>;
1327 #size-cells = <0>;
1341 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1350 reg = <0x0 0x00898000 0x0 0x4000>;
1367 reg = <0x0 0x00900000 0x0 0x60000>;
1382 dma-channel-mask = <0xfff>;
1383 iommus = <&apps_smmu 0x416 0x0>;
1389 reg = <0x0 0x9c0000 0x0 0x6000>;
1396 iommus = <&apps_smmu 0x403 0x0>;
1401 reg = <0x0 0x980000 0x0 0x4000>;
1403 #size-cells = <0>;
1417 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1418 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1426 reg = <0x0 0x980000 0x0 0x4000>;
1428 #size-cells = <0>;
1442 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1443 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1451 reg = <0x0 0x980000 0x0 0x4000>;
1466 reg = <0x0 0x984000 0x0 0x4000>;
1468 #size-cells = <0>;
1482 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1491 reg = <0x0 0x984000 0x0 0x4000>;
1493 #size-cells = <0>;
1507 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1516 reg = <0x0 0x984000 0x0 0x4000>;
1531 reg = <0x0 0x988000 0x0 0x4000>;
1533 #size-cells = <0>;
1547 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1556 reg = <0x0 0x988000 0x0 0x4000>;
1558 #size-cells = <0>;
1572 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1581 reg = <0x0 0x988000 0x0 0x4000>;
1596 reg = <0x0 0x98c000 0x0 0x4000>;
1598 #size-cells = <0>;
1612 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1621 reg = <0x0 0x98c000 0x0 0x4000>;
1623 #size-cells = <0>;
1637 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1646 reg = <0x0 0x98c000 0x0 0x4000>;
1661 reg = <0x0 0x990000 0x0 0x4000>;
1663 #size-cells = <0>;
1677 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1686 reg = <0x0 0x990000 0x0 0x4000>;
1688 #size-cells = <0>;
1702 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1711 reg = <0x0 0x990000 0x0 0x4000>;
1726 reg = <0x0 0x994000 0x0 0x4000>;
1728 #size-cells = <0>;
1742 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1751 reg = <0x0 0x994000 0x0 0x4000>;
1753 #size-cells = <0>;
1767 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1776 reg = <0x0 0x994000 0x0 0x4000>;
1792 reg = <0x0 0x00a00000 0x0 0x60000>;
1806 iommus = <&apps_smmu 0x456 0x0>;
1808 dma-channel-mask = <0xfff>;
1814 reg = <0x0 0x00ac0000 0x0 0x6000>;
1821 iommus = <&apps_smmu 0x443 0x0>;
1826 reg = <0x0 0xa80000 0x0 0x4000>;
1828 #size-cells = <0>;
1842 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1843 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1851 reg = <0x0 0xa80000 0x0 0x4000>;
1853 #size-cells = <0>;
1867 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1868 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1876 reg = <0x0 0x00a80000 0x0 0x4000>;
1892 reg = <0x0 0xa84000 0x0 0x4000>;
1894 #size-cells = <0>;
1908 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1917 reg = <0x0 0xa84000 0x0 0x4000>;
1919 #size-cells = <0>;
1933 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1942 reg = <0x0 0x00a84000 0x0 0x4000>;
1958 reg = <0x0 0xa88000 0x0 0x4000>;
1960 #size-cells = <0>;
1974 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1983 reg = <0x0 0xa88000 0x0 0x4000>;
1985 #size-cells = <0>;
1999 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
2008 reg = <0x0 0xa88000 0x0 0x4000>;
2023 reg = <0x0 0xa8c000 0x0 0x4000>;
2025 #size-cells = <0>;
2039 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
2048 reg = <0x0 0xa8c000 0x0 0x4000>;
2050 #size-cells = <0>;
2064 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
2073 reg = <0x0 0x00a8c000 0x0 0x4000>;
2078 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
2079 &clk_virt SLAVE_QUP_CORE_1 0>,
2080 <&gem_noc MASTER_APPSS_PROC 0
2081 &config_noc SLAVE_QUP_1 0>;
2089 reg = <0x0 0xa90000 0x0 0x4000>;
2091 #size-cells = <0>;
2105 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2114 reg = <0x0 0xa90000 0x0 0x4000>;
2116 #size-cells = <0>;
2130 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2139 reg = <0x0 0x00a90000 0x0 0x4000>;
2155 reg = <0x0 0xa94000 0x0 0x4000>;
2157 #size-cells = <0>;
2171 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2180 reg = <0x0 0xa94000 0x0 0x4000>;
2182 #size-cells = <0>;
2196 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2205 reg = <0x0 0x00a94000 0x0 0x4000>;
2220 reg = <0x0 0xa98000 0x0 0x4000>;
2222 #size-cells = <0>;
2236 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2247 reg = <0x0 0x00b00000 0x0 0x58000>;
2253 iommus = <&apps_smmu 0x056 0x0>;
2255 dma-channel-mask = <0xf>;
2261 reg = <0x0 0xbc0000 0x0 0x6000>;
2268 iommus = <&apps_smmu 0x43 0x0>;
2273 reg = <0x0 0xb80000 0x0 0x4000>;
2275 #size-cells = <0>;
2289 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>,
2290 <&gpi_dma3 1 0 QCOM_GPI_I2C>;
2298 reg = <0x0 0xb80000 0x0 0x4000>;
2300 #size-cells = <0>;
2314 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>,
2315 <&gpi_dma3 1 0 QCOM_GPI_SPI>;
2323 reg = <0x0 0x00b80000 0x0 0x4000>;
2340 reg = <0 0x010d2000 0 0x1000>;
2345 reg = <0x0 0x01d84000 0x0 0x3000>;
2355 iommus = <&apps_smmu 0x100 0x0>;
2374 <0 0>,
2375 <0 0>,
2377 <0 0>,
2378 <0 0>,
2379 <0 0>,
2380 <0 0>;
2387 reg = <0x0 0x01d87000 0x0 0xe10>;
2397 resets = <&ufs_mem_hc 0>;
2399 #phy-cells = <0>;
2406 reg = <0x0 0x01d88000 0x0 0x18000>;
2412 reg = <0x0 0x01dc4000 0x0 0x28000>;
2415 qcom,ee = <0>;
2417 iommus = <&apps_smmu 0x480 0x00>,
2418 <&apps_smmu 0x481 0x00>;
2423 reg = <0x0 0x01dfa000 0x0 0x6000>;
2426 iommus = <&apps_smmu 0x480 0x00>,
2427 <&apps_smmu 0x481 0x00>;
2428 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>;
2434 reg = <0x0 0x4002000 0x0 0x1000>,
2435 <0x0 0x16280000 0x0 0x180000>;
2453 reg = <0x0 0x4003000 0x0 0x1000>;
2474 reg = <0x0 0x4004000 0x0 0x1000>;
2490 #size-cells = <0>;
2492 port@0 {
2493 reg = <0>;
2512 reg = <0x0 0x400f000 0x0 0x1000>;
2532 reg = <0x0 0x4041000 0x0 0x1000>;
2548 #size-cells = <0>;
2570 reg = <0x0 0x4042000 0x0 0x1000>;
2586 #size-cells = <0>;
2600 reg = <0x0 0x4045000 0x0 0x1000>;
2616 #size-cells = <0>;
2618 port@0 {
2619 reg = <0>;
2638 reg = <0x0 0x4b04000 0x0 0x1000>;
2654 #size-cells = <0>;
2676 reg = <0x0 0x4b05000 0x0 0x1000>;
2702 reg = <0x0 0x4b06000 0x0 0x1000>;
2709 #size-cells = <0>;
2732 reg = <0x0 0x4b08000 0x0 0x1000>;
2748 #size-cells = <0>;
2750 port@0 {
2751 reg = <0>;
2794 reg = <0x0 0x4b09000 0x0 0x1000>;
2814 reg = <0x0 0x4b0a000 0x0 0x1000>;
2834 reg = <0x0 0x4b0b000 0x0 0x1000>;
2854 reg = <0x0 0x4b0c000 0x0 0x1000>;
2874 reg = <0x0 0x4b0d000 0x0 0x1000>;
2894 reg = <0x0 0x4b13000 0x0 0x1000>;
2902 reg = <0x0 0x6040000 0x0 0x1000>;
2922 reg = <0x0 0x6140000 0x0 0x1000>;
2942 reg = <0x0 0x6240000 0x0 0x1000>;
2962 reg = <0x0 0x6340000 0x0 0x1000>;
2982 reg = <0x0 0x6440000 0x0 0x1000>;
3002 reg = <0x0 0x6540000 0x0 0x1000>;
3022 reg = <0x0 0x6640000 0x0 0x1000>;
3042 reg = <0x0 0x6740000 0x0 0x1000>;
3062 reg = <0x0 0x6800000 0x0 0x1000>;
3078 #size-cells = <0>;
3080 port@0 {
3081 reg = <0>;
3148 reg = <0x0 0x6810000 0x0 0x1000>;
3164 #size-cells = <0>;
3166 port@0 {
3167 reg = <0>;
3186 reg = <0x0 0x6860000 0x0 0x1000>;
3206 reg = <0x0 0x6861000 0x0 0x1000>;
3226 reg = <0x0 0x6863000 0x0 0x1000>;
3242 #size-cells = <0>;
3244 port@0 {
3245 reg = <0>;
3288 reg = <0x0 0x68a0000 0x0 0x1000>;
3308 reg = <0x0 0x68b0000 0x0 0x1000>;
3328 reg = <0x0 0x68c0000 0x0 0x1000>;
3349 reg = <0 0x088e4000 0 0x120>;
3354 #phy-cells = <0>;
3361 reg = <0 0x088e8000 0 0x2000>;
3375 #clock-cells = <0>;
3378 #phy-cells = <0>;
3385 reg = <0 0x0a6f8800 0 0x400>;
3417 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3418 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3427 reg = <0 0x0a600000 0 0xe000>;
3429 iommus = <&apps_smmu 0x080 0x0>;
3440 reg = <0 0x088e6000 0 0x120>;
3445 #phy-cells = <0>;
3452 reg = <0 0x088ea000 0 0x2000>;
3466 #clock-cells = <0>;
3469 #phy-cells = <0>;
3476 reg = <0 0x0a8f8800 0 0x400>;
3508 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3509 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3518 reg = <0 0x0a800000 0 0xe000>;
3520 iommus = <&apps_smmu 0x0a0 0x0>;
3531 reg = <0 0x088e7000 0 0x120>;
3536 #phy-cells = <0>;
3543 reg = <0 0x0a4f8800 0 0x400>;
3573 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3574 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
3583 reg = <0 0x0a400000 0 0xe000>;
3585 iommus = <&apps_smmu 0x020 0x0>;
3595 reg = <0x0 0x01f40000 0x0 0x20000>;
3601 reg = <0x0 0x1fc0000 0x0 0x30000>;
3606 reg = <0x0 0x03d90000 0x0 0xa000>;
3621 reg = <0x0 0x03da0000 0x0 0x20000>;
3656 reg = <0x0 0x08901000 0x0 0xe10>;
3659 #phy-cells = <0>;
3665 reg = <0x0 0x08902000 0x0 0xe10>;
3668 #phy-cells = <0>;
3674 reg = <0x0 0x9091000 0x0 0x1000>;
3684 opp-0 {
3728 reg = <0x0 0x90b5400 0x0 0x600>;
3738 opp-0 {
3759 reg = <0x0 0x90b6400 0x0 0x600>;
3769 reg = <0x0 0x09200000 0x0 0x80000>,
3770 <0x0 0x09300000 0x0 0x80000>,
3771 <0x0 0x09400000 0x0 0x80000>,
3772 <0x0 0x09500000 0x0 0x80000>,
3773 <0x0 0x09600000 0x0 0x80000>,
3774 <0x0 0x09700000 0x0 0x80000>,
3775 <0x0 0x09a00000 0x0 0x80000>;
3788 reg = <0x0 0x0abf0000 0x0 0x10000>;
3801 reg = <0x0 0x0ade0000 0x0 0x20000>;
3814 reg = <0x0 0x0ae00000 0x0 0x1000>;
3840 iommus = <&apps_smmu 0x1000 0x402>;
3850 reg = <0x0 0x0ae01000 0x0 0x8f000>,
3851 <0x0 0x0aeb0000 0x0 0x2008>;
3872 interrupts = <0>;
3876 #size-cells = <0>;
3878 port@0 {
3879 reg = <0>;
3923 reg = <0x0 0x0aec2a00 0x0 0x200>,
3924 <0x0 0x0aec2200 0x0 0xd0>,
3925 <0x0 0x0aec2600 0x0 0xd0>,
3926 <0x0 0x0aec2000 0x0 0x1c8>;
3934 #phy-cells = <0>;
3942 reg = <0x0 0x0aec5a00 0x0 0x200>,
3943 <0x0 0x0aec5200 0x0 0xd0>,
3944 <0x0 0x0aec5600 0x0 0xd0>,
3945 <0x0 0x0aec5000 0x0 0x1c8>;
3953 #phy-cells = <0>;
3961 reg = <0x0 0x0af54000 0x0 0x104>,
3962 <0x0 0x0af54200 0x0 0x0c0>,
3963 <0x0 0x0af55000 0x0 0x770>,
3964 <0x0 0x0af56000 0x0 0x09c>,
3965 <0x0 0x0af57000 0x0 0x09c>;
3982 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
3989 #sound-dai-cells = <0>;
3995 #size-cells = <0>;
3997 port@0 {
3998 reg = <0>;
4040 reg = <0x0 0x0af5c000 0x0 0x104>,
4041 <0x0 0x0af5c200 0x0 0x0c0>,
4042 <0x0 0x0af5d000 0x0 0x770>,
4043 <0x0 0x0af5e000 0x0 0x09c>,
4044 <0x0 0x0af5f000 0x0 0x09c>;
4061 assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
4068 #sound-dai-cells = <0>;
4074 #size-cells = <0>;
4076 port@0 {
4077 reg = <0>;
4119 reg = <0x0 0x0af00000 0x0 0x20000>;
4124 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
4125 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
4126 <0>, <0>, <0>, <0>;
4135 reg = <0x0 0x0b220000 0x0 0x30000>,
4136 <0x0 0x17c000f0 0x0 0x64>;
4137 qcom,pdc-ranges = <0 480 40>,
4182 reg = <0x0 0x0c251000 0x0 0x1ff>,
4183 <0x0 0x0c224000 0x0 0x8>;
4193 reg = <0x0 0x0c252000 0x0 0x1ff>,
4194 <0x0 0x0c225000 0x0 0x8>;
4204 reg = <0x0 0x0c263000 0x0 0x1ff>,
4205 <0x0 0x0c222000 0x0 0x8>;
4215 reg = <0x0 0x0c265000 0x0 0x1ff>,
4216 <0x0 0x0c223000 0x0 0x8>;
4226 reg = <0x0 0x0c300000 0x0 0x400>;
4231 #clock-cells = <0>;
4236 reg = <0x0 0x0c3f0000 0x0 0x400>;
4241 reg = <0x0 0x0c440000 0x0 0x1100>,
4242 <0x0 0x0c600000 0x0 0x2000000>,
4243 <0x0 0x0e600000 0x0 0x100000>,
4244 <0x0 0x0e700000 0x0 0xa0000>,
4245 <0x0 0x0c40a000 0x0 0x26000>;
4251 qcom,channel = <0>;
4252 qcom,ee = <0>;
4258 #size-cells = <0>;
4263 reg = <0x0 0x0f000000 0x0 0x1000000>;
4269 gpio-ranges = <&tlmm 0 0 149>;
4275 reg = <0x0 0x146d8000 0x0 0x1000>;
4276 ranges = <0x0 0x0 0x146d8000 0x1000>;
4283 reg = <0x94c 0xc8>;
4289 reg = <0x0 0x15000000 0x0 0x100000>;
4428 reg = <0x0 0x15200000 0x0 0x80000>;
4503 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4504 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4509 redistributor-stride = <0x0 0x20000>;
4514 reg = <0x0 0x17c10000 0x0 0x1000>;
4516 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4521 reg = <0x0 0x17c20000 0x0 0x1000>;
4522 ranges = <0x0 0x0 0x0 0x20000000>;
4527 reg = <0x17c21000 0x1000>,
4528 <0x17c22000 0x1000>;
4531 frame-number = <0>;
4535 reg = <0x17c23000 0x1000>;
4542 reg = <0x17c25000 0x1000>;
4549 reg = <0x17c27000 0x1000>;
4556 reg = <0x17c29000 0x1000>;
4563 reg = <0x17c2b000 0x1000>;
4570 reg = <0x17c2d000 0x1000>;
4579 reg = <0x0 0x18200000 0x0 0x10000>,
4580 <0x0 0x18210000 0x0 0x10000>,
4581 <0x0 0x18220000 0x0 0x10000>;
4582 reg-names = "drv-0", "drv-1", "drv-2";
4586 qcom,tcs-offset = <0xd00>;
4591 <CONTROL_TCS 0>;
4613 rpmhpd_opp_ret: opp-0 {
4659 reg = <0x0 0x18591000 0x0 0x1000>,
4660 <0x0 0x18593000 0x0 0x1000>;
4671 reg = <0x0 0x20c00000 0x0 0x10000>;
4674 <&smp2p_gpdsp0_in 0 0>,
4675 <&smp2p_gpdsp0_in 2 0>,
4676 <&smp2p_gpdsp0_in 1 0>,
4677 <&smp2p_gpdsp0_in 3 0>;
4688 interconnects = <&gpdsp_anoc MASTER_DSP0 0
4689 &config_noc SLAVE_CLK_CTL 0>;
4695 qcom,smem-states = <&smp2p_gpdsp0_out 0>;
4714 reg = <0x0 0x21c00000 0x0 0x10000>;
4717 <&smp2p_gpdsp1_in 0 0>,
4718 <&smp2p_gpdsp1_in 2 0>,
4719 <&smp2p_gpdsp1_in 1 0>,
4720 <&smp2p_gpdsp1_in 3 0>;
4731 interconnects = <&gpdsp_anoc MASTER_DSP1 0
4732 &config_noc SLAVE_CLK_CTL 0>;
4738 qcom,smem-states = <&smp2p_gpdsp1_out 0>;
4757 reg = <0x0 0x22100000 0x0 0x20000>;
4762 <0>, <0>, <0>, <0>,
4763 <0>, <0>, <0>, <0>;
4773 reg = <0x0 0x23000000 0x0 0x10000>,
4774 <0x0 0x23016000 0x0 0x100>;
4801 iommus = <&apps_smmu 0x140 0xf>;
4814 reg = <0x0 0x23040000 0x0 0x10000>,
4815 <0x0 0x23056000 0x0 0x100>;
4842 iommus = <&apps_smmu 0x120 0xf>;
4855 reg = <0x0 0x26300000 0x0 0x10000>;
4858 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>,
4873 interconnects = <&nspa_noc MASTER_CDSP_PROC 0
4874 &mc_virt SLAVE_EBI1 0>;
4880 qcom,smem-states = <&smp2p_cdsp0_out 0>;
4900 #size-cells = <0>;
4905 iommus = <&apps_smmu 0x2141 0x04a0>,
4906 <&apps_smmu 0x2161 0x04a0>,
4907 <&apps_smmu 0x2181 0x0400>,
4908 <&apps_smmu 0x21c1 0x04a0>,
4909 <&apps_smmu 0x21e1 0x04a0>,
4910 <&apps_smmu 0x2541 0x04a0>,
4911 <&apps_smmu 0x2561 0x04a0>,
4912 <&apps_smmu 0x2581 0x0400>,
4913 <&apps_smmu 0x25c1 0x04a0>,
4914 <&apps_smmu 0x25e1 0x04a0>;
4921 iommus = <&apps_smmu 0x2142 0x04a0>,
4922 <&apps_smmu 0x2162 0x04a0>,
4923 <&apps_smmu 0x2182 0x0400>,
4924 <&apps_smmu 0x21c2 0x04a0>,
4925 <&apps_smmu 0x21e2 0x04a0>,
4926 <&apps_smmu 0x2542 0x04a0>,
4927 <&apps_smmu 0x2562 0x04a0>,
4928 <&apps_smmu 0x2582 0x0400>,
4929 <&apps_smmu 0x25c2 0x04a0>,
4930 <&apps_smmu 0x25e2 0x04a0>;
4937 iommus = <&apps_smmu 0x2143 0x04a0>,
4938 <&apps_smmu 0x2163 0x04a0>,
4939 <&apps_smmu 0x2183 0x0400>,
4940 <&apps_smmu 0x21c3 0x04a0>,
4941 <&apps_smmu 0x21e3 0x04a0>,
4942 <&apps_smmu 0x2543 0x04a0>,
4943 <&apps_smmu 0x2563 0x04a0>,
4944 <&apps_smmu 0x2583 0x0400>,
4945 <&apps_smmu 0x25c3 0x04a0>,
4946 <&apps_smmu 0x25e3 0x04a0>;
4953 iommus = <&apps_smmu 0x2144 0x04a0>,
4954 <&apps_smmu 0x2164 0x04a0>,
4955 <&apps_smmu 0x2184 0x0400>,
4956 <&apps_smmu 0x21c4 0x04a0>,
4957 <&apps_smmu 0x21e4 0x04a0>,
4958 <&apps_smmu 0x2544 0x04a0>,
4959 <&apps_smmu 0x2564 0x04a0>,
4960 <&apps_smmu 0x2584 0x0400>,
4961 <&apps_smmu 0x25c4 0x04a0>,
4962 <&apps_smmu 0x25e4 0x04a0>;
4969 iommus = <&apps_smmu 0x2145 0x04a0>,
4970 <&apps_smmu 0x2165 0x04a0>,
4971 <&apps_smmu 0x2185 0x0400>,
4972 <&apps_smmu 0x21c5 0x04a0>,
4973 <&apps_smmu 0x21e5 0x04a0>,
4974 <&apps_smmu 0x2545 0x04a0>,
4975 <&apps_smmu 0x2565 0x04a0>,
4976 <&apps_smmu 0x2585 0x0400>,
4977 <&apps_smmu 0x25c5 0x04a0>,
4978 <&apps_smmu 0x25e5 0x04a0>;
4985 iommus = <&apps_smmu 0x2146 0x04a0>,
4986 <&apps_smmu 0x2166 0x04a0>,
4987 <&apps_smmu 0x2186 0x0400>,
4988 <&apps_smmu 0x21c6 0x04a0>,
4989 <&apps_smmu 0x21e6 0x04a0>,
4990 <&apps_smmu 0x2546 0x04a0>,
4991 <&apps_smmu 0x2566 0x04a0>,
4992 <&apps_smmu 0x2586 0x0400>,
4993 <&apps_smmu 0x25c6 0x04a0>,
4994 <&apps_smmu 0x25e6 0x04a0>;
5001 iommus = <&apps_smmu 0x2147 0x04a0>,
5002 <&apps_smmu 0x2167 0x04a0>,
5003 <&apps_smmu 0x2187 0x0400>,
5004 <&apps_smmu 0x21c7 0x04a0>,
5005 <&apps_smmu 0x21e7 0x04a0>,
5006 <&apps_smmu 0x2547 0x04a0>,
5007 <&apps_smmu 0x2567 0x04a0>,
5008 <&apps_smmu 0x2587 0x0400>,
5009 <&apps_smmu 0x25c7 0x04a0>,
5010 <&apps_smmu 0x25e7 0x04a0>;
5017 iommus = <&apps_smmu 0x2148 0x04a0>,
5018 <&apps_smmu 0x2168 0x04a0>,
5019 <&apps_smmu 0x2188 0x0400>,
5020 <&apps_smmu 0x21c8 0x04a0>,
5021 <&apps_smmu 0x21e8 0x04a0>,
5022 <&apps_smmu 0x2548 0x04a0>,
5023 <&apps_smmu 0x2568 0x04a0>,
5024 <&apps_smmu 0x2588 0x0400>,
5025 <&apps_smmu 0x25c8 0x04a0>,
5026 <&apps_smmu 0x25e8 0x04a0>;
5033 iommus = <&apps_smmu 0x2149 0x04a0>,
5034 <&apps_smmu 0x2169 0x04a0>,
5035 <&apps_smmu 0x2189 0x0400>,
5036 <&apps_smmu 0x21c9 0x04a0>,
5037 <&apps_smmu 0x21e9 0x04a0>,
5038 <&apps_smmu 0x2549 0x04a0>,
5039 <&apps_smmu 0x2569 0x04a0>,
5040 <&apps_smmu 0x2589 0x0400>,
5041 <&apps_smmu 0x25c9 0x04a0>,
5042 <&apps_smmu 0x25e9 0x04a0>;
5049 iommus = <&apps_smmu 0x214a 0x04a0>,
5050 <&apps_smmu 0x216a 0x04a0>,
5051 <&apps_smmu 0x218a 0x0400>,
5052 <&apps_smmu 0x21ca 0x04a0>,
5053 <&apps_smmu 0x21ea 0x04a0>,
5054 <&apps_smmu 0x254a 0x04a0>,
5055 <&apps_smmu 0x256a 0x04a0>,
5056 <&apps_smmu 0x258a 0x0400>,
5057 <&apps_smmu 0x25ca 0x04a0>,
5058 <&apps_smmu 0x25ea 0x04a0>;
5065 iommus = <&apps_smmu 0x214b 0x04a0>,
5066 <&apps_smmu 0x216b 0x04a0>,
5067 <&apps_smmu 0x218b 0x0400>,
5068 <&apps_smmu 0x21cb 0x04a0>,
5069 <&apps_smmu 0x21eb 0x04a0>,
5070 <&apps_smmu 0x254b 0x04a0>,
5071 <&apps_smmu 0x256b 0x04a0>,
5072 <&apps_smmu 0x258b 0x0400>,
5073 <&apps_smmu 0x25cb 0x04a0>,
5074 <&apps_smmu 0x25eb 0x04a0>;
5083 reg = <0x0 0x2A300000 0x0 0x10000>;
5086 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5101 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
5102 &mc_virt SLAVE_EBI1 0>;
5108 qcom,smem-states = <&smp2p_cdsp1_out 0>;
5128 #size-cells = <0>;
5133 iommus = <&apps_smmu 0x2941 0x04a0>,
5134 <&apps_smmu 0x2961 0x04a0>,
5135 <&apps_smmu 0x2981 0x0400>,
5136 <&apps_smmu 0x29c1 0x04a0>,
5137 <&apps_smmu 0x29e1 0x04a0>,
5138 <&apps_smmu 0x2d41 0x04a0>,
5139 <&apps_smmu 0x2d61 0x04a0>,
5140 <&apps_smmu 0x2d81 0x0400>,
5141 <&apps_smmu 0x2dc1 0x04a0>,
5142 <&apps_smmu 0x2de1 0x04a0>;
5149 iommus = <&apps_smmu 0x2942 0x04a0>,
5150 <&apps_smmu 0x2962 0x04a0>,
5151 <&apps_smmu 0x2982 0x0400>,
5152 <&apps_smmu 0x29c2 0x04a0>,
5153 <&apps_smmu 0x29e2 0x04a0>,
5154 <&apps_smmu 0x2d42 0x04a0>,
5155 <&apps_smmu 0x2d62 0x04a0>,
5156 <&apps_smmu 0x2d82 0x0400>,
5157 <&apps_smmu 0x2dc2 0x04a0>,
5158 <&apps_smmu 0x2de2 0x04a0>;
5165 iommus = <&apps_smmu 0x2943 0x04a0>,
5166 <&apps_smmu 0x2963 0x04a0>,
5167 <&apps_smmu 0x2983 0x0400>,
5168 <&apps_smmu 0x29c3 0x04a0>,
5169 <&apps_smmu 0x29e3 0x04a0>,
5170 <&apps_smmu 0x2d43 0x04a0>,
5171 <&apps_smmu 0x2d63 0x04a0>,
5172 <&apps_smmu 0x2d83 0x0400>,
5173 <&apps_smmu 0x2dc3 0x04a0>,
5174 <&apps_smmu 0x2de3 0x04a0>;
5181 iommus = <&apps_smmu 0x2944 0x04a0>,
5182 <&apps_smmu 0x2964 0x04a0>,
5183 <&apps_smmu 0x2984 0x0400>,
5184 <&apps_smmu 0x29c4 0x04a0>,
5185 <&apps_smmu 0x29e4 0x04a0>,
5186 <&apps_smmu 0x2d44 0x04a0>,
5187 <&apps_smmu 0x2d64 0x04a0>,
5188 <&apps_smmu 0x2d84 0x0400>,
5189 <&apps_smmu 0x2dc4 0x04a0>,
5190 <&apps_smmu 0x2de4 0x04a0>;
5197 iommus = <&apps_smmu 0x2945 0x04a0>,
5198 <&apps_smmu 0x2965 0x04a0>,
5199 <&apps_smmu 0x2985 0x0400>,
5200 <&apps_smmu 0x29c5 0x04a0>,
5201 <&apps_smmu 0x29e5 0x04a0>,
5202 <&apps_smmu 0x2d45 0x04a0>,
5203 <&apps_smmu 0x2d65 0x04a0>,
5204 <&apps_smmu 0x2d85 0x0400>,
5205 <&apps_smmu 0x2dc5 0x04a0>,
5206 <&apps_smmu 0x2de5 0x04a0>;
5213 iommus = <&apps_smmu 0x2946 0x04a0>,
5214 <&apps_smmu 0x2966 0x04a0>,
5215 <&apps_smmu 0x2986 0x0400>,
5216 <&apps_smmu 0x29c6 0x04a0>,
5217 <&apps_smmu 0x29e6 0x04a0>,
5218 <&apps_smmu 0x2d46 0x04a0>,
5219 <&apps_smmu 0x2d66 0x04a0>,
5220 <&apps_smmu 0x2d86 0x0400>,
5221 <&apps_smmu 0x2dc6 0x04a0>,
5222 <&apps_smmu 0x2de6 0x04a0>;
5229 iommus = <&apps_smmu 0x2947 0x04a0>,
5230 <&apps_smmu 0x2967 0x04a0>,
5231 <&apps_smmu 0x2987 0x0400>,
5232 <&apps_smmu 0x29c7 0x04a0>,
5233 <&apps_smmu 0x29e7 0x04a0>,
5234 <&apps_smmu 0x2d47 0x04a0>,
5235 <&apps_smmu 0x2d67 0x04a0>,
5236 <&apps_smmu 0x2d87 0x0400>,
5237 <&apps_smmu 0x2dc7 0x04a0>,
5238 <&apps_smmu 0x2de7 0x04a0>;
5245 iommus = <&apps_smmu 0x2948 0x04a0>,
5246 <&apps_smmu 0x2968 0x04a0>,
5247 <&apps_smmu 0x2988 0x0400>,
5248 <&apps_smmu 0x29c8 0x04a0>,
5249 <&apps_smmu 0x29e8 0x04a0>,
5250 <&apps_smmu 0x2d48 0x04a0>,
5251 <&apps_smmu 0x2d68 0x04a0>,
5252 <&apps_smmu 0x2d88 0x0400>,
5253 <&apps_smmu 0x2dc8 0x04a0>,
5254 <&apps_smmu 0x2de8 0x04a0>;
5261 iommus = <&apps_smmu 0x2949 0x04a0>,
5262 <&apps_smmu 0x2969 0x04a0>,
5263 <&apps_smmu 0x2989 0x0400>,
5264 <&apps_smmu 0x29c9 0x04a0>,
5265 <&apps_smmu 0x29e9 0x04a0>,
5266 <&apps_smmu 0x2d49 0x04a0>,
5267 <&apps_smmu 0x2d69 0x04a0>,
5268 <&apps_smmu 0x2d89 0x0400>,
5269 <&apps_smmu 0x2dc9 0x04a0>,
5270 <&apps_smmu 0x2de9 0x04a0>;
5277 iommus = <&apps_smmu 0x294a 0x04a0>,
5278 <&apps_smmu 0x296a 0x04a0>,
5279 <&apps_smmu 0x298a 0x0400>,
5280 <&apps_smmu 0x29ca 0x04a0>,
5281 <&apps_smmu 0x29ea 0x04a0>,
5282 <&apps_smmu 0x2d4a 0x04a0>,
5283 <&apps_smmu 0x2d6a 0x04a0>,
5284 <&apps_smmu 0x2d8a 0x0400>,
5285 <&apps_smmu 0x2dca 0x04a0>,
5286 <&apps_smmu 0x2dea 0x04a0>;
5293 iommus = <&apps_smmu 0x294b 0x04a0>,
5294 <&apps_smmu 0x296b 0x04a0>,
5295 <&apps_smmu 0x298b 0x0400>,
5296 <&apps_smmu 0x29cb 0x04a0>,
5297 <&apps_smmu 0x29eb 0x04a0>,
5298 <&apps_smmu 0x2d4b 0x04a0>,
5299 <&apps_smmu 0x2d6b 0x04a0>,
5300 <&apps_smmu 0x2d8b 0x0400>,
5301 <&apps_smmu 0x2dcb 0x04a0>,
5302 <&apps_smmu 0x2deb 0x04a0>;
5309 iommus = <&apps_smmu 0x294c 0x04a0>,
5310 <&apps_smmu 0x296c 0x04a0>,
5311 <&apps_smmu 0x298c 0x0400>,
5312 <&apps_smmu 0x29cc 0x04a0>,
5313 <&apps_smmu 0x29ec 0x04a0>,
5314 <&apps_smmu 0x2d4c 0x04a0>,
5315 <&apps_smmu 0x2d6c 0x04a0>,
5316 <&apps_smmu 0x2d8c 0x0400>,
5317 <&apps_smmu 0x2dcc 0x04a0>,
5318 <&apps_smmu 0x2dec 0x04a0>;
5325 iommus = <&apps_smmu 0x294d 0x04a0>,
5326 <&apps_smmu 0x296d 0x04a0>,
5327 <&apps_smmu 0x298d 0x0400>,
5328 <&apps_smmu 0x29Cd 0x04a0>,
5329 <&apps_smmu 0x29ed 0x04a0>,
5330 <&apps_smmu 0x2d4d 0x04a0>,
5331 <&apps_smmu 0x2d6d 0x04a0>,
5332 <&apps_smmu 0x2d8d 0x0400>,
5333 <&apps_smmu 0x2dcd 0x04a0>,
5334 <&apps_smmu 0x2ded 0x04a0>;
5343 reg = <0x0 0x30000000 0x0 0x100>;
5346 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5360 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
5366 qcom,smem-states = <&smp2p_adsp_out 0>;
5389 #size-cells = <0>;
5394 iommus = <&apps_smmu 0x3003 0x0>;
5401 iommus = <&apps_smmu 0x3004 0x0>;
5408 iommus = <&apps_smmu 0x3005 0x0>;
5418 aoss-0-thermal {
5419 thermal-sensors = <&tsens0 0>;
5436 cpu-0-0-0-thermal {
5456 cpu-0-1-0-thermal {
5476 cpu-0-2-0-thermal {
5496 cpu-0-3-0-thermal {
5516 gpuss-0-thermal {
5594 camss-0-thermal {
5612 pcie-0-thermal {
5630 cpuss-0-0-thermal {
5649 thermal-sensors = <&tsens1 0>;
5666 cpu-0-0-1-thermal {
5686 cpu-0-1-1-thermal {
5706 cpu-0-2-1-thermal {
5726 cpu-0-3-1-thermal {
5860 cpuss-0-1-thermal {
5879 thermal-sensors = <&tsens2 0>;
5896 cpu-1-0-0-thermal {
5916 cpu-1-1-0-thermal {
5936 cpu-1-2-0-thermal {
5956 cpu-1-3-0-thermal {
5976 nsp-0-0-0-thermal {
5996 nsp-0-1-0-thermal {
6016 nsp-0-2-0-thermal {
6036 nsp-1-0-0-thermal {
6056 nsp-1-1-0-thermal {
6076 nsp-1-2-0-thermal {
6096 ddrss-0-thermal {
6114 cpuss-1-0-thermal {
6133 thermal-sensors = <&tsens3 0>;
6150 cpu-1-0-1-thermal {
6230 nsp-0-0-1-thermal {
6250 nsp-0-1-1-thermal {
6270 nsp-0-2-1-thermal {
6290 nsp-1-0-1-thermal {
6397 reg = <0x0 0x01c00000 0x0 0x3000>,
6398 <0x0 0x40000000 0x0 0xf20>,
6399 <0x0 0x40000f20 0x0 0xa8>,
6400 <0x0 0x40001000 0x0 0x4000>,
6401 <0x0 0x40100000 0x0 0x100000>,
6402 <0x0 0x01c03000 0x0 0x1000>;
6408 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
6409 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
6410 bus-range = <0x00 0xff>;
6414 linux,pci-domain = <0>;
6428 interrupt-map-mask = <0 0 0 0x7>;
6429 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
6430 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
6431 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
6432 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
6449 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
6450 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
6453 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
6454 <0x100 &pcie_smmu 0x0001 0x1>;
6465 pcieport0: pcie@0 {
6467 reg = <0x0 0x0 0x0 0x0 0x0>;
6468 bus-range = <0x01 0xff>;
6478 reg = <0x0 0x01c00000 0x0 0x3000>,
6479 <0x0 0x40000000 0x0 0xf20>,
6480 <0x0 0x40000f20 0x0 0xa8>,
6481 <0x0 0x40001000 0x0 0x4000>,
6482 <0x0 0x40200000 0x0 0x1fe00000>,
6483 <0x0 0x01c03000 0x0 0x1000>,
6484 <0x0 0x40005000 0x0 0x2000>;
6506 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
6507 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
6511 iommus = <&pcie_smmu 0x0000 0x7f>;
6519 linux,pci-domain = <0>;
6526 reg = <0x0 0x1c04000 0x0 0x2000>;
6545 #clock-cells = <0>;
6548 #phy-cells = <0>;
6555 reg = <0x0 0x01c10000 0x0 0x3000>,
6556 <0x0 0x60000000 0x0 0xf20>,
6557 <0x0 0x60000f20 0x0 0xa8>,
6558 <0x0 0x60001000 0x0 0x4000>,
6559 <0x0 0x60100000 0x0 0x100000>,
6560 <0x0 0x01c13000 0x0 0x1000>;
6566 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
6567 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
6568 bus-range = <0x00 0xff>;
6586 interrupt-map-mask = <0 0 0 0x7>;
6587 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
6588 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
6589 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
6590 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
6607 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
6608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
6611 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
6612 <0x100 &pcie_smmu 0x0081 0x1>;
6623 pcie@0 {
6625 reg = <0x0 0x0 0x0 0x0 0x0>;
6626 bus-range = <0x01 0xff>;
6636 reg = <0x0 0x01c10000 0x0 0x3000>,
6637 <0x0 0x60000000 0x0 0xf20>,
6638 <0x0 0x60000f20 0x0 0xa8>,
6639 <0x0 0x60001000 0x0 0x4000>,
6640 <0x0 0x60200000 0x0 0x1fe00000>,
6641 <0x0 0x01c13000 0x0 0x1000>,
6642 <0x0 0x60005000 0x0 0x2000>;
6664 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
6665 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
6669 iommus = <&pcie_smmu 0x80 0x7f>;
6684 reg = <0x0 0x1c14000 0x0 0x4000>;
6703 #clock-cells = <0>;
6706 #phy-cells = <0>;