Lines Matching +full:0 +full:x1d00000
34 regulators-0 {
163 pinctrl-0 = <ðernet0_default>;
170 #size-cells = <0>;
174 compatible = "ethernet-phy-id0141.0dd4";
175 reg = <0x8>;
189 /* Set MODE[2:0] to RGMII_SGMII */
190 <0x12 0x14 0xfff8 0x4>,
191 /* Soft reset required after changing MODE[2:0] */
192 <0x12 0x14 0x7fff 0x8000>;
202 snps,map-to-dma-channel = <0x0>;
204 snps,priority = <0x1>;
209 snps,map-to-dma-channel = <0x1>;
215 snps,map-to-dma-channel = <0x2>;
221 snps,map-to-dma-channel = <0x3>;
222 snps,priority = <0xc>;
240 snps,send_slope = <0x1000>;
241 snps,idle_slope = <0x1000>;
242 snps,high_credit = <0x3e800>;
243 snps,low_credit = <0xffc18000>;
248 snps,send_slope = <0x1000>;
249 snps,idle_slope = <0x1000>;
250 snps,high_credit = <0x3e800>;
251 snps,low_credit = <0xffc18000>;
264 pinctrl-0 = <ðernet1_default>;
279 snps,map-to-dma-channel = <0x0>;
281 snps,priority = <0x1>;
286 snps,map-to-dma-channel = <0x1>;
292 snps,map-to-dma-channel = <0x2>;
298 snps,map-to-dma-channel = <0x3>;
299 snps,priority = <0xc>;
317 snps,send_slope = <0x1000>;
318 snps,idle_slope = <0x1000>;
319 snps,high_credit = <0x3e800>;
320 snps,low_credit = <0xffc18000>;
325 snps,send_slope = <0x1000>;
326 snps,idle_slope = <0x1000>;
327 snps,high_credit = <0x3e800>;
328 snps,low_credit = <0xffc18000>;
335 pinctrl-0 = <&i2c0_default>;
342 pinctrl-0 = <&i2c1_default>;
349 pinctrl-0 = <&i2c12_default>;
356 pinctrl-0 = <&i2c15_default>;
363 pinctrl-0 = <&i2c18_default>;
369 ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
370 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
371 <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
377 pinctrl-0 = <&pcie2a_default>;
390 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
391 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
392 <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
398 pinctrl-0 = <&pcie3a_default>;
421 reg = <0xa0 0x4>;