Lines Matching +full:qdu1000 +full:- +full:gcc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 #address-cells = <2>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a55";
33 enable-method = "psci";
34 power-domains = <&CPU_PD0>;
35 power-domain-names = "psci";
36 qcom,freq-domains = <&cpufreq_hw 0>;
37 next-level-cache = <&L2_0>;
38 L2_0: l2-cache {
40 cache-level = <2>;
41 cache-unified;
42 next-level-cache = <&L3_0>;
43 L3_0: l3-cache {
45 cache-level = <3>;
46 cache-unified;
53 compatible = "arm,cortex-a55";
56 enable-method = "psci";
57 power-domains = <&CPU_PD1>;
58 power-domain-names = "psci";
59 qcom,freq-domains = <&cpufreq_hw 0>;
60 next-level-cache = <&L2_100>;
61 L2_100: l2-cache {
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&L3_0>;
71 compatible = "arm,cortex-a55";
74 enable-method = "psci";
75 power-domains = <&CPU_PD2>;
76 power-domain-names = "psci";
77 qcom,freq-domains = <&cpufreq_hw 0>;
78 next-level-cache = <&L2_200>;
79 L2_200: l2-cache {
81 cache-level = <2>;
82 cache-unified;
83 next-level-cache = <&L3_0>;
89 compatible = "arm,cortex-a55";
92 enable-method = "psci";
93 power-domains = <&CPU_PD3>;
94 power-domain-names = "psci";
95 qcom,freq-domains = <&cpufreq_hw 0>;
96 next-level-cache = <&L2_300>;
97 L2_300: l2-cache {
99 cache-level = <2>;
100 cache-unified;
101 next-level-cache = <&L3_0>;
105 cpu-map {
126 idle-states {
127 entry-method = "psci";
129 CPU_OFF: cpu-sleep-0 {
130 compatible = "arm,idle-state";
131 entry-latency-us = <274>;
132 exit-latency-us = <480>;
133 min-residency-us = <3934>;
134 arm,psci-suspend-param = <0x40000004>;
135 local-timer-stop;
139 domain-idle-states {
140 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 compatible = "domain-idle-state";
142 entry-latency-us = <584>;
143 exit-latency-us = <2332>;
144 min-residency-us = <6118>;
145 arm,psci-suspend-param = <0x41000044>;
148 CLUSTER_SLEEP_1: cluster-sleep-1 {
149 compatible = "domain-idle-state";
150 entry-latency-us = <2893>;
151 exit-latency-us = <4023>;
152 min-residency-us = <9987>;
153 arm,psci-suspend-param = <0x41003344>;
159 compatible = "qcom,scm-qdu1000", "qcom,scm";
163 mc_virt: interconnect-0 {
164 compatible = "qcom,qdu1000-mc-virt";
165 qcom,bcm-voters = <&apps_bcm_voter>;
166 #interconnect-cells = <2>;
169 clk_virt: interconnect-1 {
170 compatible = "qcom,qdu1000-clk-virt";
171 qcom,bcm-voters = <&apps_bcm_voter>;
172 #interconnect-cells = <2>;
182 compatible = "arm,cortex-a55-pmu";
187 compatible = "arm,psci-1.0";
190 CPU_PD0: power-domain-cpu0 {
191 #power-domain-cells = <0>;
192 power-domains = <&CLUSTER_PD>;
193 domain-idle-states = <&CPU_OFF>;
196 CPU_PD1: power-domain-cpu1 {
197 #power-domain-cells = <0>;
198 power-domains = <&CLUSTER_PD>;
199 domain-idle-states = <&CPU_OFF>;
202 CPU_PD2: power-domain-cpu2 {
203 #power-domain-cells = <0>;
204 power-domains = <&CLUSTER_PD>;
205 domain-idle-states = <&CPU_OFF>;
208 CPU_PD3: power-domain-cpu3 {
209 #power-domain-cells = <0>;
210 power-domains = <&CLUSTER_PD>;
211 domain-idle-states = <&CPU_OFF>;
214 CLUSTER_PD: power-domain-cluster {
215 #power-domain-cells = <0>;
216 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
220 reserved_memory: reserved-memory {
221 #address-cells = <2>;
222 #size-cells = <2>;
227 no-map;
230 xbl_dt_log_mem: xbl-dt-log@80600000 {
232 no-map;
235 xbl_ramdump_mem: xbl-ramdump@80640000 {
237 no-map;
240 aop_image_mem: aop-image@80800000 {
242 no-map;
245 aop_cmd_db_mem: aop-cmd-db@80860000 {
246 compatible = "qcom,cmd-db";
248 no-map;
251 aop_config_mem: aop-config@80880000 {
253 no-map;
256 tme_crash_dump_mem: tme-crash-dump@808a0000 {
258 no-map;
261 tme_log_mem: tme-log@808e0000 {
263 no-map;
266 uefi_log_mem: uefi-log@808e4000 {
268 no-map;
274 no-map;
278 cpucp_fw_mem: cpucp-fw@80b00000 {
280 no-map;
285 no-map;
288 tz_stat_mem: tz-stat@81d00000 {
290 no-map;
295 no-map;
300 no-map;
305 no-map;
310 no-map;
315 no-map;
320 no-map;
325 ipa_fw_mem: ipa-fw@8be00000 {
327 no-map;
330 ipa_gsi_mem: ipa-gsi@8be10000 {
332 no-map;
337 no-map;
340 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
342 no-map;
347 no-map;
350 oem_tenx_mem: oem-tenx@b9600000 {
352 no-map;
355 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
357 no-map;
360 ipa_buffer_mem: ipa-buffer@c3200000 {
362 no-map;
367 compatible = "simple-bus";
368 #address-cells = <2>;
369 #size-cells = <2>;
371 dma-ranges = <0 0 0 0 0x10 0>;
373 gcc: clock-controller@80000 { label
374 compatible = "qcom,qdu1000-gcc";
381 #clock-cells = <1>;
382 #reset-cells = <1>;
383 #power-domain-cells = <1>;
386 ecpricc: clock-controller@280000 {
387 compatible = "qcom,qdu1000-ecpricc";
390 <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
391 <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
392 <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
393 <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
394 <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
395 <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
396 #clock-cells = <1>;
397 #reset-cells = <1>;
400 gpi_dma0: dma-controller@900000 {
401 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
415 dma-channels = <12>;
416 dma-channel-mask = <0x3f>;
418 #dma-cells = <3>;
422 compatible = "qcom,geni-se-qup";
424 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
425 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
426 clock-names = "m-ahb", "s-ahb";
430 interconnect-names = "qup-core";
432 #address-cells = <2>;
433 #size-cells = <2>;
438 compatible = "qcom,geni-uart";
440 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
441 clock-names = "se";
442 pinctrl-0 = <&qup_uart0_default>;
443 pinctrl-names = "default";
449 compatible = "qcom,geni-i2c";
451 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
452 clock-names = "se";
454 pinctrl-0 = <&qup_i2c1_data_clk>;
455 pinctrl-names = "default";
456 #address-cells = <1>;
457 #size-cells = <0>;
462 compatible = "qcom,geni-spi";
464 #address-cells = <1>;
465 #size-cells = <0>;
467 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
468 clock-names = "se";
469 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
470 pinctrl-names = "default";
475 compatible = "qcom,geni-i2c";
477 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
478 clock-names = "se";
480 pinctrl-0 = <&qup_i2c2_data_clk>;
481 pinctrl-names = "default";
482 #address-cells = <1>;
483 #size-cells = <0>;
488 compatible = "qcom,geni-spi";
490 #address-cells = <1>;
491 #size-cells = <0>;
493 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
494 clock-names = "se";
495 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
496 pinctrl-names = "default";
501 compatible = "qcom,geni-i2c";
503 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
504 clock-names = "se";
506 pinctrl-0 = <&qup_i2c3_data_clk>;
507 pinctrl-names = "default";
508 #address-cells = <1>;
509 #size-cells = <0>;
514 compatible = "qcom,geni-spi";
516 #address-cells = <1>;
517 #size-cells = <0>;
519 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
520 clock-names = "se";
521 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
522 pinctrl-names = "default";
527 compatible = "qcom,geni-i2c";
529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
530 clock-names = "se";
532 pinctrl-0 = <&qup_i2c4_data_clk>;
533 pinctrl-names = "default";
534 #address-cells = <1>;
535 #size-cells = <0>;
540 compatible = "qcom,geni-spi";
542 #address-cells = <1>;
543 #size-cells = <0>;
545 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
546 clock-names = "se";
547 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
548 pinctrl-names = "default";
553 compatible = "qcom,geni-i2c";
555 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
556 clock-names = "se";
558 pinctrl-0 = <&qup_i2c5_data_clk>;
559 pinctrl-names = "default";
560 #address-cells = <1>;
561 #size-cells = <0>;
566 compatible = "qcom,geni-spi";
568 #address-cells = <1>;
569 #size-cells = <0>;
571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
572 clock-names = "se";
573 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
574 pinctrl-names = "default";
579 compatible = "qcom,geni-i2c";
581 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
582 clock-names = "se";
584 pinctrl-0 = <&qup_i2c6_data_clk>;
585 pinctrl-names = "default";
586 #address-cells = <1>;
587 #size-cells = <0>;
592 compatible = "qcom,geni-spi";
594 #address-cells = <1>;
595 #size-cells = <0>;
597 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
598 clock-names = "se";
599 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
600 pinctrl-names = "default";
605 compatible = "qcom,geni-debug-uart";
607 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
608 clock-names = "se";
609 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
610 pinctrl-names = "default";
616 gpi_dma1: dma-controller@a00000 {
617 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
631 dma-channels = <12>;
632 dma-channel-mask = <0x3f>;
634 #dma-cells = <3>;
638 compatible = "qcom,geni-se-qup";
640 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
641 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
642 clock-names = "m-ahb", "s-ahb";
644 #address-cells = <2>;
645 #size-cells = <2>;
650 compatible = "qcom,geni-uart";
652 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
653 clock-names = "se";
654 pinctrl-0 = <&qup_uart8_default>;
655 pinctrl-names = "default";
657 #address-cells = <1>;
658 #size-cells = <0>;
663 compatible = "qcom,geni-i2c";
665 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
666 clock-names = "se";
668 pinctrl-0 = <&qup_i2c9_data_clk>;
669 pinctrl-names = "default";
670 #address-cells = <1>;
671 #size-cells = <0>;
676 compatible = "qcom,geni-spi";
678 #address-cells = <1>;
679 #size-cells = <0>;
681 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
682 clock-names = "se";
683 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
684 pinctrl-names = "default";
689 compatible = "qcom,geni-i2c";
691 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
692 clock-names = "se";
694 pinctrl-0 = <&qup_i2c10_data_clk>;
695 pinctrl-names = "default";
696 #address-cells = <1>;
697 #size-cells = <0>;
702 compatible = "qcom,geni-spi";
704 #address-cells = <1>;
705 #size-cells = <0>;
707 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
708 clock-names = "se";
709 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
710 pinctrl-names = "default";
715 compatible = "qcom,geni-i2c";
717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
718 clock-names = "se";
720 pinctrl-0 = <&qup_i2c11_data_clk>;
721 pinctrl-names = "default";
722 #address-cells = <1>;
723 #size-cells = <0>;
728 compatible = "qcom,geni-spi";
730 #address-cells = <1>;
731 #size-cells = <0>;
733 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
734 clock-names = "se";
735 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
736 pinctrl-names = "default";
741 compatible = "qcom,geni-i2c";
743 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
744 clock-names = "se";
746 pinctrl-0 = <&qup_i2c12_data_clk>;
747 pinctrl-names = "default";
748 #address-cells = <1>;
749 #size-cells = <0>;
754 compatible = "qcom,geni-spi";
756 #address-cells = <1>;
757 #size-cells = <0>;
759 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
760 clock-names = "se";
761 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
762 pinctrl-names = "default";
767 compatible = "qcom,geni-i2c";
769 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
770 clock-names = "se";
772 pinctrl-0 = <&qup_i2c13_data_clk>;
773 pinctrl-names = "default";
774 #address-cells = <1>;
775 #size-cells = <0>;
780 compatible = "qcom,geni-uart";
782 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
783 clock-names = "se";
784 pinctrl-0 = <&qup_uart13_default>;
785 pinctrl-names = "default";
787 #address-cells = <1>;
788 #size-cells = <0>;
793 compatible = "qcom,geni-spi";
795 #address-cells = <1>;
796 #size-cells = <0>;
798 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
799 clock-names = "se";
800 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
801 pinctrl-names = "default";
806 compatible = "qcom,geni-i2c";
808 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
809 clock-names = "se";
811 pinctrl-0 = <&qup_i2c14_data_clk>;
812 pinctrl-names = "default";
813 #address-cells = <1>;
814 #size-cells = <0>;
819 compatible = "qcom,geni-spi";
821 #address-cells = <1>;
822 #size-cells = <0>;
824 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
825 clock-names = "se";
826 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
827 pinctrl-names = "default";
832 compatible = "qcom,geni-i2c";
834 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
835 clock-names = "se";
837 pinctrl-0 = <&qup_i2c15_data_clk>;
838 pinctrl-names = "default";
839 #address-cells = <1>;
840 #size-cells = <0>;
845 compatible = "qcom,geni-spi";
847 #address-cells = <1>;
848 #size-cells = <0>;
850 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
851 clock-names = "se";
852 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
853 pinctrl-names = "default";
859 compatible = "qcom,qdu1000-system-noc";
861 qcom,bcm-voters = <&apps_bcm_voter>;
862 #interconnect-cells = <2>;
866 compatible = "qcom,tcsr-mutex";
868 #hwlock-cells = <1>;
872 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
875 reg-names = "hc", "cqhci";
879 interrupt-names = "hc_irq", "pwr_irq";
881 clocks = <&gcc GCC_SDCC5_AHB_CLK>,
882 <&gcc GCC_SDCC5_APPS_CLK>,
884 clock-names = "iface",
888 resets = <&gcc GCC_SDCC5_BCR>;
892 interconnect-names = "sdhc-ddr", "cpu-sdhc";
893 power-domains = <&rpmhpd QDU1000_CX>;
894 operating-points-v2 = <&sdhc1_opp_table>;
897 dma-coherent;
899 bus-width = <8>;
901 qcom,dll-config = <0x0007642c>;
902 qcom,ddr-config = <0x80040868>;
906 sdhc1_opp_table: opp-table {
907 compatible = "operating-points-v2";
909 opp-384000000 {
910 opp-hz = /bits/ 64 <384000000>;
911 required-opps = <&rpmhpd_opp_nom>;
912 opp-peak-kBps = <6528000 1652800>;
913 opp-avg-kBps = <400000 0>;
919 compatible = "qcom,qdu1000-usb-hs-phy",
920 "qcom,usb-snps-hs-7nm-phy";
922 #phy-cells = <0>;
924 clocks =<&gcc GCC_USB2_CLKREF_EN>;
925 clock-names = "ref";
927 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
933 compatible = "qcom,qdu1000-qmp-usb3-uni-phy";
936 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
937 <&gcc GCC_USB2_CLKREF_EN>,
938 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
939 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
940 clock-names = "aux",
945 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
946 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
947 reset-names = "phy",
950 #clock-cells = <0>;
951 clock-output-names = "usb3_uni_phy_pipe_clk_src";
953 #phy-cells = <0>;
959 compatible = "qcom,qdu1000-dwc3", "qcom,dwc3";
961 #address-cells = <2>;
962 #size-cells = <2>;
965 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
966 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
967 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
968 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
969 clock-names = "cfg_noc",
974 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
975 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
976 assigned-clock-rates = <19200000>, <200000000>;
978 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
983 interrupt-names = "pwr_event",
989 power-domains = <&gcc USB30_PRIM_GDSC>;
990 required-opps = <&rpmhpd_opp_nom>;
992 resets = <&gcc GCC_USB30_PRIM_BCR>;
999 interconnect-names = "usb-ddr",
1000 "apps-usb";
1014 phy-names = "usb2-phy",
1015 "usb3-phy";
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1038 pdc: interrupt-controller@b220000 {
1039 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
1041 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
1043 #interrupt-cells = <2>;
1044 interrupt-parent = <&intc>;
1045 interrupt-controller;
1049 compatible = "qcom,spmi-pmic-arb";
1055 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1056 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1057 interrupt-names = "periph_irq";
1060 #address-cells = <2>;
1061 #size-cells = <0>;
1062 interrupt-controller;
1063 #interrupt-cells = <4>;
1067 compatible = "qcom,qdu1000-tlmm";
1070 gpio-controller;
1071 #gpio-cells = <2>;
1072 interrupt-controller;
1073 #interrupt-cells = <2>;
1074 gpio-ranges = <&tlmm 0 0 151>;
1075 wakeup-parent = <&pdc>;
1077 qup_uart0_default: qup-uart0-default-state {
1082 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1087 qup_spi1_data_clk: qup-spi1-data-clk-state {
1092 qup_spi1_cs: qup-spi1-cs-state {
1097 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1102 qup_spi2_data_clk: qup-spi2-data-clk-state {
1107 qup_spi2_cs: qup-spi2-cs-state {
1112 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1117 qup_spi3_data_clk: qup-spi3-data-clk-state {
1122 qup_spi3_cs: qup-spi3-cs-state {
1127 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1132 qup_spi4_data_clk: qup-spi4-data-clk-state {
1137 qup_spi4_cs: qup-spi4-cs-state {
1142 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1147 qup_spi5_data_clk: qup-spi5-data-clk-state {
1152 qup_spi5_cs: qup-spi5-cs-state {
1157 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1162 qup_spi6_data_clk: qup-spi6-data-clk-state {
1167 qup_spi6_cs: qup-spi6-cs-state {
1172 qup_uart7_rx: qup-uart7-rx-state {
1177 qup_uart7_tx: qup-uart7-tx-state {
1182 qup_uart8_default: qup-uart8-default-state {
1187 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1192 qup_spi9_data_clk: qup-spi9-data-clk-state {
1197 qup_spi9_cs: qup-spi9-cs-state {
1202 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1207 qup_spi10_data_clk: qup-spi10-data-clk-state {
1212 qup_spi10_cs: qup-spi10-cs-state {
1217 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1222 qup_spi11_data_clk: qup-spi11-data-clk-state {
1227 qup_spi11_cs: qup-spi11-cs-state {
1232 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1237 qup_spi12_data_clk: qup-spi12-data-clk-state {
1242 qup_spi12_cs: qup-spi12-cs-state {
1247 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1252 qup_spi13_data_clk: qup-spi13-data-clk-state {
1257 qup_spi13_cs: qup-spi13-cs-state {
1262 qup_uart13_default: qup-uart13-default-state {
1267 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1272 qup_spi14_data_clk: qup-spi14-data-clk-state {
1277 qup_spi14_cs: qup-spi14-cs-state {
1282 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1287 qup_spi15_data_clk: qup-spi15-data-clk-state {
1292 qup_spi15_cs: qup-spi15-cs-state {
1297 sdc_on_state: sdc-on-state {
1298 clk-pins {
1300 drive-strength = <16>;
1301 bias-disable;
1304 cmd-pins {
1306 drive-strength = <10>;
1307 bias-pull-up;
1310 data-pins {
1312 drive-strength = <10>;
1313 bias-pull-up;
1316 rclk-pins {
1318 bias-pull-down;
1322 sdc_off_state: sdc-off-state {
1323 clk-pins {
1325 drive-strength = <2>;
1326 bias-disable;
1329 cmd-pins {
1331 drive-strength = <2>;
1332 bias-pull-up;
1335 data-pins {
1337 drive-strength = <2>;
1338 bias-pull-up;
1341 rclk-pins {
1343 bias-pull-down;
1349 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
1352 #address-cells = <1>;
1353 #size-cells = <1>;
1355 pil-reloc@94c {
1356 compatible = "qcom,pil-reloc-info";
1362 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1364 #iommu-cells = <2>;
1365 #global-interrupts = <2>;
1417 intc: interrupt-controller@17200000 {
1418 compatible = "arm,gic-v3";
1422 #interrupt-cells = <3>;
1423 interrupt-controller;
1424 #redistributor-regions = <1>;
1425 redistributor-stride = <0x0 0x20000>;
1429 compatible = "arm,armv7-timer-mem";
1431 #address-cells = <1>;
1432 #size-cells = <1>;
1440 frame-number = <0>;
1446 frame-number = <1>;
1454 frame-number = <2>;
1461 frame-number = <3>;
1468 frame-number = <4>;
1475 frame-number = <5>;
1482 frame-number = <6>;
1488 compatible = "qcom,rpmh-rsc";
1492 reg-names = "drv-0", "drv-1", "drv-2";
1496 qcom,tcs-offset = <0xd00>;
1497 qcom,drv-id = <2>;
1498 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1501 power-domains = <&CLUSTER_PD>;
1503 apps_bcm_voter: bcm-voter {
1504 compatible = "qcom,bcm-voter";
1507 rpmhcc: clock-controller {
1508 compatible = "qcom,qdu1000-rpmh-clk";
1510 clock-names = "xo";
1511 #clock-cells = <1>;
1514 rpmhpd: power-controller {
1515 compatible = "qcom,qdu1000-rpmhpd";
1516 #power-domain-cells = <1>;
1517 operating-points-v2 = <&rpmhpd_opp_table>;
1519 rpmhpd_opp_table: opp-table {
1520 compatible = "operating-points-v2";
1523 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1527 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1531 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1535 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1539 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1543 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1547 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1551 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1555 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1559 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1566 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1568 reg-names = "freq-domain0", "freq-domain1";
1569 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1570 clock-names = "xo", "alternate";
1571 #freq-domain-cells = <1>;
1572 #clock-cells = <1>;
1576 compatible = "qcom,qdu1000-gem-noc";
1578 qcom,bcm-voters = <&apps_bcm_voter>;
1579 #interconnect-cells = <2>;
1582 system-cache-controller@19200000 {
1583 compatible = "qcom,qdu1000-llcc";
1593 reg-names = "llcc0_base",
1604 nvmem-cells = <&multi_chan_ddr>;
1605 nvmem-cell-names = "multi-chan-ddr";
1609 compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom";
1611 #address-cells = <1>;
1612 #size-cells = <1>;
1614 multi_chan_ddr: multi-chan-ddr@12b {
1622 compatible = "arm,armv8-timer";