Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
9 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/clock/qcom,sa8775p-videocc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
28 xo_board_clk: xo-board-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32000>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a78c";
49 enable-method = "psci";
50 next-level-cache = <&l2_0>;
51 power-domains = <&cpu_pd0>;
52 power-domain-names = "psci";
53 capacity-dmips-mhz = <1946>;
54 dynamic-power-coefficient = <472>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
57 l2_0: l2-cache {
59 cache-level = <2>;
60 cache-unified;
61 next-level-cache = <&l3_0>;
67 compatible = "arm,cortex-a78c";
69 enable-method = "psci";
70 next-level-cache = <&l2_1>;
71 power-domains = <&cpu_pd1>;
72 power-domain-names = "psci";
73 capacity-dmips-mhz = <1946>;
74 dynamic-power-coefficient = <472>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
77 l2_1: l2-cache {
79 cache-level = <2>;
80 cache-unified;
81 next-level-cache = <&l3_0>;
87 compatible = "arm,cortex-a78c";
89 enable-method = "psci";
90 next-level-cache = <&l2_2>;
91 power-domains = <&cpu_pd2>;
92 power-domain-names = "psci";
93 capacity-dmips-mhz = <1946>;
94 dynamic-power-coefficient = <507>;
95 qcom,freq-domain = <&cpufreq_hw 2>;
97 l2_2: l2-cache {
99 cache-level = <2>;
100 cache-unified;
101 next-level-cache = <&l3_0>;
107 compatible = "arm,cortex-a78c";
109 enable-method = "psci";
110 next-level-cache = <&l2_3>;
111 power-domains = <&cpu_pd3>;
112 power-domain-names = "psci";
113 capacity-dmips-mhz = <1946>;
114 dynamic-power-coefficient = <507>;
115 qcom,freq-domain = <&cpufreq_hw 2>;
117 l2_3: l2-cache {
119 cache-level = <2>;
120 cache-unified;
121 next-level-cache = <&l3_0>;
127 compatible = "arm,cortex-a55";
129 enable-method = "psci";
130 next-level-cache = <&l2_4>;
131 power-domains = <&cpu_pd4>;
132 power-domain-names = "psci";
133 capacity-dmips-mhz = <1024>;
134 dynamic-power-coefficient = <100>;
135 qcom,freq-domain = <&cpufreq_hw 1>;
137 l2_4: l2-cache {
139 cache-level = <2>;
140 cache-unified;
141 next-level-cache = <&l3_1>;
147 compatible = "arm,cortex-a55";
149 enable-method = "psci";
150 next-level-cache = <&l2_5>;
151 power-domains = <&cpu_pd5>;
152 power-domain-names = "psci";
153 capacity-dmips-mhz = <1024>;
154 dynamic-power-coefficient = <100>;
155 qcom,freq-domain = <&cpufreq_hw 1>;
157 l2_5: l2-cache {
159 cache-level = <2>;
160 cache-unified;
161 next-level-cache = <&l3_1>;
167 compatible = "arm,cortex-a55";
169 enable-method = "psci";
170 next-level-cache = <&l2_6>;
171 power-domains = <&cpu_pd6>;
172 power-domain-names = "psci";
173 capacity-dmips-mhz = <1024>;
174 dynamic-power-coefficient = <100>;
175 qcom,freq-domain = <&cpufreq_hw 1>;
177 l2_6: l2-cache {
179 cache-level = <2>;
180 cache-unified;
181 next-level-cache = <&l3_1>;
187 compatible = "arm,cortex-a55";
189 enable-method = "psci";
190 next-level-cache = <&l2_7>;
191 power-domains = <&cpu_pd7>;
192 power-domain-names = "psci";
193 capacity-dmips-mhz = <1024>;
194 dynamic-power-coefficient = <100>;
195 qcom,freq-domain = <&cpufreq_hw 1>;
197 l2_7: l2-cache {
199 cache-level = <2>;
200 cache-unified;
201 next-level-cache = <&l3_1>;
205 cpu-map {
243 l3_0: l3-cache-0 {
245 cache-level = <3>;
246 cache-unified;
249 l3_1: l3-cache-1 {
251 cache-level = <3>;
252 cache-unified;
255 idle-states {
256 entry-method = "psci";
258 little_cpu_sleep_0: cpu-sleep-0-0 {
259 compatible = "arm,idle-state";
260 idle-state-name = "silver-power-collapse";
261 arm,psci-suspend-param = <0x40000003>;
262 entry-latency-us = <449>;
263 exit-latency-us = <801>;
264 min-residency-us = <1574>;
265 local-timer-stop;
268 little_cpu_sleep_1: cpu-sleep-0-1 {
269 compatible = "arm,idle-state";
270 idle-state-name = "silver-rail-power-collapse";
271 arm,psci-suspend-param = <0x40000004>;
272 entry-latency-us = <602>;
273 exit-latency-us = <961>;
274 min-residency-us = <4288>;
275 local-timer-stop;
278 big_cpu_sleep_0: cpu-sleep-1-0 {
279 compatible = "arm,idle-state";
280 idle-state-name = "gold-power-collapse";
281 arm,psci-suspend-param = <0x40000003>;
282 entry-latency-us = <549>;
283 exit-latency-us = <901>;
284 min-residency-us = <1774>;
285 local-timer-stop;
288 big_cpu_sleep_1: cpu-sleep-1-1 {
289 compatible = "arm,idle-state";
290 idle-state-name = "gold-rail-power-collapse";
291 arm,psci-suspend-param = <0x40000004>;
292 entry-latency-us = <702>;
293 exit-latency-us = <1061>;
294 min-residency-us = <4488>;
295 local-timer-stop;
299 domain-idle-states {
300 silver_cluster_sleep: cluster-sleep-0 {
301 compatible = "domain-idle-state";
302 arm,psci-suspend-param = <0x41000044>;
303 entry-latency-us = <2552>;
304 exit-latency-us = <2848>;
305 min-residency-us = <5908>;
308 gold_cluster_sleep: cluster-sleep-1 {
309 compatible = "domain-idle-state";
310 arm,psci-suspend-param = <0x41000044>;
311 entry-latency-us = <2752>;
312 exit-latency-us = <3048>;
313 min-residency-us = <6118>;
316 system_sleep: domain-sleep {
317 compatible = "domain-idle-state";
318 arm,psci-suspend-param = <0x42000144>;
319 entry-latency-us = <3263>;
320 exit-latency-us = <6562>;
321 min-residency-us = <9987>;
326 dummy_eud: dummy-sink {
327 compatible = "arm,coresight-dummy-sink";
329 in-ports {
332 remote-endpoint = <&swao_rep_out1>;
340 compatible = "qcom,scm-qcs8300", "qcom,scm";
341 qcom,dload-mode = <&tcsr 0x13000>;
351 clk_virt: interconnect-0 {
352 compatible = "qcom,qcs8300-clk-virt";
353 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_voter>;
357 mc_virt: interconnect-1 {
358 compatible = "qcom,qcs8300-mc-virt";
359 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_voter>;
363 qup_opp_table: opp-table-qup {
364 compatible = "operating-points-v2";
366 opp-120000000 {
367 opp-hz = /bits/ 64 <120000000>;
368 required-opps = <&rpmhpd_opp_svs_l1>;
372 pmu-a55 {
373 compatible = "arm,cortex-a55-pmu";
377 pmu-a78 {
378 compatible = "arm,cortex-a78-pmu";
383 compatible = "arm,psci-1.0";
386 cpu_pd0: power-domain-cpu0 {
387 #power-domain-cells = <0>;
388 power-domains = <&cluster_pd0>;
389 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
392 cpu_pd1: power-domain-cpu1 {
393 #power-domain-cells = <0>;
394 power-domains = <&cluster_pd0>;
395 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
398 cpu_pd2: power-domain-cpu2 {
399 #power-domain-cells = <0>;
400 power-domains = <&cluster_pd0>;
401 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
404 cpu_pd3: power-domain-cpu3 {
405 #power-domain-cells = <0>;
406 power-domains = <&cluster_pd0>;
407 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
410 cpu_pd4: power-domain-cpu4 {
411 #power-domain-cells = <0>;
412 power-domains = <&cluster_pd1>;
413 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
416 cpu_pd5: power-domain-cpu5 {
417 #power-domain-cells = <0>;
418 power-domains = <&cluster_pd1>;
419 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
422 cpu_pd6: power-domain-cpu6 {
423 #power-domain-cells = <0>;
424 power-domains = <&cluster_pd1>;
425 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
428 cpu_pd7: power-domain-cpu7 {
429 #power-domain-cells = <0>;
430 power-domains = <&cluster_pd1>;
431 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
434 cluster_pd0: power-domain-cluster0 {
435 #power-domain-cells = <0>;
436 power-domains = <&system_pd>;
437 domain-idle-states = <&gold_cluster_sleep>;
440 cluster_pd1: power-domain-cluster1 {
441 #power-domain-cells = <0>;
442 power-domains = <&system_pd>;
443 domain-idle-states = <&silver_cluster_sleep>;
446 system_pd: power-domain-system {
447 #power-domain-cells = <0>;
448 domain-idle-states = <&system_sleep>;
452 reserved-memory {
453 #address-cells = <2>;
454 #size-cells = <2>;
457 aop_image_mem: aop-image-region@90800000 {
459 no-map;
462 aop_cmd_db_mem: aop-cmd-db-region@90860000 {
463 compatible = "qcom,cmd-db";
465 no-map;
471 no-map;
475 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
477 no-map;
480 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 {
482 no-map;
485 camera_mem: camera-region@95200000 {
487 no-map;
490 adsp_mem: adsp-region@95c00000 {
491 no-map;
495 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 {
497 no-map;
500 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 {
502 no-map;
505 gpdsp_mem: gpdsp-region@97b00000 {
507 no-map;
510 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 {
512 no-map;
515 cdsp_mem: cdsp-region@99980000 {
517 no-map;
520 gpu_microcode_mem: gpu-microcode-region@9b780000 {
522 no-map;
525 cvp_mem: cvp-region@9b782000 {
527 no-map;
530 video_mem: video-region@9be82000 {
532 no-map;
536 smp2p-adsp {
538 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
545 qcom,local-pid = <0>;
546 qcom,remote-pid = <2>;
548 smp2p_adsp_in: slave-kernel {
549 qcom,entry-name = "slave-kernel";
550 interrupt-controller;
551 #interrupt-cells = <2>;
554 smp2p_adsp_out: master-kernel {
555 qcom,entry-name = "master-kernel";
556 #qcom,smem-state-cells = <1>;
560 smp2p-cdsp {
562 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
569 qcom,local-pid = <0>;
570 qcom,remote-pid = <5>;
572 smp2p_cdsp_in: slave-kernel {
573 qcom,entry-name = "slave-kernel";
574 interrupt-controller;
575 #interrupt-cells = <2>;
578 smp2p_cdsp_out: master-kernel {
579 qcom,entry-name = "master-kernel";
580 #qcom,smem-state-cells = <1>;
584 smp2p-gpdsp {
586 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
593 qcom,local-pid = <0>;
594 qcom,remote-pid = <17>;
596 smp2p_gpdsp_in: slave-kernel {
597 qcom,entry-name = "slave-kernel";
598 interrupt-controller;
599 #interrupt-cells = <2>;
602 smp2p_gpdsp_out: master-kernel {
603 qcom,entry-name = "master-kernel";
604 #qcom,smem-state-cells = <1>;
609 compatible = "simple-bus";
611 #address-cells = <2>;
612 #size-cells = <2>;
614 gcc: clock-controller@100000 {
615 compatible = "qcom,qcs8300-gcc";
617 #clock-cells = <1>;
618 #reset-cells = <1>;
619 #power-domain-cells = <1>;
633 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
636 interrupt-controller;
637 #interrupt-cells = <3>;
638 #mbox-cells = <2>;
642 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
644 #address-cells = <1>;
645 #size-cells = <1>;
648 gpi_dma0: dma-controller@900000 {
649 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";
651 #dma-cells = <3>;
665 dma-channels = <12>;
666 dma-channel-mask = <0xfff>;
667 dma-coherent;
672 compatible = "qcom,geni-se-qup";
677 clock-names = "m-ahb",
678 "s-ahb";
679 #address-cells = <2>;
680 #size-cells = <2>;
682 dma-coherent;
686 compatible = "qcom,geni-i2c";
689 clock-names = "se";
690 pinctrl-0 = <&qup_i2c0_data_clk>;
691 pinctrl-names = "default";
693 #address-cells = <1>;
694 #size-cells = <0>;
701 interconnect-names = "qup-core",
702 "qup-config",
703 "qup-memory";
704 power-domains = <&rpmhpd RPMHPD_CX>;
705 required-opps = <&rpmhpd_opp_low_svs>;
708 dma-names = "tx",
714 compatible = "qcom,geni-spi";
717 clock-names = "se";
718 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
719 pinctrl-names = "default";
721 #address-cells = <1>;
722 #size-cells = <0>;
727 interconnect-names = "qup-core",
728 "qup-config";
729 power-domains = <&rpmhpd RPMHPD_CX>;
730 operating-points-v2 = <&qup_opp_table>;
733 dma-names = "tx",
739 compatible = "qcom,geni-uart";
742 clock-names = "se";
743 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>,
745 pinctrl-names = "default";
751 interconnect-names = "qup-core",
752 "qup-config";
753 power-domains = <&rpmhpd RPMHPD_CX>;
754 operating-points-v2 = <&qup_opp_table>;
759 compatible = "qcom,geni-i2c";
762 clock-names = "se";
763 pinctrl-0 = <&qup_i2c1_data_clk>;
764 pinctrl-names = "default";
766 #address-cells = <1>;
767 #size-cells = <0>;
774 interconnect-names = "qup-core",
775 "qup-config",
776 "qup-memory";
777 power-domains = <&rpmhpd RPMHPD_CX>;
778 required-opps = <&rpmhpd_opp_low_svs>;
781 dma-names = "tx",
787 compatible = "qcom,geni-spi";
790 clock-names = "se";
791 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
792 pinctrl-names = "default";
794 #address-cells = <1>;
795 #size-cells = <0>;
800 interconnect-names = "qup-core",
801 "qup-config";
802 power-domains = <&rpmhpd RPMHPD_CX>;
803 operating-points-v2 = <&qup_opp_table>;
806 dma-names = "tx",
812 compatible = "qcom,geni-uart";
815 clock-names = "se";
816 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>,
818 pinctrl-names = "default";
824 interconnect-names = "qup-core",
825 "qup-config";
826 power-domains = <&rpmhpd RPMHPD_CX>;
827 operating-points-v2 = <&qup_opp_table>;
832 compatible = "qcom,geni-i2c";
835 clock-names = "se";
836 pinctrl-0 = <&qup_i2c2_data_clk>;
837 pinctrl-names = "default";
839 #address-cells = <1>;
840 #size-cells = <0>;
847 interconnect-names = "qup-core",
848 "qup-config",
849 "qup-memory";
850 power-domains = <&rpmhpd RPMHPD_CX>;
851 required-opps = <&rpmhpd_opp_low_svs>;
854 dma-names = "tx",
860 compatible = "qcom,geni-spi";
863 clock-names = "se";
864 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
865 pinctrl-names = "default";
867 #address-cells = <1>;
868 #size-cells = <0>;
873 interconnect-names = "qup-core",
874 "qup-config";
875 power-domains = <&rpmhpd RPMHPD_CX>;
876 operating-points-v2 = <&qup_opp_table>;
879 dma-names = "tx",
885 compatible = "qcom,geni-uart";
888 clock-names = "se";
889 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
891 pinctrl-names = "default";
897 interconnect-names = "qup-core",
898 "qup-config";
899 power-domains = <&rpmhpd RPMHPD_CX>;
900 operating-points-v2 = <&qup_opp_table>;
905 compatible = "qcom,geni-i2c";
908 clock-names = "se";
909 pinctrl-0 = <&qup_i2c3_data_clk>;
910 pinctrl-names = "default";
912 #address-cells = <1>;
913 #size-cells = <0>;
920 interconnect-names = "qup-core",
921 "qup-config",
922 "qup-memory";
923 power-domains = <&rpmhpd RPMHPD_CX>;
924 required-opps = <&rpmhpd_opp_low_svs>;
927 dma-names = "tx",
933 compatible = "qcom,geni-spi";
936 clock-names = "se";
937 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
938 pinctrl-names = "default";
940 #address-cells = <1>;
941 #size-cells = <0>;
946 interconnect-names = "qup-core",
947 "qup-config";
948 power-domains = <&rpmhpd RPMHPD_CX>;
949 operating-points-v2 = <&qup_opp_table>;
952 dma-names = "tx",
958 compatible = "qcom,geni-uart";
961 clock-names = "se";
962 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>,
964 pinctrl-names = "default";
970 interconnect-names = "qup-core",
971 "qup-config";
972 power-domains = <&rpmhpd RPMHPD_CX>;
973 operating-points-v2 = <&qup_opp_table>;
978 compatible = "qcom,geni-i2c";
981 clock-names = "se";
982 pinctrl-0 = <&qup_i2c4_data_clk>;
983 pinctrl-names = "default";
985 #address-cells = <1>;
986 #size-cells = <0>;
993 interconnect-names = "qup-core",
994 "qup-config",
995 "qup-memory";
996 power-domains = <&rpmhpd RPMHPD_CX>;
997 required-opps = <&rpmhpd_opp_low_svs>;
1000 dma-names = "tx",
1006 compatible = "qcom,geni-spi";
1009 clock-names = "se";
1010 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1011 pinctrl-names = "default";
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1019 interconnect-names = "qup-core",
1020 "qup-config";
1021 power-domains = <&rpmhpd RPMHPD_CX>;
1022 operating-points-v2 = <&qup_opp_table>;
1025 dma-names = "tx",
1031 compatible = "qcom,geni-uart";
1034 clock-names = "se";
1035 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
1037 pinctrl-names = "default";
1043 interconnect-names = "qup-core",
1044 "qup-config";
1045 power-domains = <&rpmhpd RPMHPD_CX>;
1046 operating-points-v2 = <&qup_opp_table>;
1051 compatible = "qcom,geni-i2c";
1054 clock-names = "se";
1055 pinctrl-0 = <&qup_i2c5_data_clk>;
1056 pinctrl-names = "default";
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1066 interconnect-names = "qup-core",
1067 "qup-config",
1068 "qup-memory";
1069 power-domains = <&rpmhpd RPMHPD_CX>;
1070 required-opps = <&rpmhpd_opp_low_svs>;
1073 dma-names = "tx",
1079 compatible = "qcom,geni-spi";
1082 clock-names = "se";
1083 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1084 pinctrl-names = "default";
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1092 interconnect-names = "qup-core",
1093 "qup-config";
1094 power-domains = <&rpmhpd RPMHPD_CX>;
1095 operating-points-v2 = <&qup_opp_table>;
1098 dma-names = "tx",
1104 compatible = "qcom,geni-uart";
1107 clock-names = "se";
1108 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>,
1110 pinctrl-names = "default";
1116 interconnect-names = "qup-core",
1117 "qup-config";
1118 power-domains = <&rpmhpd RPMHPD_CX>;
1119 operating-points-v2 = <&qup_opp_table>;
1124 compatible = "qcom,geni-i2c";
1127 clock-names = "se";
1128 pinctrl-0 = <&qup_i2c6_data_clk>;
1129 pinctrl-names = "default";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1139 interconnect-names = "qup-core",
1140 "qup-config",
1141 "qup-memory";
1142 power-domains = <&rpmhpd RPMHPD_CX>;
1143 required-opps = <&rpmhpd_opp_low_svs>;
1146 dma-names = "tx",
1152 compatible = "qcom,geni-spi";
1155 clock-names = "se";
1156 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1157 pinctrl-names = "default";
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1165 interconnect-names = "qup-core",
1166 "qup-config";
1167 power-domains = <&rpmhpd RPMHPD_CX>;
1168 operating-points-v2 = <&qup_opp_table>;
1171 dma-names = "tx",
1177 compatible = "qcom,geni-uart";
1180 clock-names = "se";
1181 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
1183 pinctrl-names = "default";
1189 interconnect-names = "qup-core",
1190 "qup-config";
1191 power-domains = <&rpmhpd RPMHPD_CX>;
1192 operating-points-v2 = <&qup_opp_table>;
1197 compatible = "qcom,geni-debug-uart";
1200 clock-names = "se";
1201 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1202 pinctrl-names = "default";
1208 interconnect-names = "qup-core",
1209 "qup-config";
1210 power-domains = <&rpmhpd RPMHPD_CX>;
1211 operating-points-v2 = <&qup_opp_table>;
1216 gpi_dma1: dma-controller@a00000 {
1217 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";
1219 #dma-cells = <3>;
1233 dma-channels = <12>;
1234 dma-channel-mask = <0xfff>;
1235 dma-coherent;
1240 compatible = "qcom,geni-se-qup";
1245 clock-names = "m-ahb",
1246 "s-ahb";
1247 #address-cells = <2>;
1248 #size-cells = <2>;
1250 dma-coherent;
1254 compatible = "qcom,geni-i2c";
1257 clock-names = "se";
1258 pinctrl-0 = <&qup_i2c8_data_clk>;
1259 pinctrl-names = "default";
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1269 interconnect-names = "qup-core",
1270 "qup-config",
1271 "qup-memory";
1272 power-domains = <&rpmhpd RPMHPD_CX>;
1273 required-opps = <&rpmhpd_opp_low_svs>;
1276 dma-names = "tx",
1282 compatible = "qcom,geni-spi";
1285 clock-names = "se";
1286 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1287 pinctrl-names = "default";
1289 #address-cells = <1>;
1290 #size-cells = <0>;
1295 interconnect-names = "qup-core",
1296 "qup-config";
1297 power-domains = <&rpmhpd RPMHPD_CX>;
1298 operating-points-v2 = <&qup_opp_table>;
1301 dma-names = "tx",
1307 compatible = "qcom,geni-uart";
1310 clock-names = "se";
1311 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>,
1313 pinctrl-names = "default";
1319 interconnect-names = "qup-core",
1320 "qup-config";
1321 power-domains = <&rpmhpd RPMHPD_CX>;
1322 operating-points-v2 = <&qup_opp_table>;
1327 compatible = "qcom,geni-i2c";
1330 clock-names = "se";
1331 pinctrl-0 = <&qup_i2c9_data_clk>;
1332 pinctrl-names = "default";
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1342 interconnect-names = "qup-core",
1343 "qup-config",
1344 "qup-memory";
1345 power-domains = <&rpmhpd RPMHPD_CX>;
1346 required-opps = <&rpmhpd_opp_low_svs>;
1349 dma-names = "tx",
1355 compatible = "qcom,geni-spi";
1358 clock-names = "se";
1359 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1360 pinctrl-names = "default";
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1368 interconnect-names = "qup-core",
1369 "qup-config";
1370 power-domains = <&rpmhpd RPMHPD_CX>;
1371 operating-points-v2 = <&qup_opp_table>;
1374 dma-names = "tx",
1380 compatible = "qcom,geni-uart";
1383 clock-names = "se";
1384 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>,
1386 pinctrl-names = "default";
1392 interconnect-names = "qup-core",
1393 "qup-config";
1394 power-domains = <&rpmhpd RPMHPD_CX>;
1395 operating-points-v2 = <&qup_opp_table>;
1400 compatible = "qcom,geni-i2c";
1403 clock-names = "se";
1404 pinctrl-0 = <&qup_i2c10_data_clk>;
1405 pinctrl-names = "default";
1407 #address-cells = <1>;
1408 #size-cells = <0>;
1415 interconnect-names = "qup-core",
1416 "qup-config",
1417 "qup-memory";
1418 power-domains = <&rpmhpd RPMHPD_CX>;
1419 required-opps = <&rpmhpd_opp_low_svs>;
1422 dma-names = "tx",
1428 compatible = "qcom,geni-spi";
1431 clock-names = "se";
1432 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1433 pinctrl-names = "default";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1441 interconnect-names = "qup-core",
1442 "qup-config";
1443 power-domains = <&rpmhpd RPMHPD_CX>;
1444 operating-points-v2 = <&qup_opp_table>;
1447 dma-names = "tx",
1453 compatible = "qcom,geni-uart";
1456 clock-names = "se";
1457 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>,
1459 pinctrl-names = "default";
1465 interconnect-names = "qup-core",
1466 "qup-config";
1467 power-domains = <&rpmhpd RPMHPD_CX>;
1468 operating-points-v2 = <&qup_opp_table>;
1473 compatible = "qcom,geni-i2c";
1476 clock-names = "se";
1477 pinctrl-0 = <&qup_i2c11_data_clk>;
1478 pinctrl-names = "default";
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1488 interconnect-names = "qup-core",
1489 "qup-config",
1490 "qup-memory";
1491 power-domains = <&rpmhpd RPMHPD_CX>;
1492 required-opps = <&rpmhpd_opp_low_svs>;
1495 dma-names = "tx",
1501 compatible = "qcom,geni-uart";
1504 clock-names = "se";
1505 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>;
1506 pinctrl-names = "default";
1512 interconnect-names = "qup-core",
1513 "qup-config";
1514 power-domains = <&rpmhpd RPMHPD_CX>;
1515 operating-points-v2 = <&qup_opp_table>;
1520 compatible = "qcom,geni-i2c";
1523 clock-names = "se";
1524 pinctrl-0 = <&qup_i2c12_data_clk>;
1525 pinctrl-names = "default";
1527 #address-cells = <1>;
1528 #size-cells = <0>;
1535 interconnect-names = "qup-core",
1536 "qup-config",
1537 "qup-memory";
1538 power-domains = <&rpmhpd RPMHPD_CX>;
1539 required-opps = <&rpmhpd_opp_low_svs>;
1542 dma-names = "tx",
1548 compatible = "qcom,geni-spi";
1551 clock-names = "se";
1552 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1553 pinctrl-names = "default";
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1561 interconnect-names = "qup-core",
1562 "qup-config";
1563 power-domains = <&rpmhpd RPMHPD_CX>;
1564 operating-points-v2 = <&qup_opp_table>;
1567 dma-names = "tx",
1573 compatible = "qcom,geni-uart";
1576 clock-names = "se";
1577 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>,
1579 pinctrl-names = "default";
1585 interconnect-names = "qup-core",
1586 "qup-config";
1587 power-domains = <&rpmhpd RPMHPD_CX>;
1588 operating-points-v2 = <&qup_opp_table>;
1593 compatible = "qcom,geni-i2c";
1596 clock-names = "se";
1597 pinctrl-0 = <&qup_i2c13_data_clk>;
1598 pinctrl-names = "default";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1608 interconnect-names = "qup-core",
1609 "qup-config",
1610 "qup-memory";
1611 power-domains = <&rpmhpd RPMHPD_CX>;
1612 required-opps = <&rpmhpd_opp_low_svs>;
1615 dma-names = "tx",
1621 compatible = "qcom,geni-spi";
1624 clock-names = "se";
1625 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1626 pinctrl-names = "default";
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1634 interconnect-names = "qup-core",
1635 "qup-config";
1636 power-domains = <&rpmhpd RPMHPD_CX>;
1637 operating-points-v2 = <&qup_opp_table>;
1640 dma-names = "tx",
1646 compatible = "qcom,geni-uart";
1649 clock-names = "se";
1650 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>,
1652 pinctrl-names = "default";
1658 interconnect-names = "qup-core",
1659 "qup-config";
1660 power-domains = <&rpmhpd RPMHPD_CX>;
1661 operating-points-v2 = <&qup_opp_table>;
1666 compatible = "qcom,geni-i2c";
1669 clock-names = "se";
1670 pinctrl-0 = <&qup_i2c14_data_clk>;
1671 pinctrl-names = "default";
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1681 interconnect-names = "qup-core",
1682 "qup-config",
1683 "qup-memory";
1684 power-domains = <&rpmhpd RPMHPD_CX>;
1685 required-opps = <&rpmhpd_opp_low_svs>;
1688 dma-names = "tx",
1694 compatible = "qcom,geni-spi";
1697 clock-names = "se";
1698 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1699 pinctrl-names = "default";
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1707 interconnect-names = "qup-core",
1708 "qup-config";
1709 power-domains = <&rpmhpd RPMHPD_CX>;
1710 operating-points-v2 = <&qup_opp_table>;
1713 dma-names = "tx",
1719 compatible = "qcom,geni-uart";
1722 clock-names = "se";
1723 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>,
1725 pinctrl-names = "default";
1731 interconnect-names = "qup-core",
1732 "qup-config";
1733 power-domains = <&rpmhpd RPMHPD_CX>;
1734 operating-points-v2 = <&qup_opp_table>;
1739 compatible = "qcom,geni-i2c";
1742 clock-names = "se";
1743 pinctrl-0 = <&qup_i2c15_data_clk>;
1744 pinctrl-names = "default";
1746 #address-cells = <1>;
1747 #size-cells = <0>;
1754 interconnect-names = "qup-core",
1755 "qup-config",
1756 "qup-memory";
1757 power-domains = <&rpmhpd RPMHPD_CX>;
1758 required-opps = <&rpmhpd_opp_low_svs>;
1761 dma-names = "tx",
1767 compatible = "qcom,geni-spi";
1770 clock-names = "se";
1771 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1772 pinctrl-names = "default";
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1780 interconnect-names = "qup-core",
1781 "qup-config";
1782 power-domains = <&rpmhpd RPMHPD_CX>;
1783 operating-points-v2 = <&qup_opp_table>;
1786 dma-names = "tx",
1792 compatible = "qcom,geni-uart";
1795 clock-names = "se";
1796 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>,
1798 pinctrl-names = "default";
1804 interconnect-names = "qup-core",
1805 "qup-config";
1806 power-domains = <&rpmhpd RPMHPD_CX>;
1807 operating-points-v2 = <&qup_opp_table>;
1812 gpi_dma3: dma-controller@b00000 {
1813 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";
1815 #dma-cells = <3>;
1821 dma-channels = <4>;
1822 dma-channel-mask = <0xf>;
1823 dma-coherent;
1828 compatible = "qcom,geni-se-qup";
1833 clock-names = "m-ahb",
1834 "s-ahb";
1835 #address-cells = <2>;
1836 #size-cells = <2>;
1838 dma-coherent;
1842 compatible = "qcom,geni-i2c";
1845 clock-names = "se";
1846 pinctrl-0 = <&qup_i2c16_data_clk>;
1847 pinctrl-names = "default";
1849 #address-cells = <1>;
1850 #size-cells = <0>;
1857 interconnect-names = "qup-core",
1858 "qup-config",
1859 "qup-memory";
1860 power-domains = <&rpmhpd RPMHPD_CX>;
1861 required-opps = <&rpmhpd_opp_low_svs>;
1864 dma-names = "tx",
1870 compatible = "qcom,geni-spi";
1873 clock-names = "se";
1874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
1875 pinctrl-names = "default";
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1883 interconnect-names = "qup-core",
1884 "qup-config";
1885 power-domains = <&rpmhpd RPMHPD_CX>;
1886 operating-points-v2 = <&qup_opp_table>;
1889 dma-names = "tx",
1895 compatible = "qcom,geni-uart";
1898 clock-names = "se";
1899 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>,
1901 pinctrl-names = "default";
1907 interconnect-names = "qup-core",
1908 "qup-config";
1909 power-domains = <&rpmhpd RPMHPD_CX>;
1910 operating-points-v2 = <&qup_opp_table>;
1916 compatible = "qcom,qcs8300-trng", "qcom,trng";
1921 compatible = "qcom,qcs8300-config-noc";
1923 #interconnect-cells = <2>;
1924 qcom,bcm-voters = <&apps_bcm_voter>;
1928 compatible = "qcom,qcs8300-system-noc";
1930 #interconnect-cells = <2>;
1931 qcom,bcm-voters = <&apps_bcm_voter>;
1935 compatible = "qcom,qcs8300-aggre1-noc";
1937 #interconnect-cells = <2>;
1938 qcom,bcm-voters = <&apps_bcm_voter>;
1942 compatible = "qcom,qcs8300-aggre2-noc";
1944 #interconnect-cells = <2>;
1945 qcom,bcm-voters = <&apps_bcm_voter>;
1949 compatible = "qcom,qcs8300-pcie-anoc";
1951 #interconnect-cells = <2>;
1952 qcom,bcm-voters = <&apps_bcm_voter>;
1956 compatible = "qcom,qcs8300-gpdsp-anoc";
1958 #interconnect-cells = <2>;
1959 qcom,bcm-voters = <&apps_bcm_voter>;
1963 compatible = "qcom,qcs8300-mmss-noc";
1965 #interconnect-cells = <2>;
1966 qcom,bcm-voters = <&apps_bcm_voter>;
1969 ufs_mem_hc: ufs@1d84000 {
1970 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1974 phy-names = "ufsphy";
1975 lanes-per-direction = <2>;
1976 #reset-cells = <1>;
1978 reset-names = "rst";
1980 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1981 required-opps = <&rpmhpd_opp_nom>;
1984 dma-coherent;
1990 interconnect-names = "ufs-ddr",
1991 "cpu-ufs";
2001 clock-names = "core_clk",
2009 freq-table-hz = <75000000 300000000>,
2022 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy";
2026 * enables the CXO clock to eDP *and* UFS PHY.
2031 clock-names = "ref",
2034 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2037 reset-names = "ufsphy";
2039 #phy-cells = <0>;
2043 cryptobam: dma-controller@1dc4000 {
2044 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2047 #dma-cells = <1>;
2049 qcom,controlled-remotely;
2050 num-channels = <20>;
2051 qcom,num-ees = <4>;
2057 compatible = "qcom,qcs8300-inline-crypto-engine",
2058 "qcom,inline-crypto-engine";
2064 compatible = "qcom,tcsr-mutex";
2066 #hwlock-cells = <1>;
2070 compatible = "qcom,qcs8300-tcsr", "syscon";
2075 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas";
2078 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2083 interrupt-names = "wdog",
2087 "stop-ack";
2090 clock-names = "xo";
2092 power-domains = <&rpmhpd RPMHPD_LCX>,
2094 power-domain-names = "lcx",
2097 memory-region = <&adsp_mem>;
2101 qcom,smem-states = <&smp2p_adsp_out 0>;
2102 qcom,smem-state-names = "stop";
2106 remoteproc_adsp_glink: glink-edge {
2107 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2114 qcom,remote-pid = <2>;
2118 qcom,glink-channels = "fastrpcglink-apps-dsp";
2120 memory-region = <&adsp_rpc_remote_heap_mem>;
2123 #address-cells = <1>;
2124 #size-cells = <0>;
2126 compute-cb@3 {
2127 compatible = "qcom,fastrpc-compute-cb";
2130 dma-coherent;
2133 compute-cb@4 {
2134 compatible = "qcom,fastrpc-compute-cb";
2137 dma-coherent;
2140 compute-cb@5 {
2141 compatible = "qcom,fastrpc-compute-cb";
2144 dma-coherent;
2151 compatible = "qcom,qcs8300-lpass-ag-noc";
2153 #interconnect-cells = <2>;
2154 qcom,bcm-voters = <&apps_bcm_voter>;
2158 compatible = "arm,coresight-stm", "arm,primecell";
2161 reg-names = "stm-base",
2162 "stm-stimulus-base";
2165 clock-names = "apb_pclk";
2167 out-ports {
2170 remote-endpoint = <&funnel0_in7>;
2177 compatible = "qcom,coresight-tpda", "arm,primecell";
2181 clock-names = "apb_pclk";
2183 in-ports {
2184 #address-cells = <1>;
2185 #size-cells = <0>;
2191 remote-endpoint = <&qdss_tpdm1_out>;
2196 out-ports {
2199 remote-endpoint = <&funnel0_in6>;
2206 compatible = "qcom,coresight-tpdm", "arm,primecell";
2210 clock-names = "apb_pclk";
2212 qcom,cmb-element-bits = <32>;
2213 qcom,cmb-msrs-num = <32>;
2215 out-ports {
2218 remote-endpoint = <&qdss_tpda_in1>;
2225 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2229 clock-names = "apb_pclk";
2231 in-ports {
2232 #address-cells = <1>;
2233 #size-cells = <0>;
2239 remote-endpoint = <&qdss_tpda_out>;
2247 remote-endpoint = <&stm_out>;
2252 out-ports {
2255 remote-endpoint = <&qdss_funnel_in0>;
2262 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2266 clock-names = "apb_pclk";
2268 in-ports {
2269 #address-cells = <1>;
2270 #size-cells = <0>;
2276 remote-endpoint = <&apss_funnel1_out>;
2284 remote-endpoint = <&dlct0_funnel_out>;
2292 remote-endpoint = <&dlmm_funnel_out>;
2300 remote-endpoint = <&dlst_ch_funnel_out>;
2305 out-ports {
2308 remote-endpoint = <&qdss_funnel_in1>;
2315 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2319 clock-names = "apb_pclk";
2321 in-ports {
2322 #address-cells = <1>;
2323 #size-cells = <0>;
2329 remote-endpoint = <&funnel0_out>;
2337 remote-endpoint = <&funnel1_out>;
2342 out-ports {
2345 remote-endpoint = <&aoss_funnel_in7>;
2352 compatible = "qcom,coresight-tpdm", "arm,primecell";
2356 clock-names = "apb_pclk";
2358 qcom,cmb-element-bits = <32>;
2359 qcom,cmb-msrs-num = <32>;
2361 out-ports {
2364 remote-endpoint = <&dlct0_tpda_in19>;
2371 compatible = "qcom,coresight-tpdm", "arm,primecell";
2375 clock-names = "apb_pclk";
2377 qcom,cmb-element-bits = <64>;
2378 qcom,cmb-msrs-num = <32>;
2379 qcom,dsb-element-bits = <32>;
2380 qcom,dsb-msrs-num = <32>;
2382 out-ports {
2385 remote-endpoint = <&dlct0_tpda_in25>;
2392 compatible = "qcom,coresight-tpdm", "arm,primecell";
2396 clock-names = "apb_pclk";
2398 qcom,dsb-element-bits = <32>;
2399 qcom,dsb-msrs-num = <32>;
2401 out-ports {
2404 remote-endpoint = <&dlst_ch_tpda_in8>;
2411 compatible = "qcom,coresight-tpda", "arm,primecell";
2415 clock-names = "apb_pclk";
2417 in-ports {
2418 #address-cells = <1>;
2419 #size-cells = <0>;
2425 remote-endpoint = <&dlst_ch_tpdm0_out>;
2430 out-ports {
2433 remote-endpoint = <&dlst_ch_funnel_in0>;
2440 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2444 clock-names = "apb_pclk";
2446 in-ports {
2447 #address-cells = <1>;
2448 #size-cells = <0>;
2454 remote-endpoint = <&dlst_ch_tpda_out>;
2462 remote-endpoint = <&dlst_funnel_out>;
2470 remote-endpoint = <&gdsp_funnel_out>;
2475 out-ports {
2478 remote-endpoint = <&funnel1_in7>;
2485 compatible = "qcom,coresight-tpdm", "arm,primecell";
2489 clock-names = "apb_pclk";
2491 qcom,dsb-element-bits = <32>;
2492 qcom,dsb-msrs-num = <32>;
2494 out-ports {
2497 remote-endpoint = <&turing2_funnel_in0>;
2504 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2508 clock-names = "apb_pclk";
2510 in-ports {
2513 remote-endpoint = <&turing2_tpdm_out>;
2518 out-ports {
2521 remote-endpoint = <&gdsp_tpda_in5>;
2528 compatible = "qcom,coresight-tpdm", "arm,primecell";
2532 clock-names = "apb_pclk";
2534 qcom,dsb-element-bits = <32>;
2535 qcom,dsb-msrs-num = <32>;
2537 out-ports {
2540 remote-endpoint = <&dlmm_tpda_in27>;
2547 compatible = "qcom,coresight-tpda", "arm,primecell";
2551 clock-names = "apb_pclk";
2553 in-ports {
2554 #address-cells = <1>;
2555 #size-cells = <0>;
2561 remote-endpoint = <&dlmm_tpdm0_out>;
2566 out-ports {
2569 remote-endpoint = <&dlmm_funnel_in0>;
2576 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2580 clock-names = "apb_pclk";
2582 in-ports {
2585 remote-endpoint = <&dlmm_tpda_out>;
2590 out-ports {
2593 remote-endpoint = <&funnel1_in6>;
2600 compatible = "qcom,coresight-tpdm", "arm,primecell";
2604 clock-names = "apb_pclk";
2606 qcom,dsb-element-bits = <32>;
2607 qcom,dsb-msrs-num = <32>;
2609 out-ports {
2612 remote-endpoint = <&dlct0_tpda_in26>;
2619 compatible = "qcom,coresight-tpda", "arm,primecell";
2623 clock-names = "apb_pclk";
2625 in-ports {
2626 #address-cells = <1>;
2627 #size-cells = <0>;
2633 remote-endpoint = <&prng_tpdm_out>;
2641 remote-endpoint = <&pimem_tpdm_out>;
2649 remote-endpoint = <&dlct0_tpdm0_out>;
2654 out-ports {
2657 remote-endpoint = <&dlct0_funnel_in0>;
2664 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2668 clock-names = "apb_pclk";
2670 in-ports {
2671 #address-cells = <1>;
2672 #size-cells = <0>;
2678 remote-endpoint = <&dlct0_tpda_out>;
2686 remote-endpoint = <&ddr_funnel5_out>;
2691 out-ports {
2694 remote-endpoint = <&funnel1_in5>;
2701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2705 clock-names = "apb_pclk";
2707 in-ports {
2708 #address-cells = <1>;
2709 #size-cells = <0>;
2715 remote-endpoint = <&aoss_tpda_out>;
2723 remote-endpoint = <&qdss_funnel_out>;
2728 out-ports {
2731 remote-endpoint = <&etf0_in>;
2738 compatible = "arm,coresight-tmc", "arm,primecell";
2742 clock-names = "apb_pclk";
2744 in-ports {
2747 remote-endpoint = <&aoss_funnel_out>;
2752 out-ports {
2755 remote-endpoint = <&swao_rep_in>;
2762 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2766 clock-names = "apb_pclk";
2768 in-ports {
2771 remote-endpoint = <&etf0_out>;
2776 out-ports {
2777 #address-cells = <1>;
2778 #size-cells = <0>;
2784 remote-endpoint = <&eud_in>;
2791 compatible = "qcom,coresight-tpda", "arm,primecell";
2795 clock-names = "apb_pclk";
2797 in-ports {
2798 #address-cells = <1>;
2799 #size-cells = <0>;
2805 remote-endpoint = <&aoss_tpdm0_out>;
2813 remote-endpoint = <&aoss_tpdm1_out>;
2821 remote-endpoint = <&aoss_tpdm2_out>;
2829 remote-endpoint = <&aoss_tpdm3_out>;
2837 remote-endpoint = <&aoss_tpdm4_out>;
2842 out-ports {
2845 remote-endpoint = <&aoss_funnel_in6>;
2852 compatible = "qcom,coresight-tpdm", "arm,primecell";
2856 clock-names = "apb_pclk";
2858 qcom,cmb-element-bits = <64>;
2859 qcom,cmb-msrs-num = <32>;
2861 out-ports {
2864 remote-endpoint = <&aoss_tpda_in0>;
2871 compatible = "qcom,coresight-tpdm", "arm,primecell";
2875 clock-names = "apb_pclk";
2877 qcom,cmb-element-bits = <64>;
2878 qcom,cmb-msrs-num = <32>;
2880 out-ports {
2883 remote-endpoint = <&aoss_tpda_in1>;
2890 compatible = "qcom,coresight-tpdm", "arm,primecell";
2894 clock-names = "apb_pclk";
2896 qcom,cmb-element-bits = <64>;
2897 qcom,cmb-msrs-num = <32>;
2899 out-ports {
2902 remote-endpoint = <&aoss_tpda_in2>;
2909 compatible = "qcom,coresight-tpdm", "arm,primecell";
2913 clock-names = "apb_pclk";
2915 qcom,cmb-element-bits = <64>;
2916 qcom,cmb-msrs-num = <32>;
2918 out-ports {
2921 remote-endpoint = <&aoss_tpda_in3>;
2928 compatible = "qcom,coresight-tpdm", "arm,primecell";
2932 clock-names = "apb_pclk";
2934 qcom,dsb-element-bits = <32>;
2935 qcom,dsb-msrs-num = <32>;
2937 out-ports {
2940 remote-endpoint = <&aoss_tpda_in4>;
2947 compatible = "arm,coresight-cti", "arm,primecell";
2951 clock-names = "apb_pclk";
2955 compatible = "qcom,coresight-tpdm", "arm,primecell";
2959 clock-names = "apb_pclk";
2961 qcom,dsb-element-bits = <32>;
2962 qcom,dsb-msrs-num = <32>;
2964 out-ports {
2967 remote-endpoint = <&turing0_tpda_in0>;
2974 compatible = "qcom,coresight-tpda", "arm,primecell";
2978 clock-names = "apb_pclk";
2980 in-ports {
2983 remote-endpoint = <&turing0_tpdm0_out>;
2988 out-ports {
2991 remote-endpoint = <&turing0_funnel_in0>;
2998 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3002 clock-names = "apb_pclk";
3004 in-ports {
3007 remote-endpoint = <&turing0_tpda_out>;
3012 out-ports {
3015 remote-endpoint = <&gdsp_funnel_in4>;
3022 compatible = "arm,coresight-cti", "arm,primecell";
3026 clock-names = "apb_pclk";
3030 compatible = "qcom,coresight-tpdm", "arm,primecell";
3034 clock-names = "apb_pclk";
3036 qcom,dsb-element-bits = <32>;
3037 qcom,dsb-msrs-num = <32>;
3039 out-ports {
3042 remote-endpoint = <&gdsp_tpda_in8>;
3049 compatible = "qcom,coresight-tpda", "arm,primecell";
3053 clock-names = "apb_pclk";
3055 in-ports {
3056 #address-cells = <1>;
3057 #size-cells = <0>;
3063 remote-endpoint = <&turing2_funnel_out0>;
3071 remote-endpoint = <&gdsp_tpdm0_out>;
3076 out-ports {
3079 remote-endpoint = <&gdsp_funnel_in0>;
3086 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3090 clock-names = "apb_pclk";
3092 in-ports {
3093 #address-cells = <1>;
3094 #size-cells = <0>;
3100 remote-endpoint = <&gdsp_tpda_out>;
3108 remote-endpoint = <&turing0_funnel_out>;
3113 out-ports {
3116 remote-endpoint = <&dlst_ch_funnel_in6>;
3123 compatible = "qcom,coresight-tpdm", "arm,primecell";
3127 clock-names = "apb_pclk";
3129 qcom,dsb-element-bits = <32>;
3130 qcom,dsb-msrs-num = <32>;
3132 out-ports {
3135 remote-endpoint = <&dlst_tpda_in8>;
3142 compatible = "qcom,coresight-tpda", "arm,primecell";
3146 clock-names = "apb_pclk";
3148 in-ports {
3149 #address-cells = <1>;
3150 #size-cells = <0>;
3156 remote-endpoint = <&dlst_tpdm0_out>;
3161 out-ports {
3164 remote-endpoint = <&dlst_funnel_in0>;
3171 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3175 clock-names = "apb_pclk";
3177 in-ports {
3180 remote-endpoint = <&dlst_tpda_out>;
3185 out-ports {
3188 remote-endpoint = <&dlst_ch_funnel_in4>;
3195 compatible = "qcom,coresight-tpdm", "arm,primecell";
3199 clock-names = "apb_pclk";
3201 qcom,dsb-element-bits = <32>;
3202 qcom,dsb-msrs-num = <32>;
3203 qcom,cmb-element-bits = <32>;
3204 qcom,cmb-msrs-num = <32>;
3206 out-ports {
3209 remote-endpoint = <&ddr_tpda_in4>;
3216 compatible = "qcom,coresight-tpda", "arm,primecell";
3220 clock-names = "apb_pclk";
3222 in-ports {
3223 #address-cells = <1>;
3224 #size-cells = <0>;
3230 remote-endpoint = <&ddr_funnel0_out0>;
3238 remote-endpoint = <&ddr_funnel1_out0>;
3246 remote-endpoint = <&ddr_tpdm3_out>;
3251 out-ports {
3254 remote-endpoint = <&ddr_funnel5_in0>;
3261 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3265 clock-names = "apb_pclk";
3267 in-ports {
3270 remote-endpoint = <&ddr_tpda_out>;
3275 out-ports {
3278 remote-endpoint = <&dlct0_funnel_in4>;
3285 compatible = "qcom,coresight-tpdm", "arm,primecell";
3289 clock-names = "apb_pclk";
3291 qcom,dsb-element-bits = <32>;
3292 qcom,dsb-msrs-num = <32>;
3294 out-ports {
3297 remote-endpoint = <&ddr_funnel0_in0>;
3304 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3308 clock-names = "apb_pclk";
3310 in-ports {
3313 remote-endpoint = <&ddr_tpdm0_out>;
3318 out-ports {
3321 remote-endpoint = <&ddr_tpda_in0>;
3328 compatible = "qcom,coresight-tpdm", "arm,primecell";
3332 clock-names = "apb_pclk";
3334 qcom,dsb-element-bits = <32>;
3335 qcom,dsb-msrs-num = <32>;
3337 out-ports {
3340 remote-endpoint = <&ddr_funnel1_in0>;
3347 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3351 clock-names = "apb_pclk";
3353 in-ports {
3356 remote-endpoint = <&ddr_tpdm1_out>;
3361 out-ports {
3364 remote-endpoint = <&ddr_tpda_in1>;
3376 clock-names = "apb_pclk";
3378 arm,coresight-loses-context-with-cpu;
3379 qcom,skip-power-up;
3381 out-ports {
3384 remote-endpoint = <&apss_funnel0_in0>;
3396 clock-names = "apb_pclk";
3398 arm,coresight-loses-context-with-cpu;
3399 qcom,skip-power-up;
3401 out-ports {
3404 remote-endpoint = <&apss_funnel0_in1>;
3416 clock-names = "apb_pclk";
3418 arm,coresight-loses-context-with-cpu;
3419 qcom,skip-power-up;
3421 out-ports {
3424 remote-endpoint = <&apss_funnel0_in2>;
3436 clock-names = "apb_pclk";
3438 arm,coresight-loses-context-with-cpu;
3439 qcom,skip-power-up;
3441 out-ports {
3444 remote-endpoint = <&apss_funnel0_in3>;
3456 clock-names = "apb_pclk";
3458 arm,coresight-loses-context-with-cpu;
3459 qcom,skip-power-up;
3461 out-ports {
3464 remote-endpoint = <&apss_funnel0_in4>;
3476 clock-names = "apb_pclk";
3478 arm,coresight-loses-context-with-cpu;
3479 qcom,skip-power-up;
3481 out-ports {
3484 remote-endpoint = <&apss_funnel0_in5>;
3496 clock-names = "apb_pclk";
3498 arm,coresight-loses-context-with-cpu;
3499 qcom,skip-power-up;
3501 out-ports {
3504 remote-endpoint = <&apss_funnel0_in6>;
3516 clock-names = "apb_pclk";
3518 arm,coresight-loses-context-with-cpu;
3519 qcom,skip-power-up;
3521 out-ports {
3524 remote-endpoint = <&apss_funnel0_in7>;
3531 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3535 clock-names = "apb_pclk";
3537 in-ports {
3538 #address-cells = <1>;
3539 #size-cells = <0>;
3545 remote-endpoint = <&etm0_out>;
3553 remote-endpoint = <&etm1_out>;
3561 remote-endpoint = <&etm2_out>;
3569 remote-endpoint = <&etm3_out>;
3577 remote-endpoint = <&etm4_out>;
3585 remote-endpoint = <&etm5_out>;
3593 remote-endpoint = <&etm6_out>;
3601 remote-endpoint = <&etm7_out>;
3606 out-ports {
3609 remote-endpoint = <&apss_funnel1_in0>;
3616 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3620 clock-names = "apb_pclk";
3622 in-ports {
3623 #address-cells = <1>;
3624 #size-cells = <0>;
3630 remote-endpoint = <&apss_funnel0_out>;
3638 remote-endpoint = <&apss_tpda_out>;
3643 out-ports {
3646 remote-endpoint = <&funnel1_in4>;
3653 compatible = "arm,coresight-cti", "arm,primecell";
3657 clock-names = "apb_pclk";
3661 compatible = "qcom,coresight-tpdm", "arm,primecell";
3665 clock-names = "apb_pclk";
3667 qcom,cmb-element-bits = <64>;
3668 qcom,cmb-msrs-num = <32>;
3670 out-ports {
3673 remote-endpoint = <&apss_tpda_in3>;
3680 compatible = "qcom,coresight-tpdm", "arm,primecell";
3684 clock-names = "apb_pclk";
3686 qcom,dsb-element-bits = <32>;
3687 qcom,dsb-msrs-num = <32>;
3689 out-ports {
3692 remote-endpoint = <&apss_tpda_in4>;
3699 compatible = "qcom,coresight-tpda", "arm,primecell";
3703 clock-names = "apb_pclk";
3705 in-ports {
3706 #address-cells = <1>;
3707 #size-cells = <0>;
3713 remote-endpoint = <&apss_tpdm0_out>;
3721 remote-endpoint = <&apss_tpdm1_out>;
3729 remote-endpoint = <&apss_tpdm2_out>;
3737 remote-endpoint = <&apss_tpdm3_out>;
3745 remote-endpoint = <&apss_tpdm4_out>;
3750 out-ports {
3753 remote-endpoint = <&apss_funnel1_in3>;
3760 compatible = "qcom,coresight-tpdm", "arm,primecell";
3764 clock-names = "apb_pclk";
3766 qcom,cmb-element-bits = <32>;
3767 qcom,cmb-msrs-num = <32>;
3769 out-ports {
3772 remote-endpoint = <&apss_tpda_in1>;
3779 compatible = "qcom,coresight-tpdm", "arm,primecell";
3783 clock-names = "apb_pclk";
3785 qcom,cmb-element-bits = <32>;
3786 qcom,cmb-msrs-num = <32>;
3788 out-ports {
3791 remote-endpoint = <&apss_tpda_in0>;
3798 compatible = "qcom,coresight-tpdm", "arm,primecell";
3802 clock-names = "apb_pclk";
3804 qcom,dsb-element-bits = <32>;
3805 qcom,dsb-msrs-num = <32>;
3807 out-ports {
3810 remote-endpoint = <&apss_tpda_in2>;
3817 compatible = "arm,coresight-cti", "arm,primecell";
3821 clock-names = "apb_pclk";
3825 compatible = "arm,coresight-cti", "arm,primecell";
3829 clock-names = "apb_pclk";
3833 compatible = "arm,coresight-cti", "arm,primecell";
3837 clock-names = "apb_pclk";
3841 compatible = "qcom,qcs8300-usb-hs-phy",
3842 "qcom,usb-snps-hs-7nm-phy";
3846 clock-names = "ref";
3850 #phy-cells = <0>;
3856 compatible = "qcom,qcs8300-usb-hs-phy",
3857 "qcom,usb-snps-hs-7nm-phy";
3861 clock-names = "ref";
3865 #phy-cells = <0>;
3871 compatible = "qcom,qcs8300-qmp-usb3-uni-phy";
3878 clock-names = "aux",
3885 reset-names = "phy", "phy_phy";
3887 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3889 #clock-cells = <0>;
3890 clock-output-names = "usb3_prim_phy_pipe_clk_src";
3892 #phy-cells = <0>;
3898 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
3901 clock-names = "sgmi_ref";
3902 #phy-cells = <0>;
3906 gpucc: clock-controller@3d90000 {
3907 compatible = "qcom,qcs8300-gpucc";
3912 clock-names = "bi_tcxo",
3915 #clock-cells = <1>;
3916 #reset-cells = <1>;
3917 #power-domain-cells = <1>;
3921 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
3922 "qcom,smmu-500", "arm,mmu-500";
3924 #iommu-cells = <2>;
3925 #global-interrupts = <2>;
3948 clock-names = "gcc_gpu_memnoc_gfx_clk",
3955 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3956 dma-coherent;
3960 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3968 operating-points-v2 = <&llcc_bwmon_opp_table>;
3970 llcc_bwmon_opp_table: opp-table {
3971 compatible = "operating-points-v2";
3973 opp-0 {
3974 opp-peak-kBps = <762000>;
3977 opp-1 {
3978 opp-peak-kBps = <1720000>;
3981 opp-2 {
3982 opp-peak-kBps = <2086000>;
3985 opp-3 {
3986 opp-peak-kBps = <2601000>;
3989 opp-4 {
3990 opp-peak-kBps = <2929000>;
3993 opp-5 {
3994 opp-peak-kBps = <5931000>;
3997 opp-6 {
3998 opp-peak-kBps = <6515000>;
4001 opp-7 {
4002 opp-peak-kBps = <7984000>;
4005 opp-8 {
4006 opp-peak-kBps = <10437000>;
4009 opp-9 {
4010 opp-peak-kBps = <12195000>;
4016 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
4022 operating-points-v2 = <&cpu_bwmon_opp_table>;
4024 cpu_bwmon_opp_table: opp-table {
4025 compatible = "operating-points-v2";
4027 opp-0 {
4028 opp-peak-kBps = <9155000>;
4031 opp-1 {
4032 opp-peak-kBps = <12298000>;
4035 opp-2 {
4036 opp-peak-kBps = <14236000>;
4039 opp-3 {
4040 opp-peak-kBps = <16265000>;
4046 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
4052 operating-points-v2 = <&cpu_bwmon_opp_table>;
4056 compatible = "qcom,qcs8300-dc-noc";
4058 #interconnect-cells = <2>;
4059 qcom,bcm-voters = <&apps_bcm_voter>;
4063 compatible = "qcom,qcs8300-gem-noc";
4065 #interconnect-cells = <2>;
4066 qcom,bcm-voters = <&apps_bcm_voter>;
4069 llcc: system-cache-controller@9200000 {
4070 compatible = "qcom,qcs8300-llcc";
4076 reg-names = "llcc0_base",
4085 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
4093 clock-names = "cfg_noc",
4099 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4101 assigned-clock-rates = <19200000>, <200000000>;
4103 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
4108 interrupt-names = "pwr_event",
4114 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4115 required-opps = <&rpmhpd_opp_nom>;
4122 interconnect-names = "usb-ddr", "apps-usb";
4124 wakeup-source;
4126 #address-cells = <2>;
4127 #size-cells = <2>;
4138 phy-names = "usb2-phy", "usb3-phy";
4140 snps,dis-u1-entry-quirk;
4141 snps,dis-u2-entry-quirk;
4148 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
4156 clock-names = "cfg_noc",
4162 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4164 assigned-clock-rates = <19200000>, <120000000>;
4166 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
4170 interrupt-names = "pwr_event",
4175 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4176 required-opps = <&rpmhpd_opp_nom>;
4184 interconnect-names = "usb-ddr", "apps-usb";
4186 qcom,select-utmi-as-pipe-clk;
4187 wakeup-source;
4189 #address-cells = <2>;
4190 #size-cells = <2>;
4203 phy-names = "usb2-phy";
4204 maximum-speed = "high-speed";
4206 snps,dis-u1-entry-quirk;
4207 snps,dis-u2-entry-quirk;
4214 videocc: clock-controller@abf0000 {
4215 compatible = "qcom,qcs8300-videocc";
4221 power-domains = <&rpmhpd RPMHPD_MMCX>;
4222 #clock-cells = <1>;
4223 #reset-cells = <1>;
4224 #power-domain-cells = <1>;
4227 camcc: clock-controller@ade0000 {
4228 compatible = "qcom,qcs8300-camcc";
4234 power-domains = <&rpmhpd RPMHPD_MMCX>;
4235 #clock-cells = <1>;
4236 #reset-cells = <1>;
4237 #power-domain-cells = <1>;
4240 dispcc: clock-controller@af00000 {
4241 compatible = "qcom,sa8775p-dispcc0";
4249 power-domains = <&rpmhpd RPMHPD_MMCX>;
4250 #clock-cells = <1>;
4251 #reset-cells = <1>;
4252 #power-domain-cells = <1>;
4255 pdc: interrupt-controller@b220000 {
4256 compatible = "qcom,qcs8300-pdc", "qcom,pdc";
4259 interrupt-parent = <&intc>;
4260 #interrupt-cells = <2>;
4261 interrupt-controller;
4262 qcom,pdc-ranges = <0 480 40>,
4302 aoss_qmp: power-management@c300000 {
4303 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";
4305 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4309 #clock-cells = <0>;
4313 compatible = "qcom,rpmh-stats";
4318 compatible = "qcom,spmi-pmic-arb";
4324 reg-names = "core",
4331 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4332 interrupt-names = "periph_irq";
4333 interrupt-controller;
4334 #interrupt-cells = <4>;
4335 #address-cells = <2>;
4336 #size-cells = <0>;
4340 compatible = "qcom,qcs8300-tlmm";
4343 gpio-controller;
4344 #gpio-cells = <2>;
4345 gpio-ranges = <&tlmm 0 0 134>;
4346 interrupt-controller;
4347 #interrupt-cells = <2>;
4348 wakeup-parent = <&pdc>;
4350 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4355 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4360 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4365 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4370 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4375 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4380 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4385 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4390 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4395 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4400 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4405 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4410 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4415 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4420 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4425 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
4430 qup_spi0_data_clk: qup-spi0-data-clk-state {
4435 qup_spi0_cs: qup-spi0-cs-state {
4440 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4445 qup_spi1_data_clk: qup-spi1-data-clk-state {
4450 qup_spi1_cs: qup-spi1-cs-state {
4455 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4460 qup_spi2_data_clk: qup-spi2-data-clk-state {
4465 qup_spi2_cs: qup-spi2-cs-state {
4470 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
4475 qup_spi3_data_clk: qup-spi3-data-clk-state {
4480 qup_spi3_cs: qup-spi3-cs-state {
4485 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
4490 qup_spi4_data_clk: qup-spi4-data-clk-state {
4495 qup_spi4_cs: qup-spi4-cs-state {
4500 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
4505 qup_spi5_data_clk: qup-spi5-data-clk-state {
4510 qup_spi5_cs: qup-spi5-cs-state {
4515 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
4520 qup_spi6_data_clk: qup-spi6-data-clk-state {
4525 qup_spi6_cs: qup-spi6-cs-state {
4530 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
4535 qup_spi8_data_clk: qup-spi8-data-clk-state {
4540 qup_spi8_cs: qup-spi8-cs-state {
4545 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
4550 qup_spi9_data_clk: qup-spi9-data-clk-state {
4555 qup_spi9_cs: qup-spi9-cs-state {
4560 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
4565 qup_spi10_data_clk: qup-spi10-data-clk-state {
4570 qup_spi10_cs: qup-spi10-cs-state {
4575 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
4580 qup_spi12_data_clk: qup-spi12-data-clk-state {
4585 qup_spi12_cs: qup-spi12-cs-state {
4590 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
4595 qup_spi13_data_clk: qup-spi13-data-clk-state {
4600 qup_spi13_cs: qup-spi13-cs-state {
4605 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
4610 qup_spi14_data_clk: qup-spi14-data-clk-state {
4615 qup_spi14_cs: qup-spi14-cs-state {
4620 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
4625 qup_spi15_data_clk: qup-spi15-data-clk-state {
4630 qup_spi15_cs: qup-spi15-cs-state {
4635 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
4640 qup_spi16_data_clk: qup-spi16-data-clk-state {
4645 qup_spi16_cs: qup-spi16-cs-state {
4650 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
4655 qup_uart0_cts: qup-uart0-cts-state {
4660 qup_uart0_rts: qup-uart0-rts-state {
4665 qup_uart0_tx: qup-uart0-tx-state {
4670 qup_uart0_rx: qup-uart0-rx-state {
4675 qup_uart1_cts: qup-uart1-cts-state {
4680 qup_uart1_rts: qup-uart1-rts-state {
4685 qup_uart1_tx: qup-uart1-tx-state {
4690 qup_uart1_rx: qup-uart1-rx-state {
4695 qup_uart2_cts: qup-uart2-cts-state {
4700 qup_uart2_rts: qup-uart2-rts-state {
4705 qup_uart2_tx: qup-uart2-tx-state {
4710 qup_uart2_rx: qup-uart2-rx-state {
4715 qup_uart3_cts: qup-uart3-cts-state {
4720 qup_uart3_rts: qup-uart3-rts-state {
4725 qup_uart3_tx: qup-uart3-tx-state {
4730 qup_uart3_rx: qup-uart3-rx-state {
4735 qup_uart4_cts: qup-uart4-cts-state {
4740 qup_uart4_rts: qup-uart4-rts-state {
4745 qup_uart4_tx: qup-uart4-tx-state {
4750 qup_uart4_rx: qup-uart4-rx-state {
4755 qup_uart5_cts: qup-uart5-cts-state {
4760 qup_uart5_rts: qup-uart5-rts-state {
4765 qup_uart5_tx: qup-uart5-tx-state {
4770 qup_uart5_rx: qup-uart5-rx-state {
4775 qup_uart6_cts: qup-uart6-cts-state {
4780 qup_uart6_rts: qup-uart6-rts-state {
4785 qup_uart6_tx: qup-uart6-tx-state {
4790 qup_uart6_rx: qup-uart6-rx-state {
4795 qup_uart7_tx: qup-uart7-tx-state {
4800 qup_uart7_rx: qup-uart7-rx-state {
4805 qup_uart8_cts: qup-uart8-cts-state {
4810 qup_uart8_rts: qup-uart8-rts-state {
4815 qup_uart8_tx: qup-uart8-tx-state {
4820 qup_uart8_rx: qup-uart8-rx-state {
4825 qup_uart9_cts: qup-uart9-cts-state {
4830 qup_uart9_rts: qup-uart9-rts-state {
4835 qup_uart9_tx: qup-uart9-tx-state {
4840 qup_uart9_rx: qup-uart9-rx-state {
4845 qup_uart10_cts: qup-uart10-cts-state {
4850 qup_uart10_rts: qup-uart10-rts-state {
4855 qup_uart10_tx: qup-uart10-tx-state {
4860 qup_uart10_rx: qup-uart10-rx-state {
4865 qup_uart11_tx: qup-uart11-tx-state {
4870 qup_uart11_rx: qup-uart11-rx-state {
4875 qup_uart12_cts: qup-uart12-cts-state {
4880 qup_uart12_rts: qup-uart12-rts-state {
4885 qup_uart12_tx: qup-uart12-tx-state {
4890 qup_uart12_rx: qup-uart12-rx-state {
4895 qup_uart13_cts: qup-uart13-cts-state {
4900 qup_uart13_rts: qup-uart13-rts-state {
4905 qup_uart13_tx: qup-uart13-tx-state {
4910 qup_uart13_rx: qup-uart13-rx-state {
4915 qup_uart14_cts: qup-uart14-cts-state {
4920 qup_uart14_rts: qup-uart14-rts-state {
4925 qup_uart14_tx: qup-uart14-tx-state {
4930 qup_uart14_rx: qup-uart14-rx-state {
4935 qup_uart15_cts: qup-uart15-cts-state {
4940 qup_uart15_rts: qup-uart15-rts-state {
4945 qup_uart15_tx: qup-uart15-tx-state {
4950 qup_uart15_rx: qup-uart15-rx-state {
4955 qup_uart16_cts: qup-uart16-cts-state {
4960 qup_uart16_rts: qup-uart16-rts-state {
4965 qup_uart16_tx: qup-uart16-tx-state {
4970 qup_uart16_rx: qup-uart16-rx-state {
4977 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd";
4981 #address-cells = <1>;
4982 #size-cells = <1>;
4984 pil-reloc@94c {
4985 compatible = "qcom,pil-reloc-info";
4991 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4994 #iommu-cells = <2>;
4995 #global-interrupts = <2>;
4996 dma-coherent;
5131 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5133 #iommu-cells = <2>;
5134 #global-interrupts = <2>;
5135 dma-coherent;
5205 intc: interrupt-controller@17a00000 {
5206 compatible = "arm,gic-v3";
5210 #interrupt-cells = <3>;
5211 interrupt-controller;
5212 #redistributor-regions = <1>;
5213 redistributor-stride = <0x0 0x20000>;
5217 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
5224 compatible = "arm,armv7-timer-mem";
5227 #address-cells = <1>;
5228 #size-cells = <1>;
5233 frame-number = <0>;
5240 frame-number = <1>;
5247 frame-number = <2>;
5254 frame-number = <3>;
5261 frame-number = <4>;
5268 frame-number = <5>;
5275 frame-number = <6>;
5282 compatible = "qcom,rpmh-rsc";
5286 reg-names = "drv-0",
5287 "drv-1",
5288 "drv-2";
5293 power-domains = <&system_pd>;
5296 qcom,tcs-offset = <0xd00>;
5297 qcom,drv-id = <2>;
5298 qcom,tcs-config = <ACTIVE_TCS 2>,
5303 apps_bcm_voter: bcm-voter {
5304 compatible = "qcom,bcm-voter";
5307 rpmhcc: clock-controller {
5308 compatible = "qcom,sa8775p-rpmh-clk";
5309 #clock-cells = <1>;
5311 clock-names = "xo";
5314 rpmhpd: power-controller {
5315 compatible = "qcom,qcs8300-rpmhpd";
5316 #power-domain-cells = <1>;
5317 operating-points-v2 = <&rpmhpd_opp_table>;
5319 rpmhpd_opp_table: opp-table {
5320 compatible = "operating-points-v2";
5322 rpmhpd_opp_ret: opp-0 {
5323 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5326 rpmhpd_opp_min_svs: opp-1 {
5327 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5330 rpmhpd_opp_low_svs: opp-2 {
5331 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5334 rpmhpd_opp_svs: opp-3 {
5335 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5338 rpmhpd_opp_svs_l1: opp-4 {
5339 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5342 rpmhpd_opp_nom: opp-5 {
5343 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5346 rpmhpd_opp_nom_l1: opp-6 {
5347 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5350 rpmhpd_opp_nom_l2: opp-7 {
5351 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5354 rpmhpd_opp_turbo: opp-8 {
5355 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5358 rpmhpd_opp_turbo_l1: opp-9 {
5359 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5366 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss";
5370 reg-names = "freq-domain0",
5371 "freq-domain1",
5372 "freq-domain2";
5377 interrupt-names = "dcvsh-irq-0",
5378 "dcvsh-irq-1",
5379 "dcvsh-irq-2";
5382 clock-names = "xo", "alternate";
5384 #freq-domain-cells = <1>;
5388 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
5391 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
5396 interrupt-names = "wdog",
5400 "stop-ack";
5403 clock-names = "xo";
5405 power-domains = <&rpmhpd RPMHPD_CX>,
5407 power-domain-names = "cx",
5413 memory-region = <&gpdsp_mem>;
5417 qcom,smem-states = <&smp2p_gpdsp_out 0>;
5418 qcom,smem-state-names = "stop";
5422 glink-edge {
5423 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
5430 qcom,remote-pid = <17>;
5435 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
5438 reg-names = "stmmaceth", "rgmii";
5442 interrupt-names = "macirq", "sfty";
5448 clock-names = "stmmaceth",
5452 power-domains = <&gcc GCC_EMAC0_GDSC>;
5455 phy-names = "serdes";
5458 dma-coherent;
5462 rx-fifo-depth = <16384>;
5463 tx-fifo-depth = <20480>;
5469 compatible = "qcom,qcs8300-nspa-noc";
5471 #interconnect-cells = <2>;
5472 qcom,bcm-voters = <&apps_bcm_voter>;
5476 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas";
5479 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5484 interrupt-names = "wdog",
5488 "stop-ack";
5491 clock-names = "xo";
5493 power-domains = <&rpmhpd RPMHPD_CX>,
5497 power-domain-names = "cx",
5504 memory-region = <&cdsp_mem>;
5508 qcom,smem-states = <&smp2p_cdsp_out 0>;
5509 qcom,smem-state-names = "stop";
5513 glink-edge {
5514 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5521 qcom,remote-pid = <5>;
5525 qcom,glink-channels = "fastrpcglink-apps-dsp";
5527 #address-cells = <1>;
5528 #size-cells = <0>;
5530 compute-cb@1 {
5531 compatible = "qcom,fastrpc-compute-cb";
5535 dma-coherent;
5538 compute-cb@2 {
5539 compatible = "qcom,fastrpc-compute-cb";
5543 dma-coherent;
5546 compute-cb@3 {
5547 compatible = "qcom,fastrpc-compute-cb";
5551 dma-coherent;
5554 compute-cb@4 {
5555 compatible = "qcom,fastrpc-compute-cb";
5559 dma-coherent;
5567 compatible = "arm,armv8-timer";