Lines Matching +full:tcsr +full:- +full:mutex
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
8 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
22 xo_board: xo-board {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <19200000>;
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32764>;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 cpu-idle-states = <&cpu_sleep_0>;
45 next-level-cache = <&l2_0>;
46 #cooling-cells = <2>;
48 operating-points-v2 = <&cpu_opp_table>;
49 power-domains = <&cpr>;
50 power-domain-names = "cpr";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 cpu-idle-states = <&cpu_sleep_0>;
59 next-level-cache = <&l2_0>;
60 #cooling-cells = <2>;
62 operating-points-v2 = <&cpu_opp_table>;
63 power-domains = <&cpr>;
64 power-domain-names = "cpr";
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&cpu_sleep_0>;
73 next-level-cache = <&l2_0>;
74 #cooling-cells = <2>;
76 operating-points-v2 = <&cpu_opp_table>;
77 power-domains = <&cpr>;
78 power-domain-names = "cpr";
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 cpu-idle-states = <&cpu_sleep_0>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
90 operating-points-v2 = <&cpu_opp_table>;
91 power-domains = <&cpr>;
92 power-domain-names = "cpr";
95 l2_0: l2-cache {
97 cache-level = <2>;
98 cache-unified;
101 idle-states {
102 entry-method = "psci";
104 cpu_sleep_0: cpu-sleep-0 {
105 compatible = "arm,idle-state";
106 idle-state-name = "standalone-power-collapse";
107 arm,psci-suspend-param = <0x40000003>;
108 entry-latency-us = <125>;
109 exit-latency-us = <180>;
110 min-residency-us = <595>;
111 local-timer-stop;
116 cpu_opp_table: opp-table-cpu {
117 compatible = "operating-points-v2-kryo-cpu";
118 opp-shared;
120 opp-1094400000 {
121 opp-hz = /bits/ 64 <1094400000>;
122 required-opps = <&cpr_opp1>;
124 opp-1248000000 {
125 opp-hz = /bits/ 64 <1248000000>;
126 required-opps = <&cpr_opp2>;
128 opp-1401600000 {
129 opp-hz = /bits/ 64 <1401600000>;
130 required-opps = <&cpr_opp3>;
134 cpr_opp_table: opp-table-cpr {
135 compatible = "operating-points-v2-qcom-level";
138 opp-level = <1>;
139 qcom,opp-fuse-level = <1>;
142 opp-level = <2>;
143 qcom,opp-fuse-level = <2>;
146 opp-level = <3>;
147 qcom,opp-fuse-level = <3>;
153 compatible = "qcom,scm-qcs404", "qcom,scm";
154 #reset-cells = <1>;
165 compatible = "arm,psci-1.0";
170 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
172 glink-edge {
173 compatible = "qcom,glink-rpm";
176 qcom,rpm-msg-ram = <&rpm_msg_ram>;
179 rpm_requests: rpm-requests {
180 compatible = "qcom,rpm-qcs404", "qcom,glink-smd-rpm";
181 qcom,glink-channels = "rpm_requests";
183 rpmcc: clock-controller {
184 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
185 #clock-cells = <1>;
187 clock-names = "xo";
190 rpmpd: power-controller {
191 compatible = "qcom,qcs404-rpmpd";
192 #power-domain-cells = <1>;
193 operating-points-v2 = <&rpmpd_opp_table>;
195 rpmpd_opp_table: opp-table {
196 compatible = "operating-points-v2";
199 opp-level = <16>;
203 opp-level = <32>;
207 opp-level = <48>;
211 opp-level = <64>;
215 opp-level = <128>;
219 opp-level = <192>;
223 opp-level = <256>;
227 opp-level = <320>;
231 opp-level = <384>;
235 opp-level = <416>;
239 opp-level = <512>;
247 reserved-memory {
248 #address-cells = <2>;
249 #size-cells = <2>;
254 no-map;
259 no-map;
264 no-map;
269 no-map;
274 no-map;
279 no-map;
284 no-map;
289 no-map;
294 no-map;
301 memory-region = <&smem_region>;
302 qcom,rpm-msg-ram = <&rpm_msg_ram>;
308 #address-cells = <1>;
309 #size-cells = <1>;
311 compatible = "simple-bus";
313 turingcc: clock-controller@800000 {
314 compatible = "qcom,qcs404-turingcc";
318 #clock-cells = <1>;
319 #reset-cells = <1>;
325 compatible = "qcom,rpm-msg-ram";
330 compatible = "qcom,usb-ss-28nm-phy";
332 #phy-cells = <0>;
336 clock-names = "ref", "ahb", "pipe";
339 reset-names = "com", "phy";
344 compatible = "qcom,usb-hs-28nm-femtophy";
346 #phy-cells = <0>;
350 clock-names = "ref", "ahb", "sleep";
353 reset-names = "phy", "por";
358 compatible = "qcom,usb-hs-28nm-femtophy";
360 #phy-cells = <0>;
364 clock-names = "ref", "ahb", "sleep";
367 reset-names = "phy", "por";
372 compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
374 #address-cells = <1>;
375 #size-cells = <1>;
381 tsens_s0_p1: s0-p1@1f8 {
386 tsens_s0_p2: s0-p2@1f8 {
391 tsens_s1_p1: s1-p1@1f9 {
396 tsens_s1_p2: s1-p2@1fa {
401 tsens_s2_p1: s2-p1@1fb {
406 tsens_s2_p2: s2-p2@1fb {
411 tsens_s3_p1: s3-p1@1fc {
416 tsens_s3_p2: s3-p2@1fd {
421 tsens_s4_p1: s4-p1@1fe {
426 tsens_s4_p2: s4-p2@1fe {
431 tsens_s5_p1: s5-p1@200 {
436 tsens_s5_p2: s5-p2@200 {
441 tsens_s6_p1: s6-p1@201 {
446 tsens_s6_p2: s6-p2@202 {
451 tsens_s7_p1: s7-p1@203 {
456 tsens_s7_p2: s7-p2@203 {
461 tsens_s8_p1: s8-p1@204 {
466 tsens_s8_p2: s8-p2@205 {
471 tsens_s9_p1: s9-p1@206 {
476 tsens_s9_p2: s9-p2@206 {
551 compatible = "qcom,prng-ee";
554 clock-names = "core";
559 compatible = "qcom,qcs404-bimc";
560 #interconnect-cells = <1>;
563 tsens: thermal-sensor@4a9000 {
564 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
567 nvmem-cells = <&tsens_mode>,
579 nvmem-cell-names = "mode",
593 interrupt-names = "uplow";
594 #thermal-sensor-cells = <1>;
599 compatible = "qcom,qcs404-pcnoc";
600 #interconnect-cells = <1>;
605 compatible = "qcom,qcs404-snoc";
606 #interconnect-cells = <1>;
610 compatible = "qcom,qcs404-cdsp-pas";
613 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
618 interrupt-names = "wdog", "fatal", "ready",
619 "handover", "stop-ack";
622 clock-names = "xo";
634 * clock-names = "xo",
643 * reset-names = "restart";
644 * qcom,halt-regs = <&tcsr 0x19004>;
647 memory-region = <&cdsp_fw_mem>;
649 qcom,smem-states = <&cdsp_smp2p_out 0>;
650 qcom,smem-state-names = "stop";
654 glink-edge {
657 qcom,remote-pid = <5>;
665 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
667 #address-cells = <1>;
668 #size-cells = <1>;
674 clock-names = "core", "iface", "sleep", "mock_utmi";
675 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
677 assigned-clock-rates = <19200000>, <200000000>;
682 interrupt-names = "pwr_event",
693 phy-names = "usb2-phy", "usb3-phy";
694 snps,has-lpm-erratum;
695 snps,hird-threshold = /bits/ 8 <0x10>;
697 snps,dis-u1-entry-quirk;
698 snps,dis-u2-entry-quirk;
704 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
706 #address-cells = <1>;
707 #size-cells = <1>;
713 clock-names = "core", "iface", "sleep", "mock_utmi";
714 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
716 assigned-clock-rates = <19200000>, <133333333>;
721 interrupt-names = "pwr_event",
732 phy-names = "usb2-phy";
733 snps,has-lpm-erratum;
734 snps,hird-threshold = /bits/ 8 <0x10>;
736 snps,dis-u1-entry-quirk;
737 snps,dis-u2-entry-quirk;
743 compatible = "qcom,qcs404-pinctrl";
747 reg-names = "south", "north", "east";
749 gpio-ranges = <&tlmm 0 0 120>;
750 gpio-controller;
751 #gpio-cells = <2>;
752 interrupt-controller;
753 #interrupt-cells = <2>;
755 blsp1_i2c0_default: blsp1-i2c0-default-state {
760 blsp1_i2c1_default: blsp1-i2c1-default-state {
765 blsp1_i2c2_default: blsp1-i2c2-default-state {
766 sda-pins {
771 scl-pins {
777 blsp1_i2c3_default: blsp1-i2c3-default-state {
782 blsp1_i2c4_default: blsp1-i2c4-default-state {
787 blsp1_uart0_default: blsp1-uart0-default-state {
792 blsp1_uart1_default: blsp1-uart1-default-state {
797 blsp1_uart2_default: blsp1-uart2-default-state {
798 rx-pins {
803 tx-pins {
809 blsp1_uart3_default: blsp1-uart3-default-state {
810 cts-pins {
815 rts-tx-pins {
820 rx-pins {
826 blsp2_i2c0_default: blsp2-i2c0-default-state {
831 blsp1_spi0_default: blsp1-spi0-default-state {
836 blsp1_spi1_default: blsp1-spi1-default-state {
837 mosi-pins {
842 miso-pins {
847 cs-n-pins {
852 clk-pins {
858 blsp1_spi2_default: blsp1-spi2-default-state {
863 blsp1_spi3_default: blsp1-spi3-default-state {
868 blsp1_spi4_default: blsp1-spi4-default-state {
873 blsp2_spi0_default: blsp2-spi0-default-state {
878 blsp2_uart0_default: blsp2-uart0-default-state {
884 gcc: clock-controller@1800000 {
885 compatible = "qcom,gcc-qcs404";
887 #clock-cells = <1>;
888 #reset-cells = <1>;
889 #power-domain-cells = <1>;
898 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
899 assigned-clock-rates = <19200000>;
903 compatible = "qcom,tcsr-mutex";
905 #hwlock-cells = <1>;
908 tcsr: syscon@1937000 {
909 compatible = "qcom,qcs404-tcsr", "syscon";
914 compatible = "qcom,rpm-stats";
919 compatible = "qcom,spmi-pmic-arb";
925 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
926 interrupt-names = "periph_irq";
930 #address-cells = <2>;
931 #size-cells = <0>;
932 interrupt-controller;
933 #interrupt-cells = <4>;
937 compatible = "qcom,qcs404-wcss-pas";
940 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
945 interrupt-names = "wdog", "fatal", "ready",
946 "handover", "stop-ack";
949 clock-names = "xo";
951 memory-region = <&wlan_fw_mem>;
953 qcom,smem-states = <&wcss_smp2p_out 0>;
954 qcom,smem-state-names = "stop";
958 glink-edge {
961 qcom,remote-pid = <1>;
969 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
975 reset-names = "phy", "pipe";
977 clock-output-names = "pcie_0_pipe_clk";
978 #clock-cells = <0>;
979 #phy-cells = <0>;
985 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
987 reg-names = "hc", "cqhci";
991 interrupt-names = "hc_irq", "pwr_irq";
996 clock-names = "iface", "core", "xo";
1001 blsp1_dma: dma-controller@7884000 {
1002 compatible = "qcom,bam-v1.7.0";
1006 clock-names = "bam_clk";
1007 #dma-cells = <1>;
1013 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1017 clock-names = "core", "iface";
1019 dma-names = "tx", "rx";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&blsp1_uart0_default>;
1026 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1030 clock-names = "core", "iface";
1032 dma-names = "tx", "rx";
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&blsp1_uart1_default>;
1039 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1043 clock-names = "core", "iface";
1045 dma-names = "tx", "rx";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&blsp1_uart2_default>;
1052 compatible = "qcom,qcs404-ethqos";
1055 reg-names = "stmmaceth", "rgmii";
1056 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
1063 interrupt-names = "macirq", "eth_lpi";
1066 rx-fifo-depth = <4096>;
1067 tx-fifo-depth = <4096>;
1073 compatible = "qcom,wcn3990-wifi";
1075 reg-names = "membase";
1076 memory-region = <&wlan_msa_mem>;
1093 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1097 clock-names = "core", "iface";
1099 dma-names = "tx", "rx";
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&blsp1_uart3_default>;
1106 compatible = "qcom,i2c-qup-v2.2.1";
1111 clock-names = "core", "iface";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&blsp1_i2c0_default>;
1114 #address-cells = <1>;
1115 #size-cells = <0>;
1120 compatible = "qcom,spi-qup-v2.2.1";
1125 clock-names = "core", "iface";
1126 pinctrl-names = "default";
1127 pinctrl-0 = <&blsp1_spi0_default>;
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1134 compatible = "qcom,i2c-qup-v2.2.1";
1139 clock-names = "core", "iface";
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&blsp1_i2c1_default>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1148 compatible = "qcom,spi-qup-v2.2.1";
1153 clock-names = "core", "iface";
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&blsp1_spi1_default>;
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1162 compatible = "qcom,i2c-qup-v2.2.1";
1167 clock-names = "core", "iface";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&blsp1_i2c2_default>;
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1176 compatible = "qcom,spi-qup-v2.2.1";
1181 clock-names = "core", "iface";
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&blsp1_spi2_default>;
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1190 compatible = "qcom,i2c-qup-v2.2.1";
1195 clock-names = "core", "iface";
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&blsp1_i2c3_default>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1204 compatible = "qcom,spi-qup-v2.2.1";
1209 clock-names = "core", "iface";
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&blsp1_spi3_default>;
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1218 compatible = "qcom,i2c-qup-v2.2.1";
1223 clock-names = "core", "iface";
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&blsp1_i2c4_default>;
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1232 compatible = "qcom,spi-qup-v2.2.1";
1237 clock-names = "core", "iface";
1238 pinctrl-names = "default";
1239 pinctrl-0 = <&blsp1_spi4_default>;
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1245 blsp2_dma: dma-controller@7ac4000 {
1246 compatible = "qcom,bam-v1.7.0";
1250 clock-names = "bam_clk";
1251 #dma-cells = <1>;
1257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1261 clock-names = "core", "iface";
1263 dma-names = "tx", "rx";
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&blsp2_uart0_default>;
1270 compatible = "qcom,i2c-qup-v2.2.1";
1275 clock-names = "core", "iface";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&blsp2_i2c0_default>;
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1284 compatible = "qcom,spi-qup-v2.2.1";
1289 clock-names = "core", "iface";
1290 pinctrl-names = "default";
1291 pinctrl-0 = <&blsp2_spi0_default>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1298 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
1301 #address-cells = <1>;
1302 #size-cells = <1>;
1306 pil-reloc@94c {
1307 compatible = "qcom,pil-reloc-info";
1312 intc: interrupt-controller@b000000 {
1313 compatible = "qcom,msm-qgic2";
1314 interrupt-controller;
1315 #interrupt-cells = <3>;
1321 compatible = "qcom,qcs404-apcs-apps-global",
1322 "qcom,msm8916-apcs-kpss-global", "syscon";
1324 #mbox-cells = <1>;
1326 clock-names = "pll", "aux";
1327 #clock-cells = <0>;
1330 apcs_hfpll: clock-controller@b016000 {
1331 compatible = "qcom,qcs404-hfpll";
1333 #clock-cells = <0>;
1334 clock-output-names = "apcs_hfpll";
1336 clock-names = "xo";
1340 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1345 cpr: power-controller@b018000 {
1346 compatible = "qcom,qcs404-cpr", "qcom,cpr";
1350 clock-names = "ref";
1351 vdd-apc-supply = <&pms405_s3>;
1352 #power-domain-cells = <0>;
1353 operating-points-v2 = <&cpr_opp_table>;
1354 acc-syscon = <&tcsr>;
1356 nvmem-cells = <&cpr_efuse_quot_offset1>,
1369 nvmem-cell-names = "cpr_quotient_offset1",
1385 #address-cells = <1>;
1386 #size-cells = <1>;
1388 compatible = "arm,armv7-timer-mem";
1390 clock-frequency = <19200000>;
1393 frame-number = <0>;
1401 frame-number = <1>;
1408 frame-number = <2>;
1415 frame-number = <3>;
1422 frame-number = <4>;
1429 frame-number = <5>;
1436 frame-number = <6>;
1444 compatible = "qcom,qcs404-adsp-pas";
1447 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1452 interrupt-names = "wdog", "fatal", "ready",
1453 "handover", "stop-ack";
1456 clock-names = "xo";
1458 memory-region = <&adsp_fw_mem>;
1460 qcom,smem-states = <&adsp_smp2p_out 0>;
1461 qcom,smem-state-names = "stop";
1465 glink-edge {
1468 qcom,remote-pid = <2>;
1476 compatible = "qcom,pcie-qcs404";
1481 reg-names = "dbi", "elbi", "parf", "config";
1483 linux,pci-domain = <0>;
1484 bus-range = <0x00 0xff>;
1485 num-lanes = <1>;
1486 #address-cells = <3>;
1487 #size-cells = <2>;
1493 interrupt-names = "msi";
1494 #interrupt-cells = <1>;
1495 interrupt-map-mask = <0 0 0 0x7>;
1496 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1504 clock-names = "iface", "aux", "master_bus", "slave_bus";
1512 reset-names = "axi_m",
1520 phy-names = "pciephy";
1527 bus-range = <0x01 0xff>;
1529 #address-cells = <3>;
1530 #size-cells = <2>;
1537 compatible = "arm,armv8-timer";
1544 smp2p-adsp {
1549 qcom,local-pid = <0>;
1550 qcom,remote-pid = <2>;
1552 adsp_smp2p_out: master-kernel {
1553 qcom,entry-name = "master-kernel";
1554 #qcom,smem-state-cells = <1>;
1557 adsp_smp2p_in: slave-kernel {
1558 qcom,entry-name = "slave-kernel";
1559 interrupt-controller;
1560 #interrupt-cells = <2>;
1564 smp2p-cdsp {
1569 qcom,local-pid = <0>;
1570 qcom,remote-pid = <5>;
1572 cdsp_smp2p_out: master-kernel {
1573 qcom,entry-name = "master-kernel";
1574 #qcom,smem-state-cells = <1>;
1577 cdsp_smp2p_in: slave-kernel {
1578 qcom,entry-name = "slave-kernel";
1579 interrupt-controller;
1580 #interrupt-cells = <2>;
1584 smp2p-wcss {
1589 qcom,local-pid = <0>;
1590 qcom,remote-pid = <1>;
1592 wcss_smp2p_out: master-kernel {
1593 qcom,entry-name = "master-kernel";
1594 #qcom,smem-state-cells = <1>;
1597 wcss_smp2p_in: slave-kernel {
1598 qcom,entry-name = "slave-kernel";
1599 interrupt-controller;
1600 #interrupt-cells = <2>;
1604 thermal-zones {
1605 aoss-thermal {
1606 polling-delay-passive = <250>;
1608 thermal-sensors = <&tsens 0>;
1611 aoss_alert0: trip-point0 {
1619 q6-hvx-thermal {
1620 polling-delay-passive = <250>;
1622 thermal-sensors = <&tsens 1>;
1625 q6_hvx_alert0: trip-point0 {
1633 lpass-thermal {
1634 polling-delay-passive = <250>;
1636 thermal-sensors = <&tsens 2>;
1639 lpass_alert0: trip-point0 {
1647 wlan-thermal {
1648 polling-delay-passive = <250>;
1650 thermal-sensors = <&tsens 3>;
1653 wlan_alert0: trip-point0 {
1661 cluster-thermal {
1662 polling-delay-passive = <250>;
1664 thermal-sensors = <&tsens 4>;
1667 cluster_alert0: trip-point0 {
1672 cluster_alert1: trip-point1 {
1677 cluster_crit: cluster-crit {
1683 cooling-maps {
1686 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1694 cpu0-thermal {
1695 polling-delay-passive = <250>;
1697 thermal-sensors = <&tsens 5>;
1700 cpu0_alert0: trip-point0 {
1705 cpu0_alert1: trip-point1 {
1710 cpu0_crit: cpu-crit {
1716 cooling-maps {
1719 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1727 cpu1-thermal {
1728 polling-delay-passive = <250>;
1730 thermal-sensors = <&tsens 6>;
1733 cpu1_alert0: trip-point0 {
1738 cpu1_alert1: trip-point1 {
1743 cpu1_crit: cpu-crit {
1749 cooling-maps {
1752 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1760 cpu2-thermal {
1761 polling-delay-passive = <250>;
1763 thermal-sensors = <&tsens 7>;
1766 cpu2_alert0: trip-point0 {
1771 cpu2_alert1: trip-point1 {
1776 cpu2_crit: cpu-crit {
1782 cooling-maps {
1785 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1793 cpu3-thermal {
1794 polling-delay-passive = <250>;
1796 thermal-sensors = <&tsens 8>;
1799 cpu3_alert0: trip-point0 {
1804 cpu3_alert1: trip-point1 {
1809 cpu3_crit: cpu-crit {
1815 cooling-maps {
1818 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1826 gpu-thermal {
1827 polling-delay-passive = <250>;
1829 thermal-sensors = <&tsens 9>;
1832 gpu_alert0: trip-point0 {