Lines Matching +full:qcs404 +full:- +full:ethqos
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
8 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
22 xo_board: xo-board {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <19200000>;
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32768>;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 cpu-idle-states = <&cpu_sleep_0>;
45 next-level-cache = <&l2_0>;
46 #cooling-cells = <2>;
48 operating-points-v2 = <&cpu_opp_table>;
49 power-domains = <&cpr>;
50 power-domain-names = "cpr";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 cpu-idle-states = <&cpu_sleep_0>;
59 next-level-cache = <&l2_0>;
60 #cooling-cells = <2>;
62 operating-points-v2 = <&cpu_opp_table>;
63 power-domains = <&cpr>;
64 power-domain-names = "cpr";
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&cpu_sleep_0>;
73 next-level-cache = <&l2_0>;
74 #cooling-cells = <2>;
76 operating-points-v2 = <&cpu_opp_table>;
77 power-domains = <&cpr>;
78 power-domain-names = "cpr";
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 cpu-idle-states = <&cpu_sleep_0>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
90 operating-points-v2 = <&cpu_opp_table>;
91 power-domains = <&cpr>;
92 power-domain-names = "cpr";
95 l2_0: l2-cache {
97 cache-level = <2>;
98 cache-unified;
101 idle-states {
102 entry-method = "psci";
104 cpu_sleep_0: cpu-sleep-0 {
105 compatible = "arm,idle-state";
106 idle-state-name = "standalone-power-collapse";
107 arm,psci-suspend-param = <0x40000003>;
108 entry-latency-us = <125>;
109 exit-latency-us = <180>;
110 min-residency-us = <595>;
111 local-timer-stop;
116 cpu_opp_table: opp-table-cpu {
117 compatible = "operating-points-v2-kryo-cpu";
118 opp-shared;
120 opp-1094400000 {
121 opp-hz = /bits/ 64 <1094400000>;
122 required-opps = <&cpr_opp1>;
124 opp-1248000000 {
125 opp-hz = /bits/ 64 <1248000000>;
126 required-opps = <&cpr_opp2>;
128 opp-1401600000 {
129 opp-hz = /bits/ 64 <1401600000>;
130 required-opps = <&cpr_opp3>;
134 cpr_opp_table: opp-table-cpr {
135 compatible = "operating-points-v2-qcom-level";
138 opp-level = <1>;
139 qcom,opp-fuse-level = <1>;
142 opp-level = <2>;
143 qcom,opp-fuse-level = <2>;
146 opp-level = <3>;
147 qcom,opp-fuse-level = <3>;
153 compatible = "qcom,scm-qcs404", "qcom,scm";
154 #reset-cells = <1>;
165 compatible = "arm,psci-1.0";
170 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
172 glink-edge {
173 compatible = "qcom,glink-rpm";
176 qcom,rpm-msg-ram = <&rpm_msg_ram>;
179 rpm_requests: rpm-requests {
180 compatible = "qcom,rpm-qcs404", "qcom,glink-smd-rpm";
181 qcom,glink-channels = "rpm_requests";
183 rpmcc: clock-controller {
184 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
185 #clock-cells = <1>;
187 clock-names = "xo";
190 rpmpd: power-controller {
191 compatible = "qcom,qcs404-rpmpd";
192 #power-domain-cells = <1>;
193 operating-points-v2 = <&rpmpd_opp_table>;
195 rpmpd_opp_table: opp-table {
196 compatible = "operating-points-v2";
199 opp-level = <16>;
203 opp-level = <32>;
207 opp-level = <48>;
211 opp-level = <64>;
215 opp-level = <128>;
219 opp-level = <192>;
223 opp-level = <256>;
227 opp-level = <320>;
231 opp-level = <384>;
235 opp-level = <416>;
239 opp-level = <512>;
247 reserved-memory {
248 #address-cells = <2>;
249 #size-cells = <2>;
254 no-map;
259 no-map;
264 no-map;
269 no-map;
274 no-map;
279 no-map;
284 no-map;
289 no-map;
294 no-map;
301 memory-region = <&smem_region>;
302 qcom,rpm-msg-ram = <&rpm_msg_ram>;
308 #address-cells = <1>;
309 #size-cells = <1>;
311 compatible = "simple-bus";
313 turingcc: clock-controller@800000 {
314 compatible = "qcom,qcs404-turingcc";
318 #clock-cells = <1>;
319 #reset-cells = <1>;
325 compatible = "qcom,rpm-msg-ram";
330 compatible = "qcom,usb-ss-28nm-phy";
332 #phy-cells = <0>;
336 clock-names = "ref", "ahb", "pipe";
339 reset-names = "com", "phy";
344 compatible = "qcom,usb-hs-28nm-femtophy";
346 #phy-cells = <0>;
350 clock-names = "ref", "ahb", "sleep";
353 reset-names = "phy", "por";
358 compatible = "qcom,usb-hs-28nm-femtophy";
360 #phy-cells = <0>;
364 clock-names = "ref", "ahb", "sleep";
367 reset-names = "phy", "por";
372 compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
374 #address-cells = <1>;
375 #size-cells = <1>;
381 tsens_s0_p1: s0-p1@1f8 {
386 tsens_s0_p2: s0-p2@1f8 {
391 tsens_s1_p1: s1-p1@1f9 {
396 tsens_s1_p2: s1-p2@1fa {
401 tsens_s2_p1: s2-p1@1fb {
406 tsens_s2_p2: s2-p2@1fb {
411 tsens_s3_p1: s3-p1@1fc {
416 tsens_s3_p2: s3-p2@1fd {
421 tsens_s4_p1: s4-p1@1fe {
426 tsens_s4_p2: s4-p2@1fe {
431 tsens_s5_p1: s5-p1@200 {
436 tsens_s5_p2: s5-p2@200 {
441 tsens_s6_p1: s6-p1@201 {
446 tsens_s6_p2: s6-p2@202 {
451 tsens_s7_p1: s7-p1@203 {
456 tsens_s7_p2: s7-p2@203 {
461 tsens_s8_p1: s8-p1@204 {
466 tsens_s8_p2: s8-p2@205 {
471 tsens_s9_p1: s9-p1@206 {
476 tsens_s9_p2: s9-p2@206 {
551 compatible = "qcom,prng-ee";
554 clock-names = "core";
559 compatible = "qcom,qcs404-bimc";
560 #interconnect-cells = <1>;
563 tsens: thermal-sensor@4a9000 {
564 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
567 nvmem-cells = <&tsens_mode>,
579 nvmem-cell-names = "mode",
593 interrupt-names = "uplow";
594 #thermal-sensor-cells = <1>;
599 compatible = "qcom,qcs404-pcnoc";
600 #interconnect-cells = <1>;
605 compatible = "qcom,qcs404-snoc";
606 #interconnect-cells = <1>;
610 compatible = "qcom,qcs404-cdsp-pas";
613 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
618 interrupt-names = "wdog", "fatal", "ready",
619 "handover", "stop-ack";
622 clock-names = "xo";
634 * clock-names = "xo",
643 * reset-names = "restart";
644 * qcom,halt-regs = <&tcsr 0x19004>;
647 memory-region = <&cdsp_fw_mem>;
649 qcom,smem-states = <&cdsp_smp2p_out 0>;
650 qcom,smem-state-names = "stop";
654 glink-edge {
657 qcom,remote-pid = <5>;
665 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
667 #address-cells = <1>;
668 #size-cells = <1>;
674 clock-names = "core", "iface", "sleep", "mock_utmi";
675 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
677 assigned-clock-rates = <19200000>, <200000000>;
682 interrupt-names = "pwr_event",
693 phy-names = "usb2-phy", "usb3-phy";
694 snps,has-lpm-erratum;
695 snps,hird-threshold = /bits/ 8 <0x10>;
702 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
704 #address-cells = <1>;
705 #size-cells = <1>;
711 clock-names = "core", "iface", "sleep", "mock_utmi";
712 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
714 assigned-clock-rates = <19200000>, <133333333>;
719 interrupt-names = "pwr_event",
730 phy-names = "usb2-phy";
731 snps,has-lpm-erratum;
732 snps,hird-threshold = /bits/ 8 <0x10>;
739 compatible = "qcom,qcs404-pinctrl";
743 reg-names = "south", "north", "east";
745 gpio-ranges = <&tlmm 0 0 120>;
746 gpio-controller;
747 #gpio-cells = <2>;
748 interrupt-controller;
749 #interrupt-cells = <2>;
751 blsp1_i2c0_default: blsp1-i2c0-default-state {
756 blsp1_i2c1_default: blsp1-i2c1-default-state {
761 blsp1_i2c2_default: blsp1-i2c2-default-state {
762 sda-pins {
767 scl-pins {
773 blsp1_i2c3_default: blsp1-i2c3-default-state {
778 blsp1_i2c4_default: blsp1-i2c4-default-state {
783 blsp1_uart0_default: blsp1-uart0-default-state {
788 blsp1_uart1_default: blsp1-uart1-default-state {
793 blsp1_uart2_default: blsp1-uart2-default-state {
794 rx-pins {
799 tx-pins {
805 blsp1_uart3_default: blsp1-uart3-default-state {
806 cts-pins {
811 rts-tx-pins {
816 rx-pins {
822 blsp2_i2c0_default: blsp2-i2c0-default-state {
827 blsp1_spi0_default: blsp1-spi0-default-state {
832 blsp1_spi1_default: blsp1-spi1-default-state {
833 mosi-pins {
838 miso-pins {
843 cs-n-pins {
848 clk-pins {
854 blsp1_spi2_default: blsp1-spi2-default-state {
859 blsp1_spi3_default: blsp1-spi3-default-state {
864 blsp1_spi4_default: blsp1-spi4-default-state {
869 blsp2_spi0_default: blsp2-spi0-default-state {
874 blsp2_uart0_default: blsp2-uart0-default-state {
880 gcc: clock-controller@1800000 {
881 compatible = "qcom,gcc-qcs404";
883 #clock-cells = <1>;
884 #reset-cells = <1>;
885 #power-domain-cells = <1>;
894 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
895 assigned-clock-rates = <19200000>;
899 compatible = "qcom,tcsr-mutex";
901 #hwlock-cells = <1>;
905 compatible = "qcom,qcs404-tcsr", "syscon";
910 compatible = "qcom,rpm-stats";
915 compatible = "qcom,spmi-pmic-arb";
921 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
922 interrupt-names = "periph_irq";
926 #address-cells = <2>;
927 #size-cells = <0>;
928 interrupt-controller;
929 #interrupt-cells = <4>;
933 compatible = "qcom,qcs404-wcss-pas";
936 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
941 interrupt-names = "wdog", "fatal", "ready",
942 "handover", "stop-ack";
945 clock-names = "xo";
947 memory-region = <&wlan_fw_mem>;
949 qcom,smem-states = <&wcss_smp2p_out 0>;
950 qcom,smem-state-names = "stop";
954 glink-edge {
957 qcom,remote-pid = <1>;
965 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
971 reset-names = "phy", "pipe";
973 clock-output-names = "pcie_0_pipe_clk";
974 #clock-cells = <0>;
975 #phy-cells = <0>;
981 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
983 reg-names = "hc", "cqhci";
987 interrupt-names = "hc_irq", "pwr_irq";
992 clock-names = "iface", "core", "xo";
997 blsp1_dma: dma-controller@7884000 {
998 compatible = "qcom,bam-v1.7.0";
1002 clock-names = "bam_clk";
1003 #dma-cells = <1>;
1009 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1013 clock-names = "core", "iface";
1015 dma-names = "tx", "rx";
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&blsp1_uart0_default>;
1022 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1026 clock-names = "core", "iface";
1028 dma-names = "tx", "rx";
1029 pinctrl-names = "default";
1030 pinctrl-0 = <&blsp1_uart1_default>;
1035 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1039 clock-names = "core", "iface";
1041 dma-names = "tx", "rx";
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&blsp1_uart2_default>;
1048 compatible = "qcom,qcs404-ethqos";
1051 reg-names = "stmmaceth", "rgmii";
1052 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
1059 interrupt-names = "macirq", "eth_lpi";
1062 rx-fifo-depth = <4096>;
1063 tx-fifo-depth = <4096>;
1069 compatible = "qcom,wcn3990-wifi";
1071 reg-names = "membase";
1072 memory-region = <&wlan_msa_mem>;
1089 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1093 clock-names = "core", "iface";
1095 dma-names = "tx", "rx";
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&blsp1_uart3_default>;
1102 compatible = "qcom,i2c-qup-v2.2.1";
1107 clock-names = "core", "iface";
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&blsp1_i2c0_default>;
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1116 compatible = "qcom,spi-qup-v2.2.1";
1121 clock-names = "core", "iface";
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&blsp1_spi0_default>;
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1130 compatible = "qcom,i2c-qup-v2.2.1";
1135 clock-names = "core", "iface";
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&blsp1_i2c1_default>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1144 compatible = "qcom,spi-qup-v2.2.1";
1149 clock-names = "core", "iface";
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&blsp1_spi1_default>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1158 compatible = "qcom,i2c-qup-v2.2.1";
1163 clock-names = "core", "iface";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&blsp1_i2c2_default>;
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1172 compatible = "qcom,spi-qup-v2.2.1";
1177 clock-names = "core", "iface";
1178 pinctrl-names = "default";
1179 pinctrl-0 = <&blsp1_spi2_default>;
1180 #address-cells = <1>;
1181 #size-cells = <0>;
1186 compatible = "qcom,i2c-qup-v2.2.1";
1191 clock-names = "core", "iface";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&blsp1_i2c3_default>;
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1200 compatible = "qcom,spi-qup-v2.2.1";
1205 clock-names = "core", "iface";
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&blsp1_spi3_default>;
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1214 compatible = "qcom,i2c-qup-v2.2.1";
1219 clock-names = "core", "iface";
1220 pinctrl-names = "default";
1221 pinctrl-0 = <&blsp1_i2c4_default>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1228 compatible = "qcom,spi-qup-v2.2.1";
1233 clock-names = "core", "iface";
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&blsp1_spi4_default>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1241 blsp2_dma: dma-controller@7ac4000 {
1242 compatible = "qcom,bam-v1.7.0";
1246 clock-names = "bam_clk";
1247 #dma-cells = <1>;
1253 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1257 clock-names = "core", "iface";
1259 dma-names = "tx", "rx";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&blsp2_uart0_default>;
1266 compatible = "qcom,i2c-qup-v2.2.1";
1271 clock-names = "core", "iface";
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&blsp2_i2c0_default>;
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1280 compatible = "qcom,spi-qup-v2.2.1";
1285 clock-names = "core", "iface";
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&blsp2_spi0_default>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1294 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
1297 #address-cells = <1>;
1298 #size-cells = <1>;
1302 pil-reloc@94c {
1303 compatible = "qcom,pil-reloc-info";
1308 intc: interrupt-controller@b000000 {
1309 compatible = "qcom,msm-qgic2";
1310 interrupt-controller;
1311 #interrupt-cells = <3>;
1317 compatible = "qcom,qcs404-apcs-apps-global",
1318 "qcom,msm8916-apcs-kpss-global", "syscon";
1320 #mbox-cells = <1>;
1322 clock-names = "pll", "aux";
1323 #clock-cells = <0>;
1326 apcs_hfpll: clock-controller@b016000 {
1327 compatible = "qcom,qcs404-hfpll";
1329 #clock-cells = <0>;
1330 clock-output-names = "apcs_hfpll";
1332 clock-names = "xo";
1336 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1341 cpr: power-controller@b018000 {
1342 compatible = "qcom,qcs404-cpr", "qcom,cpr";
1346 clock-names = "ref";
1347 vdd-apc-supply = <&pms405_s3>;
1348 #power-domain-cells = <0>;
1349 operating-points-v2 = <&cpr_opp_table>;
1350 acc-syscon = <&tcsr>;
1352 nvmem-cells = <&cpr_efuse_quot_offset1>,
1365 nvmem-cell-names = "cpr_quotient_offset1",
1381 #address-cells = <1>;
1382 #size-cells = <1>;
1384 compatible = "arm,armv7-timer-mem";
1386 clock-frequency = <19200000>;
1389 frame-number = <0>;
1397 frame-number = <1>;
1404 frame-number = <2>;
1411 frame-number = <3>;
1418 frame-number = <4>;
1425 frame-number = <5>;
1432 frame-number = <6>;
1440 compatible = "qcom,qcs404-adsp-pas";
1443 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1448 interrupt-names = "wdog", "fatal", "ready",
1449 "handover", "stop-ack";
1452 clock-names = "xo";
1454 memory-region = <&adsp_fw_mem>;
1456 qcom,smem-states = <&adsp_smp2p_out 0>;
1457 qcom,smem-state-names = "stop";
1461 glink-edge {
1464 qcom,remote-pid = <2>;
1472 compatible = "qcom,pcie-qcs404";
1477 reg-names = "dbi", "elbi", "parf", "config";
1479 linux,pci-domain = <0>;
1480 bus-range = <0x00 0xff>;
1481 num-lanes = <1>;
1482 #address-cells = <3>;
1483 #size-cells = <2>;
1489 interrupt-names = "msi";
1490 #interrupt-cells = <1>;
1491 interrupt-map-mask = <0 0 0 0x7>;
1492 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1500 clock-names = "iface", "aux", "master_bus", "slave_bus";
1508 reset-names = "axi_m",
1516 phy-names = "pciephy";
1523 bus-range = <0x01 0xff>;
1525 #address-cells = <3>;
1526 #size-cells = <2>;
1533 compatible = "arm,armv8-timer";
1540 smp2p-adsp {
1545 qcom,local-pid = <0>;
1546 qcom,remote-pid = <2>;
1548 adsp_smp2p_out: master-kernel {
1549 qcom,entry-name = "master-kernel";
1550 #qcom,smem-state-cells = <1>;
1553 adsp_smp2p_in: slave-kernel {
1554 qcom,entry-name = "slave-kernel";
1555 interrupt-controller;
1556 #interrupt-cells = <2>;
1560 smp2p-cdsp {
1565 qcom,local-pid = <0>;
1566 qcom,remote-pid = <5>;
1568 cdsp_smp2p_out: master-kernel {
1569 qcom,entry-name = "master-kernel";
1570 #qcom,smem-state-cells = <1>;
1573 cdsp_smp2p_in: slave-kernel {
1574 qcom,entry-name = "slave-kernel";
1575 interrupt-controller;
1576 #interrupt-cells = <2>;
1580 smp2p-wcss {
1585 qcom,local-pid = <0>;
1586 qcom,remote-pid = <1>;
1588 wcss_smp2p_out: master-kernel {
1589 qcom,entry-name = "master-kernel";
1590 #qcom,smem-state-cells = <1>;
1593 wcss_smp2p_in: slave-kernel {
1594 qcom,entry-name = "slave-kernel";
1595 interrupt-controller;
1596 #interrupt-cells = <2>;
1600 thermal-zones {
1601 aoss-thermal {
1602 polling-delay-passive = <250>;
1604 thermal-sensors = <&tsens 0>;
1607 aoss_alert0: trip-point0 {
1615 q6-hvx-thermal {
1616 polling-delay-passive = <250>;
1618 thermal-sensors = <&tsens 1>;
1621 q6_hvx_alert0: trip-point0 {
1629 lpass-thermal {
1630 polling-delay-passive = <250>;
1632 thermal-sensors = <&tsens 2>;
1635 lpass_alert0: trip-point0 {
1643 wlan-thermal {
1644 polling-delay-passive = <250>;
1646 thermal-sensors = <&tsens 3>;
1649 wlan_alert0: trip-point0 {
1657 cluster-thermal {
1658 polling-delay-passive = <250>;
1660 thermal-sensors = <&tsens 4>;
1663 cluster_alert0: trip-point0 {
1668 cluster_alert1: trip-point1 {
1673 cluster_crit: cluster-crit {
1679 cooling-maps {
1682 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1690 cpu0-thermal {
1691 polling-delay-passive = <250>;
1693 thermal-sensors = <&tsens 5>;
1696 cpu0_alert0: trip-point0 {
1701 cpu0_alert1: trip-point1 {
1706 cpu0_crit: cpu-crit {
1712 cooling-maps {
1715 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1723 cpu1-thermal {
1724 polling-delay-passive = <250>;
1726 thermal-sensors = <&tsens 6>;
1729 cpu1_alert0: trip-point0 {
1734 cpu1_alert1: trip-point1 {
1739 cpu1_crit: cpu-crit {
1745 cooling-maps {
1748 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1756 cpu2-thermal {
1757 polling-delay-passive = <250>;
1759 thermal-sensors = <&tsens 7>;
1762 cpu2_alert0: trip-point0 {
1767 cpu2_alert1: trip-point1 {
1772 cpu2_crit: cpu-crit {
1778 cooling-maps {
1781 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1789 cpu3-thermal {
1790 polling-delay-passive = <250>;
1792 thermal-sensors = <&tsens 8>;
1795 cpu3_alert0: trip-point0 {
1800 cpu3_alert1: trip-point1 {
1805 cpu3_crit: cpu-crit {
1811 cooling-maps {
1814 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1822 gpu-thermal {
1823 polling-delay-passive = <250>;
1825 thermal-sensors = <&tsens 9>;
1828 gpu_alert0: trip-point0 {