Lines Matching +full:0 +full:xf1d
24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 cpu_sleep_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
177 mboxes = <&apcs_glb 0>;
253 reg = <0 0x85900000 0 0x500000>;
258 reg = <0 0x85e00000 0 0x100000>;
263 reg = <0 0x85f00000 0 0x200000>;
268 reg = <0 0x86100000 0 0x300000>;
273 reg = <0 0x86400000 0 0x1100000>;
278 reg = <0 0x87500000 0 0x1a00000>;
283 reg = <0 0x88f00000 0 0x600000>;
288 reg = <0 0x89500000 0 0x100000>;
293 reg = <0 0x9f800000 0 0x800000>;
307 soc: soc@0 {
310 ranges = <0 0 0 0xffffffff>;
315 reg = <0x00800000 0x30000>;
326 reg = <0x00060000 0x6000>;
331 reg = <0x00078000 0x400>;
332 #phy-cells = <0>;
345 reg = <0x0007a000 0x200>;
346 #phy-cells = <0>;
359 reg = <0x0007c000 0x200>;
360 #phy-cells = <0>;
373 reg = <0x000a4000 0x1000>;
377 reg = <0x13c 0x4>;
382 reg = <0x1f8 0x1>;
383 bits = <0 6>;
387 reg = <0x1f8 0x2>;
392 reg = <0x1f9 0x2>;
397 reg = <0x1fa 0x1>;
402 reg = <0x1fb 0x1>;
403 bits = <0 6>;
407 reg = <0x1fb 0x2>;
412 reg = <0x1fc 0x2>;
417 reg = <0x1fd 0x1>;
422 reg = <0x1fe 0x1>;
423 bits = <0 6>;
427 reg = <0x1fe 0x2>;
432 reg = <0x200 0x1>;
433 bits = <0 6>;
437 reg = <0x200 0x2>;
442 reg = <0x201 0x2>;
447 reg = <0x202 0x1>;
452 reg = <0x203 0x1>;
453 bits = <0 6>;
457 reg = <0x203 0x2>;
462 reg = <0x204 0x2>;
467 reg = <0x205 0x1>;
472 reg = <0x206 0x1>;
473 bits = <0 6>;
477 reg = <0x206 0x2>;
482 reg = <0x208 1>;
483 bits = <0 3>;
487 reg = <0x208 2>;
492 reg = <0x209 2>;
497 reg = <0x231 0x4>;
501 reg = <0x232 0x4>;
505 reg = <0x233 0x4>;
509 reg = <0x229 0x4>;
513 reg = <0x22a 0x4>;
517 reg = <0x22b 0x4>;
518 bits = <0 6>;
521 reg = <0x22b 0x4>;
525 reg = <0x22d 0x4>;
529 reg = <0x230 0x4>;
530 bits = <0 12>;
533 reg = <0x228 0x4>;
534 bits = <0 3>;
537 reg = <0x228 0x4>;
541 reg = <0x229 0x4>;
542 bits = <0 3>;
545 reg = <0x218 0x4>;
552 reg = <0x000e3000 0x1000>;
558 reg = <0x00400000 0x80000>;
565 reg = <0x004a9000 0x1000>, /* TM */
566 <0x004a8000 0x1000>; /* SROT */
598 reg = <0x00500000 0x15080>;
604 reg = <0x00580000 0x23080>;
611 reg = <0x00b00000 0x4040>;
614 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
644 * qcom,halt-regs = <&tcsr 0x19004>;
649 qcom,smem-states = <&cdsp_smp2p_out 0>;
666 reg = <0x07678800 0x400>;
690 reg = <0x07580000 0xcd00>;
695 snps,hird-threshold = /bits/ 8 <0x10>;
705 reg = <0x079b8800 0x400>;
729 reg = <0x078c0000 0xcc00>;
734 snps,hird-threshold = /bits/ 8 <0x10>;
744 reg = <0x01000000 0x200000>,
745 <0x01300000 0x200000>,
746 <0x07b00000 0x200000>;
749 gpio-ranges = <&tlmm 0 0 120>;
886 reg = <0x01800000 0x80000>;
894 <0>,
895 <0>,
896 <0>;
904 reg = <0x01905000 0x20000>;
910 reg = <0x01937000 0x25000>;
915 reg = <0x00290000 0x10000>;
920 reg = <0x0200f000 0x001000>,
921 <0x02400000 0x800000>,
922 <0x02c00000 0x800000>,
923 <0x03800000 0x200000>,
924 <0x0200a000 0x002100>;
928 qcom,ee = <0>;
929 qcom,channel = <0>;
931 #size-cells = <0>;
938 reg = <0x07400000 0x4040>;
941 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
953 qcom,smem-states = <&wcss_smp2p_out 0>;
970 reg = <0x07786000 0xb8>;
978 #clock-cells = <0>;
979 #phy-cells = <0>;
986 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
1003 reg = <0x07884000 0x25000>;
1008 qcom,ee = <0>;
1014 reg = <0x078af000 0x200>;
1018 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1021 pinctrl-0 = <&blsp1_uart0_default>;
1027 reg = <0x078b0000 0x200>;
1034 pinctrl-0 = <&blsp1_uart1_default>;
1040 reg = <0x078b1000 0x200>;
1047 pinctrl-0 = <&blsp1_uart2_default>;
1053 reg = <0x07a80000 0x10000>,
1054 <0x07a96000 0x100>;
1074 reg = <0xa000000 0x800000>;
1094 reg = <0x078b2000 0x200>;
1101 pinctrl-0 = <&blsp1_uart3_default>;
1107 reg = <0x078b5000 0x600>;
1113 pinctrl-0 = <&blsp1_i2c0_default>;
1115 #size-cells = <0>;
1121 reg = <0x078b5000 0x600>;
1127 pinctrl-0 = <&blsp1_spi0_default>;
1129 #size-cells = <0>;
1135 reg = <0x078b6000 0x600>;
1141 pinctrl-0 = <&blsp1_i2c1_default>;
1143 #size-cells = <0>;
1149 reg = <0x078b6000 0x600>;
1155 pinctrl-0 = <&blsp1_spi1_default>;
1157 #size-cells = <0>;
1163 reg = <0x078b7000 0x600>;
1169 pinctrl-0 = <&blsp1_i2c2_default>;
1171 #size-cells = <0>;
1177 reg = <0x078b7000 0x600>;
1183 pinctrl-0 = <&blsp1_spi2_default>;
1185 #size-cells = <0>;
1191 reg = <0x078b8000 0x600>;
1197 pinctrl-0 = <&blsp1_i2c3_default>;
1199 #size-cells = <0>;
1205 reg = <0x078b8000 0x600>;
1211 pinctrl-0 = <&blsp1_spi3_default>;
1213 #size-cells = <0>;
1219 reg = <0x078b9000 0x600>;
1225 pinctrl-0 = <&blsp1_i2c4_default>;
1227 #size-cells = <0>;
1233 reg = <0x078b9000 0x600>;
1239 pinctrl-0 = <&blsp1_spi4_default>;
1241 #size-cells = <0>;
1247 reg = <0x07ac4000 0x17000>;
1252 qcom,ee = <0>;
1258 reg = <0x07aef000 0x200>;
1262 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1265 pinctrl-0 = <&blsp2_uart0_default>;
1271 reg = <0x07af5000 0x600>;
1277 pinctrl-0 = <&blsp2_i2c0_default>;
1279 #size-cells = <0>;
1285 reg = <0x07af5000 0x600>;
1291 pinctrl-0 = <&blsp2_spi0_default>;
1293 #size-cells = <0>;
1299 reg = <0x08600000 0x1000>;
1304 ranges = <0 0x08600000 0x1000>;
1308 reg = <0x94c 0xc8>;
1316 reg = <0x0b000000 0x1000>,
1317 <0x0b002000 0x1000>;
1323 reg = <0x0b011000 0x1000>;
1327 #clock-cells = <0>;
1332 reg = <0x0b016000 0x30>;
1333 #clock-cells = <0>;
1341 reg = <0x0b017000 0x1000>;
1347 reg = <0x0b018000 0x1000>;
1348 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
1352 #power-domain-cells = <0>;
1389 reg = <0x0b120000 0x1000>;
1393 frame-number = <0>;
1396 reg = <0x0b121000 0x1000>,
1397 <0x0b122000 0x1000>;
1403 reg = <0x0b123000 0x1000>;
1410 reg = <0x0b124000 0x1000>;
1417 reg = <0x0b125000 0x1000>;
1424 reg = <0x0b126000 0x1000>;
1431 reg = <0xb127000 0x1000>;
1438 reg = <0x0b128000 0x1000>;
1445 reg = <0x0c700000 0x4040>;
1448 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1460 qcom,smem-states = <&adsp_smp2p_out 0>;
1477 reg = <0x10000000 0xf1d>,
1478 <0x10000f20 0xa8>,
1479 <0x07780000 0x2000>,
1480 <0x10001000 0x2000>;
1483 linux,pci-domain = <0>;
1484 bus-range = <0x00 0xff>;
1489 ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
1490 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
1495 interrupt-map-mask = <0 0 0 0x7>;
1496 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1497 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1498 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1499 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1524 pcie@0 {
1526 reg = <0x0 0x0 0x0 0x0 0x0>;
1527 bus-range = <0x01 0xff>;
1549 qcom,local-pid = <0>;
1569 qcom,local-pid = <0>;
1589 qcom,local-pid = <0>;
1608 thermal-sensors = <&tsens 0>;